Logical multicast message copying method and system based on linked list and queue scheduling

Abstract

The invention relates to the technical field of communication messages, and particularly discloses a logic multicast message copying method and system based on linked list and queue scheduling, and the method comprises the following steps: carrying out discarding rule judgment on a received logic multicast message, the logic multicast message being an Ethernet data message needing to be copied and transmitted; and storing the cache address of the logic multicast message judged according to the discarding rule in the form of a linked list, and recording the logic copying times of the message. According to the technical scheme, traditional physical replication is replaced by logic replication, only one original message is stored, the cache address is managed in the form of a linked list, and message admission is accurately controlled in combination with the discarding rule, so that the storage space occupied by the multicast message is greatly reduced, the delay among multiple copied messages is also greatly reduced, and the service life of the multicast message is prolonged. The multiple logic multicast messages are sequentially scheduled to each target user port in the same priority queue.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication messages, in particular to a logical multicast message replication method and system based on linked list and queue scheduling. BACKGROUND

[0002] In modern network communication, especially in data centers and enterprise networks, Ethernet routing and switching devices play a crucial role. A common scenario is to send a piece of data (such as video stream, market data, software update, etc.) to multiple users simultaneously, which is called "multicast".

[0003] To implement multicast, the network switching chip needs to replicate an incoming message into multiple copies and send them to different target ports. The traditional implementation method is usually "physical replication", that is, each message copy is generated completely in the buffer and then sent one by one. This method is simple and direct, but its disadvantages are also very obvious when the multicast group is large: First, the cache resource consumption is huge, each copy occupies independent cache space, when hundreds of copies are needed, the valuable cache resources in the chip will be quickly exhausted; and this method also leads to high replication delay, generating a large number of copies itself takes time, which increases the overall delay of message forwarding. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art. To this end, the purpose of the present application is to propose a logical multicast message replication method and system based on linked list and queue scheduling to realize efficient, low-delay sending and real-time resource recovery of messages.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application proposes a logical multicast message replication method based on linked list and queue scheduling, comprising the following steps: Step S1, performing discard rule judgment on the received logical multicast message, the logical multicast message being an Ethernet data message that needs to be replicated and transmitted in multiple copies; Step S2, storing the message payload of the logical multicast message passing through the discard rule judgment into the cache and storing its cache address in the form of a linked list, and recording the logical replication times of the message; Step S3, according to the priority and egress port of the logical multicast message, sending its control information to the corresponding priority queue for queuing and scheduling; Step S4, when the priority queue is selected, the logical replication times of the logical multicast message are decremented by 1, and the message content is read from the cache; Step S5, based on the preset address identifier, the corresponding destination MAC address is obtained from the MAC address storage table, and the MAC address of the read message content is replaced; Step S6, when the logical copy number is decremented to 0, the cache resources and queue resources occupied by the logical multicast message are released.

[0006] In some embodiments of the present application, the discard rule in step S1 includes discard rule A and discard rule B; The discard rule A is: according to the storage table and register lookup result of the Ethernet switch chip, combined with the control information carried by the logical multicast message and the switch matching rule, it is judged whether to discard the logical multicast message; The discard rule B is: based on the total cache space of the Ethernet routing switch chip, the total number of stored messages, and whether the cache space and the number of stored messages of the logical multicast message belong to the port or the priority queue reach the upper limit, it is judged whether to discard the logical multicast message; Only when the logical multicast message passes the judgment of discard rule A and discard rule B at the same time, step S2 is executed.

[0007] In some embodiments of the present application, the address chain table in step S2 specifically includes: The complete original content of the logical multicast message is stored in the Buf Memory storage table of the cache space, the cache address is taken out and recorded in the next Buffer storage table in the form of head and tail concatenation, forming an address chain table; The head address and tail address of the address chain table are recorded as the control information of the logical multicast message, which is used to transmit the message storage position to the subsequent module.

[0008] In some embodiments of the present application, the logical copy number of the message in step S2 specifically includes: The logical copy number is stored in the chain table storage table of the scheduling module, and the logical copy number is the total number of copies required by the logical multicast message, when the logical copy number is greater than 0, it represents that the message needs to perform multicast copy; When the logical copy number is equal to 0, it represents that the message is a unicast message without copy.

[0009] In some embodiments of the present application, the queuing and scheduling in step S3 specifically includes: The SP (strict priority) scheduling or WDRR (weighted deficit round robin) scheduling rule is used to queue and schedule the control information of the logical multicast message in the priority queue; The control information of the logical multicast message includes its head address, tail address and logical copy number.

[0010] In some embodiments of the present application, the step S4 of decreasing the logical copy number of the logical multicast message by 1 specifically comprises: When the priority queue is selected, only the logical multicast message at the current queue head is subjected to the decreasing operation of the logical copy number by 1, and the control information and the buffer resource of the message are not released.

[0011] In some embodiments of the present application, the preset address in the step S5 is ucIdx, and the ucIdx is an address code used for identifying the storage position of the MAC address corresponding to the logical multicast message in the MAC address storage table. The MAC address storage table is a logical storage table used for storing the respective destination MAC addresses of the multiple copies of the message.

[0012] In some embodiments of the present application, the step S6 of releasing the buffer resource and the queue resource occupied by the logical multicast message specifically comprises: releasing the buffer space occupied by the logical multicast message in the Buf Memory storage table, and returning the number of released buffers to the total number of available buffers of the chip; releasing the queue pointer occupied by the message in the priority queue, and increasing the number of available messages in the queue by 1.

[0013] To achieve the above object, the second aspect of the present application provides a logical multicast message copy system based on a linked list and a queue scheduling, comprising: a discard judgment module, configured to perform a discard rule judgment on the received logical multicast message; a linked list storage module, configured to store the buffer address of the logical multicast message subjected to the discard judgment in the form of a linked list, and record the logical copy number thereof; a queue scheduling module, configured to send the control information of the logical multicast message to the corresponding priority queue according to the priority and the egress port of the logical multicast message, and perform a queue scheduling; a message editing module, configured to perform a decreasing operation of the logical copy number on the logical multicast message when the target queue is selected by the queue scheduling module, read the content of the message in the buffer, and complete a MAC address replacement; a resource releasing module, configured to release the buffer resource and the queue resource occupied by the logical multicast message when the logical copy number is decreased to 0.

[0014] In some embodiments of the present application, the queue scheduling module comprises a scheduling rule storage unit and a queue management unit. The scheduling rule storage unit is configured to store the SP scheduling rule and the WDRR scheduling rule. The queue management unit is used for managing head and tail pointers of a priority queue, storing logical copy times of a next message for each logical multicast message in the same queue, and realizing chain scheduling of messages in the queue.

[0015] To achieve the above object, the third aspect of the present application provides an electronic device, comprising a memory, a processor and a computer program stored in the memory, wherein the computer program is executed by the processor to implement the logical multicast message copy method based on chain table and queue scheduling.

[0016] The logical multicast message copy method and system based on chain table and queue scheduling provided by the embodiments of the present application replace traditional physical copy with logical copy, store only one original message and manage cache addresses in the form of a chain table, and accurately control message access in combination with discard rules, thereby greatly reducing the storage space occupied by multicast messages and greatly reducing the delay between multiple copies of the messages, because multiple logical multicast messages are sequentially scheduled to each destination user port in the same priority queue, thereby avoiding repeated storage and frequent release operations of multiple messages. Moreover, the dynamic replacement of MAC addresses meets the multicast transmission requirements, and the cache and queue resources are released in time after the copy is completed, thereby significantly improving the utilization efficiency of the cache and queue resources and guaranteeing the efficiency and stability of multicast message transmission, and the method is particularly suitable for wifi multi-user scenarios and other scenarios requiring high-frequency multicast. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a flowchart of the logical multicast message copy method based on chain table and queue scheduling provided by the embodiments of the present application; Figure 2 is a storage representation diagram of BufMemory and next Buffer in the logical multicast message copy method based on chain table and queue scheduling provided by the embodiments of the present application; Figure 3 is a chain table storage representation diagram of a scheduling module in the logical multicast message copy method based on chain table and queue scheduling provided by the embodiments of the present application; Figure 4 is a queue scheduling rule diagram in the logical multicast message copy method based on chain table and queue scheduling provided by the embodiments of the present application; Figure 5 is a DsUcIdx representation diagram in the logical multicast message copy method based on chain table and queue scheduling provided by the embodiments of the present application; Figure 6 is a MAC address storage table (DMAC table) diagram in the logical multicast message copy method based on chain table and queue scheduling provided by the embodiments of the present application; Figure 7Fig. 1 is a structural schematic diagram of an electronic device according to another embodiment of the present application. DETAILED DESCRIPTION

[0018] Embodiments of the present application are described below in detail with reference to the accompanying drawings, in which the same or similar components or components having the same or similar functions are denoted by the same or similar reference numerals throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as limiting the present application.

[0019] A logical multicast message replication method, system and electronic device based on linked list and queue scheduling are described below with reference to the accompanying drawings.

[0020] Figure 1 Fig. 1 is a structural schematic diagram of an electronic device according to another embodiment of the present application.

[0021] As shown in Fig. 1, the logical multicast message replication method based on linked list and queue scheduling includes the following steps: Figure 1 Step S1, performing a discard rule judgment on a received logical multicast message, the logical multicast message being an Ethernet data message requiring multiple copies for transmission. This step is a preprocessing and system protection step of the present method. After an Ethernet data message is received by a network switching chip, whether it is a unicast message or a logical multicast replication message, a discard judgment is first performed. If the discard condition is met, the flow is terminated; if not, step S2 is entered. The difference between a unicast message and a logical multicast replication message is that when a unicast message is dequeued (deq), if the duplication count (duplicationCnt) is 0, the queue is directly dequeued, and the cache address space and the message count in the queue are released. If it is a multicast replication message, the space is not released each time deq is performed, but only when the last copy of the replication message is dequeued, i.e., when duplicationCnt is reduced to 0, all the space is released.

[0022] Step S1 specifically includes the following sub-steps:

[0023] S11, performing a logical multicast message discard rule A: according to the lookup results of the preset storage table (such as the forwarding rule table) and the registers of the Ethernet switch chip, in combination with the control information (including the source IP field, the destination IP field, the source MAC field, the destination MAC field, the VLAN field, etc.) carried by the message and the switch matching rules (such as the protocol standard or the self-defined forwarding policy), it is judged whether the message meets the forwarding requirements. If not, the "protocol discard bit" in the message control field is set to 1 (indicating that it needs to be discarded); if it does, the "protocol discard bit" is set to 0.

[0024] ​S12, execute logic multicast message discard rule B: based on chip cache space and message number access logic, judge whether the message can enter the cache. Specifically, it includes: Check whether the total chip cache space reaches the upper limit, whether the cache space of the message belongs to the output port or the priority queue reaches the upper limit; Check whether the total number of stored messages in the chip reaches the upper limit, whether the number of stored messages in the message belongs to the output port or the priority queue reaches the upper limit; If any of the above conditions reaches the upper limit, set the "admission discard bit" in the control field to 1; if none of them reaches the upper limit, set the "admission discard bit" to 0.

[0025] S13, only when the "protocol discard bit" and the "admission discard bit" are both 0, the message passes the discard rule judgment; otherwise, the message is discarded.

[0026] Step S2, store the cache address of the logic multicast message that passes the discard rule judgment in the form of a linked list, and record the number of logical copies of the message.

[0027] This step is the core of implementing "logical copy" to save cache space. For the message that passes the S1 judgment, the following operations are performed: 1. Single data storage: store the complete data content of the logic multicast message in the cache only once, and obtain a physical cache address or index pointing to the storage location; 2. Metadata linked list construction: the system does not copy the message data, but creates a set of lightweight metadata structures for it and organizes them in the form of a linked list. Please refer to the attached Figure 2 , which directly shows the specific implementation of "storing message content into BufMemory and forming address linked list through next Buffer" in step S2, which helps to understand the chained management mode of cache address.

[0028] Specifically, the following sub-steps are included: S21, cache address linked list storage: store the complete original content of the logic multicast message in the Buf Memory storage table of the chip cache space ( Figure 2 ), and record the cache address of the message in the Buf Memory in the "head and tail concatenation" way in the next Buffer storage table to form an address linked list (i.e. the cache address of the current message points to the next address in the linked list). At the same time, record the head address and tail address of the address linked list as the core control information of the message, which is used for subsequent module positioning of the message storage location.

[0029] S22, record the number of logical copies: store the total number of copies (i.e. the number of logical copies) of the message in the linked list storage table of the scheduling module, such as Figure 3As shown. Among them, the logical copy number > 0, representing the need to perform multicast replication; the logical copy number = 0, representing the unicast message, no need to copy. The number will be as the core basis of subsequent scheduling.

[0030] Step S3, according to the priority of the logical multicast message and the out port, the control information is sent to the corresponding priority queue for queuing scheduling, specifically including the following sub steps: S31, queue matching: the priority and out port (target port to be sent) are extracted from the message header information, and the corresponding priority queue of the message in the traffic management scheduling module is determined, and a plurality of priority queues are provided under each out port, and the high priority queue is preferentially scheduled.

[0031] S32, control information queuing: the control information (including the first address, the tail address, the logical copy number, etc.) of the message is sent to the matched priority queue for queuing. The chain management is used in the queue, that is, the pointer of each message stores the logical copy number (nxtPktPointer, replicationCnt, etc.) of the next message in the DsPktNxtList table of the DsPktNxtList table), realizing the ordered connection of the messages in the queue. Figure 3

[0032] S33, scheduling rule: the queue scheduling adopts SP (strict priority) or WDRR (weighted deficit round robin) rule, as shown in Figure 4 , to ensure that the high priority message or the queue with high weight is preferentially selected.

[0033] Step S4, when the priority queue is selected, the logical copy number of the logical multicast message is decremented by 1, and the message content is read from the cache, specifically including the following sub steps: S41, queue selection and count update: when a priority queue is selected by the SP / WDRR rule, the dequeue operation is performed on the logical multicast message at the head of the queue (only marked scheduling, without releasing the queue resource or the cache resource), and the logical copy number is decremented by 1 (updated through the replicationCnt field of Figure 3 ).

[0034] S42, message content reading: the complete content of the message is read from the Buf Memory storage table according to the slice (based on the first address and the tail address recorded in step S2), and the read content is transmitted to the subsequent message editing module.

[0035] S43, continuous scheduling optimization: since the message is always located at the head of the queue, it will be continuously scheduled from the queue when copied multiple times, avoiding the delay caused by message switching, significantly reducing the overall delay of multicast replication, and being especially suitable for IPTV and other services with high real-time requirements. ​

[0036] Step S5, based on the preset address identifier, the corresponding destination MAC address is obtained from the MAC address storage table, and the MAC address of the read message content is replaced, specifically including the following sub-steps: S51, address identifier positioning: taking ucIdx as a preset address identifier (such as Figure 5 DsUcIdx table, containing the nxtUcIdx field), the identifier is used to locate the storage position of the destination MAC address of the current copied message in the MAC address storage table (such as Figure 6 DMAC table in

[0037] S52, MAC address acquisition and replacement: read the destination MAC address corresponding to ucIdx from the MAC address storage table, and replace the destination MAC address of the original message in the message editing module to generate the message of the current copy. Each copy of the message is different only in the destination MAC address, and the rest of the content is consistent with the original message.

[0038] S53, next address update: if the copy needs to continue (the logical copy number is not reduced to 0), the ucIdx of the next copy message is obtained through nxtUcIdx, and the next replacement is prepared. Step S6, when the logical copy number is reduced to 0, the cache resources and queue resources occupied by the logical multicast message are released, specifically including the following sub-steps: S61, cache resource release: release the cache space occupied by the message in the Buf Memory storage table, and return the released cache number to the total available cache of the chip, and restore the allocatable state of the cache resource.

[0039] S62, queue resource release: release the queue pointer (nxtPktPointer field of Figure 3 ) occupied by the message in the priority queue, and add 1 to the available message number of the queue, so that the queue resource can be used for queuing new messages.

[0040] S63, subsequent processing: the pointer of the next logical multicast message is obtained through nxtPktPointer, and steps S3 to S6 are repeated to realize continuous processing of the messages in the queue.

[0041] Through the above steps, only one original message is stored and replaced by logical copy instead of physical copy, combined with linked list storage, chain scheduling and dynamic resource release, efficient and low-delay transmission of multicast messages is realized, and the cache resource occupation is significantly reduced.

[0042] In some embodiments of the present application, step S1 is a front-end stage for ensuring the stability and efficiency of the entire logical multicast replication system. It ensures that only compliant and system-capable messages can enter the subsequent core processing flow through a dual-dimension judgment mechanism. The discard rules in step S1 include discard rule A and discard rule B. The detailed description of discard rule A is as follows: This rule mainly implements a filtering based on strategy and security. When a logical multicast message arrives at the switch chip, the message parsing engine extracts its key control information, which can include but is not limited to: The source / destination MAC address of the second layer, the VLAN tag (including the priority PCP field), the source / destination IP address of the third layer, and the source / destination port number of the fourth layer. Subsequently, the chip's lookup engine uses these control information to perform matching lookup in the chip's internal preset hardware storage table and register. These storage tables are usually access control lists (ACLs), security policy tables, or routing policy tables configured by network administrators.

[0043] The matching rules themselves are specific embodiments of these strategies. For example, the rule can be set as "prohibit all multicast traffic from a specific IP network segment", "only allow messages targeting a specific multicast group address to pass", or "discard all messages carrying a certain specific application layer identifier".

[0044] Therefore, the essence of discard rule A is a policy execution engine. It intercepts multicast messages that do not comply with network management policies, pose security risks, or are illegal before consuming cache resources, thereby protecting the security and manageability of the network.

[0045] The detailed description of discard rule B is as follows: This rule mainly implements a congestion control and overload protection based on real-time resource status. This is a dynamic judgment process aimed at preventing the chip resources from being exhausted due to a large number of multicast replication requests at a moment, thereby causing a sharp decline in system performance or even a crash.

[0046] The judgment of this rule is hierarchical: First, global resource judgment is performed. The system monitors the occupancy rate of the entire chip's shared cache pool (i.e., the total cache space) and the total number of stored messages in real time. When the global cache occupancy rate exceeds a preset high threshold, such as 85%, or the total number of messages reaches the upper limit of the chip's specifications, it indicates that the entire chip is in a high load state. At this time, the system will discard the incoming logical multicast messages to avoid the avalanche effect and ensure the normal processing of existing services.

[0047] Secondly, under the premise of sufficient global resources, more refined local resource judgment is carried out. In the method, all the egress ports to which the logical multicast message needs to be finally copied and the service priority to which it belongs are analyzed, and the priority determines which scheduling queue it will enter. The system checks whether the dedicated cache quota or message counter of the target egress port or the corresponding priority queue has also reached the upper limit. For example, a certain egress port is continuously congested because it is connected to a slow device, and its corresponding sending queue is occupied, so the new multicast message that also needs to be sent to the port should be discarded in advance, even if the global cache is still sufficient. This local judgment mechanism realizes the refined management of resources, can effectively isolate the fault point or congestion point, and prevent individual ports or low-priority services from consuming too much resources and affecting the quality of service (QoS) of the whole system.

[0048] In summary, the logical multicast message must first pass the identity and authority review of discard rule A to prove its "legality"; then it must also pass the resource and health degree check of discard rule B to prove that the system "has the ability" to process it. Only when both conditions of the two dimensions are met, the message is considered valid and processable, and is allowed to perform the subsequent step S2, that is, to allocate cache and construct a logical replication linked list. This double filtering mechanism ensures the robustness and high efficiency of the method in complex network environment.

[0049] In some embodiments of the application, the step S2 of storing the cache address in the form of a linked list is specifically analyzed. This step is the key link between message reception and message scheduling, and its core task is to establish an efficient storage and management mechanism for the logical multicast message judged by the discard rule. Specifically, it can be divided into two levels of physical storage and logical identification.

[0050] Regarding the implementation of "storing the cache address in the form of a linked list". This specifically refers to the way of physically storing and organizing the content of a single message that may span multiple cache units. Inside the chip, large-capacity cache space is usually divided into fixed-size cache units or blocks, which are collectively referred to as Buf Memory storage table.

[0051] When a logical multicast message, especially a message with a large length (such as a jumbo frame), needs to be stored, the system allocates one or more such cache units for it. In order to manage these possibly discontinuous cache units, the conventional design logic of the chip datapath is as follows: in the chip data processing flow, the datapath generally carries the packet length as packet information, that is, the message carries the packet length attribute, the packet length records the total length of the message corresponding to the number of cache units to be read, and the end point of reading is identified through the last cache unit (tail buf), and when the number of cache units to be read reaches the packet length value or the tail buf is traversed, it is determined that the message reading is completed.

[0052] In some embodiments of the present application, the logical copy number of the message recorded in step S2 is specifically analyzed, which is to assign the identification of the copy behavior of the message at the logical level. After the control information of the message is sent to the scheduling module, the total number of copies required, i.e. the logical copy number, is recorded in a key data structure inside the scheduling module, which can be called a linked list storage table or a message descriptor table.

[0053] This logical copy number is the core basis for the scheduler to determine how to process the message. In the unified processing architecture of the present application, this field ingeniously combines the processing of multicast and unicast services: when a message needs to be copied to N targets (N>1), its logical copy number is set to N, which explicitly represents that the message needs to perform a multicast copy process, i.e. each time a copy is sent, the count value is decremented and re-queued until it is zero; when a message only needs to be sent to a single destination, i.e. a standard unicast message, its logical copy number is set to 1.

[0054] In this way, when the scheduler processes the message with a count value of 1, after sending is completed, the count value is decremented to zero, and the process directly enters the resource release link without performing any copy and re-queue operations. This design enables the chip to not need to set two independent sets of processing hardware and logic for unicast and multicast services, but to achieve process compatibility under the same architecture through a simple count value, greatly simplifying system design and improving the universality and efficiency of resource utilization.

[0055] In some embodiments of the present application, the queuing and scheduling in step S3 are specifically analyzed: This step is the core to ensure different service flows can get differentiated quality of service (QoS) guarantee. In the present scheme, instead of queuing the huge message entity directly, only the light-weight control information of the message is operated, which greatly improves the efficiency of scheduling. The control information here, i.e. the head address and tail address of the address list containing the storage location of the message in the cache, and the key metadata representing the logical replication times of the message. The present scheme configures multiple independent priority queues for each or each group of egress ports, for example, 8 queues arranged from high to low. When the control information of a message needs to be queued, the system will put it into the corresponding queue according to the priority field carried by the message itself (such as PCP value in VLAN header or DSCP value in IP header).

[0056] When the scheduler decides the next message to be sent, it will adopt flexible and efficient scheduling rules. Specifically, strict priority (SP) scheduling can be adopted, that is, as long as there is control information to be processed in the high priority queue, the scheduler will never serve the low priority queue, which guarantees the absolute priority of delay-sensitive critical services (such as voice, video conference). At the same time, in order to avoid the "starvation" of messages in the low priority queue due to long time without service, for multiple queues of the same level or low priority, weighted deficit round robin (WDRR) scheduling can be adopted. WDRR allows each queue to be allocated a weight, and according to the weight, the service opportunity is given in proportion, and it can also compensate for the queues that have not been completely served before, so as to realize flexible control of traffic on the basis of ensuring fairness. Through the combination of SP and WDRR, the present scheme can guarantee the performance of critical services while taking into account the overall throughput and fairness of the system.

[0057] In some embodiments of the present application, the logical replication times of the logical multicast message in step S4 are decremented by 1, which is the core driving link of the logical multicast replication cycle.

[0058] When the scheduler selects a winner from a priority queue according to the rules of step S3, it will read the message control information located at the head of the queue. The key point is that the operation performed by the present scheme at this time is highly atomic: Firstly, the value of the logical replication times field in the control information is decremented by 1. Secondly, and more importantly, after the decrement operation is performed, the present scheme does not immediately release the control information of the message and the original content of the message stored in the cache pointed by it. This "non-release" action is intentional, because the decrement operation only means that one of the N replication tasks has been completed, not the termination of all tasks. As long as the logical replication times after decrementing is still greater than zero, the control information and its associated cache resources must be continued to be held, because they are the only basis for generating the remaining copies.

[0059] The packet control information of this state will be re-sent to the scheduling queue, waiting to be scheduled next. This "decrement but not immediately release" mechanism constitutes the basis of the efficient loop replication of the present application, ensuring that the resource remains in a valid locked state throughout the completion of the entire multicast task, and can only be released precisely after the task is completed.

[0060] In some embodiments of the present application, the preset address identifier in step S5 is ucIdx, which is an address code used to identify the storage location of the MAC address corresponding to the logical multicast packet in the MAC address storage table; the MAC address storage table is a logical storage table used to store the destination MAC addresses of each copy of the replicated packet.

[0061] This step is a key link for implementing logical replication to physical packet generation, and its core lies in how to assign a unique target address to each logical copy. The preset address identifier in the scheme is specifically an address code called ucIdx. ucIdx itself is not a MAC address, but a lightweight index value used for indirect addressing. Its role is to serve as a bridge connecting the replication request at the logical level and the address information at the physical level. The system maintains a dedicated logical storage table, i.e., the MAC address storage table, which centrally stores all the target MAC addresses required for this multicast task. The value of ucIdx precisely corresponds to the storage location or entry of a certain target MAC address in the table.

[0062] When the scheduler processes a packet copy, it reads the corresponding ucIdx from the control information associated with the copy. Subsequently, the system uses this ucIdx as an address or key to perform an efficient hardware lookup in the MAC address storage table, thereby accurately obtaining the unique target MAC address that the copy should have. At the packet sending engine, the system replaces or overwrites this MAC address retrieved from the table onto the corresponding field of the original packet data header read from the cache. Through this "index-lookup-replace" approach, the system dynamically assembles the correct target address for each logical copy, thereby generating complete physical packets that can be correctly identified and forwarded by the network. This design avoids carrying the lengthy MAC address itself in the scheduling queue and control information, but only transmits the lightweight ucIdx, significantly saving internal processing bandwidth and storage resources, and improving processing efficiency.

[0063] In some embodiments of the present application, the execution details of the resource release in step S6 are specifically described as follows. This step is a management closed loop that ensures that system resources are completely and immediately recycled after the task is completed, which is crucial for maintaining long-term stable operation of the system. The resource release here is a coordinated process, mainly including the recycling of cache resources and queue resources.

[0064] The release of the cache resources and queue resources occupied by the logical multicast message in step S6 specifically includes: Release the cache space occupied by the logical multicast message in the Buf Memory storage table, and return the number of released caches to the total number of available caches in the chip; release the queue pointer occupied by the message in the priority queue, and add 1 to the number of available messages in the queue.

[0065] First, regarding the release of cache resources. When the logical replication times of a logical multicast message finally decrease to 0, it indicates that all replication tasks of the message have been completed. At this time, the control module will trigger instructions to release all physical cache spaces occupied by the message in the Buf Memory storage table. If the message is large and spans multiple linked cache blocks, the system will recycle all related cache blocks one by one along the address list. Furthermore, the present scheme updates the global resource statistical information, specifically, the number of released cache blocks is accurately returned to the total number of available caches or the corresponding cache pool counter maintained in the chip. This ensures that the released resources can be immediately redistributed to new messages, achieving efficient recycling of cache resources.

[0066] Second, regarding the release of queue resources. The queue resources here mainly refer to the logical positions occupied by the control information of the message in the priority queue. When the life cycle of the message ends, the memory occupied by its corresponding control information (or message descriptor) itself will be released. At the same time, the "pit position" it occupies in the priority queue must also be emptied. Specifically, the present scheme releases the queue pointer pointing to the message control information, and performs a +1 operation on the available message number or available depth counter of the priority queue. The significance of this step is that it explicitly indicates to the scheduling system that there is an available position in the queue that can accommodate new message control information. Through the double and accurate release of cache entities and queue logic, the present scheme ensures that the system state can be completely and cleanly restored after each logical multicast task is completed, avoiding any form of resource leakage.

[0067] The present scheme also proposes a logical multicast message replication system based on linked list and queue scheduling, which realizes efficient, low-cost and accurate replication and forwarding of logical multicast messages through modular functional design. The following describes the various modules of the system in detail: The discard judgment module, as the entrance and the first line of defense of the system, its core responsibility is to conduct a strict access review before allocating any substantive resources to the packet. The module integrates double judgment logic: first, it will perform policy-based judgment, that is, using the control information of the packet (such as source / destination MAC address, IP address, etc.) to match the preset access control list (ACL) or security policy table in the chip, so as to filter out packets that do not comply with the rules or have security risks. Secondly, the module will perform real-time resource state-based judgment, which dynamically monitors the global shared cache occupancy rate of the entire chip and the local cache usage of the target egress port or priority queue. When any resource reaches the preset congestion threshold, the incoming packet will be discarded to prevent system overload. Only the packets that pass both policy review and resource check will be recognized as valid packets by the module and passed to the next module.

[0068] The linked list storage module is the key module to realize the core idea of logical replication. After receiving the packet that passes the access review, the module will perform two key operations.

[0069] First, it calls the cache management unit to store only one copy of the complete data of the packet in the physical cache space of the chip (i.e., the BufMemory storage table). For large packets that span multiple cache blocks, the module will use a nextBuffer storage table to link these physical blocks in a linked list form.

[0070] Second, the module generates a set of lightweight logical control information for this physically stored packet. This set of information not only records the address of the head of the address chain that can index to the complete packet data, but more importantly, it records an initial logical replication number according to the target total number of this task. This number is the basis for all subsequent replication, scheduling, and release operations.

[0071] The queue scheduling module is responsible for fine-grained management of the forwarding order of packets to ensure quality of service (QoS). The module receives the lightweight control information generated by the linked list storage module without the packet entity, and according to the priority of the packet itself (such as PCP / DSCP field), it is placed in one of the priority queues of the corresponding egress port.

[0072] The scheduler of this module uses a hybrid scheduling algorithm such as strict priority (SP) combined with weighted deficit round robin (WDRR). This algorithm ensures that high-priority services sensitive to delay are given the highest priority, while weighted round robin ensures that medium and low-priority services are not "starved", thus achieving efficient and fair traffic scheduling at the system level.

[0073] Packet editing module, when the queue scheduling module takes out the control information of a packet from the queue, this module starts to work. It first performs a minus 1 operation on the logical copy number field in the control information. Then, it reads out the unique original packet data from the cache using the address pointer in the control information. Next, it finds the specific target MAC address in the MAC address storage table according to the address identifier (ucIdx) corresponding to the current copy, and replaces the corresponding field in the original packet header with the address, thereby dynamically generating a copy of the physical packet to be sent. After completing the editing, the module checks the logical copy number after decrementing, and if the value is still greater than zero, it will send the control information back to the queue scheduling module for queuing to process the next copy.

[0074] Resource release module, the triggering condition of this module is that the packet editing module finds that the logical copy number is decremented to 0 during processing. Once triggered, the module will immediately execute a set of accurate resource recycling procedures.

[0075] On the one hand, it will release all physical cache blocks occupied by the packet in the Buf Memory storage table according to the control information of the packet, and return these spaces to the global cache pool. On the other hand, it will release the memory occupied by the packet control information itself, and notify the queue scheduling module to clear the logical position (queue pointer) occupied by it in the priority queue, so that the available depth of the queue is increased by 1. Through the double and thorough release of physical cache and logical queue resources, this module ensures that the system can return to a clean state after each multicast task is completed, eliminates the possibility of any resource leakage, and guarantees the long-term stable operation of the system.

[0076] In some embodiments of the present application, the queue scheduling module logically mainly includes two units working cooperatively: a scheduling rule storage unit and a queue management unit.

[0077] Firstly, the scheduling rule storage unit. It is not a dynamic processing unit, but a storage area for solidifying or storing the scheduling algorithm logic. At least two kinds of mature and efficient scheduling rules in the industry, namely strict priority (SP) scheduling rule and weighted deficit round robin (WDRR) scheduling rule, are defined and stored in the unit. The SP rule ensures that the highest priority service (such as real-time voice) can obtain the most priority processing right once it arrives, thereby guaranteeing its ultra-low delay requirement. The WDRR rule is applied between the medium and low priority queues, which allows different weights to be allocated to each queue, and the sending bandwidth is allocated in proportion to the weight in a fair manner, while the "deficit" mechanism can compensate for the queues that have not obtained sufficient services, thereby effectively preventing the low priority services from being completely "starved" and improving the overall throughput and resource utilization fairness of the system. The scheduler will determine which priority queue to take out the packet for processing at the next time according to the rules stored in the unit.

[0078] Secondly, the queue management unit. The core responsibility of the unit is to efficiently and accurately manage the data structure of all priority queues. In a typical implementation, each priority queue is a first-in-first-out (FIFO) queue constructed in the form of a linked list. The queue management unit maintains a head pointer and a tail pointer for each queue. The head pointer always points to the first packet control information at the head of the queue, which is the next object to be selected by the scheduler; the tail pointer always points to the tail, so that new packet control information can be quickly added to the end of the queue.

[0079] It needs to be clarified that the chain scheduling mechanism implemented by the unit is as follows: each node in the queue stores a separate control information of a logical multicast packet. The control information itself already contains data such as the number of logical copies, the cache head address, etc. What links these independent nodes in the queue is a "next hop pointer" contained in each node, which stores the memory address of the next node. Therefore, the accurate meaning of "chain scheduling of packets in the queue" is to manage macroscopically through the head and tail pointers, and to link all the pending processing packets in the queue into a logical chain through the "next hop pointer" between the nodes. When the scheduler takes away a packet control information from the head of the queue for processing, the queue management unit only needs to update the head pointer to the address pointed to by the "next hop pointer" of the original head node, which is extremely fast, thereby realizing efficient queue maintenance and packet scheduling flow.

[0080] Corresponding to the above embodiment, the application also provides an electronic device.

[0081] As Figure 7As shown is a structural schematic diagram of an electronic device in the present application, the electronic device 200 comprises a processor 201 and a memory 203. Wherein, the processor 201 and the memory 203 are connected, such as connected through a bus 202. Optionally, the electronic device 200 can further comprise a transceiver 204. It needs to be explained that, in actual application, the transceiver 204 is not limited to one, and the structure of the electronic device 200 does not constitute a limitation to the embodiments of the present application.

[0082] The processor 201 can be a CPU, a general processor, a DSP, an ASIC, an FPGA or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can realize or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure. The processor 201 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0083] The bus 202 can comprise a channel for transmitting information between the above-mentioned components. The bus 202 can be a PCI bus or an EISA bus, etc. The bus 202 can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 7 In the figure, only one thick line is used to represent, but it does not mean that there is only one bus or only one type of bus.

[0084] The memory 203 is used for storing a computer program corresponding to the above-mentioned embodiment of the present application, the computer program is executed by the processor 201 to control. The processor 201 is used for executing the computer program stored in the memory 203, so as to realize the content shown in the foregoing method embodiments.

[0085] Wherein, the electronic device 200 comprises but is not limited to: notebook computers, PAD (tablet computers) and other mobile terminals, and fixed terminals such as desktop computers and the like. Figure 7 The electronic device 200 shown is only an example, and should not bring any limitation to the function and use range of the embodiments of the present application.

[0086] The electronic device 200 of the embodiment of the application can replace the traditional physical replication with logical replication, store only one copy of the original packet, and efficiently manage the cache address through the linked list, accurately control the packet access in combination with the discard rule, and greatly reduce the storage space occupied by the multicast packet; with the aid of the queue scheduling mechanism and dynamic management of the number of logical replication times, the repeated storage and frequent release of multiple packets are avoided, and the delay in the logical replication process is effectively reduced; the MAC address is dynamically replaced to meet the multicast transmission requirement, and the cache and queue resources are released in time after the replication is completed, the resource utilization efficiency is significantly improved, and the efficiency and stability of the multicast packet transmission are guaranteed, and the embodiment of the application is especially suitable for the scene of high-frequency multicast such as wifi multi-user.

[0087] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of ordered steps for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from the instruction execution system, apparatus or device, or in conjunction with these instruction execution systems, apparatus or devices. For the purpose of this specification, the "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport programs for use by an instruction execution system, apparatus or device, or in conjunction with these instruction execution systems, apparatus or devices. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connections having one or more wires (electronic devices), portable computer diskettes (magnetic devices), random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memories), fiber optic devices, and portable compact disk read-only memories (CDROMs). In addition, the computer-readable medium can even be paper or other suitable medium on which the program can be printed, because the program can be electronically obtained, for example, by optical scanning of the paper or other medium, followed by editing, interpreting or otherwise processing the program as necessary, and then storing it in a computer memory.

[0088] It should be understood that various parts of the present application can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or their combinations can be used: discrete logic circuitry having logic gates for implementing logic functions upon data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0089] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0090] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0091] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method for logical multicast packet replication based on linked list and queue scheduling, characterized in that, The method comprises the following steps: Step S1, performing a discard rule judgment on a received logical multicast message, the logical multicast message being an Ethernet data message needing multiple copies for transmission; Step S2, storing the message payload of the logical multicast message passed through the discard rule judgment into a cache, and storing the cache address in a linked list form, and recording the logical copy number of the message; Step S3, according to the priority and the out port of the logical multicast message, sending the control information of the logical multicast message into a corresponding priority queue for queuing and scheduling; Step S4, when the priority queue is selected, decreasing the logical copy number of the logical multicast message by 1, and reading the message content from the cache; Step S5, based on a preset address identifier, obtaining the corresponding destination MAC address from the MAC address storage table, and performing MAC address replacement on the read message content; Step S6, when the logical copy number is decreased to 0, releasing the cache resources and queue resources occupied by the logical multicast message.

2. The method of claim 1, wherein, The discard rule in the step S1 comprises a discard rule A and a discard rule B; The discard rule A is: according to the storage table and the register lookup result of the Ethernet switch chip, combining the control information carried by the logical multicast message with the switch matching rule, judging whether to discard the logical multicast message; The discard rule B is: based on the total cache space, the total number of stored messages of the Ethernet routing switch chip, and whether the cache space and the number of stored messages of the out port or the priority queue to which the logical multicast message belongs reach the upper limit, judging whether to discard the logical multicast message; Only when the logical multicast message passes through the judgment of the discard rule A and the discard rule B at the same time, the step S2 is executed.

3. The method of claim 1, wherein, The step S2 of storing the cache address in a linked list form specifically comprises: storing the complete original content of the logical multicast message in the Buf Memory storage table of the cache space, taking out the cache address and recording it in the next Buffer storage table in the form of head and tail concatenation to form an address linked list; recording the head address and the tail address of the address linked list as the control information of the logical multicast message, the control information being used to pass the message storage position to the subsequent module.

4. The method of claim 1, wherein, The step S2 of recording the logical copy number of the message specifically comprises: storing the logical copy number in the linked list storage table of the scheduling module, the logical copy number being the total number of copies needed by the logical multicast message, when the logical copy number is greater than 0, indicating that the message needs to perform multicast copy; when the logical copy number is equal to 0, indicating that the message is a unicast message and does not need to be copied.

5. The method of claim 1, wherein, The queuing and scheduling in the step S3 specifically comprises: using the SP (strict priority) scheduling or WDRR (weighted deficit round robin) scheduling rule to perform queuing and scheduling on the control information of the logical multicast message in the priority queue; the control information of the logical multicast message comprising the head address, the tail address and the logical copy number.

6. The method of claim 1, wherein, The step S4 of decreasing the logical copy number of the logical multicast message by 1 specifically comprises: when the priority queue is selected, only the logical multicast message at the head of the current queue is subjected to the decreasing operation of the logical copy number by 1, and the control information and the cache resources of the message are not released.

7. The method of claim 1, wherein, The address identifier preset in the step S5 is ucIdx, which is an address code used for identifying the storage position of the MAC address corresponding to the logical multicast message in the MAC address storage table; The MAC address storage table is a logical storage table used for storing the respective destination MAC addresses of multiple copies of the message.

8. The method of claim 1, wherein, The step S6 of releasing the cache resource and the queue resource occupied by the logical multicast message specifically includes: Releasing the cache space occupied by the logical multicast message in the Buf Memory storage table, and returning the number of released caches to the total number of available caches of the chip; Releasing the queue pointer occupied by the message in the priority queue, and adding 1 to the number of available messages in the queue.

9. A logical multicast packet replication system based on linked list and queue scheduling, characterized in that, The method comprises the following steps: A discard judgment module is used for performing discard rule judgment on the received logical multicast message; A linked list storage module is used for storing the cache address of the logical multicast message passing the discard judgment in the form of a linked list, and recording the number of logical copies thereof; A queue scheduling module is used for sending the control information of the logical multicast message to the corresponding priority queue according to the priority and the egress port of the logical multicast message, and performing queue scheduling; A message editing module is used for performing a logical copy number decrement operation on the logical multicast message when the queue scheduling module selects a target queue, reading the message content in the cache, and completing MAC address replacement; A resource release module is used for releasing the cache resource and the queue resource occupied by the logical multicast message when the number of logical copies is decremented to 0.

10. The system of claim 9, wherein, The queue scheduling module comprises a scheduling rule storage unit and a queue management unit; The scheduling rule storage unit is used for storing SP scheduling rules and WDRR scheduling rules; The queue management unit is used for managing the head pointer and the tail pointer of the priority queue, so that the pointer of each logical multicast message in the same queue stores the number of logical copies of the next message, and chain scheduling of the messages in the queue is realized.

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