Preparation method of semiconductor structure and semiconductor structure

Abstract

According to the preparation method of the semiconductor structure and the semiconductor structure provided by the invention, the longitudinal space of a chip is fully utilized, and a gate dielectric layer, an active layer and a first source-drain layer are sequentially formed on a shallow trench isolation structure in a substrate, so that a longitudinally arranged high-voltage gate oxide layer MOS (Metal Oxide Semiconductor) tube is formed; therefore, the transverse area of the high-voltage gate oxide layer MOS tube is reduced, and the integration level of a chip where the high-voltage gate oxide layer MOS tube is located is improved. As the high-voltage gate oxide MOS tube is positioned above the shallow trench isolation structure in the substrate and is positioned on a different horizontal plane from the first MOS tube positioned in the substrate in the chip, the interference of the high-voltage gate oxide MOS tube on the adjacent first MOS tube is reduced. Therefore, an isolation structure does not need to be arranged between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube, the horizontal distance between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube is reduced, the overall area of a chip is reduced, the integration degree of the chip is further improved, and the preparation cost of the chip is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a preparation method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] HVG MOS (High Voltage Gate OX MOS) is an indispensable device in display driver chips. In addition to the display field, HVG MOS is also commonly used in motor drive and industrial control.

[0003] Then, since the operating voltage of the HVG MOS is large and the voltage resistance requirement is high, the existing HVG MOS has the problem of occupying a large chip area, which reduces the integration of the chip. At the same time, the HVG MOS will also cause serious interference to the low-voltage MOS or medium-voltage MOS in the same chip due to reasons such as electric field coupling, thermal effect, parasitic devices, and electromagnetic interference, so it is necessary to additionally set an isolation structure between the HVG MOS and the low-voltage MOS or medium-voltage MOS, and to increase the spacing between the HVG MOS and the adjacent low-voltage MOS or medium-voltage MOS, thereby increasing the overall area of the chip, further reducing the integration of the chip, and increasing the preparation cost of the chip. Also, the existing HVG MOS needs to additionally set up a kind of mask when forming a gate dielectric layer, thereby further increasing the preparation cost of the chip. SUMMARY

[0004] The present application provides a preparation method of a semiconductor structure and the semiconductor structure to reduce the preparation cost of the chip while reducing the area of the chip.

[0005] According to a first aspect of the present application, a preparation method of a semiconductor structure is provided, comprising: providing a substrate, the substrate comprising a substrate, a first device structure located in the substrate, and a shallow trench isolation structure adjacent to the first device structure; forming a gate layer on the surface of the substrate, the gate layer comprising a first dielectric layer, and a first gate and a second gate located in the first dielectric layer, the first gate being located on the shallow trench isolation structure, and the second gate being located on the first device structure, the first device structure and the second gate constituting a first MOS tube; forming a gate dielectric layer and an active layer on the surface of the gate layer, the active layer covering the surface of the gate dielectric layer on the first gate, and covering the surface of the part of the gate dielectric layer on both sides of the first gate; A first source-drain layer is formed on the surface of the active layer, the first source-drain layer has an opening penetrating along the extending direction of the first gate, and the opening is located on the first gate and exposes the active layer; The first gate, the gate dielectric layer, the active layer and the first source-drain layer constitute a high-voltage gate oxide MOS tube.

[0006] Optionally, the method for forming the active layer comprises: An active material layer is formed on the surface of the gate dielectric layer; A patterned first mask layer is formed on the surface of the active material layer, and the first mask layer comprises an active layer blocking layer and a first etching window region; The active material layer is etched with the first mask layer as a mask until the surface of the gate dielectric layer is exposed, thereby forming the active layer; Before the first mask layer is formed, the method for preparing the semiconductor structure further comprises: A patterned second mask layer is formed on the surface of the active material layer based on a first mask, and the second mask layer at least comprises a first blocking layer and a first doping window region, and the first doping window region and the active layer blocking layer are positionally overlapped; The active material layer is ion implanted with the second mask layer as a mask to form an ohmic contact region on the surface layer of the active material layer.

[0007] Optionally, the method for forming the substrate comprises: A base is provided; A shallow trench isolation structure and a well region adjacent to the shallow trench isolation structure are formed in the base; A first dummy gate is formed on the shallow trench isolation structure, and a second dummy gate is formed on the well region; A patterned third mask layer is formed on the substrate through the first mask, and the third mask layer comprises a second doping window region, a third doping window region and a second blocking layer, the second doping window region is located on the first dummy gate, and the third doping window region is located on the well region; The well region is ion implanted with the third mask layer as a mask to form a second source-drain region in the well region on both sides of the second dummy gate.

[0008] Optionally, while the first source-drain layer is formed, a resistance structure is also formed on the gate dielectric layer; The method for forming the first source-drain layer and the resistance structure comprises: After the active layer is formed, a source-drain material layer is formed on the surface of the active layer and the surface of the gate dielectric layer; forming a patterned fourth mask layer on the surface of the source-drain material layer, the fourth mask layer comprising a first source-drain layer blocking layer, a resistance structure blocking layer and a second etching window region; the first source-drain blocking layer is located on the surface of the active layer, and the first source-drain blocking layer has a patterned opening extending along the extension direction of the first gate, the patterned opening is located above the first gate and exposes the source-drain material layer; the resistance structure blocking layer is located on the source-drain material layer on one side of the first source-drain layer blocking layer; etching the source-drain material layer with the fourth mask layer as a mask to form the first source-drain layer and the resistance structure.

[0009] According to a second aspect of the present application, a semiconductor structure is provided, comprising: a substrate comprising a base, a first device structure located in the base and a shallow trench isolation structure adjacent to the device structure; a gate layer located on the surface of the substrate, the gate layer comprising a first dielectric layer, a first gate and a second gate located in the first dielectric layer, the first gate being located on the shallow trench isolation structure, the second gate being located on the first device structure, the first device structure and the second gate constituting a first MOS transistor; a gate dielectric layer located on the surface of the gate layer; an active layer located on the surface of the gate dielectric layer on the first gate and on the surface of the gate dielectric layer on the part of the first dielectric layer on both sides of the first gate; a first source-drain layer located on the surface of the active layer, the first source-drain layer having an opening extending along the extension direction of the first gate, the opening being located on the first gate and exposing the active layer.

[0010] Optionally, the semiconductor structure further comprises an ohmic contact layer located on the surface of the active layer.

[0011] Optionally, the first device structure comprises: a well region located in the base, and the well region is adjacent to the shallow trench isolation structure, and the second gate is located on the well region; a second source-drain region located in the well region on both sides of the second gate.

[0012] Optionally, the semiconductor structure further comprises a resistance structure located on the surface of the gate dielectric layer on at least one side of the active layer.

[0013] Optionally, the first source-drain layer is also located on the surface of the gate dielectric layer on both sides of the active layer; The semiconductor structure further comprises: a first conductive structure, a second conductive structure and a third conductive structure; the first conductive structure is located on the surface of the first source-drain layer on the gate dielectric layer on both sides of the active layer and on the surface of the first gate electrode; the second conductive structure is located on the surface of the resistance structure; and the third conductive structure is located on the surface of the second gate electrode and the surface of the second source-drain region.

[0014] Optionally, the material of the first source-drain layer and the resistance structure both comprise a titanium nitride layer and a silicon nitride layer which are stacked in sequence.

[0015] The preparation method of the semiconductor structure provided by the application makes full use of the longitudinal space of the chip, forms a gate dielectric layer, an active layer and a first source-drain layer on the shallow trench isolation structure in the substrate in sequence to form a high-voltage gate oxide layer MOS transistor arranged longitudinally, thereby greatly reducing the lateral area of the high-voltage gate oxide layer MOS transistor and improving the integration of the chip on which the high-voltage gate oxide layer MOS transistor is arranged. Meanwhile, since the high-voltage gate oxide layer MOS transistor is located above the shallow trench isolation structure in the substrate and the first MOS transistor formed by the first device structure and the second gate electrode is located in a different horizontal plane, the interference of the high-voltage gate oxide layer MOS transistor on the adjacent first MOS transistor is greatly reduced. Therefore, no isolation structure is needed between the high-voltage gate oxide layer MOS transistor and the adjacent first MOS transistor, and the horizontal distance between the high-voltage gate oxide layer MOS transistor and the adjacent first MOS transistor is greatly reduced, which not only reduces the overall area of the chip and further improves the integration of the chip, but also reduces the preparation cost of the chip.

[0016] Since the preparation of the gate dielectric layer does not need to use a mask, the preparation cost of the chip is further reduced.

[0017] Further, since the second mask layer used to form the ohmic contact region and the third mask layer used to form the second source-drain region of the first MOS transistor are formed by the same mask and have the same structure, one mask is saved in the process of forming the ohmic contact layer, thereby reducing the preparation cost of the chip.

[0018] Further, the etching steps of the first source-drain layer and the resistance structure are simultaneously realized by one fourth mask layer, thereby further reducing the preparation cost of the chip.

[0019] Further, since the material of the resistance structure and the material of the first source-drain layer both comprise titanium nitride and silicon nitride which are stacked in sequence, the resistance structure and the first source-drain layer can share the same material, thereby further reducing the preparation cost of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0021] Figure 1 is a schematic diagram of a cross-sectional structure of an HVG MOS. Figures 2 to 4 is a schematic diagram of a cross-sectional structure of each step in the method for manufacturing a semiconductor structure provided by the present application Figure 1 . Figure 5 is a top view of the second mask layer covering the substrate. Figures 6 to 13 is a schematic diagram of a cross-sectional structure of each step in the method for manufacturing a semiconductor structure provided by the present application Figure 2 . Figure 14 is a top view of the structure shown in Figure 13 . Figures 15 to 21 is a schematic diagram of a cross-sectional structure of each step in the method for manufacturing a semiconductor structure provided by the present application Figure 3 . Figure 22 is a top view of the structure shown in Figure 21 . DETAILED DESCRIPTION

[0022] As described in the background, the existing HVG MOS has the problems of large chip area occupation (because the distance between the source-drain region and the channel is large) and high process cost (because the thickness of the gate oxide layer needs to be divided into zones for oxidation). At the same time, due to the high operating voltage of the HVGMOS, it will cause serious electromagnetic interference to the low-voltage MOS or medium-voltage MOS in the same chip, so it is necessary to additionally set an isolation structure between the HVG MOS and the low-voltage MOS or medium-voltage MOS, or simply increase the distance between the HVG MOS and the low-voltage MOS or medium-voltage MOS, thereby increasing the overall cost of the chip or increasing the area of the chip. The problems of the prior art will be explained and described through a specific embodiment.

[0023] Figure 1 is a schematic diagram of a cross-sectional structure of an HVG MOS.

[0024] Please refer to Figure 1 , the embodiment can include: a substrate 100.

[0025] a high-voltage-resistant gate oxide layer 110 located on the surface of the substrate 100.

[0026] A first gate structure 120 is located on the surface of the high-voltage gate oxide layer 110.

[0027] A source region 130 and a drain region 140 are located in the substrate 100 on both sides of the high-voltage gate oxide layer 110.

[0028] A shallow trench isolation structure 150 is located in the substrate 100 and is located between the source region 130 and the channel 170 and between the drain region 140 and the channel 170 in the horizontal direction to isolate the source and drain regions 140 and the channel 170. The channel 170 is a region of the substrate 100 directly below the high-voltage gate oxide layer 110.

[0029] A drift ion implantation region 160 is located in the substrate 100 and is used to connect the source region 130 and the channel 170 and to connect the drain region 140 and the channel 170.

[0030] The problems of this embodiment are: 1. In order to improve the voltage resistance of the HVG MOS, the shallow trench structure is needed to isolate the source region 130 and the channel 170 and the drain region 140 and the channel 170, respectively, thereby increasing the area of the HVG MOS itself. Since the HVG MOS and the low-voltage MOS or the medium-voltage MOS are arranged in the same substrate 100, in order to reduce the influence of the HVG MOS on the surrounding low-voltage MOS or medium-voltage MOS, an additional mask plate is needed for ion implantation in the isolation region (not shown) between the HVG MOS and the adjacent low-voltage MOS or medium-voltage MOS, and the spacing between the HVG MOS and the adjacent low-voltage MOS or medium-voltage MOS is increased, thereby increasing the area of the chip itself and the preparation cost.

[0031] 2. Since the high-voltage gate oxide layer 110 of the HVG MOS is very thick, for example, the high-voltage gate oxide layer 110 of a conventional low-voltage MOS only needs 1-3 nm, while the high-voltage gate oxide layer 110 of the HVG MOS needs at least 100 nm. Since the HVG MOS is usually arranged in the same substrate 100 as the low-voltage MOS or the medium-voltage MOS, a separate mask plate is needed for high-voltage area oxidation during the formation of the high-voltage gate oxide layer 110 of the HVG MOS. For example, the high-voltage area grows a very thick oxide layer by dry oxygen oxidation, while the low-voltage area is shielded by a mask to be processed by a thinner oxidation process later. Therefore, the preparation of the high-voltage gate oxide layer 110 of the HVG MOS further increases the preparation cost of the chip.

[0032] Therefore, the technical scheme of the present application provides a new semiconductor structure and a corresponding preparation method, so as to sequentially form a gate medium layer, an active layer and a first source-drain layer on a shallow trench isolation structure of a substrate, so as to form a high-voltage gate oxide layer MOS tube arranged longitudinally, which not only reduces the lateral area of the high-voltage gate oxide layer MOS tube, but also reduces the horizontal distance between the high-voltage gate oxide layer MOS tube and an adjacent conventional MOS tube due to the absence of an isolation structure, and reduces the preparation cost of the chip. Since a mask is not required for the gate medium layer in the preparation process of the high-voltage gate oxide layer MOS tube, the preparation cost of the chip is further reduced.

[0033] The technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0034] The terms "first", "second", "third", "fourth" and the like in the specification and claims of the present application and the above-described drawings (if any) are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] The technical scheme of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0036] In addition to Figure 5 , Figure 14 , Figures 2 to 21 are cross-sectional structure schematic diagrams of each step of the preparation method of the semiconductor structure provided by the present application.

[0037] Please refer to Figure 2 , a substrate is provided, which includes a substrate 200 and a shallow trench isolation structure 201 in the substrate 200.

[0038] In the embodiment, the material of the substrate 200 can be monocrystalline silicon. In other embodiments, the substrate can also be a substrate of other materials, which is not limited in the present application.

[0039] In the embodiment, a shallow trench isolation structure position can be defined on the substrate 200 by a mask, and the substrate 200 is etched to form a shallow trench, and then the shallow trench is filled with an isolation material layer to form the shallow trench isolation structure 201. The isolation material layer can be silicon oxide, silicon dioxide, etc.

[0040] Please refer to Figure 3 The well region 205 is formed in the substrate 200.

[0041] Specifically, the shallow trench isolation structure 201 is located at least one side of the well region 205.

[0042] In the embodiment, the well region 205 in the substrate 200 can be formed by ion implantation on the substrate 200.

[0043] Further, the type of the well region 205 can be different according to the type of the MOS tube. If it is an NMOS tube, the well region 205 is a P well. If it is a PMOS tube, the well region 205 is an N well.

[0044] It should be noted that, for the sake of subsequent description and understanding, Figure 3 Only one well region 205 is drawn. However, in actual application, there are multiple NMOS tubes or PMOS tubes in a chip, that is, there are multiple adjacent well regions 205 in the substrate 200, and the setting of the well region 205 is related to the design of the chip, which is not limited here.

[0045] In the embodiment, after the well region 205 is prepared, a gate layer is formed on the surface of the well region 205 and the surface of the shallow trench isolation structure 201, and a second source-drain region 204 is formed in the well region 205. The gate layer can include a first dielectric layer 207, and a first gate 217 and a second gate 218 in the first dielectric layer 207. The specific formation process of the gate layer and the second source-drain region 204 can be as shown in Figures 4 to 10 .

[0046] Please refer to Figure 4 The first dummy gate 202 is formed on the shallow trench isolation structure 201, and the second dummy gate 203 is formed on the well region 205.

[0047] Specifically, the first dummy gate 202 and the second dummy gate 203 are both polycrystalline silicon structures, and the first dummy gate 202 and the second dummy gate 203 are formed simultaneously in the same process.

[0048] Figure 5 A top view of the second mask layer covering the substrate.

[0049] Please refer to Figure 5 After forming the first dummy gate 202 and the second dummy gate 203, a third mask layer 216 is formed on the substrate by a first mask, the third mask layer 216 can include a second doping window area 2161, a third doping window area 2162 and a second blocking layer.

[0050] The second doping window area 2161 is located on the first dummy gate 202 and exposes part of the first dummy gate 202 and the shallow trench isolation structure 201 on both sides of the first dummy gate 202.

[0051] Specifically, the width of the second doping window area 2161 along the first direction BB` is less than the width of the first dummy gate 202, and the width of the second doping window area 2161 along the second direction AA` is greater than the width of the first dummy gate 202.

[0052] It should be noted that in Figure 5 The part of the first dummy gate 202 blocked by the second blocking layer is represented by a dashed line in the above.

[0053] In this embodiment, the third doping window area 2162 is located on the well region 205, and the third doping window area 2162 exposes the second dummy gate 203 and part of the well region 205 on both sides of the second dummy gate 203 (such as part of the well region 205 on both sides of the second dummy gate 203 along the AA` direction).

[0054] Specifically, the second direction AA` is the extension direction of the first dummy gate 202, and the first direction BB` and the second direction AA` are perpendicular to each other.

[0055] Please refer to Figure 6 The well region 205 in the third doping window area 2162 is ion implanted with the third mask layer 216 as a mask, so as to form a second source-drain region 204 in the well region 205 on both sides of the second dummy gate 203.

[0056] Specifically, although the shallow trench isolation structure 201 in the second doping window area 2161 will also be ion implanted (not shown in the figure), since the shallow trench isolation structure 201 only plays an isolating role, ion implantation on the shallow trench isolation structure 201 will not affect the overall performance of the device.

[0057] Further, ion implantation is different according to the type of MOS tube. If it is an NMOS tube, N-type ions such as phosphorus or arsenic are doped. If it is a PMOS tube, P-type ions such as boron or BF2 are doped.

[0058] In the embodiment, the well region 205 and the second source-drain region 204 form a first device structure.

[0059] Referring to Figure 7 After forming the second source-drain region 204, a conductive structure etching stop layer 206 is formed on the sidewall of the first dummy gate 202 and the sidewall of the second dummy gate 203, and on the surface of the substrate 200, the surface of the shallow trench isolation structure 201 and the surface of the second source-drain region 204. Specifically, the process of forming the conductive structure etching stop layer 206 is a deposition process.

[0060] Specifically, the conductive structure etching stop layer 206 is used as an etching stop layer for subsequent preparation of a conductive structure on the surface of the second source-drain region 204, so as to prevent damage to the second source-drain region 204. The material of the conductive structure etching stop layer 206 can include silicon nitride.

[0061] Referring to Figure 8 A first dielectric layer 207 is deposited on the surface of the conductive structure etching stop layer 206, and the first dielectric layer 207 fills the space between the first dummy gate 202 and the second dummy gate 203.

[0062] Specifically, the material of the first dielectric layer 207 can include silicon dioxide, and the deposition process of the first dielectric layer 207 includes at least chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or thermal oxidation process, etc., which is not limited herein.

[0063] In the embodiment, the top surface of the first dielectric layer 207 is flush with the top surface of the first dummy gate 202 and the second dummy gate 203.

[0064] Referring to Figure 9 After forming the first dielectric layer 207, the first dummy gate 202 and the second dummy gate 203 are etched to form a gate recess.

[0065] Referring to Figure 10 After forming the gate recess, a metal gate material layer is deposited to fill the gate recess.

[0066] In the embodiment, after depositing the metal gate material layer, the excess metal gate material layer is also ground to remove the excess metal gate material layer, so that the metal gate material layer and the first dielectric layer 207 are at the same level, to form a first gate 217 on the shallow trench isolation structure 201 and a second gate 218 on the first device structure.

[0067] Specifically, the material of the metal gate material layer can include single metal, such as titanium, tungsten, aluminum, etc.; metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, etc.; metal alloy, such as titanium-aluminum alloy, without limitation.

[0068] The well region 205, the second source-drain region 204, and the second gate 218 constitute a first MOS tube in the chip. The first MOS tube can be a MOS tube of a low-voltage device or a medium-voltage device in the chip.

[0069] After the low-voltage device or the medium-voltage device in the chip is prepared, a high-voltage gate oxide layer MOS tube in the chip will be prepared. Therefore, the preparation of the high-voltage gate oxide layer MOS tube will be described in detail below.

[0070] Please refer to Figure 11 After the gate layer is formed, a gate dielectric layer 208 is formed on the surface of the gate layer.

[0071] Specifically, since the high-voltage gate oxide layer MOS tube needs to withstand high voltage, the gate dielectric layer 208 needs to select a material with high dielectric constant, such as silicon nitride. Of course, other materials with high dielectric constant are also within the protection scope of the embodiment.

[0072] Further, an active layer 229 is formed on the surface of the gate dielectric layer 208, and the active layer 229 is located on the first gate 217 and part of the first dielectric layer 207 on both sides of the first gate 217. The specific formation process of the active layer can be as shown in Figures 12 to 16 .

[0073] Please refer to Figure 12 The active material layer 209 is deposited on the surface of the gate dielectric layer 208.

[0074] Specifically, the material of the active material layer 209 can be A-Si:H (doped hydrogen single crystal silicon).

[0075] Figure 14 For Figure 13 the top view of the structure is shown.

[0076] Please refer to Figure 13 and Figure 14 The second mask layer 316 is formed again on the surface of the active material layer 209 through the first photomask, and the second mask layer 316 can include the first doped window region 3161, the fourth doped window region 3162, and the first barrier layer.

[0077] Since the third mask layer 216 and the second mask layer 316 are formed by the first mask, the first doped window area 3161, the fourth doped window area 3162 and the first barrier layer in the second mask layer 316 correspond to the second doped window area 2161, the third doped window area 2162 and the second barrier layer in the third mask layer 216 respectively.

[0078] In the embodiment, the first doped window area 3161 is located on the first gate 217, and the width of the first doped window area 3161 along the first direction BB' is less than the width of the first gate 217, and the width of the first doped window area 3161 along the second direction AA' is greater than the width of the first gate 217.

[0079] It should be noted that, in the embodiment, the first gate 217 is covered by the first barrier layer in the fourth doped window area 3162. Figure 14 The part of the first gate 217 covered by the first barrier layer is represented by a dashed line.

[0080] Please refer to Figure 15 The active material layer 209 in the first doped window area 3161 and the fourth doped window area 3162 is subjected to ion implantation by taking the second mask layer 316 as a mask layer, so as to form an ohmic contact layer 211 of the high-voltage gate oxide MOS tube in the first doped window area 3161.

[0081] Specifically, the ion type of the ion implantation is related to the type of the high-voltage gate oxide MOS tube, and the doping ions are the same as the ion implantation of the second source-drain area 204, which will not be described here.

[0082] Further, the thickness of the active material layer 209 is usually 400-500 angstroms, and the thickness of the ohmic contact layer 211 is only 100-200 angstroms, so the ohmic contact layer 211 will not affect the structure below the active material layer 209.

[0083] It should be noted that the ion implantation area formed in the fourth doped window area 3162 does not actually affect the high-voltage gate oxide MOS tube, so it cannot be called the ohmic contact layer of the high-voltage gate oxide MOS tube.

[0084] In the embodiment, please refer to Figure 16 After the ohmic contact layer 211 is formed, the second mask layer can also be removed.

[0085] Further, a patterned first mask layer is formed on the surface of the active material layer 209, and the patterned first mask layer can include an active layer blocking layer and a first etching window region, and the active layer blocking layer and the first doping window region 3161 are located in the same position. The first etching window region of the first mask layer exposes the active material layer 209 outside the preset active layer 229.

[0086] Please refer to Figure 17 The first mask layer is used as a mask to etch the active material layer 209 until the surface of the gate dielectric layer 208 is exposed, and the remaining active material layer 209 forms the active layer 229.

[0087] In the above embodiment, the second mask layer and the third mask layer are formed by the same mask, that is, the patterns on the second mask layer and the third mask layer are the same, and the doping regions are also the same when ion implantation doping is performed based on the second mask layer and the third mask layer. However, since the ion implantation for the second source / drain region 204 based on the third mask layer is simultaneously performed on the shallow trench isolation structure 201, the shallow trench isolation structure 201 only serves as an isolation function, and therefore the ion implantation does not affect the overall performance of the device. When ion implantation is performed on the ohmic contact layer 211 based on the second mask layer, the implantation region in the fourth doping window region is simultaneously implanted and removed by etching through the first mask layer, that is, the active material layer 209 outside the active layer blocking layer is etched, and therefore the doped region of the fourth doping window region does not affect the high-voltage gate oxide MOS tube. Therefore, the second mask layer forming the ohmic contact region and the third mask layer forming the second source / drain region in the first MOS tube are formed by the same mask and have the same structure, which saves one mask in the process of forming the ohmic contact layer, thereby reducing the preparation cost of the chip.

[0088] In this embodiment, after the active layer is formed, a first source / drain layer 212 is also formed on the surface of the active layer 229, and the first source / drain layer 212 has an opening extending along the extension direction of the first gate 217, and the opening is located on the first gate 217 and exposes the active layer 229. As shown in Figures 18 to 19

[0089] Please refer to Figure 18 After the active layer 229 is formed, a source / drain material layer is formed on the surface of the active layer 229 and the surface of the gate dielectric layer 208.

[0090] Specifically, the source / drain material layer can include a titanium nitride layer 2121 and a silicon nitride layer 2122 stacked in sequence.

[0091] ​In the embodiment, a patterned fourth mask layer is formed on the surface of the source-drain material layer, and the patterned fourth mask layer can include a first source-drain layer blocking layer, a resistance structure blocking layer, and a second etching window region.

[0092] The first source-drain blocking layer is located on the surface of the active layer 229, and the first source-drain blocking layer shields part of the active layer and the regions on both sides of the active layer, so that the shielded active layer and the regions on both sides of the active layer are not etched. In addition, the first source-drain blocking layer has an opening extending along the extension direction of the first gate 217, and the opening is located above the first gate 217.

[0093] In the embodiment, the resistance structure blocking layer is located between the first gate and the second gate in the direction from the first gate to the second gate. The resistance structure blocking layer is used to define the position of the resistance structure formed subsequently.

[0094] Please refer to Figure 19 The source-drain material layer is etched with the fourth mask layer as a mask to reserve the source-drain material layer shielded by the first source-drain layer blocking layer and the resistance structure blocking layer, thereby forming the first source-drain layer 212 and the resistance structure 213.

[0095] In the embodiment, the first source-drain layer 212 and the resistance structure 213 are made of the same material, and the mask for the original resistance structure 213 is improved to additionally increase the first source-drain blocking layer on the basis of the original resistance blocking layer. Therefore, the first source-drain layer 212 and the resistance structure 213 can be formed simultaneously by depositing a titanium nitride layer 2121 and a silicon nitride layer 2122 only once and etching with the same mask layer once, thereby further reducing the cost of chip preparation.

[0096] Please refer to Figure 20 After the first source-drain layer 212 and the resistance structure 213 are formed, a second dielectric layer 214 is deposited. The second dielectric layer 214 covers the first source-drain layer 212, the resistance structure 213, and covers the exposed gate dielectric layer 208 and the exposed ohmic contact layer 211.

[0097] Specifically, the materials of the first dielectric layer 207 and the second dielectric layer 214 can be the same, which will not be described here.

[0098] Please refer to Figure 21 After the second dielectric layer 214 is formed, a first conductive structure 219, a second conductive structure 220, and a third conductive structure 221 are formed.

[0099] The first conductive structure 219 is located in the second dielectric layer 214 on the active layer and contacts the surface of the active layer, the second conductive structure 220 is located in the second dielectric layer 214 on the resistance structure 213 and contacts the surface of the resistance structure 213, and the third conductive structure 221 penetrates the second dielectric layer 214, the gate dielectric layer 208, the first dielectric layer 207 and the conductive structure etching stop layer 206 on the second source-drain region 204 and contacts the surface of the second source-drain region 204.

[0100] In one embodiment, the first source-drain layer 212 includes a first structure a1 on the surface of the active layer 229, a second structure a2 on part of the surface of the gate dielectric layer 208 and a third structure a3 on the sidewall of the active layer 229, and the first structure a1, the second structure a2 and the third structure a3 are integrated. The first conductive structure 219 is located on the surface of the second structure a2 and on the surface of the first gate 217 extending beyond the active layer 229 along the extension direction of the first gate 217.

[0101] Further, the first conductive structure 219, the second conductive structure 220 and the third conductive structure 221 are prepared in the same process.

[0102] In one embodiment, since titanium nitride is hard and not easy to etch, when the first conductive structure 219 and the second conductive structure 220 are formed, etching can be stopped on the surface of the titanium nitride layer of the active layer 229 and the resistance structure 213, i.e. the second dielectric layer 214 and the silicon nitride layer on the titanium nitride layer are etched away, so that the first conductive structure 219 contacts the surface of the titanium nitride layer in the second structure a2 of the active layer 229, and the second conductive structure 220 contacts the surface of the titanium nitride layer in the resistance structure 213.

[0103] It should be noted that the conductive structure of the gate of the MOS transistor is usually directly arranged on the middle region of the surface of the gate, but since the high-voltage gate oxide layer in the present embodiment is arranged in the opposite direction to the conventional MOS transistor in the longitudinal structure layout, part of the first gate 217 is blocked by the active layer 229, so that the first conductive structure 219 on the first gate 217 can only be arranged on the surface of the first gate 217 extending beyond the active layer 229 along the extension direction of the first gate 217. As shown in Figure 22 , Figure 22 , Figure 21 the top view of the structure.

[0104] In summary, the preparation method of the semiconductor structure provided by the embodiment of the present application makes full use of the longitudinal space of the chip, sequentially forms a gate dielectric layer, an active layer and a first source-drain layer on the shallow trench isolation structure in the substrate to form a high-voltage gate oxide layer MOS tube arranged longitudinally, thereby greatly reducing the lateral area of the high-voltage gate oxide layer MOS tube and improving the integration of the chip in which the high-voltage gate oxide layer MOS tube is located. Meanwhile, since the high-voltage gate oxide layer MOS tube is located above the shallow trench isolation structure in the substrate and is at a different horizontal plane from the first MOS tube located in the substrate in the chip, the interference of the high-voltage gate oxide layer MOS tube on the adjacent first MOS tube is greatly reduced. Therefore, no isolation structure is needed between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube, and the horizontal distance between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube is greatly reduced, which not only reduces the overall area of the chip and further improves the integration of the chip, but also reduces the preparation cost of the chip.

[0105] In addition, the preparation of the gate dielectric layer of the present application does not need to set a photomask, thereby further reducing the preparation cost of the chip.

[0106] Further, the third mask layer 216 made of the first photomask is used for ion implantation twice, thereby reducing the preparation cost of the chip.

[0107] Further, the first source-drain layer and the resistance structure of the embodiment are made of the same material, and the first source-drain barrier layer is additionally added on the basis of the resistance barrier layer by improving the photomask of the original resistance structure, so that the first source-drain layer and the resistance structure can be formed at the same time by depositing titanium nitride and silicon nitride once and etching once using the same mask layer, thereby further reducing the preparation cost of the chip.

[0108] Please refer to Figure 21 and Figure 22 , the embodiment also provides a new semiconductor structure, which specifically comprises: a substrate, the substrate comprising a base 200 and a first device structure and a shallow trench isolation structure 201 located in the base 200. The first device structure and the shallow trench isolation structure 201 are arranged adjacent to each other.

[0109] a gate layer, the gate layer being located on the surface of the substrate, the gate layer comprising a first dielectric layer 207, and a first gate 217 and a second gate 218 located in the first dielectric layer 207. The first gate 217 is located on the shallow trench isolation structure 201, and the second gate 218 is located on the first device structure, and the first device structure and the second gate 218 form a first MOS tube. The first MOS tube can be a medium-voltage device or a low-voltage device MOS tube.

[0110] The gate dielectric layer 208 is located on the surface of the gate layer.

[0111] The active layer 229 is located on the surface of the gate dielectric layer 208 on the first gate 217, and the active layer 229 is also located on the surface of the gate dielectric layer 208 on the first dielectric layer 207 on both sides of the first gate 217.

[0112] A first source / drain layer 212 is located on the surface of the active layer 229. The first source / drain layer 212 has an opening extending along the extension direction of the first gate 217. The opening is located on the first gate 217 and exposes the active layer 229.

[0113] Specifically, the first source / drain layer 212 may include a first structure a1 located on the surface of the active layer 229, a second structure a2 located on a portion of the surface of the gate dielectric layer 208, and a third structure a3 located on the sidewall of the active layer 229, wherein the first structure a1, the second structure a2, and the third structure a3 are a whole.

[0114] Ohmic contact layer 211, which is located in the surface area of ​​active layer 229.

[0115] The substrate 200, the first gate 217, the gate dielectric layer 208, the active layer 229, the first source / drain layer 212, and the ohmic contact layer 211 constitute a high-voltage gate oxide MOS transistor.

[0116] In this embodiment, the semiconductor structure may further include a resistor structure 213, which is located on the surface of the gate dielectric layer 208 on at least one side of the active layer 229.

[0117] exist Figure 21 In the embodiment shown, along the direction from the first gate 217 to the second gate 218, the resistor structure 213 is located on the surface of the gate dielectric layer 208 between the first gate 217 and the second gate 218.

[0118] In this embodiment, the first device structure may include a well region 205 and a second source / drain region 204.

[0119] Specifically, the well region 205 is located within the substrate 200, the well region 205 is adjacent to the shallow trench isolation structure 201, and the shallow trench isolation structure 201 is located on at least one side of the well region 205.

[0120] In this embodiment, the second gate 218 is located within the first dielectric layer 207 on the well region 205.

[0121] In the embodiment, the second source-drain region 204 is located in the well region 205 on both sides of the second gate 218.

[0122] The second gate 218, the well region 205 and the second source-drain region 204 form a first MOS transistor, i.e. a low-voltage MOS transistor or a medium-voltage MOS transistor.

[0123] It should be noted that the embodiment only illustrates one high-voltage gate oxide MOS transistor and one first MOS transistor in the chip. In actual applications, there are usually multiple high-voltage gate oxide MOS transistors and multiple first MOS transistors in the chip. Therefore, the embodiment can effectively reduce the interference of the high-voltage gate oxide MOS transistor on the adjacent first MOS transistor, avoid the setting of the isolation interference structure and reduce the horizontal distance between the high-voltage gate oxide MOS transistor and the low-voltage MOS transistor or the medium-voltage MOS transistor, thereby greatly reducing the overall area of the chip and reducing the manufacturing cost of the chip. For example, the horizontal distance between the high-voltage gate oxide MOS transistor and the adjacent first MOS transistor in the prior art is at least set to be more than 4 microns, while the horizontal distance between the high-voltage gate oxide MOS transistor and the adjacent first MOS transistor in the embodiment can be controlled to be between 1 micron and 2 microns, or even lower. The setting of the isolation interference structure requires the setting of an additional photo mask and the additional ion implantation, thereby increasing the manufacturing cost of the chip.

[0124] Meanwhile, since the high-voltage gate oxide MOS transistor in the embodiment does not need to set a drift ion implantation region to connect the channel and the first source-drain region, and does not need to additionally set a photo mask for the gate dielectric layer 208, thereby saving three photo masks, and further reducing the manufacturing cost of the chip.

[0125] Please continue to refer to Figure 21 and Figure 22 The semiconductor structure can further include a first conductive structure 219, a second conductive structure 220 and a third conductive structure 221. The first conductive structure 219 is located on the surface of the second structure a2 and on the surface of the first gate 217 extending along the extension direction of the first gate 217 and beyond the active layer 229. The second conductive structure 220 is located on the surface of the resistance structure 213. The third conductive structure 221 is located on the surface of the second gate 218 and the surface of the second source-drain region 204.

[0126] It should be noted that, in order to make the first conductive structure 219 located along the extension direction of the first gate 217 and beyond the surface of the first gate 217 of the active layer 229, it is necessary to ensure that the spacing between the first conductive structure 219 and the boundary of the active layer 229 and the spacing between the first conductive structure 219 and the boundary of the first gate 217 both conform to the minimum safety distance in the art. For example, in a 55nm process node, the minimum safety distance of the high-voltage gate oxide MOS tube is 0.1 microns.

[0127] In one of the embodiments, the semiconductor structure can further include a second dielectric layer 214.

[0128] In the embodiment, the second dielectric layer 214 covers the first source-drain layer 212, the resistance structure 213, and covers the exposed gate dielectric layer 208 and the exposed ohmic contact layer 211.

[0129] In the embodiment, the first conductive structure 219 is located in the second dielectric layer 214 on the active layer and is in contact with the surface of the active layer, the second conductive structure 220 is located in the second dielectric layer 214 on the resistance structure 213 and is in contact with the surface of the resistance structure 213, and the third conductive structure 221 penetrates through the second dielectric layer 214, the gate dielectric layer 208, the first dielectric layer 207 and the conductive structure etching stop layer 206 on the second source-drain region 204 and is in contact with the surface of the second source-drain region 204.

[0130] In one of the embodiments, the first conductive structure 219 is in contact with the surface of the titanium nitride layer in the first source-drain layer 212, and the second conductive structure 220 is in contact with the surface of the titanium nitride layer in the resistance structure 213.

[0131] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The application relates to a semiconductor structure and a preparation method thereof. The application provides a substrate, which comprises a base, a first device structure in the base, and a shallow trench isolation structure adjacent to the first device structure; A gate layer is formed on the surface of the substrate, and the gate layer comprises a first dielectric layer, a first gate and a second gate in the first dielectric layer, the first gate is on the shallow trench isolation structure, the second gate is on the first device structure, the first device structure and the second gate constitute a first MOS tube; A gate dielectric layer and an active layer are formed on the surface of the gate layer, the active layer covers the surface of the gate dielectric layer on the first gate, and covers the surface of part of the gate dielectric layer on both sides of the first gate; A first source-drain layer is formed on the surface of the active layer, and the first source-drain layer has an opening penetrating along the extension direction of the first gate, the opening is on the first gate and exposes the active layer; The first gate, the gate dielectric layer, the active layer and the first source-drain layer constitute a high-voltage gate oxide MOS tube.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method for forming the active layer comprises: An active material layer is formed on the surface of the gate dielectric layer; A patterned first mask layer is formed on the surface of the active material layer, and the first mask layer comprises an active layer blocking layer and a first etching window area; The active material layer is etched with the first mask layer as a mask until the surface of the gate dielectric layer is exposed, thereby forming an active layer; Before forming the first mask layer, the preparation method of the semiconductor structure further comprises: A patterned second mask layer is formed on the surface of the active material layer based on a first mask, and the second mask layer at least comprises a first blocking layer and a first doping window area, the first doping window area and the active layer blocking layer are positionally overlapped; An ion implantation is performed on the active material layer with the second mask layer as a mask to form an ohmic contact area on the surface layer of the active material layer.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The method for forming the substrate comprises: A base is provided; A shallow trench isolation structure and a well region adjacent to the shallow trench isolation structure are formed in the base; A first dummy gate is formed on the shallow trench isolation structure, and a second dummy gate is formed on the well region; A patterned third mask layer is formed on the substrate through the first mask, and the third mask layer comprises a second doping window area, a third doping window area and a second blocking layer, the second doping window area is on the first dummy gate, and the third doping window area is on the well region; An ion implantation is performed on the well region with the third mask layer as a mask to form a second source-drain region in the well region on both sides of the second dummy gate.

4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: An electric resistance structure is formed on the gate dielectric layer at the same time when the first source-drain layer is formed; The method for forming the first source-drain layer and the electric resistance structure comprises: A source-drain material layer is formed on the surface of the active layer and the surface of the gate dielectric layer after the active layer is formed; forming a patterned fourth mask layer on the surface of the source-drain material layer, the fourth mask layer comprising a first source-drain layer blocking layer, a resistance structure blocking layer and a second etching window region; the first source-drain blocking layer is located on the surface of the active layer, and the first source-drain blocking layer has a patterned opening extending along the extension direction of the first gate, the patterned opening is located above the first gate and exposes the source-drain material layer; the resistance structure blocking layer is located on the source-drain material layer on one side of the first source-drain layer blocking layer; using the fourth mask layer as a mask, etching the source-drain material layer to form the first source-drain layer and the resistance structure.

5. A semiconductor structure, characterized by Comprise: a substrate comprising a base, a first device structure located in the base, and a shallow trench isolation structure adjacent to the first device structure; a gate layer located on the surface of the substrate, the gate layer comprising a first dielectric layer, and a first gate and a second gate located in the first dielectric layer, the first gate being located on the shallow trench isolation structure, the second gate being located on the first device structure, the first device structure and the second gate forming a first MOS tube; a gate dielectric layer located on the surface of the gate layer; an active layer located on the surface of the gate dielectric layer on the first gate, and on the surface of the gate dielectric layer on part of the first dielectric layer on both sides of the first gate; a first source-drain layer located on the surface of the active layer, the first source-drain layer having an opening extending along the extension direction of the first gate, the opening being located on the first gate and exposing the active layer.

6. The semiconductor structure of claim 5, wherein, The semiconductor structure further comprises: an ohmic contact layer located on the surface of the active layer.

7. The semiconductor structure of claim 5, wherein, The first device structure comprises: a well region located in the base, and the well region is adjacent to the shallow trench isolation structure, and the second gate is located on the well region; a second source-drain region located in the well region on both sides of the second gate.

8. The semiconductor structure of claim 7, wherein, The semiconductor structure further comprises: a resistance structure located on the surface of the gate dielectric layer on at least one side of the active layer.

9. The semiconductor structure of claim 8, wherein, The first source-drain layer is also located on the surface of the gate dielectric layer on both sides of the active layer; The semiconductor structure further comprises: a first conductive structure, a second conductive structure and a third conductive structure; the first conductive structure is located on the surface of the first source-drain layer on the gate dielectric layer on both sides of the active layer, and on the surface of the first gate; the second conductive structure is located on the surface of the resistance structure; the third conductive structure is located on the surface of the second gate and the surface of the second source-drain region.

10. The semiconductor structure of claim 5, wherein, The material of the first source-drain layer and the resistance structure both comprise a titanium nitride layer and a silicon nitride layer stacked in sequence.

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