Method for manufacturing three-dimensional dynamic random access memory array structure

Abstract

The invention provides a method for manufacturing a three-dimensional DRAM (Dynamic Random Access Memory) array structure. The method comprises the steps that a plurality of stacked sub-arrays and a plurality of second isolation layers are sequentially formed on a circuit substrate, the step of forming the stacked sub-arrays comprises the substeps that first isolation layers and stacked layers are alternately stacked, and each stacked layer comprises a first conductive layer, a sacrificial layer and a second conductive layer; bit line holes penetrating through the first isolation layer and the lamination layer are formed, and the area of each bit line hole in the lamination layer is larger than that in the first isolation layer; forming a gate dielectric layer, a semiconductor material layer and an isolation medium in each bit line hole; forming a hole penetrating through the isolation medium, and filling the hole with a first conductive material; forming a common electrode groove which extends along the first horizontal direction and penetrates through the first isolation layer and the lamination layer; removing the sacrificial layer and a part of gate dielectric layer corresponding to the sacrificial layer in the common electrode groove; and conformally forming a capacitor dielectric layer on the inner surface of each common electrode groove, and filling the residual space of the common electrode groove with a second conductive material.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure. Background Technology

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a selection transistor for selection and a storage capacitor for storing charge (1T1C structure). In DRAM cell structures using conventional planar horizontal transistors, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the source, gate, and drain of the transistor are arranged horizontally parallel to the substrate surface. Because the source, gate, and drain each occupy an independent area in the horizontal direction, the miniaturization of DRAM cell circuit structures is limited by gate length and contact size, failing to meet the demands of continuous miniaturization of DRAM devices, thus restricting further increases in the integration density and bandwidth of DRAM devices.

[0004] Therefore, vertical DRAM cell structures have been proposed in recent years, in which the source, gate, and drain of transistors are arranged vertically perpendicular to the substrate surface, requiring no additional area and facilitating the miniaturization of DRAM array structures. Furthermore, by vertically stacking multiple layers of DRAM cells to form a three-dimensional DRAM array, memory integration density can be further improved.

[0005] DRAM manufacturing is a highly competitive industry. The industry continuously needs to reduce the size of individual cells and increase memory cell density, thereby allowing a single memory chip to hold more memory.

[0006] The information disclosed in this background section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this disclosure proposes a novel method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure.

[0008] According to one aspect of this disclosure, a method for manufacturing a three-dimensional DRAM array structure is provided, comprising: sequentially forming a plurality of stacked subarrays and a plurality of second isolation layers in a vertical direction on a circuit substrate, the plurality of stacked subarrays being separated by the plurality of second isolation layers, wherein forming each of the plurality of stacked subarrays comprises: alternately stacking a plurality of first isolation layers and a plurality of stacks in a vertical direction, each of the plurality of stacks comprising a first conductive layer, a sacrificial layer, and a second conductive layer; forming a plurality of bit line vias penetrating the plurality of first isolation layers and the plurality of stacks and extending to the circuit substrate, the bit line vias being arranged in an array, wherein the area of ​​each bit line via in the stack is larger than the area of ​​the bit line via in the first isolation layer; conformally forming a gate dielectric layer on the inner surface of each bit line via, and conformally forming a semiconductor material layer on the inner surface of the gate dielectric layer. The remaining space of the bit line via is filled with an isolation medium; a hole is formed through the isolation medium and filled with a first conductive material, wherein the portion of the first conductive material corresponding to the stack is separated from the semiconductor material layer by the isolation medium, and the portion of the first conductive material corresponding to the first isolation layer is in direct contact with the semiconductor material layer; multiple common electrode trenches are formed at locations where no bit line vias are provided, extending along a first horizontal direction and penetrating multiple first isolation layers and multiple stacks; a sacrificial layer and a portion of the gate dielectric layer corresponding to the sacrificial layer are removed from the common electrode trenches; and a capacitor dielectric layer is conformally formed on the inner surface of each of the multiple common electrode trenches, and the remaining space of the common electrode trench is filled with a second conductive material, wherein the first conductive materials in the corresponding bit line vias in the multiple stacked subarrays are electrically connected to each other.

[0009] According to another aspect of this disclosure, a method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure is provided, comprising: sequentially forming a plurality of stacked subarrays and a plurality of second isolation layers in a vertical direction on a circuit substrate, wherein the plurality of stacked subarrays are spaced apart from each other by the plurality of second isolation layers, wherein forming each of the plurality of stacked subarrays comprises: alternately stacking a plurality of first isolation layers and a plurality of stacks in a vertical direction, each of the plurality of stacks comprising a first conductive layer, a sacrificial layer and a second conductive layer; forming a plurality of bit line vias penetrating the plurality of first isolation layers and the plurality of stacks and extending to the circuit substrate, arranged in an array, wherein the area of ​​each bit line via in the stack is larger than the area of ​​the bit line via in the first isolation layer; conformally forming a gate dielectric layer on the inner surface of each bit line via, and conformally forming a semiconductor material layer on the inner surface of the gate dielectric layer and The remaining space of the bit line via is filled with an isolation medium; a hole is formed through the isolation medium and filled with a first conductive material, wherein the portion of the first conductive material corresponding to the stack is separated from the semiconductor material layer by the isolation medium, and the portion of the first conductive material corresponding to the first isolation layer is in direct contact with the semiconductor material layer; a plurality of common electrode trenches extending along a first horizontal direction and penetrating a plurality of stacked subarrays are formed at locations where no bit line vias are provided; a sacrificial layer and a portion of the gate dielectric layer corresponding to the sacrificial layer in each stack of the plurality of stacked subarrays are removed in the common electrode trenches; and a capacitor dielectric layer is conformally formed on the inner surface of each of the plurality of common electrode trenches, and the remaining space of the common electrode trench is filled with a second conductive material, wherein the first conductive material in the corresponding bit line vias of the plurality of stacked subarrays is electrically connected to each other.

[0010] The DRAM cell structure constituting the DRAM array structure according to this disclosure includes two gate-around transistors and a storage capacitor arranged in a vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-around transistors are formed from the same semiconductor material layer, thus having advantages such as simple structure and good switching performance. In particular, this cell structure solves the connection problem between the source / drain of the transistors and the inner electrode of the storage capacitor by utilizing a vertical structure, making it suitable for three-dimensional vertical integration of multilayer cells. Furthermore, the DRAM array structure according to this disclosure can be stacked on a circuit board including multiple circuits, thus enabling system-level three-dimensional vertical integration, thereby greatly reducing the area overhead of the circuit system.

[0011] The method for manufacturing a three-dimensional DRAM array structure according to this disclosure can achieve three-dimensional vertical integration by stacking multiple DRAM cells, thereby increasing integration density. The vertical structure of the method is suitable for the one-time formation of multiple cells, eliminating the need for multiple epitaxial processes and fabrication processes, resulting in low manufacturing costs. In particular, the method can further improve integration density and storage capacity by sequentially stacking multiple stacked subarrays in the vertical direction.

[0012] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further illustration of the claimed disclosure. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the specification, serve to explain the inventive concept.

[0014] Figure 1 This is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0015] Figure 2 This is a perspective view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0016] Figure 3 This is a top view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0017] Figure 4 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line AA'.

[0018] Figure 5 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken from line BB'.

[0019] Figure 6 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line CC'.

[0020] Figure 7 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line DD'.

[0021] Figure 8 This is a top view showing a DRAM cell structure according to another embodiment of the present disclosure.

[0022] Figure 9 It shows along Figure 8 The image shows a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken by line AA'.

[0023] Figure 10 It shows along Figure 8 The image shows a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken from line BB'.

[0024] Figure 11 It shows along Figure 9 The image shows a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken by line CC'.

[0025] Figure 12 It shows along Figure 9 The image shows a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken by line DD'.

[0026] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure formed by the DRAM cell structure shown is shown.

[0027] Figure 14 It is shown Figure 13 The diagram shows an equivalent circuit diagram of the DRAM cell structure in the first row of a DRAM array structure according to an embodiment of the present disclosure.

[0028] Figure 15 It is shown Figure 13 The diagram shows a schematic perspective view of the first row of DRAM cells in the first layer of a DRAM array structure according to an embodiment of the present disclosure.

[0029] Figure 16 It is shown Figure 13 The diagram shows a top view of a partial DRAM array structure according to an embodiment of the present disclosure.

[0030] Figure 17 It shows along Figure 16 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line AA'.

[0031] Figure 18 It shows along Figure 16 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken from line BB'.

[0032] Figure 19 It shows along Figure 17 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line CC'.

[0033] Figure 20 It shows along Figure 17 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line DD'.

[0034] Figure 21 A flowchart of a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure is shown.

[0035] Figures 22A to 31B These are schematic cross-sectional views illustrating the various process steps of a method for manufacturing a DRAM array structure according to embodiments of the present disclosure.

[0036] Figure 32 A flowchart of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure is shown.

[0037] Figures 33A to 39B These are schematic cross-sectional views illustrating various process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure. Detailed Implementation

[0038] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of the various exemplary embodiments of this disclosure. As used herein, “implementation” is a non-limiting example of an apparatus or method employing one or more inventive concepts disclosed herein. However, it will be apparent that the exemplary embodiments may be implemented without these specific details or with one or more equivalent configurations. Furthermore, the exemplary embodiments may be different, but not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

[0039] Unless otherwise stated, the exemplary embodiments described are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0040] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0041] Although terms such as “first” and “second” may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0042] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” mean the presence of the stated features, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or values ​​provided that are recognized by those skilled in the art.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0044] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same parts throughout the drawings. Furthermore, in the drawings, parts are not necessarily drawn to scale for clarity, and the scale and dimensions of parts may be enlarged.

[0045] The dynamic random access memory (DRAM) cell structure according to embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0046] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0047] like Figure 1 As shown, the DRAM cell structure 100 according to the embodiments of this disclosure can adopt a 2T1C (i.e., two gate transistors and one storage capacitor) cell structure. Specifically, the DRAM cell structure 100 may include two gate-around-the-axis (GAA) transistors, namely a first GAA transistor T1 and a second GAA transistor T2, which are sequentially disposed in the vertical direction (z direction) and electrically connected in parallel. Both the first and second GAA transistors T1 and T2 may have a channel with a tubular structure and serve as gate transistors of the DRAM cell structure 100.

[0048] According to an embodiment of this disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are commonly connected to one plate (internal electrode) of the memory capacitor C, and the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 are commonly connected to the bit line BL. According to an embodiment of this disclosure, the bit line BL can extend in the vertical direction (z-direction). Furthermore, according to an embodiment of this disclosure, the gate G1 of the first GAA transistor T1 can be connected to the first word line WLA, and the gate G2 of the second GAA transistor T2 can be connected to the second word line WLB. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can extend along a first horizontal direction (y-direction) and overlap in the vertical direction (z-direction). According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be shorted together. Alternatively, according to embodiments of this disclosure, the first word line WLA and the second word line WLB may not be shorted together to control the first GAA transistor T1 and the second GAA transistor T2 respectively.

[0049] Furthermore, according to embodiments of this disclosure, the other plate (external electrode) of the storage capacitor C can be connected to the source line SL. Those skilled in the art will recognize that in a DRAM array structure composed of the DRAM cell structure 100 according to this disclosure, the source lines SL of all DRAM cell structures can be connected together commonly or in groups; therefore, the source line SL can also be referred to herein as a "common electrode".

[0050] Figure 2 A perspective view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 3 A top view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 4It shows along Figure 3 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line AA'. Figure 5 It shows along Figure 3 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line BB'. Figure 6 It shows along Figure 4 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line CC'. Figure 7 It shows along Figure 4 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line DD'.

[0051] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include bit line holes (such as...) extending in the vertical direction (z-direction). Figure 3 , Figure 6 and Figure 7 The hole shown is located at the center and has, for example, a circular cross-section, and a common electrode trench (e.g., extending in the first horizontal direction (y direction) and penetrating the DRAM cell structure 100 in the vertical direction (z direction) is also present. Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 The slots located on both sides of the central bit line hole are shown.

[0052] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include conductor lines 109 disposed in bit line holes. The conductor lines 109 extend in the vertical direction (z-direction) and can be used as... Figure 1 The bit line BL of the DRAM cell structure 100 shown. According to embodiments of the present disclosure, the material used to form the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In particular, according to embodiments of the present disclosure, the conductor line 109 may have a cylindrical shape extending in the vertical direction (z-direction). For example, as Figure 3 , Figure 6 and Figure 7 As shown, conductor line 109 can be a cylinder with a first diameter d1.

[0053] like Figures 2 to 7As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 with a tubular structure and a first isolation material layer 111 disposed in a bit line hole surrounding a conductor line 109. Specifically, as Figure 4 and Figure 5 As shown more clearly, the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first insulating material layer 111. In other words, according to embodiments of this disclosure, both the semiconductor material layer 107 and the first insulating material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7 In this invention, the tubular structure has a circular cross-section, but this disclosure is not limited to this. Those skilled in the art should recognize that the tubular structure may also have other arbitrary cross-sections, such as elliptical, square or rectangular cross-sections, in which case the cross-sectional shape of the conductor line 109 can be adjusted accordingly.

[0054] According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof. According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a low-k material. Low-k materials can have a lower dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the first isolation material layer 111 can include a low-k material having a dielectric constant of about 3.9 or lower. According to embodiments of this disclosure, low-k materials can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), silsesquioxane (HSQ), silicon carbide (SiCOH), or polymer materials such as parylene and polyimide (PI). According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-k materials.

[0055] According to embodiments of this disclosure, the material used to form the semiconductor material layer 107 can be a semiconductor thin film material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof. According to embodiments of this disclosure, the material used to form the semiconductor material layer 107 can be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO) in different proportions. In particular, according to embodiments of this disclosure, the semiconductor material layer 107 may include a single layer of IGZO or a stack of multiple layers of IGZO in different proportions.

[0056] Furthermore, according to embodiments of this disclosure, as described in more detail below, the semiconductor material layer 107 can be formed as follows: Figure 1 The source / drain regions and channel regions of the first GAA transistor T1 and the second GAA transistor T2 are shown, wherein the source / drain regions of the first GAA transistor T1 and the second GAA transistor T2 correspond to the first source / drain S / D11 and the second source / drain S / D12 of the first GAA transistor T1 and the first source / drain S / D21 and the second source / drain S / D22 of the second GAA transistor T2. It should be noted that the source / drain regions described from a structural perspective are equivalent to the source / drain regions described from a circuit perspective. Furthermore, according to embodiments of this disclosure, the semiconductor material layer 107 may also be formed as shown... Figure 1 The internal electrode of the storage capacitor C is shown. Therefore, according to embodiments of this disclosure, the storage capacitor C may also have a tubular structure.

[0057] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two first dielectric layers 106 disposed in bit line vias, respectively surrounding the upper and lower ends of the semiconductor material layer 107. According to embodiments of the present disclosure, the two first dielectric layers 106 may be respectively formed as shown in the diagram. Figure 1 The gate dielectric of the first GAA transistor T1 and the second GAA transistor T2 are shown. Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, the first dielectric layer 106 may also have a tubular structure with a bent cross-section. In other words, as... Figures 2 to 5 As shown, in a cross-section along the vertical direction (z-direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion relative to the first portion and away from the end of the conductor line 109. The first and second portions may be connected by a horizontal connecting portion. According to embodiments of this disclosure, the material used to form the first dielectric layer 106 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or combinations thereof.

[0058] Therefore, according to the embodiments of this disclosure, both the first GAA transistor T1 and the second GAA transistor T2 are formed to have a tubular structure and both have a tubular channel.

[0059] like Figures 2 to 7As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include a lower first gate layer 104 and an upper second gate layer 105 configured to surround a thicker second portion of a lower and upper first dielectric layer 106, respectively. Figure 2 and Figure 6 As shown, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the first gate layer 104 may correspond to... Figure 1 The first GAA transistor T1 shown has a gate G1, and the second gate layer 105 can correspond to, as shown in the figure. Figure 1 The gate G2 of the second GAA transistor T2 is shown. Furthermore, as... Figure 2 , Figure 3 and Figure 5 As shown, according to an embodiment of this disclosure, the first gate layer 104 may extend in a first horizontal direction (y-direction) to further correspond to, as Figure 1 The first word line WLA is shown, connected to the first gate G1 of the first GAA transistor T1. Accordingly, according to embodiments of this disclosure, the second gate layer 105 may extend in the first horizontal direction (y direction) to further correspond to, as shown in the figure. Figure 1 The second word line WLB is shown connected to the gate G2 of the second GAA transistor T2. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be led out from the distal end in a first horizontal direction (y direction).

[0060] Therefore, according to embodiments of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z-direction), and a first word line WLA and a second word line WLB extending in the first horizontal direction (y-direction). According to embodiments of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend vertically within a tubular structure formed by the first GAA transistor T1, the second GAA transistor T2, and the storage capacitor C. Furthermore, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction).

[0061] Furthermore, according to embodiments of this disclosure, the materials used to form the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0062] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two second insulating material layers 103 configured to surround, respectively, a thinner first portion of a first dielectric layer 106 above and below. Figure 2 and Figure 3 As shown, according to embodiments of the present disclosure, the second insulating material layer 103 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the material used to form the second insulating material layer 103 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCOH), or aluminum oxide (Al2O3). According to embodiments of the present disclosure, the first insulating material layer 111 and the second insulating material layer 103 may be formed of the same or different insulating materials.

[0063] like Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 along the vertical direction (z-direction) may include the formation indicated by the shaded area. Figure 1 The first portion 1071 of the vertical channel region of the first and second GAA transistors T1 and T2 shown, and the formation between the first portions 1071. Figure 1 The first source / drain region of the first GAA transistor T1 (corresponding to the first source / drain S / D11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D21 of the second GAA transistor T2), and the second portion 1072 of the internal electrode of the memory capacitor C are shown. Therefore, according to an embodiment of the present disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are connected together with the internal electrode of the memory capacitor C. According to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by a first insulating material layer 111 surrounding the conductor line 109 (bit line BL).

[0064] According to embodiments of this disclosure, the doping type, doping concentration, and / or atomic composition ratio of the second portion 1072 of the semiconductor material layer 107 can be changed through material modification processes such as doping and etching, thereby improving its conductivity as the internal electrode of the memory capacitor C. In other words, according to embodiments of this disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic composition ratios. According to embodiments of this disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed by, for example, etching to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed by, for example, etching to form metal atom interstitials or oxygen atom vacancies to improve its conductivity.

[0065] In addition, such as Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 may further include, along the vertical direction (z-direction), contact conductor lines 109 at both ends serving as... Figure 1 The diagram shows the third portion 1073 of the second source / drain region of the first GAA transistor T1 (corresponding to the second source / drain S / D12 of the first GAA transistor T1) and the second source / drain region of the second GAA transistor T2 (corresponding to the second source / drain S / D22 of the second GAA transistor T2), and the first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Therefore, according to an embodiment of this disclosure, the third portion 1073 of the semiconductor material layer 107 contacts the conductor line 109, such that the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0066] like Figure 3 As shown, according to an embodiment of this disclosure, the third portion 1073 of the tubular semiconductor material layer 107 may have a second diameter d2, which is larger than the first diameter d1 of the conductor line 109. Furthermore, as... Figures 3 to 7 As shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the tubular semiconductor material layer 107 may have a third diameter d3, which is larger than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0067] like Figures 2 to 7As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 disposed in a common electrode trench as a capacitor dielectric for a storage capacitor C. According to an embodiment of the present disclosure, the second dielectric layer 108 may be formed conformally along the trench wall of the common electrode trench. For example... Figure 2 and Figure 4 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact the two second insulating material layers 103, the first gate layer 104, the second gate layer 105, and the second portion of the semiconductor material layer 107 in the second horizontal direction (x direction). Furthermore, as... Figure 2 and Figure 5 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact a second portion of the semiconductor material layer 107 in a first horizontal direction (y-direction). The first horizontal direction, i.e., the y-direction, can be perpendicular to the second horizontal direction, i.e., the x-direction.

[0068] Furthermore, according to embodiments of this disclosure, the material used to form the second dielectric layer 108 can be a high-k material. The high-k material can have a higher dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the second dielectric layer 108 can include a high-k material having a dielectric constant of about 4 or greater. According to embodiments of this disclosure, the high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTiO3), or combinations thereof.

[0069] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 extending along the surface of the second dielectric layer 108 and filling a common electrode trench. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to... Figure 1 The external electrode of the storage capacitor C is shown, i.e., the common electrode of the storage capacitor C, and the source line SL. For example... Figures 2 to 7As shown, according to an embodiment of this disclosure, the electrode layer 110 corresponding to the external electrode of the storage capacitor C and the source line SL can extend in a first horizontal direction (y-direction) and penetrate the DRAM cell structure 100 in a vertical direction (z-direction). According to an embodiment of this disclosure, the material used to form the electrode layer 110 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof. Therefore, according to an embodiment of this disclosure, the storage capacitor C of the DRAM cell structure 100 can be formed as a cylindrical capacitor.

[0070] Furthermore, although not shown in the figures, according to embodiments of this disclosure, a third isolation material layer may be provided between the first gate layer 104 and the second gate layer 105 and the second dielectric layer 108 to reduce the parasitic capacitance and leakage current between the external electrode (source line SL) of the storage capacitor and the gates G1 and G2 (i.e., the first and second word lines WLA and WLB) of the first and second GAA transistors T1 and T2.

[0071] Figure 8 This is a top view showing a DRAM cell structure 100' according to another embodiment of the present disclosure. Figure 9 It shows along Figure 8 The image shows a cross-sectional view of a DRAM cell structure 100' according to another embodiment of the present disclosure, taken by line AA'. Figure 10 It shows along Figure 8 The image shows a cross-sectional view of a DRAM cell structure 100' according to another embodiment of the present disclosure, taken from line BB'. Figure 11 It shows along Figure 9 The image shows a cross-sectional view of a DRAM cell structure 100' according to another embodiment of the present disclosure, taken by line CC'. Figure 12 It shows along Figure 9 The image shows a cross-sectional view of a DRAM cell structure 100' according to another embodiment of the present disclosure, taken by line DD'. Figures 8 to 12 The shown with Figures 3 to 7 The same elements shown are indicated by the same reference numerals and will not be described repeatedly for the sake of brevity.

[0072] Figures 8 to 12 The DRAM cell structure 100' shown is... Figures 3 to 7 The only difference in the DRAM cell structure 100 shown is that, as Figure 12As shown, the second portion 1072 of the tubular semiconductor material layer 107 of the DRAM cell structure 100' has a fourth diameter d4, which is larger than the third diameter d3 of the first portion 1071 of the semiconductor material layer 107. Therefore, accordingly, according to embodiments of this disclosure, as... Figure 9 and Figure 10 As shown, the tubular semiconductor material layer 107 of the DRAM cell structure 100' also includes a second horizontal connection portion 1075 connecting the first portion 1071 and the second portion 1072.

[0073] Compared to Figures 3 to 7 The DRAM cell structure 100 shown is in Figures 8 to 12 In the DRAM cell structure 100' shown, the inner electrode of the storage capacitor C extends outward, which increases the area between the inner and outer electrodes of the storage capacitor C, thereby increasing the capacitance value of the storage capacitor C.

[0074] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure 200 formed by the DRAM cell structure shown is as follows. Figure 13 As shown, according to an embodiment of this disclosure, by Figure 1 The DRAM array structure 200 formed by the DRAM cell structure shown can be a three-dimensional DRAM array structure stacked in the vertical direction (z direction).

[0075] like Figure 13 As shown, according to embodiments of this disclosure, the DRAM array structure 200 may include, for example: Figures 1 to 12 The diagram shows multiple DRAM cell structures 100 or 100'. For clarity, certain reference numerals within each DRAM cell structure have been omitted. According to embodiments of this disclosure, the multiple DRAM cell structures are arranged in L layers, M rows, and N columns, where L, M, and N are all natural numbers greater than 1. In this document, each of the multiple DRAM cell structures included in the DRAM array structure 200 can be represented as Clmn, i.e., the DRAM cell structure located in the m-th row, n-th column, and l-th layer of the DRAM array structure 200, where m, n, and l are natural numbers, and 1 ≤ m ≤ M, 1 ≤ n ≤ N, and 1 ≤ l ≤ L. Furthermore, in this document, M represents the number of rows of DRAM cell structures in the DRAM array structure 200 along the first horizontal direction (y-direction), N represents the number of columns of DRAM cell structures in the DRAM array structure 200 along the second horizontal direction (x-direction), and L represents the number of layers of DRAM cell structures in the DRAM array structure 200 along the vertical direction (z-direction).

[0076] According to embodiments of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M first word lines WLA11 to WLALM, L×M second word lines WLB11 to WLBLM, and M×N bit lines BL11 to BLMN.

[0077] Therefore, as Figure 13 As shown, according to the embodiments of this disclosure, in the DRAM array structure 200, each layer of the L-layer DRAM cell structure includes M rows and N columns, totaling M×N DRAM cell structures; each row of the M-row DRAM cell structure includes L layers and N columns, totaling L×N DRAM cell structures; and each column of the N-column DRAM cell structure includes L layers and M rows, totaling L×M DRAM cell structures.

[0078] As mentioned above Figures 1 to 12 As described, each of the plurality of DRAM cell structures included in the DRAM array structure 200 may include: a first GAA transistor and a second GAA transistor, both having a tubular channel structure, arranged sequentially in the vertical direction and electrically connected in parallel; and a storage capacitor having a tubular structure, arranged in the vertical direction between the first GAA transistor and the second GAA transistor, the internal electrode of which is connected to the first source / drain of the first GAA transistor and the second GAA transistor.

[0079] In addition, such as Figure 13 As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend vertically inside a tubular structure formed by L first GAA transistors, L second GAA transistors, and L storage capacitors in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the L first GAA transistors and L second GAA transistors in the M-row N-column DRAM cell structure.

[0080] Furthermore, although not shown, according to embodiments of this disclosure, in each row of an M-row DRAM array structure, L first word lines WLA1m to WLALm can be respectively connected to L second word lines WLB1m to WLBLm. For example, as Figure 13As shown, in the first row of the DRAM array structure, the first word line WLA11 can be connected to the second word line WLB11, the first word line WLA21 can be connected to the second word line WLB21, and so on, until the first word line WLAL1 can be connected to the second word line WLBL1. According to an embodiment of this disclosure, in each row of the M-row DRAM array structure, the corresponding connections of L first word lines and L second word lines can be implemented from the remote end outside the array. In this document, since the paired first word lines WLAlm and second word lines WLBlm extending along the first horizontal direction (y direction) can be connected together, they can be collectively referred to as word lines WL and assigned the same number as the corresponding first word line WLAlm and second word line WLBlm, i.e., WLlm. At this time, according to an embodiment of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M word lines WL11 to WLLM and M×N bit lines BL11 to BLMN.

[0081] Furthermore, according to embodiments of this disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L-layer DRAM cell structure, which extend along a first horizontal direction (y-direction) and are respectively connected to the external electrodes of the storage capacitors in the L-layer DRAM cell structure. Additionally, as... Figure 13 As shown, according to an embodiment of this disclosure, L source lines SL can be connected together by a common electrode trench disposed between the bit lines that runs vertically (z-direction) through the entire DRAM array structure 200, while the source lines SL also extend vertically (z-direction). Although not shown, according to an alternative embodiment of this disclosure, the L source lines SL can also be connected together simply outside the DRAM array structure 200, either commonly or in groups, thus omitting the common electrode trench.

[0082] Figure 14 It is shown Figure 13 The diagram shown is an equivalent circuit diagram of the DRAM cell structures C111 to CL1N in the first row of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 14 As shown, a first-row, first-column DRAM cell structure C111 is provided at the intersection of the first row, first column bit line BL11 extending vertically (z-direction) and the first layer word line (first word line WLA11 and second word line WLB11) extending horizontally (y-direction). And so on. Figure 14 The first row of the DRAM array structure 200 shown includes N×L DRAM cell structures C111 to CL1N.

[0083] As mentioned above Figure 1As described, according to embodiments of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example Figure 9 The DRAM cell structure C111 shown includes a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C.

[0084] Figure 15 It is shown Figure 13 The diagram shows a schematic perspective view of the first row of DRAM cells in the first layer of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 15 As shown, in the first row of the first layer of the DRAM array structure, the first word line WL11 (first word line WLA11 and second word line WLB11) can extend along a first horizontal direction (y-direction), and the first row bit lines (only BL11 to BL13 are shown) can extend along a vertical direction (z-direction). According to an embodiment of this disclosure, the source line SL of the first layer of the DRAM cell structure can extend along the first horizontal direction (y-direction). Furthermore, as... Figure 15 As shown, the source line SL can also be connected to the source lines SL in other layers in a common electrode trench that extends along the vertical direction (z direction).

[0085] In addition, such as Figures 13 to 15 As shown, according to an embodiment of this disclosure, the bit line BLmn in the m-th row and n-th column can be connected to the second source / drain of the L first GAA transistors and the L second GAA transistors in the m-th row and n-th column DRAM cell structure of the DRAM array structure 200, for performing a cell selection operation on the m-th row and n-th column DRAM cell structure.

[0086] Figure 16 It is shown Figure 13 The diagram shows a top view of a partial DRAM array structure 201 of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 17 It shows along Figure 16 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line AA'. Figure 18 It shows along Figure 16 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line BB'. Figure 19 It shows along Figure 17 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line CC'. Figure 20 It shows along Figure 17 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line DD'.

[0087] It should be noted that Figures 16 to 20 The example shown is as follows Figure 13 The partial DRAM array structure 201 of the DRAM array structure 200 shown includes DRAM cell structures C111, C112, C121, C122, C211, C212, C221 and C222 in the first row and first column of the first layer to the second row and second column of the second layer. These eight DRAM cell structures are arranged in two rows, two columns and two layers.

[0088] According to embodiments of this disclosure, the M rows and N columns of the DRAM array structure 200, from bit lines BL11 to BLMN, can extend vertically (z-direction) and be arranged in an M×N matrix in the first horizontal direction (y-direction) and the second horizontal direction (x-direction). Furthermore, according to embodiments of this disclosure, the L layers of DRAM cell structures of the DRAM array structure 200 are stacked sequentially in the vertical direction, and each layer of DRAM cell structure includes M×N DRAM cell structures.

[0089] Specifically, such as Figures 16 to 20 As shown, the four bit lines BL11, BL12, BL21, and BL22, arranged in two rows and two columns, can extend vertically (z-direction) and be arranged in a 2×2 matrix in the first horizontal direction (y-direction) and the second horizontal direction (x-direction). Furthermore, as... Figure 17 and Figure 18 As shown, the first-layer DRAM cell structures C111, C112, C121 and C122 are stacked on top of the second-layer DRAM cell structures C211, C212, C121 and C222.

[0090] like Figure 16 and Figure 17As shown, the first word line WLA11 of the first row of the first layer is connected to the gate of the first GAA transistor in the first row of the first layer DRAM cell structures C111 and C112, and the second word line WLB11 of the first layer is connected to the gate of the second GAA transistor in the first row of the first layer DRAM cell structures C111 and C112. Similarly, the first word line WLA12 of the second row of the first layer is connected to the gate of the first GAA transistor in the second row of the first layer DRAM cell structures C121 and C122, and the second word line WLB12 of the second row of the first layer is connected to the gate of the second GAA transistor in the second row of the first layer DRAM cell structures C121 and C122. Similarly, the first word line WLA21 of the first row of the second layer is connected to the gate of the first GAA transistor in the first row of the second layer DRAM cell structures C211 and C212, and the second word line WLB21 of the first row of the second layer is connected to the gate of the second GAA transistor in the first row of the second layer DRAM cell structures C211 and C212. Similarly, the first word line WLA22 of the second row of the second layer is connected to the gate of the first GAA transistor in the second row of the second layer DRAM cell structure C221 and C222, and the second word line WLB22 of the second row of the second layer is connected to the gate of the second GAA transistor in the second row of the second layer DRAM cell structure C221 and C222.

[0091] like Figures 16 to 20As shown, four bit lines BL11, BL12, BL21, and BL22 are formed in four bit line holes extending vertically (z-direction) through the DRAM array structure. Specifically, bit line BL11 in the first row and first column extends vertically inside the tubular structure formed by the first GAA transistor, the second GAA transistor, and the storage capacitor in the first row and first column DRAM cell structures C111 and C211, and connects to the second source / drain of the first GAA transistor and the second GAA transistor in the first row and first column DRAM cell structures C111 and C211. Similarly, bit line BL12 in the first row and second column extends vertically inside the tubular structure formed by the first GAA transistor, the second GAA transistor, and the storage capacitor in the first row and second column DRAM cell structures C112 and C212, and connects to the second source / drain of the first GAA transistor and the second GAA transistor in the first row and second column DRAM cell structures C112 and C212. Similarly, bit line BL21 in the second row and first column extends vertically inside the tubular structure formed by the first and second GAA transistors and the storage capacitor in the DRAM cell structures C121 and C221 in the second row and first column, and connects to the second source / drain of the first and second GAA transistors in the DRAM cell structures C121 and C221 in the second row and first column. Similarly, bit line BL22 in the second row and second column extends vertically inside the tubular structure formed by the first and second GAA transistors and the storage capacitor in the DRAM cell structures C122 and C222 in the second row and second column, and connects to the second source / drain of the first and second GAA transistors in the DRAM cell structures C122 and C222 in the second row and second column.

[0092] According to embodiments of this disclosure, in each of the DRAM cell structures in M ​​rows × N columns, the first source / drain and second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the internal electrode of the storage capacitor are formed from the same semiconductor material layer. That is, according to embodiments of this disclosure, in each of the M × N bit line vias penetrating the L-layer DRAM cell structure in the vertical direction (z-direction), the first source / drain and second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the internal electrode of the storage capacitor in the L-layer DRAM cell structure are formed from the same semiconductor material layer having a tubular structure. In other words, this tubular semiconductor material layer extends vertically (z-direction) throughout the entire DRAM array structure 200.

[0093] Specifically, such as Figures 16 to 20As shown, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of the first GAA transistor and the second source / drain electrode, and the storage capacitor in the first-layer DRAM cell structure C111 and the second-layer DRAM cell structure C211 connected to the first row, first column bit line BL11 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain electrode, channel regions, and internal electrodes of the first GAA transistor and the second source / drain electrode, and the storage capacitor in the first-layer DRAM cell structure C112 and the second-layer DRAM cell structure C212 connected to the first row, second column bit line BL12 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain electrode, channel regions, and internal electrodes of the storage capacitor in the first-layer DRAM cell structure C121 and the second-layer DRAM cell structure C221 connected to the second row, first column bit line BL21 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain of the first GAA transistor and the second source / drain of the second GAA transistor, the channel region and the internal electrode of the storage capacitor in the first layer DRAM cell structure C122 and the second layer DRAM cell structure C222 connected to the second row and second column bit line BL22 are formed by the same semiconductor material layer.

[0094] According to embodiments of this disclosure, the common electrode trench can extend in the first horizontal direction (y-direction) and penetrate the L-layer DRAM array structure in the vertical direction (z-direction). In this case, the L source lines SL corresponding to the L-layer DRAM cell structure can be connected together in the vertical direction (z-direction). Furthermore, according to embodiments of this disclosure, adjacent rows of DRAM cell structures in the second horizontal direction (x-direction) can share the common electrode trench. Additionally, as described above, the capacitor dielectric and external electrodes of the storage capacitors in each DRAM cell structure of the DRAM array structure 200 can be disposed in the common electrode trench.

[0095] The following will combine Figure 21 as well as Figures 22A to 31B A method for manufacturing a DRAM array structure according to embodiments of the present disclosure is described. The method for manufacturing a DRAM array structure according to embodiments of the present disclosure can be employed by stacking multiple subarrays in the vertical direction (z-direction) to maximize the utilization of the area in the horizontal direction.

[0096] Specifically, Figure 21 A flowchart of a method 2100 for manufacturing a DRAM array structure 200 according to an embodiment of the present disclosure is shown. Figures 22A to 31B Schematic cross-sectional views are shown of various process steps in a method for manufacturing a DRAM array structure 200 according to embodiments of the present disclosure. It should be noted that... Figures 22A to 31AIt is a cross-sectional view taken along the second horizontal direction (x direction) in the vertical direction (z direction) of the DRAM array structure, and Figures 22B to 31B It is a cross-sectional view taken along the first horizontal direction (y direction) in the vertical direction (z direction) of the DRAM array structure.

[0097] Although for ease of description, Figures 22A to 31B Only an exemplary method is shown for fabricating a DRAM array structure 200 by stacking two subarrays, namely a first stacked subarray and a second stacked subarray, wherein each stacked subarray comprises a 2-layer × 2-row × 2-column DRAM cell structure. However, those skilled in the art will recognize that, according to the combination of Figure 21 as well as Figures 22A to 31B The described method for manufacturing a DRAM array structure according to embodiments of the present disclosure can be readily extended to manufacture a DRAM array structure 200 having three or more stacked subarrays, comprising an L-layer × M-row × N-column DRAM cell structure. Furthermore, although in Figures 22A to 31B In the present invention, the first stacked subarray and the second stacked subarray have DRAM cell structures with the same number of layers, but this disclosure is not limited thereto. According to embodiments of the present disclosure, the number of layers of the DRAM cell structures in the stacked subarrays included in the DRAM array structure may be the same or different from each other.

[0098] Furthermore, although for ease of description, Figures 22A to 31B Only the DRAM array structure 200 is shown, as referenced above. Figures 1 to 7 The DRAM cell structure 100 shown is configured as described above. However, those skilled in the art will recognize that, by making minor adjustments to the process steps, the DRAM array structure described above can be easily manufactured using the method for manufacturing the DRAM array structure according to embodiments of this disclosure. Figures 8 to 12 The DRAM array structure 200 is composed of the DRAM cell structure 100' shown.

[0099] In the following description, the materials for each layer are illustrated. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description, "(relative to A) selective etching of B," means that the etching formulation used can primarily affect B, while having little or no effect on A or other material layers exposed to the etching formulation during the etching of B (where A is not explicitly mentioned or only part of such material layers is mentioned). Those skilled in the art will understand from these descriptions how to select the materials for each layer, rather than being limited to the materials illustrated herein.

[0100] exist Figure 21 In step S2101 shown, as Figure 22A and Figure 22BAs shown, multiple material layers can be repeatedly stacked on the circuit substrate 300, as described below. These multiple material layers may include alternating stacked first isolation layers 303 and multiple stacked layers 304. According to embodiments of this disclosure, the circuit substrate 300 may be a semiconductor substrate on which multiple circuits can be fabricated using semiconductor manufacturing processes, such as standard CMOS processes. According to embodiments of this disclosure, as... Figure 13 The L-layer DRAM cell structure of the DRAM array structure 200 shown can be stacked on the circuit board 300 in the vertical direction (z direction) to achieve system-level three-dimensional vertical integration.

[0101] like Figure 22A and Figure 22B As shown, a pad structure 301 can be pre-formed in the circuit board 300 to achieve electrical connections, such as bit lines, with the DRAM array structure 200. Furthermore, as... Figure 22A and Figure 22B As shown, a capping layer 302 may be provided on the circuit board 300 to cover the circuit board 300 (including the pad structure 301 therein), for protecting the circuit board 300 and achieving electrical isolation between the circuit board 300 and the DRAM array structure 200 fabricated thereon. According to embodiments of this disclosure, the material used to form the capping layer 302 may be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0102] like Figure 22A and Figure 22B As shown, according to an embodiment of the present disclosure, a plurality of first isolation layers 303 and a plurality of stacked layers 304 can be alternately stacked from bottom to top in the vertical direction (z direction) above the cover layer 302 disposed on the circuit board 300.

[0103] According to embodiments of this disclosure, the first isolation layer 303 can be formed in subsequent process steps as described above. Figures 1 to 12 The second isolation material layer 103 of the described DRAM cell structure 100 or 100'. Therefore, according to embodiments of the present disclosure, the material used to form the first isolation layer 303 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCOH), or aluminum oxide (Al2O3).

[0104] like Figure 22A and Figure 22B As shown, according to embodiments of the present disclosure, each of the plurality of stacked layers 304 may include a first conductive layer 3041, a sacrificial layer 3042, and a second conductive layer 3043. According to embodiments of the present disclosure, the first conductive layer 3041 and the second conductive layer 3043 may be formed respectively in subsequent process steps as described above. Figures 1 to 12 The DRAM cell structure 100 or 100' described includes a first gate layer 104 and a second gate layer 105. Therefore, according to embodiments of this disclosure, the materials used to form the first conductive layer 3041 and the second conductive layer 3043 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0105] Furthermore, according to embodiments of this disclosure, the sacrificial layer 3042 can be formed of any material having etching selectivity relative to the isolation layer 303 and the first conductive layer 3041 and the second conductive layer 3043. For example, when the isolation layer 303 is formed of silicon oxide (SiO2) and the first conductive layer 3041 and the second conductive layer 3043 are formed of titanium nitride (TiN), the material used to form the sacrificial layer 3042 can be a material different from silicon oxide (SiO2) and titanium nitride (TiN), such as silicon nitride (SiN), high-k dielectric, low-k dielectric, polymer material, polycrystalline silicon, amorphous silicon, silicon-germanium compound, metal and metal compound, etc. For example, when the isolation layer 303 is formed of silicon nitride (SiN) and the first conductive layer 3041 and the second conductive layer 3043 are formed of polycrystalline silicon, the material used to form the sacrificial layer 3042 can be a material different from silicon nitride (SiN) and polycrystalline silicon, such as silicon oxide (SiO2), high-k dielectric, low-k dielectric, polymer material, silicon-germanium compound, metal and metal compound, etc.

[0106] Furthermore, according to embodiments of this disclosure, the first conductive layer 3041 and the second conductive layer 3043 can be formed respectively in subsequent process steps as described above. Figures 1 to 12 The first word line WL1 and the second word line WL2 of the described DRAM cell structure 100 or 100' are such that the first conductive layer 3041 and the second conductive layer 3043 can also be connected together.

[0107] Subsequently, Figure 21 In step S2102 shown, as Figure 23A and Figure 23B As shown, a plurality of first isolation layers 303 and a plurality of stacked layers 304 can be etched, for example, by an etching process to form a plurality of bit line holes T1 extending to the upper surface of the circuit board 300, i.e. the upper surface of the capping layer 302.

[0108] According to embodiments of this disclosure, the bit line hole T1 can correspond to the above reference. Figures 1 to 12The described DRAM cell structure 100 or 100' has a bit line via, wherein conductor lines 109, a first insulating material layer 111, a semiconductor material layer 107, and a first dielectric layer 106 are sequentially disposed from the inside out. Therefore, according to embodiments of this disclosure, as referred to above... Figure 13 The bit line holes T1 can be arranged in an array of M rows × N columns.

[0109] According to embodiments of the present disclosure, the number of bit line vias T1 can be the same as the number of bit lines M×N of the DRAM array structure 200 to be fabricated above the circuit board 300. According to embodiments of the present disclosure, the bit line vias T1 can have a circular cross-section, but the present disclosure is not limited thereto. Those skilled in the art will recognize that the bit line vias T1 can also have other arbitrary cross-sections, such as elliptical, square, or rectangular cross-sections.

[0110] According to embodiments of this disclosure, the diameters of the bit line holes T1 in each layer can be set to be different from each other, for example, by differences in etching selectivity between materials. Specifically, as Figure 23A and Figure 23B As shown, according to an embodiment of the present disclosure, by means of the difference in etching selectivity between the material forming the first isolation layer 303 and the material forming the stack 304, the diameter of the bit line hole T1 in the stack 304 can be larger than the diameter of the bit line hole T1 in the first isolation layer 303.

[0111] Furthermore, despite Figure 23A and Figure 23B The diagram shows that the bit line hole T1 has a uniform diameter in the stack 304. However, according to embodiments of this disclosure, in the stack 304, due to the difference in etching selectivity between the materials forming the first conductive layer 3041 and the second conductive layer 3043 and the material forming the sacrificial layer 3042, the diameter of the bit line hole T1 in the sacrificial layer 3042 can also be larger than the diameter of the bit line hole T1 in the first conductive layer 3041 and the second conductive layer 3043. In this case, due to the internal electrode of the storage capacitor C formed in subsequent process steps (see below in conjunction with...), Figure 24A and Figure 24B The semiconductor material layer 306 (corresponding to the portion of the sacrificial layer 3042) extends outward, increasing the facing area between the inner and outer electrodes of the storage capacitor C, thereby increasing the capacitance value of the storage capacitor C. In this case, the final DRAM array structure 200 is as described above. Figures 8 to 12 The DRAM cell structure described is 100'. For the sake of brevity, the manufacturing process for this configuration will not be described in more detail here.

[0112] Subsequently, Figure 21 In step S2103 shown, as Figure 24A and Figure 24B As shown, a gate dielectric layer 305 can be conformally formed on the inner surface of the bit line hole T1 by, for example, a deposition process (e.g., atomic layer deposition (ALD) process), a semiconductor material layer 306 can be conformally formed on the inner surface of the gate dielectric layer 305, and the remaining space of the bit line hole T1 can be filled with an isolation medium 307.

[0113] like Figure 24A and Figure 24B As shown above, due to the reference Figure 23A and Figure 23B The diameter of the bit line hole T1 in the stack 304 can be larger than the diameter of the bit line hole T1 in the first isolation layer 303, and the first conductive material 308 has a uniform diameter in the bit line hole T1. Therefore, the gate dielectric layer 305 in the bit line hole T1 may include a portion with a smaller diameter corresponding to the first isolation layer 303 and a portion with a larger diameter corresponding to the stack 304. Similarly, the semiconductor material layer 306 in the bit line hole T1 may include a portion with a smaller diameter corresponding to the first isolation layer 303 and a portion with a larger diameter corresponding to the stack 304.

[0114] According to embodiments of this disclosure, the gate dielectric layer 305 can be formed in subsequent process steps as described above. Figures 1 to 12 The first dielectric layer 106 of the described DRAM cell structure 100 or 100' can be used as such Figure 1 The gate dielectrics of the first GAA transistor T1 and the second GAA transistor T2 are shown. According to embodiments of this disclosure, the material used to form the gate dielectric layer 305 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or combinations thereof.

[0115] According to embodiments of this disclosure, the semiconductor material layer 306 can be formed in subsequent process steps as described above. Figures 1 to 12 The semiconductor material layer 107 of the described DRAM cell structure 100 or 100' can be used as such Figure 1The first GAA transistor T1 and the second GAA transistor T2 are shown, including their source / drain regions, channel regions, and the internal electrode of the storage capacitor C. According to embodiments of this disclosure, the material used to form the semiconductor material layer 306 can be a semiconductor thin film material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or combinations thereof. According to embodiments of this disclosure, the oxide semiconductor material used to form the semiconductor material layer 306 can be indium gallium zinc oxide (IGZO), indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO) in different proportions. In particular, according to embodiments of this disclosure, the semiconductor material layer 306 can include a single layer of IGZO or a stack of multiple layers of IGZO in different proportions.

[0116] Furthermore, according to embodiments of this disclosure, in Figure 21 In step S2103 or subsequent steps S2104 and S2106, the doping type, doping concentration, and / or atomic composition ratio of a specific portion of the semiconductor material layer 306 can be changed through material modification processes such as doping and etching to alter the conductivity of the corresponding portion. For example, in subsequent step S2104, the conductivity of the semiconductor material layer 306 corresponding to the doping type, doping concentration, and / or atomic composition ratio can be changed through material modification processes such as doping and etching. Figure 4 and Figure 5 The doping type, doping concentration, and / or atomic composition ratio of the third portion 1073 of the semiconductor layer 107 (i.e., the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2) are modified to improve its contact characteristics with the bit line BL. Alternatively, in a subsequent step S2106, the semiconductor material layer 306 can be modified by material modification processes such as doping and etching to alter the doping characteristics of the portion corresponding to the bit line BL. Figure 4 and Figure 5 The doping type, doping concentration, and / or atomic composition ratio of the second portion 1072 of the semiconductor layer 107 (i.e., the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2, and the internal electrode of the memory capacitor C) are specified to improve the conductivity characteristics of the internal electrode of the capacitor C.

[0117] According to embodiments of this disclosure, the isolation medium 307 can be formed in subsequent process steps as described above. Figures 1 to 12The first isolation material layer 111 of the described DRAM cell structure 100 or 100'. According to embodiments of the present disclosure, the material used to form the isolation dielectric 307 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or a combination thereof. Furthermore, according to embodiments of the present disclosure, the material used to form the isolation dielectric 307 can also be a low-k material. According to embodiments of the present disclosure, the low-k material used to form the isolation dielectric 307 can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), silsesquioxane (HSQ), silicon carbide (SiCOH), or polymer materials such as parylene and polyimide (PI). Furthermore, according to embodiments of the present disclosure, the material used to form the isolation dielectric 307 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-k materials. Furthermore, according to embodiments of the present disclosure, a cavity may also be provided in the isolation dielectric 307.

[0118] Subsequently, Figure 21 In step S2104 shown, as Figure 25A and Figure 25B As shown, the isolation medium 307 and the capping layer 302 of the circuit substrate 300 can be self-aligned etched using, for example, an etching process (e.g., anisotropic etching process) with the uppermost isolation layer 303 and semiconductor material layer 306 as a mask, to form holes extending to the upper surface of the pad structure 301 included in the circuit substrate 300, and these holes are filled with a first conductive material 308 using, for example, a deposition process, such that the first conductive material 308 contacts the pad structure 301.

[0119] According to embodiments of this disclosure, the first conductive material 308 can correspond to the above-mentioned reference. Figures 1 to 12 The conductor line 109 of the described DRAM cell structure 100 or 100' can be used as such Figure 1 The bit line BL is shown. According to embodiments of this disclosure, the first conductive material 308 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0120] like Figure 25A and Figure 25B As shown above, due to the reference Figure 23A and Figure 23B The diameter of the bit line hole T1 in the stack 304 can be larger than the diameter of the bit line hole T1 in the first isolation layer 303. Therefore, the portion of the first conductive material 308 corresponding to the first isolation layer 303 is in direct contact with the semiconductor material layer 306, and the portion of the first conductive material 308 corresponding to the stack 304 is separated from the semiconductor material layer 306 by the isolation medium 307.

[0121] Subsequently, Figure 21 In step S2105 shown, as Figure 26A and Figure 26B As shown, a common electrode trench T2 extending along a first horizontal direction (y-direction) and penetrating multiple first isolation layers 303 and stacked layers 304 in a vertical direction (z-direction) can be formed in the area where no bit line holes T1 are provided by an etching process. In other words, according to an embodiment of the present disclosure, the common electrode trench T2 can extend to the upper surface of the capping layer 302 in the circuit board 300. According to an embodiment of the present disclosure, the common electrode trench T2 can be provided on both sides of each row of M rows of bit line holes T1, and adjacent rows of bit line holes T1 share one common electrode trench T2. Alternatively, the common electrode trench T2 can also be provided on both sides of every few rows of M rows of bit line holes T1.

[0122] Subsequently, Figure 21 In step S2106 shown, as Figure 27A and Figure 27B As shown, the sacrificial layer 3042 exposed in the common electrode trench T2 and a portion of the gate dielectric layer 305 corresponding to the sacrificial layer 3042 can be selectively removed by an etching process. At this time, the sacrificial layer 3042 in the stack 304 has been completely removed.

[0123] Subsequently, Figure 21 In step S2107 shown, as Figure 28A and Figure 28B As shown, a capacitor dielectric layer 309 can be conformally formed on the inner surface of the common electrode trench T2 by, for example, a deposition process (e.g., atomic layer deposition (ALD) process), and the remaining space of the common electrode trench T2 can be filled with a second conductive material 310.

[0124] According to embodiments of this disclosure, the capacitor dielectric layer 309 filled in the common electrode groove T2 can correspond to the above-mentioned reference. Figures 1 to 12 The second dielectric layer 108 of the described DRAM cell structure 100 or 100' serves as the capacitor dielectric for the storage capacitor C. According to embodiments of this disclosure, the capacitor dielectric layer 309 may be in direct contact with the semiconductor material layer 306. According to embodiments of this disclosure, the material used to form the capacitor dielectric layer 309 may be a high-k material. According to embodiments of this disclosure, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTiO3), or combinations thereof.

[0125] like Figure 28A and Figure 28BAs shown, according to an embodiment of the present disclosure, the second conductive material 310 filling the common electrode groove T2 may include a vertical portion extending in the common electrode groove T2 in the vertical direction (z direction) and the first horizontal direction (y direction), and a horizontal portion located in the cavity formed after removing the sacrificial layer 3042 and part of the gate dielectric layer 305 in the horizontal direction (x direction and y direction).

[0126] According to embodiments of this disclosure, the first portion of the second conductive material 310 may correspond to the above-mentioned reference. Figures 1 to 12 The source line SL of the described DRAM cell structure 100 or 100'. Furthermore, according to embodiments of this disclosure, the second portion of the second conductive material 310 may correspond to the above-mentioned reference. Figures 1 to 12 The external electrode of the storage capacitor C in the described DRAM cell structure 100 or 100'.

[0127] Thus, by means of steps S2101 to S2107 of method 2100 of this disclosure, a first stacked subarray STA1 can be fabricated on the circuit board 300. As described above, although the first stacked subarray STA1 is shown as comprising a 2-layer × 2-row × 2-column DRAM cell structure, it can also be fabricated as a DRAM cell structure having more layers × more rows × more columns.

[0128] Subsequently, Figure 21 In step S2108 shown, as Figure 29A and Figure 29B As shown, the interconnect dielectric layer 313 can be formed on the first stacked subarray STA1 by, for example, a deposition process, and the interconnect 311 can be formed in the interconnect dielectric layer 313 at the positions of the first conductive material 308, i.e., each bit line, by, for example, an etching process.

[0129] According to embodiments of the present disclosure, the interconnect dielectric layer 313 may be formed of a dielectric material that is the same as or different from that of the capping layer 302. According to embodiments of the present disclosure, the material used to form the interconnect dielectric layer 313 may be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0130] According to embodiments of this disclosure, the connection portion 311 can be used to implement the first conductive material 308 in the first stacked subarray STA1, i.e., the respective bit lines of the first stacked subarray and the subsequently formed second stacked subarray STA2 (see description below). Figure 31A and Figure 31BThe first conductive material 308 in the first stacked subarray represents the electrical connection between corresponding bit lines of the second stacked subarray. Therefore, according to embodiments of this disclosure, the connection portion 311 can be formed of a conductive material. According to embodiments of this disclosure, the material used to form the connection portion 311 can be the same as or different from the material used to form the first conductive material 308. According to embodiments of this disclosure, the material used to form the connection portion 311 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0131] It should be noted that, in combination Figure 29A and Figure 29B Description Figure 21 Step S2108 is optional and can be omitted, therefore in Figure 21 In the diagram, step S2108 is shown within a dashed box. For example... Figure 29A and Figure 29B As shown, according to the embodiments of this disclosure, the area of ​​the connection portion 311 in the horizontal direction can be larger than the area of ​​the first conductive material 308 (but it is still necessary to ensure that there is no electrical contact between adjacent connection portions 311), so that a larger alignment tolerance can be allowed between the bit lines of the first stacked subarray STA1 and the corresponding bit lines of the subsequently formed second stacked subarray STA2. That is, due to the presence of the larger area connection portion 311, even if the first stacked subarray STA1 and the second stacked subarray STA2 are not completely aligned in the vertical direction (z direction), that is, the first stacked subarray STA1 and the second stacked subarray STA2 are misaligned in the horizontal direction, as long as there is an electrical connection between the second conductive material 308 in the second stacked subarray STA2 and the connection portion 311, the electrical connection between the corresponding bit lines of the first stacked subarray STA1 and the second stacked subarray STA2 can still be achieved.

[0132] Subsequently, Figure 21 In step S2109 shown, as Figure 30A and Figure 30B As shown, a second isolation layer 312 can be formed over the connecting dielectric layer 313 and the connecting portion 311 by, for example, a deposition process. According to embodiments of this disclosure, the second isolation layer 312 may be formed of a dielectric material that is the same as or different from the capping layer 302. According to embodiments of this disclosure, the material used to form the second isolation layer 312 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0133] According to embodiments of the present disclosure, the second isolation layer 312 can be used to achieve isolation between the first stacked subarray STA1 and the second stacked subarray STA2, while the first isolation layer 303 can be used to achieve isolation between the DRAM cell structures of each layer in each stacked subarray.

[0134] Subsequently, Figure 21 In step S2110 shown, as Figure 31A and Figure 31B As shown, this can be achieved by repeating the description above. Figure 21 Steps S2101 to S2107 form the second stacked subarray STA2. For example... Figure 31A and Figure 31B As shown, the second stacked subarray STA2 may have the same structure as the first stacked subarray STA1, and therefore its internal components are indicated by the same reference numerals as the corresponding components in the first stacked subarray STA1.

[0135] like Figure 31A and Figure 31B As shown, the first conductive material 308 in the second stacked subarray STA2 can be electrically connected to the first conductive material 308 in the first stacked subarray STA1 below it, either directly or through the connecting part 311, by penetrating the second isolation layer 312.

[0136] Thus, by means of method 2100 according to this disclosure, a circuit board 300 can be fabricated as described above. Figures 13 to 20 The described DRAM array structure 200 includes two identical stacked subarrays, each stacked subarray comprising multiple arrays as described above. Figures 1 to 12 The described DRAM cell structure is 100 or 100'.

[0137] Those skilled in the art should recognize that, although Figure 21 The method for manufacturing a DRAM array structure according to an embodiment of the present disclosure is described using two stacked subarrays as an example; however, the present disclosure is not limited thereto, and the process can be repeated on a second stacked subarray STA2. Figure 21 Steps S2108 to S2110 are used to continue forming additional stacked subarrays, which can make the DRAM array structure include three or more stacked subarrays.

[0138] Figure 32 A flowchart of a method 3200 for manufacturing a DRAM array structure according to another embodiment of the present disclosure is shown. Figures 33A to 39B These are schematic cross-sectional views illustrating various process steps of a method for manufacturing a DRAM array structure 200 according to another embodiment of this disclosure. It should be noted that... Figures 33A to 39AIt is a cross-sectional view taken along the second horizontal direction (x direction) in the vertical direction (z direction) of the DRAM array structure, and Figures 33B to 39B It is a cross-sectional view taken along the first horizontal direction (y direction) in the vertical direction (z direction) of the DRAM array structure.

[0139] The following text refers to Figure 32 as well as Figures 33A to 39B The method 3200 described above for manufacturing DRAM array structures is referenced above. Figure 21 as well as Figures 22A to 31B The difference between the described methods 2100 for manufacturing a DRAM array structure lies in the steps of forming a common electrode trench T2 and the capacitor dielectric layer 309 and the second conductive material 310 in the common electrode trench T2. Specifically, referring to the above... Figure 21 as well as Figures 22A to 31B In the described method 2100 for manufacturing a DRAM array structure, a common electrode trench is formed in each stacked subarray before sequentially stacking multiple stacked subarrays. For comparison, reference will be made below. Figure 32 as well as Figures 33A to 39B In the described method 3200 for manufacturing a DRAM array structure, a common electrode trench can be formed all at once after multiple stacked subarrays have been stacked. This simplifies the process flow and reduces manufacturing costs.

[0140] Specifically, Figure 32 Steps S3201 to S3204 of method 3200 shown above are the same as those described above. Figures 22A to 25B Description Figure 21 Steps S2101 to S2104 of method 2100 shown are exactly the same, and therefore detailed descriptions and corresponding schematic cross-sectional views of steps S3201 to S3204 of method 3200 are omitted.

[0141] Therefore, the following text begins Figure 32 The method 3200 shown is described starting with step S3204. Figure 33A and Figure 33B Based on the first stacked subarray STA1 shown in step S3204, in addition to Figure 32 In step S3205 shown, as Figure 34A and Figure 34B As shown, similar to the reference above. Figure 21 as well as Figure 29A and Figure 29BStep S2108 of the described method 2100 can be performed by, for example, a deposition process to form a connection dielectric layer 313 on the first stacked subarray STA1, and by, for example, an etching process to form connections 311 in the connection dielectric layer 313 at the positions of the first conductive material 308, i.e., each bit line. It should be noted that, in conjunction with... Figure 34A and Figure 34B Description Figure 32 Step S3205 is optional and can be omitted, therefore in Figure 32 In the diagram, step S3205 is shown with a dashed box.

[0142] Subsequently, Figure 32 In step S3206 shown, as Figure 35A and Figure 35B As shown, similar to the reference above. Figure 21 as well as Figure 30A and Figure 30B In step S2109 of the described method 2100, a second isolation layer 312 may be formed over the connecting medium layer 313 and the connecting portion 311 by, for example, a deposition process.

[0143] Subsequently, Figure 32 In step S3207 shown, as Figure 36A and Figure 36B As shown, this can be achieved by repeating the description above. Figure 32 Steps S3201 to S3204 form the second stacked subarray STA2. For example... Figure 36A and Figure 36B As shown, the second stacked subarray STA2 may have the same structure as the first stacked subarray STA1, and therefore its internal components are indicated by the same reference numerals as the corresponding components in the first stacked subarray STA1.

[0144] Subsequently, Figure 32 In step S3208 shown, as Figure 37A and Figure 37B As shown, a common electrode trench T2 extending along a first horizontal direction (y-direction) and penetrating the first stacked subarray STA1 and the second stacked subarray STA2 in a vertical direction (z-direction) can be formed in the region where no bit line via T1 is provided by an etching process. In other words, according to an embodiment of this disclosure, the common electrode trench T2 can extend to the upper surface of the capping layer 302 in the circuit board 300.

[0145] Subsequently, Figure 32 In step S3209 shown, as Figure 38A and Figure 38BAs shown, the exposed sacrificial layer 3042 and the portion of the gate dielectric layer 305 corresponding to the sacrificial layer 304 in the stacked layers 304 of the first stacked subarray STA1 and the second stacked subarray STA2 in the common electrode trench T2 can be selectively removed by an etching process. At this time, the sacrificial layer 3042 in the stacked layers 304 has been completely removed.

[0146] Subsequently, Figure 32 In step S3210 shown, as Figure 39A and Figure 39B As shown, a capacitor dielectric layer 309 can be conformally formed on the inner surface of the common electrode trench T2 by, for example, a deposition process (e.g., atomic layer deposition (ALD) process), and the remaining space of the common electrode trench T2 can be filled with a second conductive material 310.

[0147] Thus, by means of method 3200 according to this disclosure, a circuit board 300 can be fabricated as described above. Figures 13 to 20 The described DRAM array structure 200 includes two identical stacked subarrays, each stacked subarray comprising multiple arrays as described above. Figures 1 to 12 The described DRAM cell structure is 100 or 100'.

[0148] Those skilled in the art should recognize that, although Figure 32 The method for manufacturing a DRAM array structure according to an embodiment of the present disclosure is described using two stacked subarrays as an example; however, the present disclosure is not limited thereto, and the process can be repeated on a second stacked subarray STA2. Figure 32 Steps S3205 to S3207 are used to continue forming additional stacked subarrays, which can make the DRAM array structure include three or more stacked subarrays.

[0149] The DRAM cell structure constituting the DRAM array structure according to this disclosure includes two gate-around transistors and a storage capacitor arranged in a vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-around transistors are formed from the same semiconductor material layer, thus having advantages such as simple structure and good switching performance. In particular, this cell structure solves the connection problem between the source / drain of the transistors and the inner electrode of the storage capacitor by utilizing a vertical structure, making it suitable for three-dimensional vertical integration of multilayer cells. Furthermore, the DRAM array structure according to this disclosure can be stacked on a circuit board including multiple circuits, thus enabling system-level three-dimensional vertical integration, thereby greatly reducing the area overhead of the circuit system.

[0150] The method for manufacturing a three-dimensional DRAM array structure according to this disclosure can achieve three-dimensional vertical integration by stacking multiple DRAM cells, thereby increasing integration density. The vertical structure of the method is suitable for the one-time formation of multiple cells, eliminating the need for multiple epitaxial processes and fabrication processes, resulting in low manufacturing costs. In particular, the method can further improve integration density and storage capacity by sequentially stacking multiple stacked subarrays in the vertical direction.

[0151] Although this document contains numerous details, these details should not be construed as limiting the scope of this disclosure or any potentially claimed protection, but rather as descriptions of features that may be specific to a particular implementation. Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated so, in some cases one or more features may be removed from the claimed combination, and the claimed combination may involve sub-combinations or variations thereof.

Claims

1. A method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure, comprising: A plurality of stacked subarrays and a plurality of second isolation layers are sequentially formed in a vertical direction on a circuit board. The plurality of stacked subarrays are separated from each other by the plurality of second isolation layers. Each of the plurality of stacked subarrays comprises: Multiple first isolation layers and multiple stacked layers are alternately stacked in the vertical direction, each of the multiple stacked layers including a first conductive layer, a sacrificial layer and a second conductive layer; A plurality of bit line vias are formed, penetrating the plurality of first isolation layers and the plurality of stacked layers and extending to the circuit board, and are arranged in an array, wherein the area of ​​each bit line via in the stacked layer is larger than the area of ​​the bit line via in the first isolation layer; A gate dielectric layer is conformally formed on the inner surface of each bit line via, a semiconductor material layer is conformally formed on the inner surface of the gate dielectric layer, and the remaining space of the bit line via is filled with an isolation dielectric. A hole is formed through the isolation medium, and the hole is filled with a first conductive material, wherein the portion of the first conductive material corresponding to the stack is separated from the semiconductor material layer by the isolation medium, and the portion of the first conductive material corresponding to the first isolation layer is in direct contact with the semiconductor material layer; Multiple common electrode grooves are formed at locations where the bit line holes are not provided, extending along a first horizontal direction and penetrating the plurality of first isolation layers and the plurality of stacked layers; The sacrificial layer and a portion of the gate dielectric layer corresponding to the sacrificial layer are removed in the common electrode trench; and A capacitor dielectric layer is conformally formed on the inner surface of each of the plurality of common electrode slots, and the remaining space of the common electrode slot is filled with a second conductive material. In this configuration, the first conductive materials in the corresponding bit line holes of the plurality of stacked subarrays are electrically connected to each other.

2. The method according to claim 1, further comprising: A connection is formed on each of the plurality of stacked subarrays except the topmost stacked subarray at a position corresponding to a bit line hole, such that the first conductive material in the corresponding bit line hole of the plurality of stacked subarrays is electrically connected to each other through the connection.

3. The method according to claim 1, wherein, The circuit board is a semiconductor substrate on which multiple circuits are disposed. The circuit board is provided with a pad structure and a cover layer covering the circuit board.

4. The method according to claim 3, wherein, The first conductive material of the bottommost stacked subarray of the plurality of stacked subarrays contacts the pad structure.

5. The method according to claim 3, wherein, The second isolation layer is formed of the same or different material as the cover layer.

6. The method according to claim 1, wherein, When forming each of the plurality of stacked subarrays At each bit line via in each stack, the gate dielectric layer, the semiconductor material layer, and the capacitor dielectric layer form a DRAM cell structure with a tubular structure, which includes a first gate-around transistor, a second gate-around transistor, and a storage capacitor. The gate dielectric layer forms the gate dielectric of the first gate-around transistor and the second gate-around transistor. The semiconductor material layer forms the source / drain regions and channel regions of the first gate-around transistor and the second gate-around transistor, as well as the internal electrodes of the storage capacitor. The capacitor dielectric layer forms the capacitor dielectric of the storage capacitor, and The first gate-enclosed transistor and the second gate-enclosed transistor are connected in parallel via corresponding bit lines.

7. The method according to claim 6, wherein, When forming each of the plurality of stacked subarrays In each stack, the first conductive layer forms the gate of the first gate-around transistor in each row of DRAM cell structure and the first word line connected thereto, and In each stack, the second conductive layer forms the gate of the second gate-around transistor in each row of DRAM cell structure and the second word line connected thereto.

8. The method according to claim 6, wherein, When forming each of the plurality of stacked subarrays The second conductive material includes a vertical portion extending in the common electrode groove in the vertical direction and the first horizontal direction, and a horizontal portion located in the cavity formed after the removal of the sacrificial layer and the portion of the gate dielectric layer in the first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. The horizontal portion of the second conductive material forms the external electrode of the storage capacitor, and The vertical portion of the second conductive material forms the source line.

9. The method according to claim 7, wherein, When forming each of the plurality of stacked subarrays In each of the plurality of stacks, the first word line is connected to the second word line.

10. The method according to claim 6, wherein, The bit lines in the multiple stacked subarrays are not perfectly aligned in the vertical direction.

11. The method according to claim 1, wherein, Forming each of the plurality of stacked subarrays further includes: The doping type, doping concentration, and / or atomic composition ratio of a specific portion of the semiconductor material layer are altered through a material modification process.

12. The method according to claim 1, wherein, The semiconductor material layer includes a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

13. The method according to claim 1, wherein, The semiconductor material layer includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof.

14. The method according to claim 1, wherein, In each stack, the area of ​​each bit line via in the sacrificial layer is greater than the area of ​​the bit line via in the first conductive layer and the second conductive layer.

15. The method according to claim 1, wherein, Each bit line hole has a circular cross-section.

16. The method according to claim 1, wherein, The isolation medium is formed of a low-K material.

17. The method according to claim 1, wherein, A cavity is provided in the isolation medium.

18. The method according to claim 1, wherein, The capacitor dielectric layer is formed of a high-K material.

19. The method according to claim 1, wherein, The number of stacks included in the plurality of stacked subarrays may be the same or different from each other.

20. A method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure, comprising: A plurality of stacked subarrays and a plurality of second isolation layers are sequentially formed in a vertical direction on a circuit board. The plurality of stacked subarrays are separated from each other by the plurality of second isolation layers. Each of the plurality of stacked subarrays comprises: Multiple first isolation layers and multiple stacked layers are alternately stacked in the vertical direction, each of the multiple stacked layers including a first conductive layer, a sacrificial layer and a second conductive layer; A plurality of bit line vias are formed, penetrating the plurality of first isolation layers and the plurality of stacked layers and extending to the circuit board, and are arranged in an array, wherein the area of ​​each bit line via in the stacked layer is larger than the area of ​​the bit line via in the first isolation layer; A gate dielectric layer is conformally formed on the inner surface of each bit line via, a semiconductor material layer is conformally formed on the inner surface of the gate dielectric layer, and the remaining space of the bit line via is filled with an isolation dielectric; and A hole is formed through the isolation medium, and the hole is filled with a first conductive material, wherein the portion of the first conductive material corresponding to the stack is separated from the semiconductor material layer by the isolation medium, and the portion of the first conductive material corresponding to the first isolation layer is in direct contact with the semiconductor material layer; Multiple common electrode slots are formed at locations where the bit line holes are not provided, extending along the first horizontal direction and penetrating the multiple stacked subarrays; In the common electrode trench, the sacrificial layer and the corresponding portion of the gate dielectric layer in each of the plurality of stacked subarrays are removed; and A capacitor dielectric layer is conformally formed on the inner surface of each of the plurality of common electrode slots, and the remaining space of the common electrode slot is filled with a second conductive material. In this configuration, the first conductive materials in the corresponding bit line holes of the plurality of stacked subarrays are electrically connected to each other.

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