Semiconductor structure for electrostatic discharge protection and manufacturing method thereof

Abstract

The invention provides a semiconductor structure for electrostatic discharge protection and a manufacturing method thereof, and aims to solve the technical problem that local overheating failure is easily caused by non-uniform starting of electrostatic discharge current of an existing grid grounding NMOS (N-channel Metal Oxide Semiconductor) device. The semiconductor structure comprises a substrate, an active region, a grid, a source and a drain. The drain electrode comprises a first area where a refractory silicide layer is formed and a second area where no refractory silicide layer is formed in the width direction of the drain electrode. According to the manufacturing method, the structure is realized by selectively forming the refractory silicide barrier layer on the drain region and then carrying out a silicification process. According to the invention, the second region with high resistance is used as a ballast resistor, the current is forced to be uniformly distributed in an electrostatic discharge event, and the formation of local hot spots is effectively avoided, so that the electrostatic discharge endurance and reliability of the device are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure for electrostatic discharge protection and a method for manufacturing the same. Background Technology

[0002] FDSOI (fully depletion silicon on insulator) technology, due to its structural characteristics, features an ultra-thin insulating layer, also known as a buried oxide layer (BOX), on the substrate. A very thin silicon film is used to fabricate the transistor channel. Because the channel is so thin, no doping process is required, and the depletion layer fills the entire channel region, resulting in a fully depleted transistor. Figure 1 As shown. Structurally, FD-SOI transistors exhibit superior electrostatic characteristics compared to traditional bulk silicon technology. The buried oxide layer reduces parasitic capacitance between the source and drain and effectively suppresses electron flow from the source to the drain, thereby significantly reducing leakage current that leads to performance degradation. Furthermore, FD-SOI offers many other unique advantages, including back-bias capability, excellent transistor matching characteristics, the ability to operate at near-threshold low supply voltages, ultra-low sensitivity to radiation, and very high intrinsic transistor operating speed. These advantages enable its operation in millimeter-wave frequency band applications.

[0003] Despite the numerous advantages of FDSOI, developing an electrostatic discharge (ESD) protection network entirely on the SOI remains a challenge in practical applications. The thickness limitation of silicon-on-insulator (SOI) (typically less than 10 nanometers) precludes the use of traditional planar diode structures or shallow isolation (STI) diodes. Furthermore, the presence of the buried oxide layer causes the capacitance-voltage ratio of FDSOI devices to approach zero in the accumulation region due to the inability to obtain carrier replenishment from the substrate. This abrupt change from the accumulation region to the inversion region further degrades the capacitance. Figure 2 As shown. Furthermore, due to the low doping concentration of SOI, the base of the NPN transistor in its parasitic bipolar junction transistor (BJT) has very weak electrostatic control, making it easily triggered and reducing the overall discharge current. The breakdown voltage of the hybrid bulk region is higher than that of the SOI region (thin film), causing the device to fail to protect itself; that is, the device on the SOI is damaged, but the corresponding protection device has not yet activated. Figure 3 As shown.

[0004] The current structural approach involves introducing a bipolar MOS structure, which introduces a high resistance between the gate and the substrate to reduce the trigger voltage (when the electric field reaches a certain strength, avalanche breakdown occurs, and the drain voltage at this point is called the trigger voltage) while maintaining a high current. Figure 4 andFigure 5 as shown in FIG. 1, Figure 4 a conventional gate-grounded nmos (GGNMOS) is shown, Figure 5 a bipolar MOS in FDSOI is shown. On one hand, it improves the total current of the device on SOI, and on the other hand, it reduces the trigger voltage of the device on hybrid bulk, so that it can open the protection internal circuit before SOI is damaged. However, this structure still uses the original conventional MOS structure, and the resistance of the corresponding substrate is not uniform due to the uneven distribution of the distance from the gate, so this structure has the same non-uniform opening problem as the conventional GGNMOS.

[0005] Please refer to Figure 6 which shows a schematic diagram of the layout of the ESD protection structure of the IO device in the prior art; please refer to Figure 7 which shows a schematic diagram of the ESD protection structure of the FDSOI device in the prior art along Figure 6 the AA' plane.

[0006] Therefore, the industry urgently needs a new technical solution to improve the current opening uniformity of the ESD protection device in the FDSOI process, thereby improving the overall protection capability. SUMMARY

[0007] The technical problem to be solved by the present application is that the GGNMOS electrostatic protection device for FDSOI process in the prior art has the problem of non-uniform current opening. This non-uniformity causes the current to concentrate in the local area of the device during the electrostatic discharge event, causing local overheating and causing the device to fail prematurely far below its theoretical maximum tolerance, thereby reducing the performance and reliability of the entire ESD protection structure.

[0008] To achieve the above object and other related objects, the present application provides a semiconductor structure for electrostatic discharge protection, comprising:

[0009] a substrate;

[0010] an active region formed on the substrate;

[0011] a gate formed on the active region; and

[0012] a source and a drain formed in the active region and located on both sides of the gate;

[0013] wherein the drain includes, in the direction along its width:

[0014] a first region having a refractory silicide layer formed on the surface of the first region; and

[0015] a second region having no refractory silicide layer formed on the surface of the second region.

[0016] Preferably, the first regions and the second regions are arranged alternately along a width direction of the drain.

[0017] Preferably, the substrate is a P-type substrate.

[0018] Preferably, the active region is formed in a P-type well; and the source and the drain are N-type doped regions.

[0019] Preferably, the method further comprises forming a P-type doped contact region in the P-type well, the P-type doped contact region being used to provide electrical connection for the P-type well.

[0020] Preferably, the semiconductor structure is configured as a gate-grounded NMOS structure, wherein the gate, the source and the P-type well are electrically connected to a ground terminal, and the drain is electrically connected to a pad terminal for electrostatic discharge.

[0021] Preferably, the structure is a full-depletion silicon-on-insulator structure, and further comprises: a buried oxide layer formed on the substrate; and the active region formed on the buried oxide layer.

[0022] Preferably, the semiconductor structure further comprises a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure being used to define the active region.

[0023] Preferably, a refractory silicide barrier layer is arranged on the surface of the second region, the refractory silicide barrier layer being used to prevent the formation of a refractory silicide layer in a silicidation process.

[0024] The present application also provides a method for manufacturing the semiconductor structure for electrostatic discharge protection as described above, comprising:

[0025] Step one, providing a substrate, and forming a gate structure and source and drain regions on both sides of the gate structure on the substrate;

[0026] Step two, forming a refractory silicide barrier layer on the drain region to divide the drain region into a first region exposed and a second region covered by the refractory silicide barrier layer;

[0027] Step three, performing a silicidation process to form a refractory silicide layer on the surface of the first region, and no refractory silicide layer is formed on the surface of the second region.

[0028] Preferably, in step one, the substrate is a P-type substrate.

[0029] Preferably, in step one, after the P-type substrate is provided, before the gate structure is formed, the method further comprises forming a P-type well in the P-type substrate.

[0030] Preferably, after forming the gate structure in step one, the method further comprises: forming the source region and the drain region of N-type doping in the P-type well by N-type ion implantation.

[0031] Preferably, in step one, the substrate is a silicon-on-insulator substrate comprising a substrate layer and a buried oxide layer formed thereon, and the gate structure, the source region and the drain region are formed in a silicon film above the buried oxide layer.

[0032] As described above, the semiconductor structure for electrostatic discharge protection and the manufacturing method thereof have the following beneficial effects:

[0033] The present application builds a ballast resistance network by alternately arranging a low-resistance first region with a refractory silicide layer and a high-resistance second region without a refractory silicide layer along the width direction of the drain of the GGNMOS structure. When an ESD event occurs, the low-resistance first region ensures that the discharge path has a low enough on-resistance to quickly discharge a large part of the current, and at the same time, the high-resistance second region plays a key ballast role, which can force the current to be more evenly distributed on the entire device width, effectively avoiding the formation of current congestion and local hot spots.

[0034] Therefore, the structure and method of the present application significantly improve the current opening uniformity of the GGNMOS device, greatly improve the breakdown current and overall ESD tolerance of the device, prevent premature breakdown due to local overheating, and comprehensively improve the performance and reliability of the ESD protection structure. The scheme is highly compatible with existing semiconductor processes and easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A structure schematic diagram of a full-depletion silicon-on-insulator (FDSOI) in the prior art is shown;

[0036] Figure 2 A comparison schematic diagram of the capacitance-voltage relationship under the FDSOI and bulk silicon structure in the prior art is shown;

[0037] Figure 3 A transmission line pulse (TLP) characteristic schematic diagram of a gate-grounded NMOS (GGNMOS) device under different substrate types in the prior art is shown;

[0038] Figure 4 A schematic diagram of a conventional gate-grounded structure (GGNMOS) in the prior art is shown;

[0039] Figure 5 A schematic diagram of a bipolar MOS (Bipolar MOS) structure in the prior art is shown;

[0040] Figure 6 Figure 1 shows a layout diagram of an ESD protection structure of an IO device in the prior art;

[0041] Figure 7 Figure 2 shows a cross-sectional diagram of an ESD protection structure of an FDSOI device in the prior art along line AA'; Figure 6

[0042] Figure 8 Figure 3 shows a layout diagram of an ESD protection structure of an embodiment of the present application;

[0043] Figure 9 Figure 4 shows a cross-sectional diagram of a semiconductor structure of an embodiment of the present application along line AA'; Figure 8

[0044] Figure 10 Figure 5 shows a cross-sectional diagram of a semiconductor structure of an embodiment of the present application along line BB'; Figure 8

[0045] Figure 6 shows a manufacturing method of a semiconductor structure for ESD protection of an embodiment of the present application. Figure 11 DETAILED DESCRIPTION

[0046] Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description of the embodiments of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the present description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0047] An embodiment of the present application provides a semiconductor structure for ESD protection. When an ESD event occurs, the ESD protection device needs to be able to quickly and effectively discharge a large amount of transient current to the ground to protect the internal core circuit. However, the conventional ESD protection device, especially the gate-grounded NMOS (GGNMOS) structure, often has the problem of non-uniform current opening, which causes the current to concentrate in the local area of the device, triggering local overheating and premature failure, which limits the overall protection capability of the device.

[0048] The present application effectively solves this problem by designing a resistance distribution on the drain 105.

[0049] A semiconductor structure for ESD protection, comprising:

[0050] a substrate 101;

[0051] In some embodiments, the substrate 101 is a P-type substrate.

[0052] ​​​In some embodiments, the structure is a fully depleted silicon-on-insulator (FDSOI) structure, further comprising: a buried oxide layer formed on the substrate 101; and an active region formed on the buried oxide layer. The buried oxide layer can effectively isolate the substrate 101 from the active region, reduce parasitic capacitance, suppress leakage current, and thus make the device have excellent high-frequency performance and low-power consumption characteristics.

[0053] In some embodiments, the silicon film thickness of the active region is less than 10 nanometers to ensure that the device operates in a fully depleted mode.

[0054] an active region formed on the substrate 101;

[0055] In some embodiments, the semiconductor structure further comprises a shallow trench isolation structure 103 formed in the substrate 101, which is used to define the active region.

[0056] In some embodiments, the active region is formed within a P-type well 102; the source and drain 105 are N-type doped regions.

[0057] In some embodiments, further comprising a P-type doped contact region 106 formed within the P-type well 102, which is used to provide electrical connection for the P-type well 102.

[0058] a gate 104 formed on the active region; and

[0059] a source and a drain 105 in the active region and located on both sides of the gate 104;

[0060] wherein the drain 105, in the direction along its width, comprises:

[0061] a first region, on the surface of which a refractory silicide layer 108 is formed; and

[0062] a second region, on the surface of which no refractory silicide layer is formed.

[0063] In some embodiments, referring to Figure 8 , a refractory silicide barrier layer 107 is provided on the surface of the second region, which is used to prevent the formation of the refractory silicide layer 108 in the silicidation process. The barrier layer can be a physical layer defined by a "block" pattern on the layout, usually composed of dielectric materials such as silicon dioxide or silicon nitride.

[0064] In some embodiments, the first region and the second region are alternately arranged along the width direction of the drain 105. This kind of alternating layout forms a parallel resistance network in the drain region, which allows the current to be redistributed across the entire device width.

[0065] By forming regions with different surface resistivity in the width direction of the drain 105, the current path at the time of an electrostatic discharge event can be effectively regulated. Specifically, the first region (low resistance region) with refractory silicide layer 108 can ensure that the electrostatic discharge path has sufficiently low on-resistance, thereby rapidly discharging large currents and protecting the internal circuit from over-voltage surges. At the same time, the second region (high resistance region) without refractory silicide layer acts as a kind of series ballast resistance, which can force the current to be more evenly distributed across the entire device width, avoiding local hot spots caused by current flowing only through the path with the smallest resistance. This uniform current distribution significantly improves the breakdown current of the device, enhances the ability of the device to withstand electrostatic energy, and prevents premature failure due to local overheating, thereby improving the overall performance and reliability of the electrostatic discharge protection structure.

[0066] In some embodiments, the semiconductor structure is configured as a gate-grounded NMOS (GGNMOS) structure, in which the gate 104, source, and P-type well 102 are collectively electrically connected to the ground terminal, and the drain 105 is electrically connected to the pad terminal for electrostatic discharge. When a high-voltage electrostatic pulse occurs at the pad terminal, the reverse-biased junction between the drain 105 and the P-type well 102 undergoes avalanche breakdown, generating a current that flows through the P-type well resistance, raising the potential of the P-type well 102, and in turn forward-biases the PN junction between the source and the P-type well 102, turning on the parasitic NPN bipolar transistor, thereby forming a low-impedance discharge path that safely discharges the electrostatic current to ground. The structure of the present application optimizes the current distribution in the drain 105 region of this discharge path.

[0067] To more clearly illustrate the structure of the present application, please refer to Figure 9 which shows the cross-sectional view of a semiconductor structure according to an embodiment of the present application. Figure 8Schematic cross-section of plan view AA'. The structure includes a P-type substrate 101 on which a P-type well 102 is formed. A shallow trench isolation (STI) structure 103 is used to define the active region for forming the device in the substrate 101. The semiconductor structure is specifically a multi-finger gate-grounded NMOS device, in which an N-type drain 105 as a common drain is formed in the P-type well 102, and a gate 104 and an N-type source are located on both sides thereon. As shown, a low-resistance refractory silicide layer 108 is formed on the surface of the source. Crucially, on the surface of the drain 105, in the region shown in this cross-section, a refractory silicide barrier layer 107 (SAB) is provided so that the surface of this region does not form a refractory silicide layer, thereby forming a relatively high-resistance second region. In other regions along the drain width direction (cross-section not shown), this barrier layer is not provided, thereby forming a low-resistance first region with the refractory silicide layer 108. In terms of electrical connections, the drain 105 is connected to the pad that requires electrostatic protection, while the gate 104, the source, and the P-type well 102, which is electrically connected through the P-type doped contact region 106, are all connected to the ground terminal (GND), forming a complete GGNMOS protection circuit.

[0068] To further illustrate the structure of this invention, please refer to [link / reference]. Figure 10 It shows along Figure 8 This is a cross-sectional view along the BB' direction of the planar diagram, perpendicular to the channel length of the device and extending through the drain region. This cross-sectional view primarily shows the drain structure formed on the P-type substrate 101 and the P-type well 102. Specifically, this cross-section shows the structural variation of the N-type doped drain 105 along its width. In some regions, the surface of the drain 105 is covered by a refractory silicide barrier layer 107 (SAB), thus forming a second region where no refractory silicide layer forms on the surface. In other adjacent regions, the surface of the drain 105 is exposed, and a low-resistance refractory silicide layer 108 forms after the silicide process, thus forming a first region. A shallow trench isolation (STI) structure 103 defines the lateral boundary of the drain region. This alternating arrangement of low-resistance regions (first region) and high-resistance regions (second region) along the device width direction achieves effective ballasting of the electrostatic discharge current. When an ESD event occurs, the current is forced to flow more evenly across the entire width of the drain 105, rather than just concentrated in the area with the shortest turn-on path, thereby effectively preventing the formation of local hot spots and significantly improving the device's ESD tolerance.

[0069] Please see Figure 11 The present invention also provides a method for manufacturing a semiconductor structure with improved electrostatic discharge uniformity, comprising the following steps:

[0070] Step 1. Provide a substrate 101, and form a gate structure 104 and source and drain regions 105 on both sides of the gate structure 104 on the substrate 101.

[0071] In some embodiments, in step 1, the substrate 101 is a P-type substrate.

[0072] In some embodiments, in step 1, the substrate 101 is a silicon-on-insulator substrate including a substrate layer and a buried oxide layer formed thereon, and the gate structure 104 and the source and drain regions 105 are formed in a silicon film on the buried oxide layer.

[0073] In some embodiments, in step 1, after providing the P-type substrate 101 and before forming the gate structure 104, the method further includes forming a P-type well 102 in the P-type substrate 101.

[0074] In some embodiments, in step 1, after forming the gate structure 104, the method further includes forming N-type doped source and drain regions 105 in the P-type well 102 by N-type ion implantation. More specifically, step 1 can include first defining an active region and forming a shallow trench isolation structure 103 by a shallow trench isolation (STI) process on the P-type substrate 101. Then, forming the P-type well 102 by ion implantation in the active region. Next, depositing a gate dielectric layer (such as GOX / HK) and a gate electrode material (such as polysilicon or metal gate), and forming the gate structure 104 by photolithography and etching. Finally, forming the source and drain regions 105 in the P-type well 102 on both sides of the gate structure 104 by N-type ion implantation, and further forming a P-type doped contact region 106 for electrical connection of the P-type well 102.

[0075] Step 2. Form a refractory silicide barrier layer 107 on the drain region 105 to divide the drain region 105 into a first region exposed and a second region covered by the refractory silicide barrier layer 107.

[0076] This step is the key to the present application. By adding a photolithography mask (usually referred to as the refractory silicide barrier layer 107 pattern on the layout, i.e. SAB layer), the pattern of the refractory silicide barrier layer 107 on the drain region 105 can be accurately controlled. The barrier layer can be a dielectric material such as silicon oxide or silicon nitride, and its formation method is compatible with existing semiconductor processes, such as chemical vapor deposition (CVD) followed by patterning and etching.

[0077] Step 3. Perform a silicidation process to form a refractory silicide layer 108 on the surface of the first region, while no refractory silicide layer is formed on the surface of the second region.

[0078] The silicide process is typically a self-aligned silicide process, which can form a low-resistivity refractory silicide layer such as tungsten silicide, cobalt silicide, or nickel silicide. Due to the presence of the refractory silicide barrier layer 107, the silicide reaction only occurs in the first region where the drain region 105 is exposed, while in the second region covered by the barrier layer, the surface remains a high-resistivity doped silicon surface.

[0079] In some embodiments, the semiconductor structure is configured as a gate-grounded NMOS (GGNMOS) structure, wherein the gate 104, source, and P-type well 102 are electrically connected to the ground terminal, and the drain 105 is electrically connected to the electrostatic discharge pad terminal. When a high-voltage electrostatic pulse occurs at the pad terminal, the reverse-biased junction between the drain 105 and the P-type well 102 undergoes avalanche breakdown. The resulting current flows through the P-type well resistor, raising the potential of the P-type well 102, which in turn forward conducts the PN junction between the source and the P-type well 102, turning on the parasitic NPN bipolar transistor, thereby forming a low-impedance discharge path to safely discharge the electrostatic current to ground. The structure of the present invention optimizes the current distribution in the drain 105 region of this discharge path.

[0080] For a clearer illustration of the structure of this invention, please refer to [link / reference]. Figure 9 It illustrates a semiconductor structure along an embodiment of the present invention. Figure 8 Schematic cross-section of plan view AA'. The structure includes a P-type substrate 101 on which a P-type well 102 is formed. A shallow trench isolation (STI) structure 103 is used to define the active region for forming the device in the substrate 101. The semiconductor structure is specifically a multi-finger gate-grounded NMOS device, in which an N-type drain 105 as a common drain is formed in the P-type well 102, and a gate 104 and an N-type source are located on both sides thereon. As shown, a low-resistance refractory silicide layer 108 is formed on the surface of the source. Crucially, on the surface of the drain 105, in the region shown in this cross-section, a refractory silicide barrier layer 107 (SAB) is provided so that the surface of this region does not form a refractory silicide layer, thereby forming a relatively high-resistance second region. In other regions along the drain width direction (cross-section not shown), this barrier layer is not provided, thereby forming a low-resistance first region with the refractory silicide layer 108. In terms of electrical connections, the drain 105 is connected to the pad that requires electrostatic protection, while the gate 104, the source, and the P-type well 102, which is electrically connected through the P-type doped contact region 106, are all connected to the ground terminal (GND), forming a complete GGNMOS protection circuit.

[0081] To further illustrate the structure of this invention, please refer to [link / reference]. Figure 10 It shows along Figure 8Figure 6 is a cross-sectional view of the device along the BB' direction. The cross-section is perpendicular to the channel length direction of the device and passes through the drain region. This cross-sectional view mainly illustrates the drain structure formed on top of the P-type substrate 101 and P-type well 102. Specifically, the cross-section illustrates the structure variation of the N-type doped drain 105 along its width direction. In certain regions, the surface of the drain 105 is covered by a refractory silicide block layer 107 (SAB), thus constituting a second region where no refractory silicide layer is formed on the surface. In other regions adjacent to the first region, the surface of the drain 105 is exposed and will form a low-resistance refractory silicide layer 108 after the silicidation process, thus constituting a first region. The shallow trench isolation (STI) structure 103 defines the lateral boundary of the drain region. This alternating arrangement of low-resistance regions (first regions) and high-resistance regions (second regions) along the device width direction effectively ballasts the electrostatic discharge current. When an ESD event occurs, the current is forced to flow more uniformly across the entire width of the drain 105, rather than being concentrated in the region with the shortest on-path, thus effectively preventing the formation of local hot spots and significantly improving the ESD tolerance of the device.

[0082] The semiconductor structure manufactured by the above method can significantly improve the current uniformity of the gate-grounded NMOS in an electrostatic discharge event with minimal process modification (only one additional photolithography mask) and cost, thus significantly improving the ruggedness and reliability of the device without sacrificing its inherent discharge capability, and is particularly suitable for advanced FDSOI process nodes with stringent electrostatic protection requirements.

[0083] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only show the components related to the present application in the diagrams, rather than being drawn according to the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of its type, number and proportion, and the layout pattern of the components can also be more complex.

[0084] The above embodiments only illustratively explain the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A semiconductor structure for electrostatic discharge protection, characterized by, The semiconductor structure comprises: a substrate; an active region formed on the substrate; a gate formed on the active region; and a source and a drain formed in the active region and located on both sides of the gate; wherein the drain comprises, along a direction of its width: a first region on a surface of which a refractory silicide layer is formed; and a second region on a surface of which no refractory silicide layer is formed. The first region and the second region are alternately arranged along the width direction of the drain.

2. The semiconductor structure for electrostatic discharge protection according to claim 1, wherein: The substrate is a P-type substrate.

3. The semiconductor structure for electrostatic discharge protection according to claim 1, wherein: The active region is formed in a P-type well; the source and the drain are N-type doped regions.

4. The semiconductor structure for electrostatic discharge protection according to claim 3, wherein: A P-type doped contact region formed in the P-type well is further included for providing electrical connection for the P-type well.

5. The semiconductor structure for electrostatic discharge protection according to claim 4, wherein: The semiconductor structure is configured as a gate-grounded NMOS structure, wherein the gate, the source and the P-type well are collectively electrically connected to a ground terminal, and the drain is electrically connected to a pad terminal for electrostatic discharge.

6. The semiconductor structure for electrostatic discharge protection according to claim 4, wherein: The structure is a full-depletion silicon-on-insulator structure, further comprising: a buried oxide layer formed on the substrate; and the active region formed on the buried oxide layer.

7. The semiconductor structure for electrostatic discharge protection according to claim 1, wherein: The semiconductor structure further comprises a shallow trench isolation structure formed in the substrate for defining the active region.

8. The semiconductor structure for electrostatic discharge protection according to claim 1, wherein: A refractory silicide barrier layer is arranged on the surface of the second region for preventing the formation of the refractory silicide layer in a silicidation process.

9. The semiconductor structure for electrostatic discharge protection according to claim 1, wherein: The method comprises:

10. A method of manufacturing a semiconductor structure for electrostatic discharge protection, characterized in that, Step 1: providing a substrate, and forming a gate structure and a source region and a drain region located on both sides of the gate structure on the substrate; Step 2: forming a refractory silicide barrier layer on the drain region to divide the drain region into a first region exposed and a second region covered by the refractory silicide barrier layer; Step 3: performing a silicidation process to form a refractory silicide layer on the surface of the first region, and no refractory silicide layer is formed on the surface of the second region. In Step 1, the substrate is a P-type substrate.

11. The method of manufacturing a semiconductor structure for electrostatic discharge protection according to claim 10, wherein: In Step 1, after the P-type substrate is provided and before the gate structure is formed, the method further comprises: forming a P-type well in the P-type substrate.

12. The method of manufacturing a semiconductor structure for electrostatic discharge protection according to claim 11, wherein: In Step 1, after the gate structure is formed, the method further comprises: forming the source region and the drain region doped with N-type in the P-type well by N-type ion implantation.

13. The method of manufacturing a semiconductor structure for electrostatic discharge protection according to claim 12, wherein: In Step 1, the substrate is a silicon-on-insulator substrate comprising a substrate layer and a buried oxide layer formed thereon, and the gate structure, the source region and the drain region are formed in a silicon film above the buried oxide layer.

14. The method of manufacturing a semiconductor structure for electrostatic discharge protection of claim 10, wherein: ​

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