An IGBT device with anti-latch-up capability

Abstract

This invention relates to an IGBT device with latch-up resistance, belonging to the field of power semiconductor device technology. The invention proposes using a segmented N-type source region and segmented source contact vias, and controlling the magnitude of the introduced ballast resistor by adjusting the overlap area between the N-type source region and the source contact vias, thereby controlling the N-type source region potential during conduction and achieving latch-up resistance. The structure proposed in this invention, which reduces the latch-up risk of IGBT devices, employs a method of providing ballast resistance by controlling the electron flow path itself. This method is simple to implement, requires low equipment standards, eliminates the need for additional P-type injection, and effectively suppresses latch-up while improving short-circuit capability.

Description

Technical Field

[0001] This invention belongs to the field of IGBT device technology and relates to an IGBT device with anti-latch-up capability. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) are composite, fully controllable, voltage-driven power semiconductor devices composed of a bipolar transistor and a MOSFET, combining the high input impedance of a MOSFET and the low on-state voltage drop of a GTR. Currently, IGBTs have become the mainstream devices in power electronic equipment, with wide applications in switching power supplies, rectifiers, inverters, UPS, and other fields.

[0003] Compared to N-channel MOSFETs, N-channel IGBTs have an additional P-type collector layer on the back, resulting in a parasitic pnpn structure in the vertical direction. In the past, to suppress latch-up caused by parasitic pnpn and thus device failure, existing technologies typically used source contact holes to short-circuit the N-type source region and the P-type body region, and added a P-type injection between the trench gate. However, as device capabilities have increased year by year, the number of cells per unit area in IGBT devices has gradually increased, and the mesa region between the trench gate has become narrower and narrower, making it more difficult to align the P-plus injection. Moreover, as the mesa region becomes narrower, the P-plus injection will have a serious impact on parameters such as the threshold voltage.

[0004] Therefore, providing an IGBT device that effectively suppresses latch-up and is unaffected by small device pitch is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned research status and existing problems, the present invention provides an IGBT device with anti-latch-up capability, which overcomes the shortcomings of the prior art, can effectively suppress the occurrence of latch-up, and is not affected by the small pitch of the device.

[0006] The specific plan to achieve the above objectives is as follows:

[0007] An IGBT device with latch-up resistance includes a segmented N-type source region and a segmented source region contact hole region. The N-type source region and the source region contact hole region have an overlapping area. The size of the overlapping area is adjustable to control the magnitude of the introduced ballast resistor, thereby achieving latch-up resistance.

[0008] Preferably, it also includes an N-type drift region, in which a plurality of groove grids are provided at the upper position, and a P-type body region is formed between the groove grids, the lower boundary of the P-type body region being higher than the position of the bottom of the groove grid;

[0009] The segmented N-type source region is located between the trench gates and embedded above the P-type body region;

[0010] The segmented source region contact hole area is located between the trench gates and embedded above the P-type body region. The source region contact hole area is used to form an ohmic contact with the source metal.

[0011] Preferably, the trench gate is filled with gate polysilicon and the area between the gate polysilicon and the trench gate sidewall is filled with gate oxide.

[0012] Preferably, the trench gate is provided with an insulating dielectric layer, and the insulating dielectric layer is provided with a source metal. The source metal makes ohmic contact with the P-type body region and the N-type source region through the source region contact hole region, respectively.

[0013] Preferably, an N-type buffer layer, a P-type drain region, and a drain metal are sequentially provided on the lower side of the N-type drift region, and the P-type drain region and the drain metal form an ohmic contact.

[0014] Preferably, the area of ​​the overlapping region is smaller than the area of ​​the contacting N-type source region and the source region contact hole region, and the width and length of the overlapping region between the source region contact hole and the N-type source region are adjustable.

[0015] Preferably, the length of the N-type source region is 1–10 μm, the segment interval length is 1–10 μm, the length of the overlapping region is 1–5 μm, and the length of the source region contact hole is the sum of the N-type source region interval length and the overlapping region length.

[0016] Preferably, the segmented N-type source region and the segmented source region contact hole region are spaced apart between every two of the trench gates.

[0017] Preferably, the segmented N-type source region extends from one side of the trench gate to the other side between the two trench gates.

[0018] Preferably, the segmented N-type source region between the two trench gates contacts only one side of the trench gate; and adjacent segmented N-type source regions located between the two trench gates contact the trench gates on different sides.

[0019] The present invention has the following advantages over the prior art:

[0020] The structural arrangement of the N-type source region and the segmented source region contact hole region in this invention allows the source metal to be partially connected to the N-type source region rather than being connected over a large area. This simplifies the process, reduces equipment requirements, and eliminates the need for additional P-type injection. As a result, the width and length of the path through which source electrons converge to the source metal via the inversion channel when the device is in the on state can be freely adjusted. An adjustable ballast resistor is introduced to control the N-type source region potential, suppressing pnpn latch-up and improving the short-circuit capability and latch-up resistance of the IGBT at both room temperature and high temperature. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention, and those skilled in the art can obtain other drawings based on the provided drawings without creative effort.

[0022] Figure 1 This is a three-dimensional schematic diagram of the cell layout structure of the IGBT device of the present invention. Figure 1 ;

[0023] Figure 2 This is a three-dimensional schematic diagram of the cell layout structure of the IGBT device of the present invention. Figure 2 ;

[0024] Figure 3 This is a cross-sectional schematic diagram of the IGBT device of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Example 1

[0027] This embodiment provides an IGBT device structure. Please refer to [link / reference]. Figure 1 and Figure 3 The figures show a perspective view and a cross-sectional view of the IGBT device structure, as shown in the figure. The IGBT device structure includes:

[0028] The segmented N-type source region 6 and the segmented source region contact hole region 7 have an overlapping region 8, the size of which is adjustable to control the magnitude of the introduced ballast resistor.

[0029] Below the P-type body region 5, an N-type drift region 1 is provided. Several trench gates 2 are provided above the N-type drift region 1. The P-type body region 5 is located between the trench gates 2. The lower boundary of the P-type body region 5 is higher than the bottom of the trench gate 2. The segmented N-type source region 6 is located between the trench gates 3 and is embedded above the P-type body region 5. The segmented source region contact hole region 7 is located between the trench gates 3 and is embedded above the P-type body region 5. The source region contact hole region 7 is used to form an ohmic contact with the source metal.

[0030] The trench gate 2 is filled with gate polysilicon 3 and the gate oxide layer 4 is filled between the outer side of the gate polysilicon 3 and the sidewall of the trench gate 2.

[0031] The trench grid 2 is provided with an insulating dielectric layer 9, and the insulating dielectric layer 9 is provided with a source metal 10. The source metal 10 makes ohmic contact with the P-type body region 5 and the N-type source region 6 through the source region contact hole region 7 respectively.

[0032] An N-type buffer layer 11, a P-type drain region 12, and a drain metal 13 are sequentially arranged on the lower side of the N-type drift region 1. The P-type drain region 12 and the drain metal 13 form an ohmic contact.

[0033] The area of ​​the overlapping region 8 is smaller than the area of ​​the contacting N-type source region 6 and the source region contact hole region 7. The source region contact hole 6 and the N-type source region 5 are not in complete contact. The width and length of the overlapping region 8 of the source region contact hole 6 and the N-type source region 5 are adjustable.

[0034] The length of the N-type source region 6 is 1–10 μm, the segment interval length is 1–10 μm, the length of the overlapping region 8 is 1–5 μm, and the length of the source region contact hole 7 is the sum of the interval length of the N-type source region 6 and the length of the overlapping region 8. In this embodiment, as shown... Figure 1 As shown, the source region contact hole 6 and the N-type source region 5 have an overlap region 8 with a length of 1 μm.

[0035] Segmented N-type source regions 6 and segmented source region contact hole regions 7 are spaced apart between every two trench gates 2. The segmented N-type source regions 6 extend from one side of the trench gate 2 to the other side between the two trench gates 2, that is, the N-type source regions 6 are segmented and their width fills the width of two adjacent trench gates 2.

[0036] Example 2

[0037] This embodiment uses essentially the same technical solution as Embodiment 1, except that in Embodiment 1, the width of the N-type source region 6 fills both adjacent trench gates 2; while in this embodiment, the segmented N-type source region 6 between the two trench gates 2 only contacts one side of the trench gate 2, meaning the width of the N-type source region 6 does not fill both adjacent trench gates 2; and adjacent segmented N-type source regions 6 located between the two trench gates 2 contact different sides of the trench gate 2. In Embodiment 1, the length of the overlapping area 8 between the source region contact hole area 7 and the N-type source region 6 is 1 μm, while in this embodiment, the length of the overlapping area 8 between the source region contact hole area 7 and the N-type source region 6 is 2 μm.

[0038] Please see Figure 2 The figure shows a three-dimensional view of the IGBT device structure described in this embodiment. As shown in the figure, the length of the overlapping area (8) of the source region contact hole (6) and the N-type source region (5) is 2μm, and the width of the N-type source region (5) does not fill the two adjacent trench gates (2).

[0039] In the IGBT device structure of this invention, the source metal is not connected to the N-type source region over a large area, but is only partially connected to the N-type source region. This achieves the following: the length of the path through which source electrons converge to the source metal via the inversion channel when the device is in the on state is increased; a ballast resistor is introduced, thereby increasing the potential of the N-type source region; and the latch-up resistance and short-circuit capability of the device at room temperature and high temperature can be improved by controlling the electron current path of the N-type source region.

[0040] The above provides a detailed description of an IGBT device with anti-latch-up capability provided by the present invention. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0041] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. An IGBT device with latch-up resistance, characterized in that: It includes an N-type drift region (1), a segmented N-type source region (6), and a segmented source region contact hole region (7). The N-type source region (6) and the source region contact hole region (7) have an overlapping region (8). The area of ​​the overlapping region (8) is smaller than the area of ​​the contacting N-type source region (6) and the source region contact hole region (7). The width and length of the overlapping region (8) between the source region contact hole region (7) and the N-type source region (6) are adjustable to control the magnitude of the introduced ballast resistor. Several groove grids (2) are provided above the N-type drift region (1), and P-type body regions (5) are located between the groove grids (2). The lower boundary of the P-type body regions (5) is higher than the bottom of the groove grids (2). The segmented N-type source region (6) is located between adjacent trench gates (2) and embedded above the P-type body region (5); The segmented source region contact hole region (7) is located between adjacent trench gates (2) and embedded above the P-type body region (5). The source region contact hole region (7) is used to form an ohmic contact with the source metal. The length of the N-type source region (6) is 1~10μm, the length of the segment interval is 1~10μm, the length of the overlapping region (8) is 1~5μm, and the length of the source region contact hole region (7) is the sum of the length of the N-type source region (6) interval and the length of the overlapping region (8); The segmented N-type source region (6) between two adjacent trench gates (2) is in contact with only one side of the trench gate (2); and the two adjacent segments of the N-type source region (6) located between the two adjacent trench gates (2) are in contact with the trench gates (2) on different sides.

2. The IGBT device with anti-latch-up capability according to claim 1, characterized in that: The trench gate (2) is filled with gate polysilicon (3) and the gate oxide layer (4) is filled between the outer side of the gate polysilicon (3) and the sidewall of the trench gate (2).

3. The IGBT device with anti-latch-up capability according to claim 1, characterized in that: The trench grid (2) is provided with an insulating dielectric layer (9), and the insulating dielectric layer (9) is provided with a source metal (10). The source metal (10) makes ohmic contact with the P-type body region (5) and the N-type source region (6) respectively through the source region contact hole region (7).

4. The IGBT device with anti-latch-up capability according to claim 1, characterized in that: The N-type drift region (1) is provided with an N-type buffer layer (11), a P-type drain region (12) and a drain metal (13) in sequence on the lower side, and the P-type drain region (12) and the drain metal (13) form an ohmic contact.

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