Power semiconductor device and power semiconductor module

Abstract

A power semiconductor device may comprise a semiconductor layer, a gate contact disposed on the semiconductor layer, a source contact disposed on the semiconductor layer, an insulating layer disposed on the gate contact and the source contact, a scalable gate pad disposed on the insulating layer and electrically connected to the gate contact, and a scalable source pad disposed on the insulating layer and electrically connected to the source contact. An area of the scalable gate pad may be larger than an area of the gate contact, an area of the scalable source pad may be smaller than an area of the source contact, and the scalable gate pad may be vertically overlapped with the gate contact and the source contact.

Description

Power semiconductor devices and power semiconductor modules

[0001] The present disclosure relates to a power semiconductor device and a power semiconductor module.

[0002] Unlike system semiconductors or memory that process and store information or signals, power semiconductor devices are core components that convert, store, distribute, and control the power entering electronic devices, and are widely used in most electronic products.

[0003] In line with the recent global trend toward strengthening environmental protection, electric and hydrogen-powered eco-friendly vehicles are gaining widespread attention as alternatives to conventional fossil fuel-powered vehicles. These eco-friendly vehicles utilize numerous power semiconductor components. These eco-friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0004] Meanwhile, power semiconductor devices are being used in high-power conversion devices to drive inverters for electric vehicles. Power semiconductor devices used in these devices require both high output and low heat generation. High output requires a large active region size (or area), while low heat generation requires a reduced Rds(on).

[0005] Figure 1 is a plan view illustrating a conventional power semiconductor device.

[0006] As illustrated in Fig. 1, a conventional power semiconductor device is applied to a high-output power conversion device. The power semiconductor device may include a gate contact (10) and a source contact (20) for electrical connection to the outside.

[0007] In a power semiconductor device, the active area is reduced by the area (or surface area) of the gate contact (10). In order for the gate contact (10) to be easily connected to the outside, a minimum area must be secured. Therefore, as the area of ​​the gate contact (10) increases for easy connection, the active area becomes smaller, which limits the high output of the power semiconductor device and causes a problem of heat generation due to an increase in Rds(on).

[0008] In particular, as the size of power semiconductor devices is reduced to reduce manufacturing costs, maximizing the active area becomes more difficult, which increases the problem of high output limitations and heat generation issues.

[0009] Meanwhile, as shown in Fig. 1, as the size of the power semiconductor device decreases, the distance between the gate contact (10) and the source contact (20) decreases, which causes a problem in that the yield decreases due to defects such as an electrical short between the gate contact (10) and the source contact (20).

[0010] In addition, there is a problem that design convenience is reduced and assembly yield or reliability is reduced due to the inability to secure flexibility in the location or area of ​​the gate contact (10).

[0011] The present disclosure is intended to solve the above-mentioned and other problems.

[0012] Accordingly, the present disclosure provides a power semiconductor device and a power semiconductor module capable of reducing size.

[0013] In addition, the present disclosure provides a power semiconductor device and a power semiconductor module capable of reducing heat generation.

[0014] Additionally, the present disclosure provides a power semiconductor device and a power semiconductor module capable of improving assembly yield.

[0015] In addition, the present disclosure provides a power semiconductor device and a power semiconductor module that can provide design convenience.

[0016] The present disclosure is not limited to what has been described, but includes things that can be understood through the description of the disclosure.

[0017] According to one aspect of the present invention, to achieve the above or other purposes, a power semiconductor device includes: a semiconductor layer; a gate contact disposed on the semiconductor layer; a source contact disposed on the semiconductor layer; an insulating layer disposed on the gate contact and the source contact; a scalable gate pad disposed on the insulating layer and electrically connected to the gate contact; and a scalable source pad disposed on the insulating layer and electrically connected to the source contact; wherein an area of ​​the scalable gate pad is larger than an area of ​​the gate contact, an area of ​​the scalable source pad is smaller than an area of ​​the source contact, and the scalable gate pad vertically overlaps the gate contact and the source contact.

[0018] The above scalable source pad can be vertically overlapped with the gate contact and the source contact.

[0019] The distance between the scalable gate pad and the scalable source pad may be greater than the distance between the gate contact and the source contact.

[0020] The source contact may include a first source contact and a second source contact, and the gate contact may have a stripe shape arranged along a first direction between the first source contact and the second source contact.

[0021] The above scalable gate pad can vertically overlap the first source contact, the gate contact, and the second source contact along the second direction.

[0022] The above scalable source pad can vertically overlap the first source contact, the gate contact, and the second source contact along the second direction.

[0023] The gate contact may be vertically overlapped with the scalable gate pad and the scalable source pad along the first direction.

[0024] The distance between the scalable source pads may be greater than the width of the gate contact.

[0025] The above source contacts may be provided in multiple numbers, and the semiconductor layer may include gate electrodes arranged lengthwise along a first direction. The gate electrodes and the source contacts may be arranged alternately along a second direction.

[0026] The gate electrodes are electrically connected to each other, and the gate contact can be electrically connected to at least one of the gate electrodes.

[0027] The scalable gate pad may vertically overlap with the at least one gate electrode, and the scalable source pad may vertically overlap with the remaining gate electrodes excluding the at least one gate electrode among the gate electrodes.

[0028] According to another aspect to achieve the above or other purposes, a power semiconductor module comprises: a first substrate; a second substrate; and a first power semiconductor element and a second power semiconductor element between the first substrate and the second substrate; wherein the first power semiconductor element and the second power semiconductor element each comprise: a semiconductor layer; a gate contact disposed on the semiconductor layer; a source contact disposed on the semiconductor layer; an insulating layer disposed on the gate contact and the source contact; a scalable gate pad disposed on the insulating layer and electrically connected to the gate contact; and a scalable source pad disposed on the insulating layer and electrically connected to the source contact; wherein an area of ​​the scalable gate pad is larger than an area of ​​the gate contact, an area of ​​the scalable source pad is smaller than an area of ​​the source contact, and the scalable gate pad vertically overlaps the gate contact and the source contact.

[0029] The scalable gate pad and the scalable source pad of the first power semiconductor device may be electrically connected to the second substrate, and the scalable gate pad and the scalable source pad of the second power semiconductor device may be electrically connected to the first substrate.

[0030] The above scalable source pad can be vertically overlapped with the gate contact and the source contact.

[0031] The distance between the scalable gate pad and the scalable source pad may be greater than the distance between the gate contact and the source contact.

[0032] The effects of power semiconductor devices and power semiconductor modules according to the above aspects are described as follows.

[0033] According to at least one of the above aspects, the area of ​​the gate contact can be minimized to maximize the active area. Accordingly, the size of the power semiconductor device can be reduced, a high-output power semiconductor device can be realized, and low heat generation can be achieved due to a reduction in Rds(on).

[0034] According to at least one of the above aspects, the area of ​​the scalable gate pad can be freely increased without any restrictions on the gate contact as well as the source contact. In addition, flexibility or freedom in the location or size (or area) of the scalable gate pad is secured, thereby increasing design convenience and improving assembly yield or reliability.

[0035] The accompanying drawings are included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. Furthermore, the accompanying drawings may serve to illustrate features of the present disclosure and, together with the description of the disclosure, to explain the principles of the present disclosure.

[0036] In the drawing:

[0037] Figure 1 is a plan view illustrating a conventional power semiconductor device.

[0038] Figure 2 is a circuit diagram illustrating an inverter according to the present disclosure.

[0039] FIG. 3 is a plan view illustrating a power semiconductor device according to the present disclosure.

[0040] FIG. 4 is a cross-sectional view illustrating a power semiconductor device according to the present disclosure.

[0041] FIGS. 5A to 5E illustrate a manufacturing process of a power semiconductor device according to the present disclosure.

[0042] Figure 6a illustrates a first power semiconductor element and a second power semiconductor element mounted on a first substrate.

[0043] FIG. 6b is a cross-sectional view illustrating a power semiconductor module according to the present disclosure.

[0044] The sizes, shapes, and dimensions of components depicted in the drawings may differ from the actual components. Furthermore, even if the same components are depicted with different sizes, shapes, and dimensions across drawings, this is merely an example within the drawings, and the same components may have the same sizes, shapes, and dimensions across drawings.

[0045] Hereinafter, aspects disclosed in the present specification will be described in detail with reference to the attached drawings, and regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' used for components in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to facilitate easy understanding of aspects disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element, or that other intermediate elements may exist therebetween.

[0046] Hereinafter, “~module”, “~part”, “~device”, etc. may be composed of “~circuit” or “integrated circuit”. “~module”, “~part”, “~device”, etc. may be used interchangeably with “~circuit” or “integrated circuit”.

[0047] Figure 2 is a circuit diagram illustrating an inverter according to the present disclosure.

[0048] Referring to FIG. 2, the inverter (1000) according to the present disclosure can be applied to applications such as three-phase motors or compressors. The inverter (1000) can output three-phase power. The inverter (1000) can be a power conversion device or can be included in a power conversion device. The inverter (1000) can include a switching circuit. The power conversion device can also be referred to as a power semiconductor device.

[0049] An inverter (1000) according to the present disclosure can convert DC power into AC power and supply the converted AC power to a load (1200) to drive the load (1200). A converter may be connected to the input side of the inverter (1000) according to the present disclosure to convert AC power into DC power. In this case, the DC power converted by the converter can be converted into AC power by the inverter (1000) and then used to drive the load (1200). The load (1200) may be a motor or an electric motor, but is not limited thereto.

[0050] The inverter (1000) according to the present disclosure may include a three-phase inverter, but is not limited thereto. In this case, a phase difference of 120 degrees may be present between the first phase, the second phase, and the third phase. The inverter (1000) according to the present disclosure may include a plurality of legs (100A, 100B, 100C). For example, the first leg (100A), the second leg (100B), and the third leg (100C) may be connected in parallel to a load (1200), i.e., a motor, through a first node (N1), a second node (N2), and a third node (N3), respectively. The first leg (100A) may include a first arm (100a) and a second arm (100b) that are connected in series to each other, the second leg (100B) may include a third arm (100c) and a fourth arm (100d) that are connected in series to each other, and the third leg (100C) may include a fifth arm (100e) and a sixth arm (100f) that are connected in series to each other. Here, the first arm (100a), the third arm (100c), and the fifth arm (100e) may be referred to as upper arms, and the second arm (100b), the fourth arm (100d), and the sixth arm (100f) may be referred to as lower arms. Each of the first arm (100a) to the sixth arm (100f) may be referred to as a switching module, a submodule, or the like.

[0051] The first arm (100a) to the sixth arm (100f) may each include switching elements (Q1 to Q6) and diodes (100a-2 to 100f-2). The switching elements (Q1 to Q6) and the diodes (100a-2 to 100f-2) may be formed simultaneously using the same semiconductor process. The switching elements (Q1 to Q6) may include power semiconductor elements.

[0052] In order for DC power to be converted into AC power by the inverter (1000) according to the present disclosure, the switching elements (Q1 to Q6) of each of the first arm (100a) to the sixth arm (100f) can be controlled to be turned on / off.

[0053] For example, when the first switching element (Q1) of the first arm (100a) of the first leg (100A) is in the ON state, the fourth switching element (Q4) of the fourth arm (100d) of the second leg (100B) and / or the sixth switching element (Q6) of the sixth arm (100f) of the third leg (100C) may be in the ON state. Accordingly, DC power may be supplied to the first phase inductor of the motor.

[0054] For example, when the third switching element (Q3) of the third arm (100c) of the second leg (100B) is turned on, the sixth switching element (Q6) of the sixth arm (100f) of the third leg (100C) and / or the second switching element (Q2) of the second arm (100b) of the first leg (100A) may be turned on. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be 120 degrees behind the first phase.

[0055] For example, when the fifth switching element (Q5) of the fifth arm (100e) of the third leg (100C) is turned on, the second switching element (Q2) of the second arm (100b) of the first leg (100A) and / or the fourth switching element (Q4) of the fourth arm (100d) of the second leg (100B) may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be 120 degrees behind the second phase.

[0056] Accordingly, AC power can be generated by DC power supplied to each of the first phase inductor, the second phase inductor, and the third inductor.

[0057] Meanwhile, although not shown, in order to increase the internal pressure characteristics, the switching elements (Q1 to Q6) of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements, may be provided in multiple numbers, each connected in series with each other.

[0058] Although not shown, in order to increase the current characteristics, the switching elements (Q1 to Q6), i.e., the power semiconductor elements, of each of the first arm (100a) to the sixth arm (100f) may be provided in a plurality of units that are connected in parallel with each other. That is, each of the first switching elements (Q1) to the sixth switching elements (Q6) may include a power semiconductor module including a plurality of power semiconductor elements connected in parallel with each other. As will be described later, each of the first arm (100a) to the sixth arm (100f), i.e., each of the first switching elements (Q1) to the sixth switching elements (Q6), may include a plurality of power semiconductor modules, and the plurality of power semiconductor modules may include a plurality of power semiconductor elements connected in parallel with each other.

[0059] VDC is the input voltage, which can be, for example, DC voltage. CDC is a capacitor that can charge the input voltage (VDC).

[0060] Meanwhile, power semiconductor devices are typically called "dies" when manufactured on wafers, and "chips" after being separated by cutting the wafer. Hereinafter, dies and chips will be collectively referred to as "power semiconductor devices."

[0061] Fig. 3 is a plan view illustrating a power semiconductor device according to the present disclosure. Fig. 4 is a cross-sectional view illustrating a power semiconductor device according to the present disclosure. Fig. 4 may be a cross-sectional view of the power semiconductor device of Fig. 3 taken along line AB.

[0062] Referring to FIGS. 3 and 4, a power semiconductor device (200) according to the present disclosure may include a semiconductor layer (210), a gate contact (230), a source contact (240), an insulating layer (250), a scalable gate pad (260), a scalable source pad (270), etc.

[0063] The semiconductor layer (210) may include a substrate (211), a drift layer (212), bodies (213-1, 213-2), source regions (214-1, 214-2), gate electrodes (215), an insulating layer (216), etc.

[0064] The substrate (211) and / or the drift layer (212) may include a compound semiconductor such as SiC, GaN, Ga2O3, etc. For example, the substrate (211) and / or the drift layer (212) may include a 4H-SiC material, but is not limited thereto. For example, the substrate (211) and / or the drift layer (212) may include 3C-SiC or 6H-SiC.

[0065] The drift layer (212) may be disposed on the substrate (211). The drift layer (212) may be the substrate (211) or an epitaxial layer. The substrate (211) and the drift layer (212) may form a drain region, but are not limited thereto.

[0066] The substrate (211) and the drift layer (212) may have the same conductivity type. For example, the substrate (211) and the drift layer (212) may have a first conductivity type. The first conductivity type may be N-type, but is not limited thereto. For this purpose, the substrate (211) and the drift layer (212) may include an N-type dopant.

[0067] A gate electrode (215) may be disposed on the drift layer (212). The gate electrodes (215) may be configured in multiple numbers. For example, the gate electrodes (215) may be disposed lengthwise along the first direction (X).

[0068] An insulating layer (216) may surround each of the gate electrodes (215). The insulating layer (216) may be referred to as a gate oxide film. The insulating layer (216) may be referred to as an interlayer dielectric (ILD).

[0069] The bodies (213-1, 213-2) may be formed spaced apart from each other within the drift layer (212) below the gate electrodes (215). The bodies (213-1, 213-2) may be arranged between adjacent gate electrodes (215) within the drift layer (212). The bodies (213-1, 213-2) may have a second conductivity type. The bodies (213-1, 213-2) may include, for example, a P-type dopant. When the bodies (213-1, 213-2) include a P-type dopant, the bodies (213-1, 213-2) may be referred to as a P-well. The bodies (213-1, 213-2) may be referred to as a base region.

[0070] The source regions (214-1, 214-2) may be arranged within the bodies (213-1, 213-2). The source regions (214-1, 214-2) may be formed spaced apart from each other within the bodies (213-1, 213-2) below the gate electrodes (215). The source regions (214-1, 214-2) may have the same conductivity type as the drift layer (212), i.e., the first conductivity type. The source regions (214-1, 214-2) may have a stripe shape (or line shape) that is arranged long along the first direction (X).

[0071] The upper surface of the drift layer (212), the upper surface of the body (213-1, 213-2), and the upper surface of the source region (214-1, 214-2) may be in contact with the lower surface of the insulating layer (216). The drift layer (212) and the source region (214-1, 214-2) may be spaced apart from each other with the body (213-1, 213-2) therebetween. The upper region of the body (213-1, 213-2) in contact with the insulating layer (216) may form a channel region that electrically connects or disconnects the source region (214-1, 214-2) and the drift layer (212) depending on whether a voltage is applied. For example, a gate voltage may be applied to the gate electrode (215), and a source voltage may be applied to the source region (214-1, 214-2). Depending on whether the gate voltage and source voltage are applied, the channel region of the body (213-1, 213-2) can be conducted or blocked.

[0072] Since a plurality of gate electrodes (215) are provided, a channel region can be formed in an upper region of a body (213-1, 213-2) disposed under each of the plurality of gate electrodes (215). Accordingly, since two active cells are provided under each of the gate electrodes (215), an active region including twice the number of active cells as the number of the plurality of gate electrodes (215) can be formed.

[0073] Meanwhile, the gate contact (230) may be disposed on the semiconductor layer (210). The gate contact (230) may have a stripe shape (or line shape) disposed along the first direction (X).

[0074] The gate contact (230) may be electrically connected to at least one gate electrode among the plurality of gate electrodes (215). The plurality of gate electrodes (215) may be electrically connected to each other. In this case, the gate voltage provided to the gate contact (230) may be supplied to the plurality of gate electrodes (215) that are connected to each other.

[0075] The source contact (240) may be arranged on the semiconductor layer (210). The source contact (240) and the gate contact (230) may be arranged in parallel.

[0076] The source contact (240) may be disposed on a plurality of gate electrodes (215). Although not shown in FIG. 3, a plurality of gate electrodes (215) may be disposed along the first direction (X) below the source contact (240). Since the plurality of gate electrodes (215) are each surrounded by an insulating layer (216), the plurality of gate electrodes (215) and the source contact (240) may be electrically insulated from each other.

[0077] The source contact (240) may be in contact with the upper surfaces of the source regions (214-1, 214-2) and may be electrically connected to the source regions (214-1, 214-2). A source voltage provided to the source contact (240) may be supplied to the source regions (214-1, 214-2). The source contact (240) may be in contact with the upper surfaces of the bodies (213-1, 213-2).

[0078] The gate contact (230) and the source contact (240) may be formed simultaneously using the same metal and through the same process, but are not limited thereto. The gate contact (230) and the source contact (240) may be a single layer, such as nickel (Ni), or may include multiple layers. An annealing process may be performed to form an ohmic contact with the source contact (240) and the source regions (214-1, 214-2).

[0079] The source contact (240) may include a first source contact (241), a second source contact (242), etc. In this case, the gate contact (230) may have a stripe shape (or line shape) along the first direction (X) between the first source contact (241) and the second source contact (242).

[0080] The separation distance between the first source contact (241) and the second source contact (242) may be the minimum distance that does not cause an electrical short with the gate contact (230). As will be described later, an insulating layer (250) is disposed between each of the first source contact (241) and the second source contact (242) and the gate contact (230), so that the distance between the first source contact (241) and the gate contact (230) or the distance between the second source contact (242) and the gate contact (230) may be the minimum distance.

[0081] Although the drawing shows two source contacts (241, 242) and one gate contact (230), multiple source contacts (240) and multiple gate contacts (230) may be provided. In this case, multiple source contacts (240) and multiple gate contacts (230) may be alternately arranged along the second direction (Y), but this is not limited thereto.

[0082] Table 1 shows the chip size, Rds(on), assembly yield, and manufacturing cost reduction rate according to comparative examples and examples.

[0083] Size [mm] 2 ]Rds(on)[mΩ]Assembly yieldManufacturing cost reduction rateComparison Example5×513.9985%-ExampleSame size5×512.5995%8.3%Same Rds(on)4.77×4.7713.9995%18.1%

[0084] The comparative example may be a conventional power semiconductor device (Fig. 1), and the embodiment may be a power semiconductor device of the present disclosure (200 of Figs. 3 and 4). When the comparative example and the embodiment have the same size (or area), it can be seen that the Rds(on) is reduced, the assembly yield is increased, and the manufacturing cost is reduced in the embodiment compared to the comparative example. In addition, when the comparative example and the embodiment have the same Rds(on), it can be seen that the size is reduced, the assembly yield is increased, and the manufacturing cost is reduced in the embodiment compared to the comparative example. As described above, in the conventional power semiconductor device (Fig. 1), the gate contact (230) must have a minimum area to be easily connected to the outside, and therefore the area of ​​the gate contact (230) cannot but be large.

[0085] However, in the present disclosure, in order to maximize the active area, the area of ​​the gate contact (230) can be minimized. To this end, the gate contact (230) can be arranged long with a minimum width along the first direction (X). Accordingly, as the area of ​​the gate contact (230) is minimized, the active area increases, so that the size of the power semiconductor device (200) can be reduced, a high-output power semiconductor device (200) can be implemented, and low heat generation can be possible due to a decrease in Rds(on).

[0086] Meanwhile, an insulating layer (250) may be disposed on the gate contact (230) and the source contact (240). The insulating layer (250) may protect the gate contact (230) and the source contact (240). The insulating layer (250) may prevent an electrical short between the scalable gate pad (260) and the source contact (240) or an electrical short between the scalable source pad (270) and the gate contact (230), which will be described later.

[0087] The insulating layer (250) may be referred to as a planarizing layer that makes the upper surface flat. The insulating layer (250) may be referred to as an intermetal dielectric (IMD) layer.

[0088] A scalable gate pad (260) may be disposed on an insulating layer (250) and electrically connected to a gate contact (230). The scalable gate pad (260) may be disposed on an upper surface of the insulating layer (250) and may penetrate the insulating layer (250) to contact an upper surface of the gate contact (230).

[0089] A scalable gate pad (260) can be provided to facilitate electrical connection to the outside, as the gate contact (230) has a very narrow width and is therefore difficult to electrically connect to the outside.

[0090] The scalable gate pad (260) can be vertically overlapped with the gate contact (230) and the source contact (240). Since an insulating layer (250) is disposed between the scalable gate pad (260) and the source contact (240), even if the scalable gate pad (260) is vertically overlapped with the source contact (240), an electrical short between the scalable gate pad (260) and the source contact (240) can be prevented.

[0091] The area of ​​the scalable gate pad (260) may be larger than the area of ​​the gate contact (230). As described above, since the gate contact (230) has a stripe shape along the first direction (X) with a minimum width, the area of ​​the gate contact (230) may be minimized. By minimizing the gate area, the active area is maximized, so that the size of the power semiconductor device (200) may be reduced, a high-output power semiconductor device (200) may be implemented, and low heat generation may be possible due to a decrease in Rds(on).

[0092] In addition, the area of ​​the scalable gate pad (260) can be freely increased without any restrictions not only on the gate contact (230) but also on the source contact (240). In addition, flexibility or freedom in the position or size (or area) of the scalable gate pad (260) is secured, so that design convenience can be increased and assembly yield or reliability can be improved. That is, one area of ​​the scalable gate pad (260) is electrically connected to the gate contact (230), and the remaining area can be positioned anywhere in the entire area on the upper side of the power semiconductor device (200) of the present disclosure, and its size (or area) can also be freely increased or decreased.

[0093] The scalable gate pad (260) can be vertically overlapped with the first source contact (241), the gate contact (230), and the second source contact (242) along the second direction (Y). The scalable gate pad (260) can be formed to have a desired area freely on the first source contact (241), the gate contact (230), and the second source contact (242).

[0094] The scalable gate pad (260) may vertically overlap with at least one gate electrode among the gate electrodes (215). The scalable gate pad (260) may vertically overlap with a gate electrode (215) electrically connected to the gate contact (230) among the gate electrodes (215). The scalable source pad (270) may be disposed on the insulating layer (250) and electrically connected to the source contact (240). The scalable source pad (270) may be disposed on the upper surface of the insulating layer (250) and may penetrate the insulating layer (250) to contact the upper surface of the source contact (240).

[0095] A scalable source pad (270) may be provided for electrical connection to a source contact (240). The scalable source pad (270) and the scalable gate pad (260) may be arranged in parallel.

[0096] The scalable source pad (270) can be vertically overlapped with the gate contact (230) and the source contact (240). Since an insulating layer (250) is disposed between the scalable source pad (270) and the source contact (240), even if the scalable source pad (270) is vertically overlapped with the gate contact (230), an electrical short between the scalable source pad (270) and the gate contact (230) can be prevented.

[0097] The scalable source pad (270) may be vertically overlapped with the gate electrodes (215). The scalable gate pad (260) may be vertically overlapped with the remaining gate electrodes (215) except for the gate electrode (215) electrically connected to the gate contact (230) among the gate electrodes (215).

[0098] In order to maximize the active area in the power semiconductor device (200) of the present disclosure, the area of ​​the source contact (240) can be made as large as possible. As the area of ​​the scalable gate pad (260) increases, the area of ​​the scalable source pad (270) can decrease. Accordingly, the area of ​​the scalable source pad (270) can be smaller than the area of ​​the source contact (240). Since the source voltage is usually larger than the gate voltage, the area of ​​the scalable source pad (270) can be larger than the area of ​​the scalable gate pad (260) to match the voltage, but this is not limited thereto.

[0099] The scalable source pad (270) can be vertically overlapped with the gate contact (230) and the source contact (240). The scalable source pad (270) can be vertically overlapped with the first source contact (241), the gate contact (230), and the second source contact (242) along the second direction (Y). The scalable source pad (270) can be formed to have a freely desired area on the first source contact (241), the gate contact (230), and the second source contact (242).

[0100] The gate contact (230) is positioned between the first source contact (241) and the second source contact (242), so that it can vertically overlap with the scalable gate pad (260) and the scalable source pad (270) that are positioned across the gate contact (230) along the second direction (Y).

[0101] Although the scalable gate pad (260) and the scalable source pad (270) are depicted in the drawing as each having a square shape, variations into other various shapes may also be possible.

[0102] The distance (d2) between the scalable gate pad (260) and the scalable source pad (270) may be greater than the distance (d1) between the gate contact (230) and the source contact (240). As the distance (d2) between the scalable gate pad (260) and the scalable source pad (270) is greater, when the scalable gate pad (260) and the scalable source pad (270) are each electrically connected to the outside, an electrical short between the scalable gate pad (260) and the scalable source pad (270) due to a defect such as misalignment can be prevented.

[0103] The distance (d2) between the scalable gate pad (260) and the scalable source pad (270) may be greater than the width (W1) of the gate contact (230). The distance (d2) between the scalable gate pad (260) and the scalable source pad (270) may be greater than the distance between the first source contact (241) and the second source contact (242).

[0104] Meanwhile, the power semiconductor device (200) according to the present disclosure may further include a drain electrode (220).

[0105] The drain electrode (220) may be placed below the substrate (211). The drain electrode (220) may supply a drain voltage to the substrate (211). Since the drain electrode (220) is grounded, the drain voltage may be 0 V, but is not limited thereto.

[0106] In a power semiconductor device (200) having a structure as described above, the channel regions of the bodies (213-1, 213-2) between the drift layer (212) and the source regions (214-1, 214-2) are made conductive by the gate voltage supplied to the scalable gate pad (260), so that current can flow between the source regions (214-1, 214-2) and the drift layer (212) by the source voltage supplied to the scalable source pad (270). Accordingly, a switching function can be implemented by making the channel regions of the bodies (213-1, 213-2) between the drift layer (212) and the source regions (214-1, 214-2) conductive or closed depending on the high and low levels of the gate voltage.

[0107] FIGS. 5A to 5E illustrate a manufacturing process of a power semiconductor device according to the present disclosure. FIGS. 5A to 5E may be cross-sectional views taken along the CD line of the power semiconductor device of FIG. 3.

[0108] As illustrated in FIG. 5A, a semiconductor layer (210) may be formed on a substrate (211), and a plurality of gate electrodes (215) may be formed on the semiconductor layer (210). An insulating layer (216) may be formed to surround the plurality of gate electrodes (215). The upper surface of the semiconductor layer (210) between the plurality of gate electrodes (215) may be exposed.

[0109] As illustrated in FIG. 5b, a gate contact (230) and a source contact (240) can be formed on the insulating layer (216). For example, a metal film can be formed and patterned on the insulating layer (216) to form the gate contact (230) and the source contact (240).

[0110] The gate contact (230) may have a long stripe shape along one direction with a minimum width.

[0111] The gate contact (230) can contact the upper surface of at least one gate electrode among the plurality of gate electrodes (215) through the insulating layer (216). The source contact (240) can contact the upper surface of the semiconductor layer (210), i.e., the upper surface of the source region (214-1, 214-2), between the plurality of gate electrodes (215) through the insulating layer (216).

[0112] As illustrated in FIG. 5c, an insulating layer (250) may be formed on the gate contact (230) and the source contact (240). The insulating layer (250) may protect the gate contact (230) and the source contact (240).

[0113] A first contact hole (251) may be formed by removing the insulating layer (250) on the gate contact (230) so that the upper surface of the gate contact (230) is exposed. A second contact hole (252) may be formed by removing the insulating layer (250) on the source contact (240) so that the upper surface of the source contact (240) is exposed.

[0114] As illustrated in FIG. 5d, a scalable gate pad (260) and a scalable source pad (270) can be formed on the insulating layer (250). For example, a metal film can be formed and patterned on the insulating layer (250) to form a scalable gate pad (260) and a scalable source pad (270).

[0115] The scalable gate pad (260) may be electrically connected to the gate contact (230) by contacting the upper surface of the gate contact (230) through the first contact hole (251). The scalable source pad (270) may be electrically connected to the source contact (240) by contacting the upper surface of the source contact (240) through the second contact hole (252).

[0116] The scalable gate pad (260) may be formed to vertically overlap with the gate contact (230) and the source contact (240). The scalable source pad (270) may be formed to vertically overlap with the source contact (240). Although not shown, the scalable source pad (270) may be formed to vertically overlap with the gate contact (230).

[0117] The scalable gate pad (260) and the scalable source pad (270) can be spaced apart from each other.

[0118] The distance between the scalable gate pad (260) and the scalable source pad (270) may be greater than the width of the gate contact (230).

[0119] As illustrated in FIG. 5e, an insulating layer (280) may be formed between the scalable gate pad (260) and the scalable source pad (270). The insulating layer (280) may be referred to as a passivation layer or a protective layer.

[0120] The insulating layer (280) can be in contact with the upper surface of the insulating layer (280) between the scalable gate pad (260) and the scalable source pad (270). The insulating layer (280) may partially vertically overlap with the scalable gate pad (260) and / or the scalable source pad (270), but is not limited thereto. By this structure, the contact area between the insulating layer (280) and the scalable gate pad (260) and / or the scalable source pad (270) is increased, thereby preventing peel off of the scalable gate pad (260) and / or the scalable source pad (270).

[0121] Although not shown, an insulating layer (280) may be formed along a side of a scalable gate pad (260). Although not shown, an insulating layer (280) may be formed along a side of a scalable source pad (270).

[0122] For example, the insulating layer (250) may be made of an inorganic material, and the insulating layer (280) may be made of an organic material, but this is not limited thereto.

[0123] Figure 6a illustrates a first power semiconductor element and a second power semiconductor element mounted on a first substrate.

[0124] As illustrated in Fig. 6a, a first power semiconductor element (331) and a second power semiconductor element (332) can be mounted on a first substrate (310). The first power semiconductor element (331) and the second power semiconductor element (332) can be mounted on the first substrate (310).

[0125] In the drawing, eight first power semiconductor elements (331) and eight second power semiconductor elements (332) are provided, but more or fewer elements may be provided.

[0126] Since the structure of each of the first power semiconductor element (331) and the second power semiconductor element (332) is the same as the structure of the power semiconductor element of the present disclosure (FIGS. 3 and 4), a detailed description thereof is omitted.

[0127] FIG. 6b is a cross-sectional view illustrating a power semiconductor module according to the present disclosure.

[0128] Referring to FIG. 6b, a power semiconductor module (300) according to the present disclosure may include a first substrate (310), a second substrate (320), a first power semiconductor element (331), a second power semiconductor element (332), terminals (350), etc.

[0129] The first substrate (310) and the second substrate (320) may each include an insulating layer (311, 321), a first metal layer (313, 323), a second metal layer (315, 325), etc. The insulating layers (311, 321) may be made of an inorganic material, a ceramic material, an alumina material, a plastic material, a glass material, etc.

[0130] The first metal layer (313, 323) may include a plurality of circuit patterns (not shown). The plurality of circuit patterns may be electrically connected to the first power semiconductor element (331) and the second power semiconductor element (332). Therefore, the first metal layer (313, 323) may be formed of a metal material having excellent electrical conductivity. For example, the first metal layer (313, 323) may have a single-layer structure or a multi-layer structure made of copper (Cu), gold (Au), aluminum (Al), platinum (Pt), or the like.

[0131] The second metal layer (315, 325) can quickly discharge heat generated from the first power semiconductor element (331) and the second power semiconductor element (332) to the outside. Therefore, the second metal layer (315, 325) can be formed of a material having excellent heat dissipation properties. For example, the second metal layer (315, 325) can be aluminum (Al) or an aluminum alloy, but is not limited thereto. The second metal layer (315, 325) can be called a heat dissipation layer or a heat dissipation plate.

[0132] The first power semiconductor element (331) and the second power semiconductor element (332) can be mounted between the first substrate (310) and the second substrate (320).

[0133] In the present disclosure, the first power semiconductor element (331) and the second power semiconductor element (332) may each include at least two power semiconductor elements. The two or more power semiconductor elements may be connected in parallel with each other.

[0134] Meanwhile, terminals (350) (or lead frames) may serve to connect an external circuit (or driver) to the first power semiconductor element (331) and the second power semiconductor element (332).

[0135] For example, at least five terminals (350) may be provided, but this is not limited thereto. For example, the first terminal and the second terminal may be electrically connected to the scalable gate pad (331a) and the scalable source pad (331b) of the first power semiconductor element (331) via corresponding circuit patterns of the second substrate (320), respectively. For example, the third terminal may be commonly connected to the first power semiconductor element (331) and the second power semiconductor element (332) via corresponding circuit patterns of the first substrate (310). The third terminal may be electrically connected to the drain electrode (220) of the first power semiconductor element (331) via the first spacer (341). The third terminal may be electrically connected to the scalable source pad (332b) of the second power semiconductor element (332).

[0136] For example, the fourth terminal may be electrically connected to a scalable gate pad (332a) of the second power semiconductor element (332) via a corresponding circuit pattern of the first substrate (310). The first terminal and the fourth terminal may provide a switching signal, a gate signal, a control signal, etc. that control on / off of the first power semiconductor element (331) and the second power semiconductor element (332), respectively.

[0137] For example, the fifth terminal may be electrically connected to the second power semiconductor element (332) via a corresponding circuit pattern of the second substrate (320). The fifth terminal may be electrically connected to the drain electrode (220) of the second power semiconductor element (332) via the second spacer (342).

[0138] In the present disclosure, the thickness of the terminal (350) may be greater than the thickness of the first power semiconductor element (331) or the second power semiconductor element (332). By providing a first spacer (341) and a second spacer (342) between the first substrate (310) and the second substrate (320), a thickness difference between the terminal (350) and the first power semiconductor element (331) (or the second power semiconductor element (332)) may be compensated. The first spacer (341) may be mounted on the drain electrode (220) of the first power semiconductor element (331), and the second spacer (342) may be mounted on the drain electrode (220) of the second power semiconductor element (332). The first spacer (341) and the second spacer (342) may be made of a material having excellent electrical conductivity, for example, copper (Cu).

[0139] When the thickness of the terminal (350) and the thickness of the first power semiconductor element (331) or the second power semiconductor element (332) are the same, the first spacer (341) and the second spacer (342) may be omitted.

[0140] The above detailed description should not be construed as limiting in any respect and should be considered illustrative. The scope of the above-described aspects should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalency range of the above-described aspects are intended to be included within the scope of the above-described aspects.

Claims

1. Semiconductor layer; A gate contact disposed on the semiconductor layer; A source contact disposed on the semiconductor layer; An insulating layer disposed on the gate contact and the source contact; a scalable gate pad disposed on the insulating layer and electrically connected to the gate contact; and a scalable source pad disposed on the insulating layer and electrically connected to the source contact; The area of ​​the above scalable gate pad is larger than the area of ​​the above gate contact, The area of ​​the above scalable source pad is smaller than the area of ​​the above source contact, The above scalable gate pad vertically overlaps the gate contact and the source contact, Power semiconductor devices.

2. In paragraph 1, The above scalable source pad vertically overlaps the gate contact and the source contact, Power semiconductor devices.

3. In paragraph 1, The distance between the scalable gate pad and the scalable source pad is greater than the distance between the gate contact and the source contact. Power semiconductor devices.

4. In paragraph 1, The above source contact includes a first source contact and a second source contact, The gate contact has a stripe shape arranged along the first direction between the first source contact and the second source contact, Power semiconductor devices.

5. In paragraph 1, The above source contacts are provided in multiple numbers, The semiconductor layer includes gate electrodes arranged lengthwise along the first direction, The gate electrodes and the source contacts are alternately arranged along the second direction, Power semiconductor devices.

6. In paragraph 5, The above gate electrodes are electrically connected to each other, The gate contact is electrically connected to at least one of the gate electrodes, Power semiconductor devices.

7. First substrate; Second substrate; and A first power semiconductor element and a second power semiconductor element are included between the first substrate and the second substrate; The first power semiconductor element and the second power semiconductor element are each, semiconductor layer; A gate contact disposed on the semiconductor layer; A source contact disposed on the semiconductor layer; An insulating layer disposed on the gate contact and the source contact; a scalable gate pad disposed on the insulating layer and electrically connected to the gate contact; and a scalable source pad disposed on the insulating layer and electrically connected to the source contact; The area of ​​the above scalable gate pad is larger than the area of ​​the above gate contact, The area of ​​the above scalable source pad is smaller than the area of ​​the above source contact, The above scalable gate pad vertically overlaps the gate contact and the source contact, Power semiconductor modules.

8. In paragraph 7, The scalable gate pad and the scalable source pad of the first power semiconductor device are electrically connected to the second substrate, The scalable gate pad and the scalable source pad of the second power semiconductor device are electrically connected to the first substrate. Power semiconductor modules.

9. In paragraph 7, The above scalable source pad vertically overlaps the gate contact and the source contact, Power semiconductor modules.

10. In paragraph 7, The distance between the scalable gate pad and the scalable source pad is greater than the distance between the gate contact and the source contact. Power semiconductor modules.

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