VLD terminal structure, preparation method and preparation system thereof, and storage medium
By employing a two-stage stepped LOCOS oxide layer structure in the VLD terminal structure, combined with boron ion implantation and annealing, the problem of insufficient reliability of traditional VLD terminal structures under high-dose implantation is solved, achieving higher ring dose and pressure resistance performance, and simplifying the process flow.
Patent Information
- Application Number
- CN202511054970.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-07
AI Technical Summary
Traditional VLD terminal structures have low reliability when the injection dose in the ring region reaches the order of 1e12cm-3, and it is difficult to further improve them by increasing the annealing temperature or time, resulting in insufficient overall system stability.
A two-stage stepped LOCOS oxide layer structure is adopted. First and second trench regions are formed in the VLD terminal ring region, and LOCOS oxide layers of different depths are grown in each region. Combined with boron ion implantation and annealing, a stable terminal structure is formed.
This achievement enabled a breakthrough in the injection dose in the ring region to the order of 1e13cm-3, improving the reliability and pressure resistance of the VLD terminal, simplifying the process flow, and reducing the process difficulty.
Smart Images
Figure CN120916468A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a semiconductor device and a preparation method, a preparation system and a storage medium thereof, in particular to a VLD terminal structure and a preparation method, a preparation system and a storage medium thereof. BACKGROUND
[0002] In modern high-power wind power, photovoltaic inverter and energy storage converter applications, as an important component of switching, the reliability of the chip in the module affects the long-term stable operation of the whole machine.
[0003] In order to solve the problem of low reliability of the traditional VLD terminal, especially when the ring injection dose is in the order of 1e12cm -3 , the terminal structure manufactured based on the traditional LOCOS process is difficult to break through the maximum available boron dose, so the industry often starts from increasing the ring annealing temperature or time, and improves the reliability by increasing the junction depth, but the effect is very small. SUMMARY
[0004] The purpose of the application is to provide a VLD terminal structure which can realize the ring dose breaking through the order of 1e13cm -3 ;
[0005] The second purpose of the application is to provide a preparation method of the VLD terminal structure.
[0006] The third purpose of the application is to provide a preparation system of the VLD terminal structure.
[0007] The fourth purpose of the application is to provide a computer readable storage medium.
[0008] Technical scheme: the VLD terminal structure provided by the application comprises:
[0009] a substrate;
[0010] a VLD terminal ring region formed on the substrate;
[0011] a first trench region formed in the front part of the VLD terminal ring region, and a first LOCOS oxide layer formed in the first trench region;
[0012] a second trench region formed in the rear part of the VLD terminal ring region, and a second LOCOS oxide layer formed in the second trench region;
[0013] the rear part of the first trench region is connected with the front part of the second trench region, or there is an overlap; the depths of the second trench region and the first trench region are different.
[0014] The depth of the first trench region is 1-2 um; the depth of the second trench region is 0.2-1 um; the back part of the first trench region overlaps the front part of the second trench region, and the width of the overlap is 10-50 um.
[0015] The thickness of the first LOCOS oxide layer is 1.5-2.5 um, and the thickness of the second LOCOS oxide layer is 0.7-1.5 um.
[0016] The preparation method of the VLD terminal structure comprises the following steps:
[0017] (A) performing VLD terminal ring zone implantation and annealing from the substrate surface downward;
[0018] (B) etching from the top downward in the front part of the VLD terminal ring zone to form a first trench region;
[0019] (C) growing a first LOCOS oxide layer in the first trench region and performing first CMP to remove the first LOCOS oxide layer above the substrate surface;
[0020] (D) etching from the top downward in the back part of the VLD terminal ring zone to form a second trench region, and making the depth of the second trench region different from that of the first trench region;
[0021] (E) growing a second LOCOS oxide layer in the second trench region and performing second CMP to remove the second LOCOS oxide layer above the substrate surface, to obtain a final two-stage stepped LOCOS structure.
[0022] In step (A), boron material is implanted into the VLD terminal ring zone, and effective doping is formed through high-temperature annealing; the boron dose implanted into the VLD terminal ring zone is 1e13-1e14 cm -3 , the implantation energy is 30-100 KeV, the high-temperature annealing temperature is 1150-1200℃, and the time is 100-400 min. The N-type substrate resistivity is 30-90 Ωcm.
[0023] In step (B), the etched first trench region is located in the VLD terminal ring zone generated in step (1), the depth of the first trench region is 1-2 um, and the depth of the second trench region is 0.2-1 um.
[0024] In step (C), the first LOCOS oxide layer is grown by using a long-time low-temperature process; the temperature is 950-1000℃, and the time is 800-1050 min; the thickness of the first LOCOS oxide layer is 1.5-2.5 um.
[0025] In step (D), the etched second trench region is located in the VLD termination ring region generated in step (1), and the depth of the second trench region is 0.2-1 um; the back of the first trench region and the front of the second trench region overlap, and the overlapping lateral width is 10-50 um.
[0026] In step (E), the second LOCOS oxide layer is grown by using a long-time low-temperature process; the temperature is 950-1000 DEG C, and the time is 800-1050 min; the thickness of the second LOCOS oxide layer is 0.7-1.5 um.
[0027] In the two-stage stepped LOCOS structure formed by the method, the first LOCOS oxide layer depth and the second LOCOS oxide layer depth, the length of the intersection, and the VLD implantation dose are matched to form a final structure with stable voltage resistance.
[0028] In the method, the first LOCOS oxide layer and the second LOCOS oxide layer are both oxide layers grown by using a local oxidation of silicon isolation process.
[0029] The preparation system of the VLD termination structure includes:
[0030] A substrate module is configured to provide a substrate.
[0031] An ion implantation and annealing module is configured to implant and anneal a VLD termination ring region on the substrate.
[0032] A first etching module is configured to form a first trench region from the top down in the front part of the VLD termination ring region, and grow a first LOCOS oxide layer in the first trench region.
[0033] A first CMP module is configured to perform a first CMP to remove the first LOCOS oxide layer above the substrate surface.
[0034] A second etching module is configured to etch a second trench region from the top down in the back part of the VLD termination ring region, and grow a second LOCOS oxide layer in the second trench region.
[0035] A second CMP module is configured to perform a second CMP to remove the second LOCOS oxide layer above the substrate surface.
[0036] A computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement the steps of the method according to any one of the above.
[0037] Beneficial effects: Compared with the prior art, the method has the following remarkable effects:
[0038] (1) The terminal structure of the present application can consume the dopant on the surface of the semiconductor substrate with a certain thickness through the step of the two layers of LOCOS oxide layers formed after the terminal ring region is implanted, so that the ring region implantation dose can be increased to the order of 1e13cm -3 (2) The present application realizes the step of the two layers of LOCOS oxide layers through two mask lithography, growth of LOCOS oxide layer and CMP removal in sequence, and forms the VLD terminal structure with high reliability by combining the boron ion implantation and annealing of the terminal region, so that the boron ion implantation dose can be further increased without the influence of the movable ion charge of the process line, the ring region dose is broken through to the order of 1e13cm -3 , the process is simple and reliable, and the realization difficulty is low. BRIEF DESCRIPTION OF DRAWINGS
[0039] Figure 1 is a flow chart of a preparation method of a terminal structure provided by the present application;
[0040] Figures 2 to 6 is a schematic diagram of each flow of the preparation process. DETAILED DESCRIPTION
[0041] The present application will be further described in detail below.
[0042] Example 1
[0043] A preparation method of a terminal structure, a flow chart thereof is shown as Figure 1 , and specifically includes the following steps:
[0044] (1) A FZ silicon wafer with a resistivity of 30Ωcm is used as the substrate 1, wherein the FZ silicon wafer refers to the silicon wafer obtained by the zone melting process in the prior art, and the substrate can also be other N-type semiconductor materials; a VLD terminal ring region 2 is formed at the terminal ring region position of the substrate 1, and the length of the formed VLD terminal ring region 2 is 160um; wherein the method for forming the VLD terminal ring region 2 at the terminal ring region position of the substrate 1 is the prior art. The boron ion implantation dose used for forming the VLD terminal ring region 2 is 1.5e13cm -3 , the implantation energy is 80KeV, and the annealing condition is 1150℃ for 300 minutes. The structure obtained in this step is shown as Figure 2 .
[0045] (2) A first trench region 3 is etched from the top down in the front part of the substrate 1 of the VLD, and the depth is 1.5um. The etching angle is kept at 89 degrees, the first trench region 3 etched is a reverse trapezoid with a large top opening and a small bottom opening, the width etched is about 100um, which includes 10um of the overlapping part with the second trench region 5, and the formed structure is shown as Figure 3 .
[0046] (3) The first LOCOS oxide layer 4 is grown in the first trench area 3 by LOCOS process, the material of the oxide layer is silicon dioxide, then CMP is implemented, and the extra silicon dioxide is removed by grinding to the top of the substrate; wherein the thickness of the first LOCOS oxide layer 4 is 2um, the oxidation condition is 980℃ for 1000 minutes, and the formed structure is as shown in Figure 4 .
[0047] (4) The second trench area 5 is etched from the top down in the rear part of the substrate 1 area, and the depth is 1um. The etching angle is kept at 89 degrees, the etched second trench area 5 is an inverted trapezoid with a large upper opening and a small lower opening, and the etched width is about 60um, which includes 15um of the tail part of the first trench area 3. The first trench area 3 and the second trench area 5 of the embodiment are in an intersecting and overlapping state, and the intersecting part is 15um wide; the formed structure is as shown in Figure 5 .
[0048] (5) The second LOCOS oxide layer 6 is grown in the second trench area 5 by LOCOS growth process, the material of the oxide layer is silicon dioxide, then CMP is implemented, and the extra silicon dioxide is removed by grinding to the top of the substrate; wherein the thickness of the second LOCOS oxide layer 6 is 1.5um, thereby forming the final terminal structure, as shown in Figure 6 .
[0049] The breakdown voltage of the terminal structure of the embodiment can reach 718V.
[0050] The application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps of the above method.
[0051] The application provides a preparation system of a new terminal used in the above method, which comprises the following modules:
[0052] A substrate 1 module is used to provide a substrate 1.
[0053] An ion implantation and annealing module is used to implant and anneal the VLD terminal ring area 2 on the substrate 1.
[0054] A first etching module is used to form a first trench area 3 from the top down in the front part of the VLD terminal ring area 2, and grow a first LOCOS oxide layer 4 in the first trench area 3.
[0055] A first CMP module is used to implement the first CMP to remove the first LOCOS oxide layer 4 above the surface of the substrate 1.
[0056] Second etching module: for etching a second trench region 5 from the top down in the rear part of the VLD terminal ring region 2, and growing a second LOCOS oxide layer 6 in the second trench region 5;
[0057] Second CMP module: for implementing the second CMP to remove the second LOCOS oxide layer 6 above the surface of the substrate 1.
[0058] Example 2
[0059] Different from Example 1, the depth of the first LOCOS oxide layer 4 is 2.5um. The breakdown voltage of the structure can reach 820V after testing.
[0060] Example 3
[0061] Different from Example 1, the lateral width of the cross-over overlap is 10um. The breakdown voltage of the structure can reach 605V after testing.
[0062] Example 4
[0063] Different from Example 1, the VLD injection dose is 1.2e13cm -3 . The breakdown voltage of the structure can reach 587V after testing.
[0064] Example 5
[0065] Different from Example 1, the depth of the first LOCOS oxide layer 4 is 1.5um. The breakdown voltage of the structure can reach 623V after testing.
[0066] Example 6
[0067] Different from Example 1, the depth of the second LOCOS oxide layer 6 is 1um. The breakdown voltage of the structure can only reach 645V after testing.
[0068] Comparative Example 1
[0069] Different from Example 1, the depth of the first LOCOS oxide layer 4 is 1.2um. The breakdown voltage of the structure can reach 412V after testing.
[0070] Comparative Example 2
[0071] Different from Example 1, the lateral width of the cross-over overlap is 5um. The breakdown voltage of the structure can reach 552V after testing.
[0072] Comparative Example 3
[0073] Different from Example 1, the VLD injection dose is 5e12cm -3 . The breakdown voltage of the structure can reach 374V after testing.
Claims
1. A VLD terminal structure, characterized by, It comprises: a substrate (1); a VLD terminal ring region (2) formed on the substrate (1); a first trench region (3) formed on the front part of the VLD terminal ring region (2), and a first LOCOS oxide layer (4) formed in the first trench region (3); a second trench region (5) formed on the back part of the VLD terminal ring region (2), and a second LOCOS oxide layer (6) formed in the second trench region (5); the back part of the first trench region (3) is connected with the front part of the second trench region (5), or there is an overlap; the depth of the second trench region (5) is different from that of the first trench region (3).
2. The VLD terminal structure of claim 1, wherein, The depth of the first trench region (3) is 1-2 um, and the depth of the second trench region (5) is 0.2-1 um.
3. The VLD terminal structure of claim 1, wherein, The thickness of the first LOCOS oxide layer (4) is 1.5-2.5 um, and the thickness of the second LOCOS oxide layer (6) is 0.7-1.5 um.
4. The VLD terminal structure of claim 1, wherein, The back part of the first trench region (3) overlaps with the front part of the second trench region (5), and the lateral width of the overlap is 10-50 um.
5. A method for preparing the VLD terminal structure according to claim 1, characterized in that it comprises the following steps: (A) implanting and annealing the VLD terminal ring region (2) from the surface of the substrate (1) downward; (B) etching from the top downward in the front part of the VLD terminal ring region (2) to form the first trench region (3); (C) growing the first LOCOS oxide layer (4) in the first trench region (3), and performing the first CMP to remove the first LOCOS oxide layer (4) above the surface of the substrate (1); (D) etching from the top downward in the back part of the VLD terminal ring region (2) to form the second trench region (5), and making the depth of the second trench region (5) different from that of the first trench region (3); (E) growing the second LOCOS oxide layer (6) in the second trench region (5), and performing the second CMP to remove the second LOCOS oxide layer (6) above the surface of the substrate (1), to obtain the final two-stage stepped LOCOS structure.
6. The method of claim 5, wherein the VLD terminal structure is prepared by, The conditions for growing the LOCOS oxide layer in the first trench region (3) and the second trench region (5) are: temperature 950-1000 ℃, time 800-1050 min.
7. The method of claim 5, wherein the VLD terminal structure is prepared by, The thickness of the first LOCOS oxide layer (4) is 1.5-2.5 um, and the thickness of the second LOCOS oxide layer (6) is 0.7-1.5 um.
8. The method of claim 5, wherein the VLD terminal structure is prepared by, In step (A), boron material is implanted into the VLD terminal ring region (2) and high-temperature annealing is performed to form effective doping; the boron dose implanted into the VLD terminal ring region (2) is 1e13-1e14 cm -3 , and the implantation energy is 30-100 KeV.
9. A system for producing the VLD termination structure of claim 1, characterized by, It comprises: a substrate (1) module for providing the substrate (1); an ion implantation and annealing module for implanting and annealing the VLD terminal ring region (2) on the substrate (1); a first etching module for forming the first trench region (3) from the top downward in the front part of the VLD terminal ring region (2), and growing the first LOCOS oxide layer (4) in the first trench region (3); a first CMP module for performing the first CMP to remove the first LOCOS oxide layer (4) above the surface of the substrate (1); a second etching module for etching from the top downward in the back part of the VLD terminal ring region (2) to form the second trench region (5), and making the depth of the second trench region (5) different from that of the first trench region (3); Secondary etching module: for etching a second trench region (5) from the top down in the rear part of the VLD terminal ring region (2), and growing a second LOCOS oxide layer (6) in the second trench region (5); Secondary CMP module: for implementing secondary CMP to remove the second LOCOS oxide layer (6) above the surface of the substrate (1).
10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method according to any one of claims 5-8.