Spliced screen phase synchronization method and device, storage medium and computer program product

Abstract

The invention discloses a spliced screen phase synchronization method and device, a storage medium and a computer program product, and relates to the technical field of computer multimedia, and the method comprises the steps: selecting a master node and a slave node from a distributed decoder system; calculating a phase error value of the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; and if the phase error value exceeds a preset error threshold value, adjusting a frequency multiplication coefficient in a node phase-locked loop to perform phase synchronization. And the slave node phase is pulled to the master node by adjusting the frequency multiplication coefficient of the node phase-locked loop, so that the phase synchronization of the master and slave nodes is realized. As the adjusting quantity is small and only parameters of the node phase-locked loop are modified, and no hardware is added, low-cost multiplexing on all universal embedded processors can be realized, and high-precision phase synchronization among distributed decoders is realized in a low-cost and universal manner.

Description

Technical Field

[0001] This application relates to the field of computer multimedia technology, and in particular to methods, devices, storage media and computer program products for phase synchronization of video walls. Background Technology

[0002] The key to a distributed decoder system lies in the phase synchronization accuracy among multiple nodes. Display synchronization is primarily addressed in two ways: one is to ignore phase differences and control each decoder to output the same frame image solely through software; the other is to use additional equipment (such as a master node) to coordinate phase synchronization uniformly. The former cannot eliminate phase asynchrony, and tearing or desynchronization will still occur when the image is moving rapidly; the latter increases system complexity, construction difficulty, and hardware costs, while also reducing system stability.

[0003] Therefore, how to achieve high-precision phase synchronization between distributed decoders in a low-cost and universal manner has become a technical problem that this application urgently needs to solve.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a method, device, storage medium, and computer program product for phase synchronization of video walls, aiming to solve the technical problem of how to achieve high-precision phase synchronization between distributed decoders in a low-cost and universal manner.

[0006] To achieve the above objectives, this application proposes a phase synchronization method for video wall splicing screens, the method comprising: Select a master node and a slave node from the distributed decoder system; Calculate the phase error between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; If the phase error value exceeds the preset error threshold, the frequency multiplication coefficient in the node phase-locked loop is adjusted to perform phase synchronization.

[0007] In one embodiment, the step of calculating the phase error value between the local timestamp in the slave node and the timestamp of the master node includes: The master node and the slave node are synchronized based on a precise time protocol. The master node periodically broadcasts its timestamp to the slave node; In the interrupt procedure of the slave node's own vertical synchronization signal, the phase error value of the first vertical synchronization signal in the master node and the second vertical synchronization signal in the slave node is calculated.

[0008] In one embodiment, the node phase-locked loop includes a master node phase-locked loop and a slave node phase-locked loop. The step of adjusting the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization if the phase error value exceeds a preset error threshold includes: If the phase error value exceeds the preset error threshold, the first incremental value, which is pre-stacked on the fractional part of the frequency multiplication coefficient in the master node phase-locked loop, is maintained. Based on the pre-addition of a second incremental value to the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop is adjusted; The second vertical synchronization signal of the slave node is adjusted based on the fractional part of the frequency multiplication coefficient in the adjusted slave node phase-locked loop; Phase synchronization is achieved by eliminating the phase error value based on the adjusted second vertical synchronization signal.

[0009] In one embodiment, after the step of selecting a master node and a slave node from the distributed decoder system and synchronizing the master node and the slave node based on a precise time protocol, the method further includes: Calculate the pixel clock cycle adjustment amount corresponding to the preset error threshold; The first increment value and the second increment value are obtained by reverse calculation based on the pixel clock cycle adjustment amount; The first incremental value is superimposed on the fractional part of the frequency multiplication coefficient in the master node phase-locked loop; The second incremental value is superimposed on the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop.

[0010] In one embodiment, the step of adjusting the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, based on the pre-addition of a second incremental value to the fractional part of the frequency multiplication coefficient, includes: The adjustment threshold of the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop is determined based on the second incremental value pre-superimposed on the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop; Based on the adjustment threshold, and with the second incremental value pre-added to the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, a recursive smoothing calculation method is used to progressively adjust the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop.

[0011] In one embodiment, the step of adjusting the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization if the phase error value exceeds a preset error threshold further includes: On the slave node, statistical methods are used to filter out abnormal timestamp data packets to obtain valid timestamp data packets; The preset error threshold is adjusted based on the jitter characteristics of the valid timestamp data packet.

[0012] In one embodiment, the step of adjusting the preset error threshold based on the jitter characteristics of the valid timestamp data packet includes: The mean and standard deviation of the time interval between adjacent frames are calculated based on a sliding window of valid timestamps maintained by the nodes. The jitter characteristics of the valid timestamp data packets are quantified based on the mean and the standard deviation. The preset error threshold is adjusted based on the quantized jitter characteristics.

[0013] In addition, to achieve the above objectives, this application also proposes a video wall phase synchronization device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the video wall phase synchronization method described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the splicing screen phase synchronization method described above.

[0015] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the splicing screen phase synchronization method described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: A master node and slave nodes are selected from the distributed decoder system. The phase error between the local timestamp of the slave node and the timestamp of the master node is calculated. If the phase error exceeds a preset error threshold, the fractional part of the frequency multiplication coefficient in the node's phase-locked loop (PLL) is adjusted for phase synchronization. First, the distributed decoder system is reused, selecting master and slave nodes from an existing system. This establishes a synchronization reference without additional hardware, reducing system costs. Further, after selecting the master and slave nodes, each slave node subtracts the master node's timestamp from its local timestamp to obtain the phase error. When this error exceeds the preset threshold, only the fractional part of the PLL's frequency multiplication coefficient is adjusted. By adjusting the fractional part of the PLL's frequency multiplication coefficient, the output pixel clock frequency of the slave node undergoes a very small change, thereby pulling the slave node's phase towards the master node's, achieving phase synchronization between the master and slave nodes. Because the adjustment is minimal and only modifies the parameters of the node's PLL without adding any hardware, it can be reused at low cost on all general-purpose embedded processors to achieve high-precision phase synchronization between distributed decoders. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the first embodiment of the splicing screen phase synchronization method of this application; Figure 2 A schematic diagram of a typical distributed decoder system provided in this application; Figure 3 This is a flowchart illustrating the second embodiment of the splicing screen phase synchronization method of this application. Figure 4 This is a flowchart illustrating the third embodiment of the splicing screen phase synchronization method of this application; Figure 5 This is a flowchart illustrating the fourth embodiment of the splicing screen phase synchronization method of this application; Figure 6 This is a schematic diagram of the module structure of the splicing screen phase synchronization device according to an embodiment of this application; Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the splicing screen phase synchronization method in the embodiments of this application.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] The main solution of this application embodiment is to address the problem of inconsistent vertical synchronization signal phases among decoding nodes in a distributed video wall caused by network latency, crystal oscillator errors, and differences in power-on times. A phase synchronization method for video walls, entirely based on a general-purpose embedded processor and requiring no additional hardware, is proposed: First, a unique master node is elected in the distributed decoder system, and the remaining nodes automatically become slave nodes. Then, the master node and the slave nodes are synchronized using a precise time protocol. When each vertical synchronization signal interruption occurs, the master node periodically broadcasts the interrupted master node timestamp to the slave nodes via multicast. Each slave node receives and parses the timestamp from its local vertical synchronization signal interruption service routine, subtracting it from its local timestamp to obtain the timestamp difference. Since the timestamp is a precise quantized record of the physical trigger time of the vertical synchronization signal, under the premise of time base synchronization, the timestamp difference directly reflects the phase deviation of the vertical synchronization signal. No additional conversion is required, and the timestamp difference can be directly used as the phase error value of the vertical synchronization signal between the master and slave nodes. If the error exceeds a preset threshold, the slave node initiates a phase correction process. The phase correction process adjusts only the fractional part of the frequency multiplication coefficient in the node's phase-locked loop (PLL). By adjusting this fractional part, the output pixel clock is instantaneously sped up or slowed down, thus aligning the slave node's vertical synchronization signal phase with the master node. Simultaneously, to avoid misadjustment caused by network jitter, the slave node performs statistical filtering on multiple consecutive error values ​​before adjustment, ensuring system stability. Throughout the process, the fractional increment of the master node's frequency multiplication coefficient remains fixed, with only the slave nodes uniformly adding the same fractional offset during initialization. Subsequent small closed-loop corrections are performed near this offset, ensuring universality across any resolution (including custom resolutions) without introducing screen flicker or system lockout due to excessive adjustment. This achieves high-precision phase synchronization between distributed decoders using purely software methods with zero additional hardware cost, ultimately resulting in a tear-free and misaligned fully synchronized display on the large screen.

[0024] This application's embodiments take into account that the key to a distributed decoder system lies in the phase synchronization accuracy between multiple nodes. The display synchronization problem is mainly solved in two ways: one is to ignore phase differences and control each decoder to output the same frame image solely through software control; the other is to use additional equipment (such as a master control node) to uniformly coordinate phase synchronization. The former cannot eliminate phase asynchrony problems, and tearing or asynchrony will still occur when the image moves rapidly; the latter increases system complexity, construction difficulty, and hardware costs, while also reducing system stability.

[0025] Therefore, this application provides a solution that selects a master node and a slave node from the distributed decoder system; calculates the phase error value between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; if the phase error value exceeds a preset error threshold, the fractional part of the frequency multiplication coefficient in the node's phase-locked loop is adjusted for phase synchronization. First, the distributed decoder system is reused, and master and slave nodes are selected from the existing distributed decoder system, establishing a synchronization reference without additional hardware, thus reducing system costs. Further, after selecting the master and slave nodes, each slave node subtracts the phase error value between the second vertical synchronization signal in its local slave node and the first vertical synchronization signal in the master node to obtain the phase error value. When this error value exceeds a preset threshold, only the fractional part of the frequency multiplication coefficient in the node's phase-locked loop is adjusted. By adjusting the fractional part of the frequency multiplication coefficient, the output pixel clock frequency of the slave node undergoes a very small change, thereby pulling the slave node's phase towards the master node, achieving phase synchronization between the master and slave nodes. Because the adjustment amount is small and only the parameters of the node phase-locked loop are modified without adding any hardware, it can be reused at low cost on all general-purpose embedded processors to achieve high-precision phase synchronization between distributed decoders.

[0026] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or distributed decoder system capable of performing the above functions. The following description uses a distributed decoder system as an example to illustrate this embodiment and the subsequent embodiments.

[0027] Based on this, embodiments of this application provide a method for phase synchronization of video wall displays, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the splicing screen phase synchronization method of this application.

[0028] In this embodiment, the splicing screen phase synchronization method includes steps S10~S30: Step S10: Select a master node and a slave node from the distributed decoder system; Distributed decoder system: A splicing screen system composed of multiple embedded processor nodes with independent network interfaces, video decoding units and display output interfaces. The nodes are interconnected through Ethernet or similar local area networks, and together they decode one or more bit streams, trim, scale and output them to the physical display unit, thereby visually splicing them into a complete picture.

[0029] refer to Figure 2 , Figure 2 A schematic diagram of a typical distributed decoder system provided in this application is shown. Figure 2 As shown, Figure 2The system consists of four decoding nodes forming a 2x2 large video wall, which can be configured into any mxn size in engineering practice. Each decoding node independently decodes the bitstream from the network, then performs operations such as cropping, scaling, and overlaying before sending it to the output module to ultimately present a complete large screen to the user. However, due to differences in the network transmission time of the same video frame data from different nodes, the load on different nodes, and the phase of the output vsync (Vertical Sync) signal, the same video frame may be sent to the video memory at different times, resulting in tearing and desynchronization problems.

[0030] Additionally, it should be noted that the master node refers to the single decoder node elected as the time base within the system, whose local crystal oscillator and vsync interrupt are considered as references for phase alignment across the entire system. Slave nodes refer to the remaining decoder nodes besides the master node; these nodes need to correct their own vsync phase based on the master node's timestamp.

[0031] The purpose of electing a master node is to provide a unified and stable clock reference for the entire distributed system, thereby avoiding phase drift caused by the independent operation of each node. The election operation can be completed during the system power-on initialization phase or dynamically triggered when the network topology changes.

[0032] In one possible implementation, the system can automatically select the master node by using a preset minimum MAC address rule; in another possible implementation, the system can elect the master node based on the node's real-time load, crystal oscillator stability, or a manually configured strategy to ensure that the master node has optimal clock stability.

[0033] For example, in one specific implementation, when the 2×2 distributed splicing screen is powered on, each of the four decoder nodes broadcasts an "election message" containing its own MAC address, crystal oscillator temperature drift compensation value, and CPU load. After comparison over three heartbeat cycles, the node with the smallest MAC address and the best crystal oscillator compensation value is selected as the master node, and the other three automatically become slave nodes and continuously listen to the vsync timestamp message sent by the master node in subsequent operation.

[0034] Step S20: Calculate the phase error value between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; The Vertical Synchronization Signal (Vsync) is a hardware signal used in display devices to synchronize frame refreshes. It is triggered once after each frame of image is drawn and determines the screen's refresh rate. The phase error value is the difference in triggering time between the master node Vsync1 and the slave node Vsync2, which directly causes screen tearing or misalignment in the video wall.

[0035] Specifically, the master node and the slave node are synchronized using a precise time protocol. When each vertical synchronization signal interruption occurs, the master node periodically broadcasts the interrupted master node timestamp to the slave node via multicast. Each slave node receives and parses the timestamp from its local vertical synchronization signal interruption service routine, and calculates the difference between the timestamp and its local timestamp. Since the timestamp is a precise quantized record of the physical trigger time of the vertical synchronization signal, under the premise of time base synchronization, the timestamp difference directly reflects the phase deviation of the vertical synchronization signal. No additional conversion is required, and the timestamp difference can be directly used as the phase error value of the vertical synchronization signal between the master and slave nodes.

[0036] Additionally, it should be noted that the purpose of calculating the phase error value is to quantify the deviation between the current output phase of the slave node and the reference phase of the master node, providing a basis for subsequent closed-loop adjustment; this calculation process is completed within the vsync interrupt service routine of the slave node to ensure that the error value is strictly aligned with the video frame period.

[0037] Step S30: If the phase error value exceeds the preset error threshold, adjust the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization.

[0038] The preset error threshold refers to the phase tolerance allowed by the system. It can be set according to the physical specifications of the splicing screen, the threshold that can be perceived by the human eye, and the statistical results of network jitter. The typical value is between ±500ns and ±2µs. A phase-locked loop (PLL) refers to a programmable PLL used within an embedded processor to generate video pixel clocks. Its output frequency is determined by the integer part (fbdiv) and the fractional part (frac) of the multiplication factor. Adjusting the multiplication factor in a PLL specifically refers to adjusting the fractional part of the multiplication factor, i.e., frac, as shown in the following formula: FOUTVCO=FREF×(fbdiv+frac / 2 24 ) / refdiv(1) FOUTPOSTDIV = FOUTVCO / (pstdiv1× pstdiv2) (2) Here, FOUTVCO refers to the core operating frequency of the PLL, which is recommended to be between 600MHz and 1.6GHz; FREF refers to the input reference clock, which must be 24MHz; frac is the fractional part of the PLL multiplication factor; fbdiv is the integer part of the multiplication factor; refdiv is the division factor of the input reference clock; the adjustment step size can be accurate to 1 / 2. 24FOUTPOSTDIV represents the output frequency after frequency division. For example, the target FOUTPOSTDIV corresponding to 1080P60 resolution is 148.5MHz. pstdiv1 represents the first-stage output frequency division coefficient. pstdiv2 represents the second-stage output frequency division coefficient.

[0039] Phase synchronization refers to the process of continuously fine-tuning the frac value of the slave node's phase-locked loop so that the difference between the slave node's vsync interruption time and the master node's vsync interruption time converges to within a preset error threshold.

[0040] Additionally, it should be noted that when the phase error value exceeds the threshold, the system gradually approaches the target phase in a closed-loop manner: first, the direction of frac increase or decrease is determined according to the polarity of the error, then a small step Δ is output according to the preset proportional coefficient K, and then the phase error change in the next frame is observed. If the error decreases, the adjustment continues in the same direction; otherwise, the correction is performed in the opposite direction until the error converges. The entire adjustment process has an impact of less than 50 ppm on the output frequency, and the change in screen brightness or size is imperceptible to the naked eye.

[0041] This embodiment provides a phase synchronization method for video wall displays. It reuses a distributed decoder system, selecting master and slave nodes from an existing system. This allows for the establishment of a synchronization reference without additional hardware, reducing system costs. Further, after selecting the master and slave nodes, each slave node subtracts the second vertical synchronization signal from the slave node's signal from the first vertical synchronization signal from the master node to obtain the phase error value. When this error value exceeds a preset threshold, only the fractional part of the node's phase-locked loop (PLL) frequency multiplication coefficient is adjusted. By adjusting this fractional part, the output pixel clock frequency of the slave node undergoes a very small change, thereby pulling the slave node's phase towards the master node, achieving phase synchronization between the master and slave nodes. Because the adjustment is minimal and only modifies the parameters of the node's PLL without adding any hardware, it can be reused at low cost on all general-purpose embedded processors to achieve high-precision phase synchronization between distributed decoders.

[0042] In one feasible implementation, step S20 may include steps S21 to S23: Step S21: Synchronize the time of the master node and the slave node based on the Precision Time Protocol; Precision Time Protocol (PTP) is a protocol used to achieve sub-microsecond clock synchronization in packet networks such as Ethernet.

[0043] The distributed decoder system distributes the absolute time information of the master node to all slave nodes through the PTP protocol, so that the clock deviation of each node converges to an acceptable nanosecond range, laying a unified time reference for subsequent vsync phase alignment.

[0044] Additionally, it should be noted that the time synchronization process using the PTP protocol includes a delayed request-response mechanism and an optimal master clock algorithm. The system can dynamically adjust the master-slave relationship according to the network topology to ensure rapid switching even if the master node goes offline, thus maintaining time continuity.

[0045] In one possible implementation, PTP packets are timestamped directly at the MAC (Media Access Control) layer to eliminate protocol stack jitter, bypass the software processing delay of the operating system protocol stack, and reduce timestamp errors caused by network protocol stack scheduling jitter.

[0046] In another possible implementation, the system can use a hardware PTP engine to complete the timestamp overlay at the PHY (Physical Layer), which further moves the timestamp acquisition point forward to the physical layer signal transmission and reception time, minimizing delay fluctuations in the hardware transmission path. This provides a more accurate time reference for subsequent decoding nodes to perform phase adjustment based on timestamps, ultimately improving the stability and accuracy of the splicing screen's phase synchronization.

[0047] Step S22: Periodically broadcast the master node timestamp from the master node to the slave node; Periodic broadcasting refers to the master node sending its timestamp to all slave nodes at fixed or variable intervals via UDP (User Datagram Protocol) multicast or Ethernet Layer 2 multicast frames. The master node timestamp is a nanosecond-level count value obtained by the master node from its local PTP clock at the moment a vsync interrupt is triggered. The broadcast mechanism ensures that all slave nodes receive the timestamp almost simultaneously, avoiding the latency differences caused by point-to-point polling, thereby guaranteeing the consistency of phase error calculation.

[0048] Additionally, it should be noted that the broadcast cycle can be dynamically adjusted based on network load: the frequency is reduced when the network is congested and increased when it is idle, in order to balance bandwidth usage and real-time synchronization.

[0049] Step S23: Calculate the phase error value between the first vertical synchronization signal in the master node and the second vertical synchronization signal in the slave node in the slave node's own vertical synchronization signal interruption procedure.

[0050] The self-vertical synchronization signal interrupt routine refers to the interrupt service routine running on the slave node processor and directly associated with the vsync signal; the phase error value refers to the difference between the local timestamp recorded by the slave node at the moment of the vsync interrupt and the timestamp just received from the master node. The signed result directly reflects the leading or lagging relationship. This interrupt routine ensures that the error value is strictly aligned with the video frame, avoids sampling jitter, and provides real-time input for subsequent closed-loop adjustment.

[0051] Specifically, the master node and the slave node are synchronized using a precise time protocol. When each vertical synchronization signal interruption occurs, the master node periodically broadcasts the interrupted master node timestamp to the slave node via multicast. Each slave node receives and parses the timestamp from its local vertical synchronization signal interruption service routine, and calculates the difference between the timestamp and its local timestamp. Since the timestamp is a precise quantized record of the physical trigger time of the vertical synchronization signal, under the premise of time base synchronization, the timestamp difference directly reflects the phase deviation of the vertical synchronization signal. No additional conversion is required, and the timestamp difference can be directly used as the phase error value of the vertical synchronization signal between the master and slave nodes.

[0052] Additionally, it should be noted that interrupt service routines typically perform only the lightest operations: reading registers, calculating differences, and pushing into a circular buffer. Complex filtering and adjustment logic is handled by user-mode tasks to reduce interrupt latency.

[0053] Based on the first embodiment of this application, a second embodiment of this application is proposed. In the second embodiment of this application, content that is the same as or similar to that in the first embodiment described above can be referred to the above description and will not be repeated hereafter.

[0054] Based on this, please refer to Figure 3 , Figure 3 This is a schematic diagram of the process of the second embodiment of this application. Figure 3 As shown, if the phase error value exceeds a preset error value, step S30, which involves adjusting the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization, includes steps S31 to S34: Step S31: If the phase error value exceeds the preset error threshold, then maintain the first incremental value pre-stacked on the fractional part of the frequency multiplication coefficient in the master node phase-locked loop; The preset error threshold refers to the maximum allowable error range that the distributed decoder system pre-sets to determine whether the phase error needs to be corrected. It is usually expressed in milliseconds or microseconds, and can also be converted into the number of pixel clock cycles. The first increment value DELTA1 refers to a fixed small offset superimposed on the fractional part frac of the phase-locked loop frequency multiplication coefficient of the master node during the initialization phase of the distributed decoder system. Its purpose is to make the output frequency of the master node slightly deviate from the nominal value, so as to provide symmetrical adjustment space for subsequent bidirectional fine-tuning of the slave node. "Maintain" means that the master node does not change the increment value throughout the entire operation, ensuring that the master node's phase reference remains constant. This strategy guarantees the stability of the master node while providing a traceable reference for the slave nodes.

[0055] Additionally, it should be noted that the size of the first increment value is typically designed to produce a pixel clock offset of less than 50 ppm in order to avoid visually noticeable changes in image quality.

[0056] Step S32: Based on the pre-addition of the second incremental value to the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, adjust the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop; The second increment value, DELTA2, refers to another fixed, small offset that is uniformly superimposed on the fractional part of the phase-locked loop frequency multiplication coefficients (frac) of all slave nodes during the initialization phase of the distributed decoder system. It is typically equal to the value of the first increment value, DELTA1. "Adjustment" refers to the closed-loop fine-tuning performed by the slave nodes based on the second increment value, correcting phase errors in real time through ±Δ steps. This allows the slave nodes to achieve bidirectional fine-grained adjustment without crossing integer boundaries, ensuring a symmetrical and monotonic adjustment range.

[0057] Step S33: Adjust the second vertical synchronization signal of the slave node based on the fractional part of the frequency multiplication coefficient in the adjusted slave node phase-locked loop; It's important to note that the vertical synchronization signal, or Vsync, is a pulse signal used by the video output port to indicate the start of a new frame. Adjusting the Vsync signal involves changing the fractional part of the slave node's phase-locked loop (PLL) multiplication factor, thereby altering the pixel clock frequency and indirectly changing the Vsync period and phase, aligning the rising edge of the slave node's Vsync with that of the master node. Since Vsync originates from pixel clock frequency division, and the pixel clock is output by the PLL, fine-tuning the frac can adjust the phase of the second Vsync within the next frame period, achieving frame-by-frame approximation.

[0058] Step S34: Eliminate the phase error value based on the adjusted second vertical synchronization signal and perform phase synchronization.

[0059] Eliminating phase error refers to continuously adjusting the closed-loop system until the error value eventually converges to within a preset error threshold. Phase synchronization refers to ensuring that the vsync interruption times of all decoding nodes within the distributed decoder system remain consistent within a tolerable range, thereby achieving a tear-free and misaligned large-screen splicing display. This process relies on a negative feedback loop of error detection, adjustment, and re-detection until the error is consistently below the threshold, at which point the system enters a maintenance state.

[0060] In addition, it should be noted that the system still periodically monitors the error in the maintenance state, and only triggers the adjustment again when the error exceeds the limit again, thus balancing stability and power consumption.

[0061] In this embodiment, the fractional part of the master node's phase-locked loop (PLL) frequency multiplication coefficient is fixed at a preset first increment value, ensuring that the master node's output clock maintains a stable phase reference. A second increment value is pre-added to the fractional part of the PLL frequency multiplication coefficients of all slave nodes, and closed-loop fine-tuning is performed on this basis to ensure that the slave nodes have symmetrical and continuous adjustment space. The fine-tuned frequency multiplication coefficients are used to change the pixel clock frequency of the slave nodes in real time, thereby aligning the phase of the vertical synchronization signal to the master node frame by frame. By continuously monitoring the error and stopping adjustment when the error enters a preset threshold range, the error is eventually converged and maintained. In summary, phase errors between distributed decoders are eliminated in a low-cost and high-precision manner on a general-purpose embedded processor platform using a software approach with zero additional hardware. This ensures that the vertical synchronization signals of each display unit of the splicing screen are completely aligned, resulting in a tear-free and misaligned image, achieving a visual synchronization effect equivalent to that of a single device output.

[0062] In one possible implementation, step S32 may include steps S321 to S322: Step S321: Determine the adjustment threshold of the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop based on the second incremental value pre-superimposed on the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop; The adjustment threshold refers to the maximum absolute range within which frac can change again during subsequent progressive adjustments, to prevent over-adjustment from causing screen flickering or PLL lockout. The adjustment threshold is ±DELTA2, which means that the slave node adjusts within the range of ±DELTA2 based on the fractional part of the frequency multiplication coefficient in the slave node's PLL, which is then superimposed with DELTA2.

[0063] Step S322: Based on the adjustment threshold, and on the basis of pre-adding a second incremental value to the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, a recursive smoothing calculation method is used to progressively adjust the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop.

[0064] Recursive smoothing calculation refers to using algorithms such as exponential weighting, first-order low-pass filtering, or moving average to recursively merge the current phase error with historical correction values ​​and output a smoothed correction value.

[0065] Gradual adjustment emphasizes changing only a tiny amount of frac each time, gradually approaching the target phase over multiple frames to avoid abrupt changes. When each vsync interrupt occurs, the system first calculates the current phase error. When the phase error exceeds a preset threshold, since the pixel clock frequency is determined by the PLL's multiplication factor, the pixel clock frequency fine-tuning amount and the fractional part of the PLL multiplication factor (frac amount) represent the target and its implementation. Therefore, when the phase error exceeds the preset threshold, the fractional part of the slave node's PLL multiplication factor is adjusted, thereby achieving pixel clock frequency fine-tuning.

[0066] The specific calculation formula is as follows: (3) in, This represents the phase error value between the slave node and the master node in the nth iteration. This represents the amount of pixel clock frequency fine-tuning that needs to be adjusted in the nth iteration. This represents the amount of pixel clock frequency fine-tuning from the last adjustment. K and a are preset fixed parameters used to control the sensitivity and smoothness of the adjustment.

[0067] Based on the first and / or second embodiments of this application, a third embodiment of this application is proposed. In the third embodiment of this application, content that is the same as or similar to the first and / or second embodiments described above can be referred to the above description and will not be repeated hereafter.

[0068] Based on this, please refer to Figure 4 , Figure 4 This is a schematic diagram of the process of the third embodiment of this application, as shown below. Figure 4 As shown, after step S10 of selecting the master node and slave node from the distributed decoder system, steps S121 to S124 are further included: Step S121: Calculate the pixel clock cycle adjustment amount corresponding to the preset error threshold; The pixel clock cycle adjustment refers to the number of pixel clock cycles that need to be added or reduced to compensate for a preset phase error at the video output. The default initial maximum allowable phase deviation, i.e., the preset error threshold, is used as the basis for calculating DELTA1 and DELTA2.

[0069] Based on a preset error threshold, the system calculates the number of pixel clock cycles that need to be adjusted per unit time, thereby ensuring the accuracy and stability of subsequent phase synchronization adjustments. This calculation process takes into account display resolution, refresh rate, PLL lock range, and network jitter statistics, ensuring that the adjustment amount is sufficient to correct the phase error without causing screen flickering or system lockout due to excessive adjustment.

[0070] Step S122: The first increment value and the second increment value are obtained by reverse calculation based on the pixel clock cycle adjustment amount; The system converts the pixel clock cycle adjustment into the corresponding fractional part of the change in frac using the formula (1) above, thereby deriving the first and second increment values. This reverse deduction process ensures that the increment values ​​can achieve phase fine-tuning without causing the FOUTVCO frequency to exceed the chip's allowable range.

[0071] Step S123: The first incremental value is superimposed on the fractional part of the frequency multiplication coefficient in the master node phase-locked loop; By writing the sum of the original value and the first increment value to the frac register of the master node's phase-locked loop, a small and constant offset is generated in the master node's FOUTVCO frequency, thus making the master node's vsync signal the time reference for the entire video wall system. This overlay operation is performed only once and is completed during the system initialization phase, without subsequent changes, thereby avoiding reference frequency drift.

[0072] Additionally, it should be noted that in one possible implementation, the system writes the updated frac value to the PLL register inside the video processing chip; in another possible implementation, the system can also directly modify the register contents through memory-mapped I / O.

[0073] Step S124: The second incremental value is superimposed on the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop.

[0074] The slave node PLL has the same structure as the master node PLL, but its frac value can be dynamically adjusted according to the phase error during operation. During system initialization, both the master and slave nodes add a very small increment DELTA, i.e., a second increment value, to the base frac value in the PLL.

[0075] In this embodiment, the preset phase error threshold is precisely converted into an adjustment amount at the pixel clock cycle level. The adjustment amount is then reverse-mapped using the PLL's frac field resolution into a first increment value and a second increment value that can be directly written to the hardware register. The first increment is superimposed on the fractional part of the master node's phase-locked loop, causing its output frequency to produce a constant and minute reference offset. The second increment value is dynamically superimposed on the fractional part of each slave node's phase-locked loop, continuously reducing the phase difference by fine-tuning the pixel clock frequency in real time. Thus, the entire distributed splicing screen achieves high-precision phase alignment of the vsync signals of all decoding nodes without adding any extra hardware or modifying the video link. This eliminates tearing and asynchrony in fast-moving scenes, simplifies construction and wiring, improves display consistency, and ensures the algorithm's portability to various general-purpose embedded processor platforms and the system's long-term operational stability.

[0076] Based on the above embodiments of this application, a fourth embodiment of this application is proposed. In this fourth embodiment, content that is the same as or similar to that in the above embodiments can be referred to the above description, and will not be repeated hereafter.

[0077] Based on this, please refer to Figure 5 , Figure 5 This is a flowchart illustrating the fourth embodiment of this application, as shown below. Figure 5 As shown, if the phase error value exceeds a preset error threshold, steps S231-S232 are included before step S30, which involves adjusting the fractional part of the frequency multiplication coefficient in the node phase-locked loop for phase synchronization: Step S231: Statistical methods are used on the slave node to filter out abnormal timestamp data packets to obtain valid timestamp data packets; Statistical methods refer to the analysis and filtering of timestamp data packets received from the node using mathematical statistical methods; abnormal timestamp data packets refer to data packets whose timestamps deviate too much from the expected values ​​due to network jitter, link congestion, or clock mutations; valid timestamp data packets refer to data packets that have been filtered and retained and can truly reflect the time of the master node's vsync interruption.

[0078] To avoid misadjustment caused by network jitter, the slave node performs statistical filtering on multiple consecutive sets of error values ​​before performing adjustments, ensuring system stability. The slave node performs sliding window statistics on the received multicast timestamps, calculating the deviation of each timestamp from the mean within the window, and removing outliers exceeding 3σ (three standard deviations). This effectively suppresses instantaneous errors caused by network jitter, ensuring that subsequent phase synchronization algorithms operate based on reliable data and improving system robustness.

[0079] Additionally, it should be noted that in one possible implementation, the system uses a moving median filter instead of a moving mean filter to further enhance the ability to suppress sudden jitter; in another possible implementation, the system introduces a timestamp sequence number consistency check to discard data packets with alternating or duplicate sequence numbers.

[0080] Step S232: Adjust the preset error threshold according to the jitter characteristics of the valid timestamp data packet.

[0081] Jitter refers to the degree of time interval fluctuation exhibited by valid timestamp data packets during transmission, typically characterized by statistics such as standard deviation, peak-to-peak value, or jitter coefficient. The system dynamically adjusts a preset error threshold by analyzing jitter characteristics in real time: when the network environment is good and jitter is low, the threshold is reduced to improve synchronization accuracy; when network jitter increases, the threshold is appropriately widened to avoid frequent misalignments. This mechanism enables the phase synchronization algorithm to adapt to different network conditions, balancing synchronization accuracy and stability.

[0082] Additionally, it should be noted that in one possible implementation, the system uses a linear mapping to directly map the standard deviation to the threshold increment; in another possible implementation, the system uses a piecewise function to keep the threshold unchanged when the standard deviation is below the first threshold, and to relax the threshold exponentially when it is above the second threshold.

[0083] In this embodiment, a safe and accurate adjustment threshold is first calculated based on the second incremental value superimposed on the frac field of the slave node's phase-locked loop (PLL). This strictly limits any possible changes in frac during the subsequent recursive smoothing process to a small range allowed by the chip specifications, thereby preventing screen flickering or PLL lockout due to over-correction. Subsequently, using a recursive smoothing calculation method, only a gradual, minute correction is applied to frac in each vsync cycle, causing the phase error to gradually decrease at an exponential convergence rate. This effectively filters out high-frequency disturbances from network jitter while maintaining continuous PLL locking and smooth transition of the pixel clock. Ultimately, the entire distributed splicing screen achieves high-precision, tear-free, and flicker-free phase synchronization of the vsync signals between all slave nodes and the master node without adding any additional hardware, significantly improving display consistency and system robustness.

[0084] In one feasible implementation, step S232 may include steps S1 to S3: Step S1: Calculate the mean and standard deviation of the time interval between adjacent frames based on the sliding window of the valid timestamps maintained by the slave node; A sliding window refers to a fixed-length or fixed-time first-in-first-out (FIFO) buffer used to store the N most recent valid timestamps. The adjacent frame time interval refers to the difference between the current and previous timestamps, reflecting the actual period of the master node's vsync interruption. The mean is the arithmetic average of all interval values ​​within the window, used to estimate the expected period. The standard deviation refers to the degree to which the interval values ​​deviate from the mean, used to quantify the jitter magnitude. When each vsync interruption occurs, the slave node pushes the latest timestamp into the window and removes the oldest timestamp, updating the mean and standard deviation in real time to provide input for subsequent jitter feature quantization. The window length is adaptively adjusted according to network conditions; when jitter is high, the window is shortened to improve response speed.

[0085] Step S2: Quantify the jitter characteristics of the valid timestamp data packet based on the mean and the standard deviation; The statistically obtained mean and standard deviation are converted into a dimensionless or comparable jitter metric. The jitter characteristic is ultimately output as a numerical value to drive threshold adjustment. The system can use the standard deviation itself as the jitter metric, or the ratio of the standard deviation to the mean (coefficient of variation) as the normalization metric, thereby eliminating the influence of different refresh rates. This quantification result directly determines the direction and magnitude of the preset error threshold adjustment.

[0086] Additionally, it should be noted that in one possible implementation, the system uses peak-to-peak value as a jitter metric; in another possible implementation, the system uses exponentially weighted moving standard deviation to improve sensitivity to sudden jitter.

[0087] Step S3: Adjust the preset error threshold based on the quantized jitter characteristics.

[0088] The system receives the quantized jitter feature value output from the previous step and converts it into a new preset error threshold using a pre-defined mapping rule or lookup table mechanism. The aim is to ensure that the phase synchronization algorithm maintains performance that is both fast-converging and infrequently jittering when network conditions change. The mapping rule can be designed as a monotonically increasing function to ensure that the threshold widens as jitter increases; alternatively, a hysteresis interval can be introduced to prevent the threshold from frequently fluctuating near the critical point. The final output threshold is written to the synchronization control register for real-time use by the phase error judgment logic.

[0089] This application also provides a phase synchronization device for video wall displays; please refer to [reference needed]. Figure 6 The splicing screen phase synchronization device includes: The node selection module 10 is used to select master nodes and slave nodes from the distributed decoder system. Error calculation module 20 is used to calculate the phase error value between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; The phase synchronization module 30 is used to adjust the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization if the phase error value exceeds a preset error threshold.

[0090] The video wall phase synchronization device provided in this application, employing the video wall phase synchronization method in the above embodiments, can solve the technical problem of video wall phase synchronization. Compared with the prior art, the beneficial effects of the video wall phase synchronization device provided in this application are the same as those of the video wall phase synchronization method provided in the above embodiments, and other technical features in the video wall phase synchronization device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0091] This application provides a video wall phase synchronization device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the video wall phase synchronization method in the above embodiment 1.

[0092] The following is for reference. Figure 7This document illustrates a structural schematic diagram of a video wall phase synchronization device suitable for implementing embodiments of this application. The video wall phase synchronization device in this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 7 The splicing screen phase synchronization device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0093] like Figure 7 As shown, the video wall phase synchronization device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the video wall phase synchronization device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, touch screens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the video wall phase synchronization device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows video wall phase synchronization devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0094] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0095] The video wall phase synchronization device provided in this application, employing the video wall phase synchronization method described in the above embodiments, can solve the technical problem of video wall phase synchronization. Compared with the prior art, the beneficial effects of the video wall phase synchronization device provided in this application are the same as those of the video wall phase synchronization method provided in the above embodiments, and other technical features in this video wall phase synchronization device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0096] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0097] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0098] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the splicing screen phase synchronization method in the above embodiments.

[0099] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0100] The aforementioned computer-readable storage medium may be included in the video wall phase synchronization device; or it may exist independently and not be assembled into the video wall phase synchronization device.

[0101] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the splicing screen phase synchronization device, the splicing screen phase synchronization device: selects a master node and a slave node from the distributed decoder system; calculates the phase error value between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; and if the phase error value exceeds a preset error threshold, adjusts the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization.

[0102] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0104] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0105] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described splicing screen phase synchronization method, thereby solving the technical problem of splicing screen phase synchronization. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the splicing screen phase synchronization method provided in the above embodiments, and will not be repeated here.

[0106] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the splicing screen phase synchronization method described above.

[0107] The computer program product provided in this application can solve the technical problem of phase synchronization of video wall displays. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the phase synchronization method for video wall displays provided in the above embodiments, and will not be repeated here.

[0108] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A phase synchronization method for video wall splicing screens, characterized in that, The splicing screen phase synchronization method, applied to a distributed decoder system, includes: Select a master node and a slave node from the distributed decoder system; Calculate the phase error between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node; If the phase error value exceeds the preset error threshold, the frequency multiplication coefficient in the node phase-locked loop is adjusted to perform phase synchronization.

2. The method for phase synchronization of splicing screens as described in claim 1, characterized in that, The step of calculating the phase error value between the second vertical synchronization signal in the slave node and the first vertical synchronization signal in the master node includes: The master node and the slave node are synchronized based on a precise time protocol. The master node periodically broadcasts its timestamp to the slave node; In the interrupt procedure of the slave node's own vertical synchronization signal, the phase error value of the first vertical synchronization signal in the master node and the second vertical synchronization signal in the slave node is calculated.

3. The method for phase synchronization of splicing screens as described in claim 1, characterized in that, The node phase-locked loop includes a master node phase-locked loop and a slave node phase-locked loop. The step of adjusting the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization if the phase error value exceeds a preset error threshold includes: If the phase error value exceeds the preset error threshold, the first incremental value, which is pre-stacked on the fractional part of the frequency multiplication coefficient in the master node phase-locked loop, is maintained. Based on the pre-addition of a second incremental value to the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop is adjusted; The second vertical synchronization signal of the slave node is adjusted based on the fractional part of the frequency multiplication coefficient in the adjusted slave node phase-locked loop; Phase synchronization is achieved by eliminating the phase error value based on the adjusted second vertical synchronization signal.

4. The splicing screen phase synchronization method as described in claim 3, characterized in that, Following the step of selecting a master node and a slave node from the distributed decoder system, the following further steps are also included: Calculate the pixel clock cycle adjustment amount corresponding to the preset error threshold; The first increment value and the second increment value are obtained by reverse calculation based on the pixel clock cycle adjustment amount; The first incremental value is superimposed on the fractional part of the frequency multiplication coefficient in the master node phase-locked loop; The second incremental value is superimposed on the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop.

5. The method for phase synchronization of splicing screens as described in claim 3, characterized in that, The step of adjusting the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, based on the pre-addition of a second incremental value to the fractional part of the frequency multiplication coefficient, includes: The adjustment threshold of the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop is determined based on the second incremental value pre-superimposed on the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop; Based on the adjustment threshold, and with the second incremental value pre-added to the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop, a recursive smoothing calculation method is used to progressively adjust the fractional part of the frequency multiplication coefficient in the slave node phase-locked loop.

6. The method for phase synchronization of splicing screens as described in claim 1, characterized in that, Before the step of adjusting the frequency multiplication coefficient in the node phase-locked loop to perform phase synchronization if the phase error value exceeds a preset error threshold, the method further includes: On the slave node, statistical methods are used to filter out abnormal timestamp data packets to obtain valid timestamp data packets; The preset error threshold is adjusted based on the jitter characteristics of the valid timestamp data packet.

7. The method for phase synchronization of splicing screens as described in claim 6, characterized in that, The step of adjusting the preset error threshold based on the jitter characteristics of the valid timestamp data packet includes: The mean and standard deviation of the time interval between adjacent frames are calculated based on a sliding window of valid timestamps maintained by the nodes. The jitter characteristics of the valid timestamp data packets are quantified based on the mean and the standard deviation. The preset error threshold is adjusted based on the quantized jitter characteristics.

8. A phase synchronization device for video wall displays, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the splicing screen phase synchronization method as described in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the splicing screen phase synchronization method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the splicing screen phase synchronization method as described in any one of claims 1 to 7.

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