Sigma-Delta modulation system, control method thereof, chip and motor control system

Abstract

The invention discloses a Sigma-Delta modulation system, and the system comprises a two-way modulator module which is configured to process an analog signal to be sampled. The first modulation circuit processes the analog signal and outputs a first bit stream. And the second modulation circuit comprises an analog differential unit for performing analog differential processing on the analog signal to obtain a differential difference signal, processing the differential difference signal and outputting a second bit stream. And the microcontroller is used for receiving the first bit stream and the second bit stream output by the two-way modulator, and processing the first bit stream and the second bit stream through a Sigma-Delta modulation module in the microcontroller to obtain an original discrete signal and an original differential discrete signal. And predicting a signal value at a next sampling moment based on a linear combination of the original discrete signal and the original differential discrete signal so as to compensate the sampling delay of the system. The low-frequency-band quantization noise is reduced, the current data signal-to-noise ratio and the sampling resolution are improved, and the requirements of a motor control system for synchronism and data precision are met.

Description

Technical Field

[0001] This invention relates to the field of motor control technology, and in particular to a Sigma-Delta modulation system and its control method. Background Technology

[0002] In motor control systems, Sigma-Delta (Σ-Δ) modulators are commonly used for three-phase current sampling. They achieve high-precision data acquisition through oversampling and noise shaping. The oversampling rate and the module clock determine the sampling accuracy and time.

[0003] However, the sampling principle of the Sigma-Delta modulator results in significant data lag, which severely impacts the response speed of closed-loop control. Furthermore, the current sampling of each phase demands extremely high synchronization and real-time performance, but in traditional SDFM solutions, the first two data points after the synchronization signal trigger are prone to anomalies, failing to meet the dynamic adjustment requirements of motor control. For example, at a 20MHz clock speed and an oversampling rate of 250%, the sampling period is 12.5μs; this 12.5μs delay significantly affects the response speed of closed-loop control. In motor control applications, the Sigma-Delta sampling principle dictates that the current data acquired at time t via SDFM is actually lagging behind the current at time t-1. Similarly, the data acquired at time t+1 essentially corresponds to the signal value at time t, leading to a time misalignment between the sampling timing and the actual signal.

[0004] Existing Sigma-Delta modulators can only output a single current signal and lack a mechanism to compensate for delays. Directly using this data can lead to errors in the control algorithm. Therefore, the key to solving the motor control delay problem lies in achieving real-time current estimation by improving the Sigma-Delta modulator structure and combining it with differential compensation without reducing sampling accuracy. Summary of the Invention

[0005] The purpose of this invention is to provide a Sigma-Delta modulation system and its control method. By improving the Sigma-delta modulator structure to synchronously output the current signal and the differential signal, and combining the principle of linear slope compensation, dynamic compensation for current sampling delay is achieved without reducing sampling accuracy, effectively improving the real-time response capability of closed-loop control. Simultaneously, by utilizing the noise shaping characteristics of second-order modulation and oversampling technology, low-frequency quantization noise is reduced, improving the signal-to-noise ratio and sampling resolution of the current data, thus meeting the requirements of motor control systems for sampling synchronization and data accuracy.

[0006] This invention provides a Sigma-Delta modulation system comprising: a dual-channel modulator module configured to process an analog signal to be sampled. Specifically: a first modulation circuit processes the analog signal x(t) and outputs a first bitstream X(k). A second modulation circuit includes an analog differentiating unit that performs analog differentiating processing on the analog signal x(t) to obtain a differential difference signal dx(t), and processes the differential difference signal dx(t) to output a second bitstream dX(k). A microcontroller receives the first bitstream X(k) and the second bitstream dX(k) output by the dual-channel modulator, and processes the first bitstream X(k) and the second bitstream dX(k) through the Sigma-Delta modulation module within the microcontroller to obtain the original signal X(t') and the original differential signal dX(t'). Based on a linear combination of the original signal X(t') and the original differential signal dX(t'), the signal value at the next sampling time is predicted to compensate for the system sampling delay.

[0007] Further, the first modulation circuit includes: a first differential input unit for receiving the analog signal to be sampled x(t) and a first feedback analog signal and outputting a first difference signal; two cascaded integrators for performing second-order integration processing on the first difference signal; a first quantizer connected to the output of the final integrator for comparing the output of the final integrator with a reference level; and a first DAC feedback unit for converting the output of the first quantizer into a first feedback analog signal and feeding it back to the first differential input unit, forming a first closed-loop modulation structure. The output of the first modulation circuit is the first bit stream X(k) output by the first quantizer.

[0008] Further, the second modulation circuit includes: an analog differentiating unit; a second differential input unit for receiving the differential difference signal dx(t) and the second feedback analog signal and outputting the second difference signal; two cascaded integrators for performing second-order integration on the second difference signal; a second quantizer connected to the output of the final integrator for comparing the output of the final integrator with a reference level; and a second DAC feedback unit for converting the output of the second quantizer into a second analog feedback signal and feeding it back to the second differential input unit, forming a second closed-loop modulation structure. The output of the second modulation circuit is the second bitstream dX(k) output by the second quantizer.

[0009] Furthermore, the process of comparing the output of the final stage integrator with the reference level is as follows: the output is compared with the reference level, and the comparison operation is triggered by the rising or falling edge of the clock of the dual-channel modulation module. Specifically, when the output is greater than the reference level, the first quantizer and / or the second quantizer outputs a high-level signal. When the integration result is less than or equal to the reference level, the first quantizer and / or the second quantizer outputs a low-level signal.

[0010] Furthermore, the minimum time difference Δt of the system sampling delay satisfies: Δt=OSR×(T_SYSCLK / T_SDCLK). Where OSR is the oversampling rate, T_SYSCLK is the system clock period, and T_SDCLK ​​is the operating clock period of the Sigma-Delta modulation module.

[0011] Furthermore, the oversampling rate of the Sigma-Delta modulation module can be dynamically configured.

[0012] Furthermore, the analog differential unit includes two paths: one path directly transmits the analog signal x(t) to obtain the current value, and the other path delays the analog signal x(t) by one cycle through the delay unit to obtain the value of the previous moment. The signals output from the two paths are then subjected to a difference operation to output the difference signal, thereby completing the difference operation on the analog signal x(t) and realizing the differential function.

[0013] The present invention also provides a control method for a Sigma-Delta modulator, which utilizes any of the above-mentioned Sigma-Delta modulation systems. The method includes: predicting the signal value at the next sampling time using the formula X(t'+1)=X(t')+dX(t')·Δt by applying the properties of calculus and the slope compensation principle.

[0014] The present invention also provides an integrated Sigma-Delta modulator chip, comprising a dual-channel modulator structure in any of the above-mentioned Sigma-Delta modulation systems, wherein the first modulation circuit and the second modulation circuit share a clock source.

[0015] The present invention also provides a motor control system, including a Sigma-Delta modulation system utilizing any of the above-mentioned methods.

[0016] Compared with existing technologies, this invention improves the Sigma-delta modulator structure to synchronously output the current signal and the differential signal. Combined with the linear slope compensation principle, it achieves dynamic compensation for current sampling delay without reducing sampling accuracy, effectively improving the real-time response capability of closed-loop control. Simultaneously, it utilizes the noise shaping characteristics of second-order modulation and oversampling technology to reduce low-frequency quantization noise, improve the signal-to-noise ratio and sampling resolution of the current data, and meet the requirements of motor control systems for sampling synchronization and data accuracy. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a Sigma-Delta sampling timing misalignment in this invention;

[0018] Figure 2 This is a schematic diagram of a Sigma-Delta modulation system structure according to the first embodiment of the present invention;

[0019] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0021] Reference Figure 1 , Figure 1 The time nodes t-1 and t are clearly marked. According to the Sigma-Delta sampling principle, we want to obtain the current data at time t, but we actually obtain the current value at time t-1, causing a time misalignment between the sampling timing and the actual signal. Similarly, when we obtain data at time t+1, we do not get the actual current value at t+1, but rather the signal value at time t. This time misalignment can have certain impacts in motor control. For example, during real-time motor control, the controller relies on current data from previous times; without appropriate compensation or processing, this may lead to deviations in the control strategy. To solve the above technical problems, this invention provides a Sigma-Delta modulation system.

[0022] First embodiment:

[0023] Please see Figure 2 , Figure 2 A Sigma-Delta modulation system is provided, comprising: a dual-channel modulator module configured to process an analog signal to be sampled. This includes: a first modulation circuit 1, which processes the analog signal x(t) and outputs a first bitstream X(k); a second modulation circuit 2, comprising an analog differentiating unit 204 that performs analog differentiating processing on the analog signal x(t) to obtain a differential difference signal dx(t), and processes the differential difference signal dx(t) to output a second bitstream dX(k); and a microcontroller, which receives the first bitstream X(k) and the second bitstream dX(k) output by the dual-channel modulator, and processes the first bitstream X(k) and the second bitstream dX(k) through the Sigma-Delta modulation module within the microcontroller to obtain the original signal X(t') and the original differential signal dX(t'). Based on a linear combination of the original signal X(t') and the original differential signal dX(t'), the signal value at the next sampling time is predicted to compensate for the system sampling delay.

[0024] Specifically, the microcontroller receives the first bit stream X(k) and the second bit stream dX(k) output from the first modulation circuit 1 and the second modulation circuit 2 in the dual-channel modulator module. It then samples and processes the two signals using the built-in SDFM (Sigma-Delta Filter Module) to obtain the original signal X(t') and the differential signal dX(t') at the corresponding sampling time. Based on the principles of calculus, assuming the signal changes linearly within a small time interval, the microcontroller predicts the signal value at the next sampling time, thereby compensating for the delay caused by the Sigma-Delta sampling mechanism and achieving real-time estimation of the current signal.

[0025] By synchronously acquiring the original signal and the differential signal through a dual-channel modulator, and using the linear characteristics of the signal in a short time to make calculations, the lag data of traditional sampling is converted into predicted values. Without changing the oversampling rate and noise shaping mechanism, the delay problem of Sigma-Delta sampling is effectively solved, and the closed-loop response accuracy of the motor control system is improved.

[0026] Further, please see Figure 2 In another embodiment, the first modulation circuit 1 includes: a first differential input unit for receiving the analog signal to be sampled x(t) and a first feedback analog signal and outputting a first difference signal; two cascaded integrators, such as second-order integrators 101 (the specific form is determined according to the actual situation), for performing second-order integration processing on the first difference signal; a first quantizer 102 connected to the output of the final integrator (second-order integrator 101), for comparing the output of the final integrator (second-order integrator 101) with a reference level; and a first DAC feedback unit 103 for converting the output of the first quantizer 102 into a first feedback analog signal and feeding it back to the first differential input unit, forming a first closed-loop modulation structure. The output of the first modulation circuit 1 is the first bitstream X(k) output by the first quantizer 102.

[0027] Specifically, the first modulation circuit 1, as the core component of the dual-channel modulator module, has the following structure and operating logic: The first differential input unit receives the analog signal x(t) to be sampled and simultaneously receives the first feedback analog signal output by the first DAC feedback unit 103. The first differential input unit performs differential operations on the two signals to generate a first difference signal. Two cascaded integrators (second-order integrators 101) are used to perform second-order integration on the first difference signal. The first difference signal is first integrated by the first-stage integrator in the second-order integrator 101, and the output result is then fed into the second-stage integrator in the second-order integrator 101 for secondary integration. Finally, the integrated signal is output by the final integrator (second stage). The first quantizer 102 is connected to the output of the final integrator (second-order integrator 101) and has a built-in reference level. When the clock signal is triggered, the first quantizer 102 compares the output of the final integrator (second-order integrator 101) with the reference level. If the output result is greater than the reference level, the first quantizer 102 outputs a high level 1; if it is less than or equal to the reference level, it outputs a low level 0, thereby generating the first bit stream X(k). The first DAC feedback unit 103 is used to convert the digital signal (0 or 1) output by the first quantizer 102 into a corresponding first feedback analog signal. For example, a high level 1 is converted into +Vref (positive reference voltage, such as +280mV), and a low level 0 is converted into -Vref (negative reference voltage, such as -280mV), and this first feedback analog signal is sent back to the first differential input unit to form a closed-loop feedback with the input signal x(t).

[0028] This structure achieves noise shaping through second-order integration, increasing the power spectral density of the quantization noise to (f / fs)⁴, while simultaneously dispersing the noise and significantly reducing the noise density in the low-frequency band, meeting the requirements of high-precision current sampling. The closed-loop structure of the first modulation circuit 1 ensures that the output first bit stream X(k) can accurately represent the information of the input analog signal x(t), providing a data basis for subsequent delay compensation by the microcontroller.

[0029] Further, please see Figure 2 The second modulation circuit 2 includes: an analog differentiating unit; a second differential input unit for receiving the differential difference signal dx(t) and a second feedback analog signal and outputting a second difference signal; two cascaded integrators (second-order integrators 201) for performing second-order integration on the second difference signal; a second quantizer 202 connected to the output of the final integrator (second-order integrator 201) for comparing the output of the final integrator (second-order integrator 201) with a reference level; and a second DAC feedback unit 203 for converting the output of the second quantizer 202 into a second analog feedback signal and feeding it back to the second differential input unit, forming a second closed-loop modulation structure. The output of the second modulation circuit 2 is the second bitstream dX(k) output by the second quantizer 202.

[0030] Specifically, the analog differentiating unit receives the analog signal x(t) to be sampled and performs differentiating processing on it through a differentiating circuit. The second differential input unit is used to input the differential difference signal dx(t) and the second feedback analog signal output by the second DAC feedback unit 203, performing differential operation on the two signals to generate a second difference signal, i.e., the difference between dx(t) and the second feedback analog signal, which serves as the input for subsequent integration processing. Two cascaded integrators (second-order integrators 201) are used to perform second-order integration processing on the second difference signal. The first-stage integrator in the second-order integrator 201 first accumulates and integrates the second difference signal, and the output result is then fed into the second-stage integrator in the second-order integrator 201 for a second integration. Finally, the integrated signal is output by the final stage integrator (second stage). The second quantizer 202 is connected to the output of the final stage integrator (second-order integrator 201) and has a built-in reference level. When the clock signal is triggered, the second quantizer 202 compares the output result of the final stage integrator with the reference level. If the output result is greater than the reference level, the second quantizer 202 outputs a high level 1; if it is less than or equal to the reference level, it outputs a low level 0, thereby generating the second bit stream dX(k). The second DAC feedback unit 203 is used to convert the digital signal (0 or 1) output by the second quantizer into a corresponding second feedback analog signal. For example, a high level 1 is converted to +Vref (positive reference voltage, such as +280mV), and a low level 0 is converted to -Vref (negative reference voltage, such as -280mV), and this second feedback analog signal is sent back to the second differential input unit to form a closed-loop feedback with the input signal dx(t).

[0031] The second modulation circuit 2 operates in parallel with the first modulation circuit 1. Both circuits employ a second-order modulation structure and utilize an integrator to achieve noise shaping, thereby increasing the quantization noise power spectral density to (f / fs). 4 Simultaneously, it disperses noise, significantly reducing noise density in the low-frequency band to meet the requirements of high-precision current sampling. Furthermore, this structure enables the microcontroller to simultaneously acquire the first bit stream X(k) and the second bit stream dX(k), providing data support for linear delay compensation and solving the delay problem of traditional Sigma-Delta modulation sampling.

[0032] Furthermore, the process for comparing the output of the final stage integrator (second-order integrator 101 and / or second-order integrator 201) with the reference level is as follows: the output is compared with the reference level, and the comparison operation is triggered by the rising or falling edge of the clock of the dual-channel modulation module. Specifically, when the output is greater than the reference level, the quantizer outputs a high-level signal; specifically, the first quantizer 102 and / or the second quantizer 202 outputs a high-level signal. When the integration result is less than or equal to the reference level, the quantizer outputs a low-level signal; specifically, the first quantizer 102 and / or the second quantizer 202 outputs a low-level signal.

[0033] Specifically, in the dual-channel modulator module, the comparison operation of the first quantizer 102 and the second quantizer 202 is triggered by the edge of the module clock. The clock signal of the dual-channel modulation module is simultaneously connected to the trigger terminals of the first quantizer 102 and the second quantizer 202. When the rising edge or falling edge of the clock signal arrives, the quantizer immediately performs the comparison operation. The trigger edge can be configured to be rising edge or falling edge triggered according to the system design requirements to ensure that the two quantizers work synchronously. For example, if rising edge triggering is selected, at the rising edge of each clock cycle, the first quantizer 102 compares the output of its final stage integrator (second-order integrator 101) with the reference level, while the second quantizer 202 performs the same operation on the output of its final stage integrator (second-order integrator 201). Specifically, the comparison process of the first quantizer 102 is as follows: when the output of the final stage integrator of the first modulation circuit 1 is greater than the reference level, the first quantizer 102 outputs a high-level signal (logic 1). Conversely, if the output is less than or equal to the reference level, it outputs a low-level signal (logic 0). The output signal is converted into an analog quantity (e.g., +280mV or -280mV) by the first DAC feedback unit 103 and participates in closed-loop feedback. The comparison process of the second quantizer 202 involves comparing the output of the final integrator of the second modulation circuit 2 with the reference level. When the result is greater than the reference level, the second quantizer 202 outputs a high level (logic 1). Conversely, it outputs a low level (logic 0). This output signal is converted into an analog quantity by the second DAC feedback unit 203, forming closed-loop feedback.

[0034] This comparison mechanism and clock edge triggering operation enable the system to sample the input signal at high speed, further disperse noise power, and meet the requirements of high-precision current sampling.

[0035] Further, please see Figure 1 The minimum time difference Δt of the system sampling delay satisfies: Δt=OSR×(T_SYSCLK / T_SDCLK). Where OSR is the oversampling rate, T_SYSCLK is the system clock period, and T_SDCLK ​​is the operating clock period of the Sigma-Delta modulation module.

[0036] Specifically, in the Sigma-Delta modulation system of this invention, the minimum time difference Δt of the system sampling delay is jointly determined by the oversampling rate OSR, the system clock cycle T_SYSCLK, and the modulation module's operating clock cycle T_SDCLK. The oversampling rate represents the number of bits required for a complete sample; for example, OSR = 250 means that 250 clock cycles are needed to complete one sample. If the system clock frequency is 100MHz, T_SYSCLK = 10ns, T_SDCLK ​​= 50ns, and OSR = 250, then: Δt = 250 × (10ns / 50ns) = 50 system clock cycles = 500ns. This time difference represents the minimum delay from signal input to usable sampled data, i.e., the currently acquired data actually corresponds to the signal value 500ns ago. This formula reveals the influence of system parameters on the sampling delay; reducing the oversampling rate OSR or increasing the frequency of the modulation module's operating clock cycle T_SDCLK ​​can reduce Δt, thereby shortening the delay. In practical design, both accuracy and speed need to be considered. For example, although increasing the oversampling rate (OSR) will prolong the sampling time, it can improve the resolution.

[0037] Furthermore, the oversampling rate of the Sigma-Delta modulation module can be dynamically configured.

[0038] Specifically, the oversampling rate (OSR) of the Sigma-Delta modulation module supports dynamic configuration to adapt to the needs of different application scenarios. Users can write the corresponding OSR value to the configuration register according to the trade-off between sampling accuracy and response speed. For example, in motor control scenarios, if fast response is required but accuracy is low, the OSR can be dynamically set to 128. If high-precision sampling is required, such as current monitoring in a battery management system, the OSR can be increased to 512. When the OSR changes, the system automatically adjusts the minimum delay time difference.

[0039] By dynamically configuring the oversampling rate, the stability of the sampling timing is ensured, enabling flexible switching between high precision and real-time performance.

[0040] Further, please see Figure 2 The analog differential unit 204 includes two paths: one path directly transmits the analog signal x(t) to obtain the current value, and the other path delays the analog signal x(t) by one period through the delay unit to obtain the value of the previous moment. The signals output from the two paths are subjected to a difference operation to output the difference signal, thereby completing the difference operation on the analog signal x(t) and realizing the differential function.

[0041] Specifically, in the second modulation circuit 2, when the analog differentiating unit 204 processes the input analog signal x(t), it simultaneously sends the signal to two paths: one path directly transmits the signal to obtain the value at the current moment, and the other path delays the signal by one system clock cycle through the delay unit to obtain the value at the previous moment. Subsequently, the two signals enter the difference operation unit for subtraction to obtain the difference signal. After amplification, this difference signal can be approximately represented as the differential signal of the input analog signal x(t), which then enters the differential input unit of the second modulation circuit 2.

[0042] The analog differential unit combined with Sigma-Delta modulation shapes noise, and the differential structure synchronous clock ensures timing alignment, solving the delay problem without additional circuitry and improving system response.

[0043] Furthermore, in another embodiment, the present invention also provides a control method for a Sigma-Delta modulator, utilizing any of the aforementioned Sigma-Delta modulation systems. The method includes: predicting the signal value at the next sampling time using the formula X(t'+1)=X(t')+dX(t')·Δt based on the properties of calculus and the slope compensation principle.

[0044] Specifically, in the Sigma-Delta modulation system of this invention, when the Sigma-Delta modulation module acquires the current data at time t, due to the inherent characteristics of the Sigma-Delta sampling mechanism, this data actually corresponds to the current value at time t-1. Time t' is the true time node after compensation by this invention, at which point the current data X(t') has been corrected for delay through the compensation mechanism. Specifically, based on the properties of calculus and the slope compensation principle, the system uses the formula X(t'+1)=X(t')+dX(t')·Δt for prediction. Here, time t refers to the nominal time node at which the Sigma-Delta modulation module acquires the current data, but due to the inherent delay of Sigma-Delta sampling, this data actually corresponds to the physical signal x(t-1) at time t-1 (i.e., the sampled data lags behind the actual signal). Time t' refers to the true time node after correction through the differential compensation mechanism of this invention, at which point the signal value X(t') is the compensation result for the delayed data at time t, aligning it with the actual signal in time.

[0045] Specifically, two scenarios are illustrated: In the Sigma-Delta modulation system of this invention, a differential compensation mechanism is used to achieve accurate correction and prediction of the sampled signal. When the Sigma-Delta modulation module acquires lagging data x(t-1) at nominal time t, the system uses the formula X(t') = X(t'-1) + dX(t'-1)·Δt to correct the data to a signal value at the real time t' = t-Δt. This process solves the problem of time misalignment of historical data, synchronizing the sampled value with the actual signal. Based on this, using the compensated signal value X(t') and its differential signal dX(t') at the current time t', the signal value at the future time t'+1 is predicted using the formula X(t'+1) = X(t') + dX(t')·Δt.

[0046] The above calculations can be directly used for closed-loop control decisions, thereby effectively solving the inherent delay problem of traditional sampling systems while maintaining high-precision sampling, and improving the response speed and real-time performance of the control system.

[0047] Furthermore, in another embodiment, the present invention also provides an integrated Sigma-Delta modulator chip, comprising a dual-channel modulator structure in any of the above-described Sigma-Delta modulation systems, wherein the first modulation circuit 1 and the second modulation circuit 2 share a clock source.

[0048] Specifically, the integrated Sigma-Delta modulator chip incorporates a dual-channel modulator module to achieve parallel processing of analog signals. In the chip architecture, the first modulation circuit 1 and the second modulation circuit 2 share the same clock source, ensuring strict synchronization of sampling and quantization operations between the two circuits. The dual-channel modulator design allows the chip to simultaneously output both the original signal bitstream and the differentiated signal bitstream, providing a precise data foundation for subsequent delay compensation algorithms.

[0049] The integrated Sigma-Delta modulator chip adopts a highly integrated design, integrating the dual-channel modulator module and clock management unit on a single silicon chip. This effectively reduces the impact of external clock jitter on sampling accuracy and has advantages such as small size, strong anti-interference ability, and high signal processing efficiency. It is suitable for industrial control, precision measurement and other scenarios with stringent requirements for timing consistency and data accuracy.

[0050] Furthermore, in another embodiment, the present invention also provides a motor control system including a Sigma-Delta modulation system utilizing any of the above-described methods.

[0051] The motor control system employs the aforementioned Sigma-Delta modulation system to achieve high-precision current sampling and real-time control. In the system, the Sigma-Delta modulation system serves as the front-end module, acquiring the raw and differential signals of the motor current in parallel through dual modulators, and correcting the sampling delay in real time based on a differential compensation algorithm. This system works collaboratively with the motor drive unit, microcontroller, and control algorithm module to form a closed-loop control architecture.

[0052] The overall design of the motor control system deeply integrates signal acquisition, processing and control functions, which improves the dynamic performance and stability of the motor control system and is suitable for applications with high real-time requirements such as servo control and frequency conversion speed regulation.

[0053] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A Sigma-Delta modulation system, characterized in that, include: A dual-channel modulator module, configured to process the analog signal to be sampled. Wherein: the first modulation circuit processes the analog signal x(t) and outputs a first bit stream X(k); the second modulation circuit includes an analog differentiation unit that performs analog differentiation processing on the analog signal x(t) to obtain a differential difference signal dx(t), and processes the differential difference signal dx(t) to output a second bit stream dX(k). A microcontroller is used to receive the first bit stream X(k) and the second bit stream dX(k) output by the dual-channel modulator, and to process the first bit stream X(k) and the second bit stream dX(k) through the Sigma-Delta modulation module in the microcontroller to obtain the original signal X(t') and the original differential signal dX(t'); based on the linear combination of the original signal X(t') and the original differential signal dX(t'), the signal value at the next sampling time is predicted to compensate for the system sampling delay.

2. The Sigma-Delta modulation system according to claim 1, characterized in that, The first modulation circuit includes: The first differential input unit is used to receive the analog signal to be sampled x(t) and the first feedback analog signal and output the first difference signal; Two integrators connected in series are used to perform second-order integration on the first difference signal; The first quantizer is connected to the output of the final stage integrator and is used to compare the output of the final stage integrator with a reference level. The first DAC feedback unit converts the output of the first quantizer into a first feedback analog signal and feeds it back to the first differential input unit to form a first closed-loop modulation structure. The output of the first modulation circuit is the first bit stream X(k) output by the first quantizer.

3. The Sigma-Delta modulation system according to claim 1, characterized in that, The second modulation circuit includes: Simulated differential unit; The second differential input unit is used to receive the differential difference signal dx(t) and the second feedback analog signal and output the second difference signal; Two integrators connected in series are used to perform second-order integration on the second difference signal; The second quantizer is connected to the output of the final stage integrator and is used to compare the output of the final stage integrator with a reference level. The second DAC feedback unit converts the output of the second quantizer into a second analog feedback signal and feeds it back to the second differential input unit to form a second closed-loop modulation structure. The output of the second modulation circuit is the second bit stream dX(k) output by the second quantizer.

4. The Sigma-Delta modulation system according to claim 2 or 3, characterized in that, The process of comparing the output of the final integrator with the reference level is as follows: The output result is compared with a reference level, and the comparison operation is triggered by the rising or falling edge of the clock of the dual-channel modulation module. Specifically, when the output result is greater than the reference level, the quantizer outputs a high-level signal; when the integration result is less than or equal to the reference level, the quantizer outputs a low-level signal.

5. The Sigma-Delta modulation system according to claim 4, characterized in that, The minimum time difference Δt of the system sampling delay satisfies: Δt=OSR×(T_SYSCLK / T_SDCLK); Wherein, OSR is the oversampling rate, T_SYSCLK is the system clock cycle, and T_SDCLK ​​is the operating clock cycle of the Sigma-Delta modulation module.

6. The Sigma-Delta modulation system according to claim 5, characterized in that, The oversampling rate of the Sigma-Delta modulation module can be dynamically configured.

7. The Sigma-Delta modulation system according to claim 3, characterized in that, The analog differentiation unit includes two paths: one path directly transmits the analog signal x(t) to obtain the current value, and the other path delays the analog signal x(t) by one period through a delay unit to obtain the value of the previous moment. The signals output from the two paths are subjected to a difference operation to output a difference signal, thereby completing the difference operation on the analog signal x(t) and realizing the differentiation function.

8. The control method based on the Sigma-Delta modulation system according to claim 6, characterized in that, include: By utilizing the properties of calculus and the principle of slope compensation, the signal value at the next sampling time is predicted using the formula X(t'+1)=X(t')+dX(t')·Δt.

9. An integrated Sigma-Delta modulator chip, characterized in that, It includes a dual-channel modulator module as described in any one of claims 1-6, wherein the first modulation circuit and the second modulation circuit share a clock source.

10. A motor control system comprising the Sigma-Delta modulation system as described in any one of claims 1-6.

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