Semiconductor structure and forming method thereof

Abstract

The invention provides a method for forming a semiconductor structure, which comprises the following steps of: providing a semiconductor substrate which comprises a first dielectric layer and a metal plug positioned in the first dielectric layer; sequentially forming a first isolation layer, a second dielectric layer, a second isolation layer and a hard mask layer on the top surface of the first dielectric layer; etching and removing the hard mask layer, the second isolation layer and a part of the second dielectric layer in a region corresponding to the metal plug to form an opening; the hard mask layer is removed; and etching is continued along the opening so as to expose the metal plug. The invention also provides a semiconductor structure. According to the semiconductor structure and the forming method provided by the invention, hole defects can be prevented from being formed in the metal layer when the opening is filled with the metal layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the back-end of line (BEOL) process of chip manufacturing, several layers of conductive metal lines need to be built. The first layer of metal wires is connected to the metal plug in the dielectric layer through an interconnect structure. When depositing metal into the connection hole between the first layer of metal wires and the metal plug to form the interconnect structure, the depth-to-width ratio of the connection hole is high, usually greater than 5.5, which causes hole defects to appear in the interconnect structure during the deposition process, affecting the performance of the interconnect structure. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure and its formation method, which reduces the aspect ratio of interconnect holes and avoids the formation of hole defects in the interconnect structure during the deposition process.

[0004] In a first aspect, a method for forming a semiconductor structure includes: providing a semiconductor substrate, the semiconductor substrate including a first dielectric layer and a metal plug located in the first dielectric layer; sequentially forming a first isolation layer, a second dielectric layer, a second isolation layer and a hard mask layer on the surface of the first dielectric layer; etching away the hard mask layer, the second isolation layer and a portion of the second dielectric layer in a region corresponding to the metal plug to form an opening; removing the hard mask layer; and continuing etching along the opening to expose the metal plug.

[0005] In some embodiments, in the etching process of removing the hard mask layer, the second isolation layer, and a portion of the second dielectric layer corresponding to the metal plug, the ratio of the thickness of the second dielectric layer removed to the original thickness of the second dielectric layer is 1:(1.3 to 1.7).

[0006] In some embodiments, after etching away the hard mask layer, the second isolation layer, and a portion of the second dielectric layer in the region corresponding to the metal plug to form an opening, and before removing the hard mask layer, the method further includes: continuing etching along the opening to expose the first isolation layer.

[0007] In some embodiments, the first isolation layer includes a first sub-isolation layer and a second sub-isolation layer stacked sequentially on the surface of the first dielectric layer. After etching away the hard mask layer, the second isolation layer and a portion of the second dielectric layer corresponding to the metal plug to form an opening, and before removing the hard mask layer, the method further includes: continuing to etch along the opening to expose the first sub-isolation layer.

[0008] In some embodiments, the material of the first sub-isolation layer includes nitrogen-doped silicon carbide.

[0009] In some embodiments, the material of the second sub-isolation layer includes TEOS.

[0010] In some embodiments, the material of the hard mask layer includes TiN.

[0011] In some embodiments, the second isolation layer includes a third sub-isolation layer and a fourth sub-isolation layer stacked sequentially.

[0012] In some embodiments, the method of forming the semiconductor structure further includes: forming a metal layer such that the metal layer completely fills the opening and covers a second isolation layer.

[0013] The beneficial effects of the semiconductor structure formation method provided in this application include, but are not limited to, the following:

[0014] This application provides a method for forming a semiconductor structure. When etching the connection hole between the metal layer and the metal plug, a step-by-step etching method is adopted. Before completing the etching of the connection hole, the hard mask layer is removed by etching. Due to the protection of the dielectric layer and / or the isolation layer, the metal plug will not be etched and damaged by the etchant when the hard mask layer is removed. Since the hard mask layer is removed, the aspect ratio of the final connection hole is reduced, avoiding the formation of voids inside the connection structure during the deposition of the connection structure.

[0015] In a second aspect, this application also provides a semiconductor structure prepared by the semiconductor structure formation method provided in the first aspect of this application, comprising: a semiconductor substrate, the semiconductor substrate including a first dielectric layer and a metal plug located in the first dielectric layer; a first isolation layer, a second dielectric layer and a second isolation layer sequentially stacked on the top surface of the first dielectric layer; and an opening penetrating the first isolation layer, the second dielectric layer and the second isolation layer and exposing the metal plug.

[0016] The semiconductor structure provided in this application has no hard mask layer on top. The aspect ratio of the opening used to expose the metal plug and fill the metal layer is smaller than that of the opening of the same structure that retains a hard mask layer on top. The aspect ratio of the opening satisfies the requirement of uniform filling of the metal layer when filling the opening with the metal layer, thus avoiding the formation of void defects inside the metal layer. Attached Figure Description

[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1-8 This is a schematic diagram of the steps of a method for forming a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0021] Typically, in the interconnect process of subsequent steps, the hard mask layer is removed by etching with H2O2 after the interconnect hole is formed. However, for the interconnect hole between the first layer of metal conductors and the metal plug, if the hard mask layer is removed by etching with H2O2 after the interconnect hole etching is completed, the exposed metal plug of the interconnect hole will be etched and damaged. Therefore, for the interconnect hole between the first layer of metal conductors and the metal plug, the hard mask layer from when the interconnect hole was etched will still be retained after the interconnect hole is etched. This increases the aspect ratio of the interconnect hole, which makes it easy to form void defects inside the interconnect structure during subsequent deposition of the interconnect structure.

[0022] The method for forming a semiconductor structure according to this application specifically includes: providing a semiconductor substrate, the semiconductor substrate including a first dielectric layer and a metal plug located in the first dielectric layer; sequentially forming a first isolation layer, a second isolation layer, a second dielectric layer, a second isolation layer and a hard mask layer on the top surface of the first dielectric layer; etching away the hard mask layer, the second isolation layer and a portion of the second dielectric layer in the region corresponding to the metal plug to form an opening; removing the hard mask layer; and continuing to etch along the opening to expose the metal plug.

[0023] This application provides a method for forming a semiconductor structure. When etching the connection hole between the first layer of metal wire and the metal plug, step-by-step etching is adopted. Before completing the etching of the connection hole, the hard mask layer is removed by etching, thereby reducing the aspect ratio of the final connection hole and avoiding the formation of voids inside the connection structure during the deposition of the connection structure.

[0024] The method for forming the semiconductor structure provided in this application will be described in detail below with reference to the embodiments and accompanying drawings.

[0025] The various operations are described sequentially as multiple discrete operations in a manner most conducive to understanding this application; however, the order of description should not be interpreted as implying that these operations must depend on the order. More specifically, these operations need not be performed in the order presented.

[0026] refer to Figure 1 A semiconductor substrate is provided, the semiconductor substrate including a first dielectric layer 100 and a metal plug 101 located in the first dielectric layer 100.

[0027] In some embodiments, the material of the first dielectric layer 100 includes silicon oxide, silicon dioxide, etc. Methods for forming the first dielectric layer 100 include, but are not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering processes.

[0028] In some embodiments, the metal plug 101 is disposed through the first dielectric layer 100 to serve as a conductive structure for electrically connecting corresponding structures located on the bottom and top surfaces of the first dielectric layer 100. The methods for forming the metal plug 101 include, but are not limited to, photolithography, chemical vapor deposition, atomic layer deposition, and physical vapor deposition.

[0029] In some embodiments, the metal plug 101 is made of tungsten.

[0030] In some embodiments, the semiconductor substrate may further include a silicon substrate or other substrate located on the bottom surface of the first dielectric layer 100. The method for forming the semiconductor structure provided in this application does not limit the structure of the bottom surface of the first dielectric layer 100, so it will not be described in detail here.

[0031] refer to Figure 2 A first isolation layer 200, a second dielectric layer 300, a second isolation layer 400, and a hard mask layer 500 are sequentially formed on the top surface of the first dielectric layer 100.

[0032] In some embodiments, the first isolation layer 200 includes a first sub-isolation layer 201 and a second sub-isolation layer 202 sequentially stacked on the surface of the first dielectric layer 100.

[0033] In some embodiments, the material of the first sub-isolation layer 201 includes nitrogen-doped silicon carbide (NDC). Methods for forming the first sub-isolation layer 201 include, but are not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering processes.

[0034] In some embodiments, the material of the second sub-isolation layer 202 includes TEOS. The methods for forming the second sub-isolation layer 202 include, but are not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering processes. The second sub-isolation layer 202 can reduce the interface resistance between the first sub-isolation layer 201 and the second dielectric layer 300. Since either the first sub-isolation layer 201 or the second sub-isolation layer 202 alone cannot achieve the desired effect in reducing the interface resistance between the first dielectric layer 100 and the second dielectric layer 300, a material with low interface resistance to the first dielectric layer is selected as the first sub-isolation layer 201, and a material with low interface resistance to the second dielectric layer 300 is selected as the second sub-isolation layer 202. Furthermore, the interface resistance between the first sub-isolation layer 201 and the second sub-isolation layer 202 is within an ideal range, thereby reducing the total interface resistance between the first dielectric layer 100 and the second dielectric layer 300.

[0035] In some embodiments, the dielectric constant of the material of the second dielectric layer 300 is less than or equal to 2.65, which is an ultra-low k dielectric material, in order to reduce interlayer parasitic capacitance, thereby reducing the resistive capacitance delay, crosstalk noise and power consumption of the semiconductor device.

[0036] In some embodiments, the material of the second dielectric layer 300 includes a Si-OC complex.

[0037] The second isolation layer 400 can prevent the metal in the subsequently deposited metal layer from diffusing into the second dielectric layer 300, and can also replace the hard mask layer 500 to continue etching the opening after the hard mask layer 500 is etched.

[0038] In some embodiments, the thickness ratio of the second isolation layer 400 to the first isolation layer 200 is 1:(0.9 to 1.1), for example 1:0.9, 1:1 or 1:1.1.

[0039] In some embodiments, the second isolation layer 400 includes a third sub-isolation layer 401 and a fourth sub-isolation layer 402 stacked sequentially.

[0040] In some embodiments, the material of the third sub-isolation layer 401 includes OMCTS; and the material of the fourth sub-isolation layer 402 includes SiOC. The methods for forming the third sub-isolation layer 401 and the fourth sub-isolation layer 402 include, but are not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering processes.

[0041] In some embodiments, the material of the hard mask layer 500 includes TiN. The methods for forming the hard mask layer 500 include, but are not limited to, processes such as chemical vapor deposition.

[0042] In some embodiments, the opening 600 is formed in steps using method one, as shown in the reference. Figure 3 The hard mask layer 500, the second isolation layer 400, and a portion of the second dielectric layer 300 in the corresponding area of ​​the metal plug 101 are etched away to form an opening 600. The etching process is a dry etching process. The shape of the opening 600 can be a straight hole or a stepped hole. A straight hole refers to an opening 600 whose cross-sectional area remains consistent from the top to the bottom. A stepped hole refers to an opening 600 comprising a wide section near the top and a narrow section near the bottom, where the cross-sectional area of ​​the wide section is larger than that of the narrow section. To simplify the description of the technical solution of this application, the following will use a straight hole as an example to illustrate the method for forming the semiconductor structure.

[0043] In some embodiments, the thickness ratio of the second dielectric layer 300 to the thickness of the second insulating layer 400 is 1:(0.08 to 0.12), for example, 1:0.08, 1:0.1, or 1:1.12. The etching removal of the thickness of the second dielectric layer 300 to the original thickness of the second dielectric layer 300 is in the ratio of 1:(1.3 to 1.7), for example, 1:1.3, 1:1.4, 1:1.5, 1:1.6, or 1:1.7.

[0044] refer to Figure 4 The hard mask layer 500 is removed. In some embodiments, the method for removing the hard mask layer 500 includes wet etching, wherein the wet etching agent includes at least one selected from H2O2, HF, and H2SO4.

[0045] In the wet etching process to remove the hard mask layer 500, even if the etchant flows into the opening 600, the top surface of the metal plug 101 will not be etched by the etchant because of the presence of the first isolation layer 200 and part of the second dielectric layer 300.

[0046] refer to Figure 5 The etching continues along the opening 600 to expose the metal plug 101.

[0047] Since the hard mask layer 500 is removed, the second isolation layer 400 acts as a hard mask in the step of continuing to etch along the opening 600 to expose the metal plug 101.

[0048] In some embodiments, during the process of continuing etching along the opening 600 to expose the metal plug 101, the etching selectivity ratio of the etchant to the second isolation layer 400 and the second dielectric layer 300 is 1:(3.8-4.2). Optionally, the etching selectivity ratio of the etchant to the second isolation layer 400 and the second dielectric layer 300 is 1:3.8, 1:4, or 1:4.2. The etching selectivity ratio of the etchant to the second isolation layer 400 and the first isolation layer 200 is 1:(2.8-3.2). Optionally, the etching selectivity ratio of the etchant to the second isolation layer 400 and the first isolation layer 200 is 1:2.8, 1:3, or 1:3.2.

[0049] In some embodiments, after completing the step of continuing etching along the opening 600 to expose the metal plug 101, the aspect ratio of the opening 600 is generally less than 4.1, such as 4.1, 4.0, or 3.9. Assuming that the hard mask layer 500 is not removed, the aspect ratio of the opening 600 is generally greater than 5.0. By removing the hard mask layer 500 before exposing the metal plug 101, the aspect ratio of the opening 600 is reduced, avoiding void defects when depositing a metal layer into the opening 600 subsequently.

[0050] In some embodiments, after completing the step of continuing etching along the opening 600 to expose the metal plug 101, the thickness of the remaining second isolation layer 400 is in the ratio of 1:(4.8 to 5.2) to the thickness of the second isolation layer 400 before etching, for example, 1:4.8, 1:5.0 or 1:5.2.

[0051] Since the second isolation layer 400 still needs to maintain a certain thickness to function as an isolation layer in subsequent processes, the opening 600 can be further etched before the hard mask layer 500 is removed, so as to reduce the etching of the second isolation layer 400 when the opening 600 is etched after the hard mask layer 500 is removed.

[0052] In other embodiments, reference is made to... Figure 6Method 2 involves step-by-step etching of the opening 600. After etching away the hard mask layer 500, the second isolation layer 400, and part of the second dielectric layer 300 in the area corresponding to the metal plug 101 to form the opening 600, and before removing the hard mask layer 500, etching continues along the opening 600 to expose the first isolation layer 200.

[0053] Because of the protection of the first isolation layer 200, the metal plug 101 can still avoid being etched and damaged by the etchant during the subsequent etching process to remove the hard mask layer 500.

[0054] The subsequent processes for removing the hard mask layer 500 and continuing to etch the opening 600 to expose the metal plug 101 are the same as or similar to those used in Method 1, and will not be described in detail here.

[0055] In some embodiments, after the etching process to expose the metal plug 101 is completed, the aspect ratio of the opening 600 is greater than 4.1 and less than or equal to 4.6, such as 4.2, 4.34, 4.57 or 4.6; the thickness ratio of the remaining second isolation layer 400 to the thickness of the second isolation layer 400 before etching is 1:(5.0 to 5.5), such as 1:5.0, 1:5.1, 1:5.2, 1:5.3 or 1:5.5.

[0056] Although the aspect ratio of the final opening 600 obtained by method two is greater than that obtained by method one, compared to the etching method that does not remove the hard mask layer 500, the aspect ratio of the opening 600 obtained by method two can still avoid void defects when depositing metal layers into the opening 600 subsequently. Furthermore, the thickness of the second isolation layer 400 obtained by method two is greater than that obtained by method one, preventing the second isolation layer 400 from failing to function as an isolation layer in subsequent processes due to excessive thickness loss.

[0057] It should also be noted that in Method 1, since the etching stop point before the hard mask layer 500 is located inside the second dielectric layer 300, it is difficult to ensure that the height of the bottom of the opening 600 is consistent before etching the hard mask layer 500, which is detrimental to the consistency of the etching depth of the bottom area when the opening 600 is continued to be etched. In contrast to Method 1, in Method 2, the etching stop point before etching the hard mask layer 500 is located in the first isolation layer 200. The materials of the first isolation layer 200 and the second dielectric layer 300 have a large physical and chemical difference. Therefore, by controlling the etching selectivity ratio, it can be ensured that the second dielectric layer 300 inside the opening 600 is completely removed and the first isolation layer 200 is completely retained before etching the hard mask layer 500, so that the height of the bottom of the opening 600 is consistent, which is beneficial to the consistency of the etching depth of the bottom area when the opening 600 is continued to be etched.

[0058] In other embodiments, reference is made to... Figure 7 The opening 600 is etched in three steps. After the hard mask layer 500, the second isolation layer 400 and part of the second dielectric layer 300 in the corresponding area of ​​the metal plug 101 are etched to form the opening 600, and before the hard mask layer 500 is removed, the etching continues along the opening 600 to expose the first sub-isolation layer 201.

[0059] Because of the protection of the first sub-isolation layer 201, the metal plug 101 can still avoid being etched and damaged by the etchant during the subsequent etching process to remove the hard mask layer 500.

[0060] The subsequent processes for removing the hard mask layer 500 and continuing to etch the opening 600 to expose the metal plug 101 are the same as or similar to those used in Method 1, and will not be described in detail here.

[0061] In some embodiments, after the etching process to expose the metal plug 101 is completed, the aspect ratio of the opening 600 is greater than 4.6 and less than or equal to 4.7, for example, 4.6, 4.64, 4.65, 4.67 or 4.7; the thickness ratio of the remaining second isolation layer 400 to the thickness of the second isolation layer 400 before etching is 1:(5.3 to 5.6), for example, 1:5.3, 1:5.5 or 1:5.6, etc.

[0062] In method three, the aspect ratio of the final opening 600 is greater than that obtained in methods one and two. However, compared to etching without removing the hard mask layer 500, the aspect ratio of the opening 600 obtained in method two can still prevent void defects when depositing a metal layer into the opening 600. Furthermore, the thickness of the second isolation layer 400 obtained in method two is greater than that obtained in methods one and two, preventing the second isolation layer 400 from failing to function as an isolation layer in subsequent processes due to excessive thickness loss. The etching position of the opening 600 before removing the hard mask layer 500 can be selected according to actual needs.

[0063] The etching methods for the opening 600 include, but are not limited to, sputtering and ion beam milling, plasma etching, high-pressure plasma etching, high-density plasma etching, reactive ion etching, and other etching processes.

[0064] refer to Figure 8 A metal layer 700 is formed, which completely fills the opening 600 and covers the second isolation layer 400.

[0065] The metal layer 700 is used to form a conductive interconnect structure. In some embodiments, the material of the metal layer 700 includes copper. Methods for forming the metal layer 700 include, but are not limited to, processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering.

[0066] The beneficial effects of the semiconductor structure formation method provided in this application include, but are not limited to, the following:

[0067] This application provides a method for forming a semiconductor structure. When etching the connection hole between the metal layer and the metal plug, a step-by-step etching method is adopted. Before completing the etching of the connection hole, the hard mask layer is removed by etching. Due to the protection of the dielectric layer and / or the isolation layer, the metal plug will not be etched and damaged by the etchant when the hard mask layer is removed. Since the hard mask layer is removed, the aspect ratio of the final connection hole is reduced, avoiding the formation of voids inside the connection structure during the deposition of the connection structure.

[0068] refer to Figure 5 This application also provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate including a first dielectric layer 100 and a metal plug 101 located in the first dielectric layer 100; a first isolation layer 200, a second dielectric layer 300 and a second isolation layer 400 sequentially stacked on the top surface of the first dielectric layer 100; and an opening 600 penetrating the first isolation layer 200, the second dielectric layer and the second isolation layer 400 and exposing the metal plug 101.

[0069] In some embodiments, the first isolation layer 200 includes a first sub-isolation layer 201 and a second sub-isolation layer 202 sequentially stacked on the surface of the first dielectric layer 100.

[0070] In some embodiments, the second isolation layer 400 includes a third sub-isolation layer 401 and a fourth sub-isolation layer 402 stacked sequentially.

[0071] It should be noted that, Figure 5 In the semiconductor structure shown, and Figures 1-8 The semiconductor structure shown is formed using methods that share some conventional structures. Therefore, for the sake of brevity, some repetitive conventional structures will not be described again here.

[0072] The beneficial effects of the semiconductor structure provided in this application embodiment include, but are not limited to, the following:

[0073] The semiconductor structure provided in this application has no hard mask layer on top. The aspect ratio of the opening used to expose the metal plug and fill the metal layer is smaller than that of the opening of the same structure that retains a hard mask layer on top. The aspect ratio of the opening satisfies the requirement of uniform filling of the metal layer when filling the opening with the metal layer, thus avoiding the formation of void defects inside the metal layer.

[0074] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects may be any one or a combination of the above, or any other possible beneficial effects.

[0075] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this specification. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this specification, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0076] It should be noted that, in the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a rotating connection or a sliding connection; a direct connection or an indirect connection through an intermediate medium; or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application in light of the specific circumstances.

[0077] Furthermore, when the terms "first," "second," "third," etc., are used in this application specification to describe various features, these terms are only used to distinguish these features and should not be construed as indicating or implying the correlation or relative importance between features or implicitly indicating the number of features indicated.

[0078] In addition, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor to limit the scope of the exemplary embodiments.

[0079] Furthermore, this application uses specific terms to describe embodiments of this specification. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this application do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application can be appropriately combined.

[0080] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0081] Finally, it should be understood that the embodiments described in this application are merely illustrative of the principles of the embodiments of this application. Other modifications may also fall within the scope of this application. Therefore, alternative configurations of the embodiments of this application are considered as examples and not limitations, and are regarded as consistent with the teachings of this application. Accordingly, the embodiments of this application are not limited to the embodiments explicitly described and illustrated in this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first dielectric layer and a metal plug located in the first dielectric layer; A first isolation layer, a second dielectric layer, a second isolation layer, and a hard mask layer are sequentially formed on the surface of the first dielectric layer; Etching removes the hard mask layer, the second isolation layer, and a portion of the second dielectric layer in the area corresponding to the metal plug, forming an opening; Remove the hard mask layer; as well as Etching continues along the opening to expose the metal plug.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, In the etching process that removes the hard mask layer, the second isolation layer, and a portion of the second dielectric layer in the region corresponding to the metal plug, the ratio of the thickness of the second dielectric layer removed to the original thickness of the second dielectric layer is 1:(1.3~1.7).

3. The method for forming a semiconductor structure according to claim 1, characterized in that, After etching away the hard mask layer, the second isolation layer, and a portion of the second dielectric layer in the area corresponding to the metal plug to form an opening, and before removing the hard mask layer, the process further includes: Etching continues along the opening to expose the first isolation layer.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The first isolation layer includes a first sub-isolation layer and a second sub-isolation layer stacked sequentially on the surface of the first dielectric layer. After etching away the hard mask layer, the second isolation layer, and a portion of the second dielectric layer corresponding to the metal plug to form an opening, and before removing the hard mask layer, the layer further includes: Etching continues along the opening to expose the first sub-isolation layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The material of the first sub-isolation layer includes nitrogen-doped silicon carbide.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The material of the second sub-isolation layer includes TEOS.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The material of the hard mask layer includes TiN.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The second isolation layer includes a third sub-isolation layer and a fourth sub-isolation layer stacked sequentially.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: A metal layer is formed, which completely fills the opening and covers the second insulating layer.

10. A semiconductor structure prepared by the method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising a first dielectric layer and a metal plug located in the first dielectric layer; A first insulating layer, a second dielectric layer, and a second insulating layer are sequentially stacked on the top surface of the first dielectric layer; and The opening penetrates the first isolation layer, the second dielectric layer, and the second isolation layer, exposing the metal plug.

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