Network system of long-distance Ethernet and related control method

Abstract

The invention discloses a network system of a long-distance Ethernet and a related control method. In a physical layer circuit (PHY) of a network module, an ultra-long line transmit-receive specification is designed. In a network system, when both network modules support the ultra-long line transmit-receive specification, the ultra-long line transmit-receive specification can be selectively used for data exchange after an auto-negotiation process. In this embodiment, a unique hardware architecture is designed in physical layer circuitry (PHY) of a network module. When the two network modules of the network system both comprise the unique hardware architecture, the ultra-long line transceiving specification can be selectively used for data exchange after the auto-negotiation process.

Description

Technical Field

[0001] This invention relates to a network system and related control methods, and more particularly to a network system and related control methods for a long-distance Ethernet network. Background Technology

[0002] Please refer to Figure 1A The diagram illustrates a network system of Ethernet. Network system 100 includes two network modules 110 and 120 and a transmission medium 130. Network modules 110 and 120 are connected to the transmission medium 130, and the two network modules 110 and 120 exchange data via the transmission medium 130.

[0003] Network module 110 includes at least a physical layer circuit (PHY) 112 and a medium access control circuit (MAC) 116. Data is transmitted between the PHY 112 and the MAC 116 via a media independent interface (MII) 114. Similarly, network module 120 includes at least a physical layer circuit (PHY) 122 and a MAC 126. Data is transmitted between the PHY 122 and the MAC 126 via a media independent interface (MII) 124. The MII can be a gigabit media independent interface (GMII) or a reduced media independent interface (RMII). The PHYs 112 and 122 can be gigabit physical layer circuits (GPHYs).

[0004] Furthermore, the transmission medium 130 is connected between the two physical layer circuits (PHYs) 112 and 122, and the transmission medium 130 can be a network cable. Of course, the network modules 110 and 120 also include a controller (not shown) to provide parameters to set the corresponding physical layer circuits (PHYs) 112 and 122 and media access control circuits (MACs) 116 and 126.

[0005] According to the IEEE 802.3 standard, when the length of the transmission medium 130 is less than or equal to 100 meters, the gigabit physical layer circuit (GPHY) supports data rates of 1000BASE-T, 100BASE-Tx X, and 10BASE-T / TE. Specifically, the data rate of 10BASE-T / TE is 10 Mbps, 100BASE-Tx X is 100 Mbps, and 1000BASE-T is 1000 Mbps (1 Gbps). For example, the transmission medium 130 is a network cable, which includes four pairs of twisted-pair cables.

[0006] Please refer to Figure 1B The diagram shown is a schematic of an existing physical layer circuit (PHY). This physical layer circuit (PHY) 200 can be used in... Figure 1A The two physical layer circuits (PHY) 112 and 122 are in the middle, and the physical layer circuit (PHY) 200 is a gigabit physical layer circuit (GPHY).

[0007] The physical layer circuit (PHY) 200 includes: analog front end (AFE) 210, physical medium attachment (PMA) 220, physical coding sublayer (PCS) 230, and media-independent interface (MII) 240.

[0008] Analog front-end circuitry (AFE) 210 is connected to a first end of transmission medium 130, while a second end of transmission medium 130 is connected to the physical layer circuitry (PHY) of another network module. Furthermore, media-independent interface (MII) 240 is connected to media access control circuitry (MAC).

[0009] The physical medium connection circuit (PMA) 220 includes: a receiver-side physical medium connection element (Rx PMA) 222 and a transmitter-side physical medium connection element (Tx PMA) 226.

[0010] Furthermore, the physical coding sublayer circuit (PCS) 230 includes: a 10M receiver-side physical coding sublayer element (10M RxPCS) 231, a 100M receiver-side physical coding sublayer element (100M Rx PCS) 232, a 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 233, a 10M transmitter-side physical coding sublayer element (10M Tx PCS) 239, a 100M transmitter-side physical coding sublayer element (100M Tx PCS) 238, and a 1000M transmitter-side physical coding sublayer element (100M Tx PCS) 239. Here, 10M, 100M, and 1000M represent different data transmission rates (Mbps).

[0011] When the physical layer circuit (PHY) 200 operates in 10BASE-T / TE specification, the receiver data path consists of the analog front-end circuit (AFE) 210, the 10M receiver-side physical coding sublayer element (10M Rx PCS) 231, and the media-independent interface (MII) 240. The transmitter data path consists of the media-independent interface (MII) 240, the 10M transmitter-side physical coding sublayer element (10MTx PCS) 239, and the analog front-end circuit (AFE) 210. Additionally, the receiver-side physical media connection element (Rx PMA) 222 and the transmitter-side physical media connection element (Tx PMA) 226 in the physical media connection circuit (PMA) 220 are inactivated. The 100M receiver-side physical coding sublayer element (100M Rx PCS) 232, the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 233, the 100M transmitter-side physical coding sublayer element (100M Tx PCS) 238, and the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 237 in the physical coding sublayer circuit (PCS) 230 did not operate.

[0012] Similarly, when the physical layer circuit (PHY) 200 operates in 100BASE-Tx X specification, the receiver data path consists of analog front-end circuit (AFE) 210, receiver-side physical medium connection element (Rx PMA) 222, 100M receiver-side physical coding sublayer element (100M Rx PCS) 232, and media-independent interface (MII) 240. The transmitter data path consists of media-independent interface (MII) 240, 100M transmitter-side physical coding sublayer element (100M Tx PCS) 238, and analog front-end circuit (AFE) 210.

[0013] When the physical layer circuit (PHY) 200 operates in 1000BASE-T specification, the receiver data path consists of analog front-end circuit (AFE) 210, receiver-side physical medium connection element (Rx PMA) 222, 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 233, and media-independent interface (MII) 240. The transmitter data path consists of media-independent interface (MII) 240, 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 237, transmitter-side physical medium connection element (TxPMA) 226, and analog front-end circuit (AFE) 210. Basically, when the network system operates according to the 1000BASE-T specification, the clock signal of the receiver-side physical media connection element (Rx PMA) 222, the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 233, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 237, and the transmitter-side physical media connection element (TxPMA) 226 is 125MHz. Thus, in the transmission medium 130, the data transmission rate of each twisted-pair cable is 250Mbps, and four twisted-pair cables can achieve a data transmission rate of 1000Mbps (1Gbps).

[0014] Basically, in Ethernet system 100, if the physical layer circuits 112 and 122 in two network modules 110 and 120 are both gigabitant physical layer circuits (GPHY), then the physical layer circuits 112 and 122 of Ethernet system 100 have an auto-negotiation mechanism. The auto-negotiation mechanism is responsible for communicating the operation mode between the two network modules 110 and 120, determining the data transfer rate specified by the 1000BASE-T, 100BASE-TxX, or 10BASE-T / TE specifications for data exchange. Generally, the auto-negotiation mechanism first confirms the specifications supported by the two network modules 110 and 120, and begins training from the highest simultaneously supported specification. For example, if both network modules 110 and 120 support the 1000BASE-T specification, then training will be performed using the 1000BASE-T specification. If one network module 110 supports the 1000BASE-T specification and another network module 120 supports the 100BASE-Tx X specification, then training will be performed using the 100BASE-Tx X specification.

[0015] Please refer to Figure 1C The diagram depicts the self-negotiation process of an existing network system. For example... Figure 1C As shown, assuming both network modules 110 and 120 support the 1000BASE-T standard, when the transmission medium 130 is connected to either network module 110 or 120, or when the network system 100 is powered on, negotiation begins, confirming that both network modules 110 and 120 support the 1000BASE-T standard. First, the two physical layer circuits 112 and 122 are trained using the 1000BASE-T standard (step S162). If it is confirmed that the two network modules 110 and 120 can be successfully linked (step S164), then the two network modules 110 and 120 exchange data using the 1000BASE-T standard (step S166).

[0016] If a link-up fails (step S164), the two physical layer circuits 112 and 122 will be trained using the 100BASE-Tx X specification (step S172). Similarly, if a link-up fails (step S174), the two network modules 110 and 120 will exchange data using the 100BASE-Tx X specification (step S176).

[0017] If a link-up fails (step S174), the two physical layer circuits 112 and 122 will be trained using the 10BASE-T / TE specification (step S182). Similarly, if a link-up fails (step S184), the two network modules 110 and 120 will exchange data using the 10BASE-T / TE specification (step S186).

[0018] Conversely, if it is confirmed that the link-up cannot be successfully established (step S184), then return to step S162. For example, if after multiple training attempts using the 10BASE-T / TE specification (step S182), it is confirmed that the link-up still cannot be successfully established (step S184), then it means that the link between the two network modules 110 and 120 has failed.

[0019] Essentially, the IEEE 802.3 standard does not specify the operating mode when the transmission medium 130 is longer than 100 meters. When the transmission medium 130 is longer than 100 meters, the physical layer circuits (PHYs) 112 and 122 in the two network modules 110 and 120 will lose sufficient performance, making it impossible for the network system to connect successfully. In other words, when the length of the transmission medium 130 is greater than 100 meters, according to... Figure 1C During the self-negotiation process, the two network modules 110 and 120 in network system 100 may fail to connect successfully due to continuous training at various specifications between steps S162 and S184. Alternatively, the connection failure may be confirmed after multiple training sessions at various specifications. Summary of the Invention

[0020] This invention relates to a network system, comprising: a first network module, a second network module, and a transmission medium, wherein the first network module and the second network module are connected to the transmission medium; wherein the first network module includes: a first analog front-end circuit connected to a first end of the transmission medium; a first physical medium connection circuit including a first receiver physical medium connection element and a first transmitter physical medium connection element, wherein the first receiver physical medium connection element operates according to a clock signal of a first frequency; a first physical coding sublayer circuit including a first receiver physical coding sublayer element and a first transmitter physical coding sublayer element; a first symbol synchronization circuit; a first media-independent interface connected to the first media access control circuit; and a first clock switching circuit; wherein, when the first network module operates at a first data transmission rate specification, the first clock switching circuit provides the first frequency clock signal to the first receiver physical coding sublayer element, the first transmitter physical coding sublayer element, and the first transmitter physical medium connection element; a receiver data path of the first physical layer circuit is the first... The first network module comprises an analog front-end circuit, a first receiver-side physical medium connection element, a first receiver-side physical coding sublayer element, and a first medium-independent interface; and a transmitter data path of the first physical layer circuit includes the first medium-independent interface, the first transmitter-side physical coding sublayer element, the first transmitter-side physical medium connection element, and the first analog front-end circuit; wherein, when the first network module operates in a very long-haul (VLSI) transceiver specification, the first clock switching circuit provides a clock signal of a second frequency to the first receiver-side physical coding sublayer element, the first transmitter-side physical coding sublayer element, and the first transmitter-side physical medium connection element, and the first frequency is greater than the second frequency; the receiver data path of the first physical layer circuit includes the first analog front-end circuit, the first receiver-side physical medium connection element, the symbol synchronization circuit, the first receiver-side physical coding sublayer element, and the first medium-independent interface; and the transmitter data path of the first physical layer circuit includes the first medium-independent interface, the first transmitter-side physical coding sublayer element, the first transmitter-side physical medium connection element, and the first analog front-end circuit.

[0021] The present invention further proposes an auto-negotiation method for the above-mentioned network system, comprising the following steps: (b1) when it is confirmed that both the first network module and the second network module support the first data transmission rate specification and the VLTV transmission specification, training is performed using the first data transmission rate specification; (b2) when the first network module and the second network module are trained using the first data transmission rate specification and it is confirmed that the first network module and the second network module are successfully connected, data exchange is performed between the first network module and the second network module using the first data transmission rate specification; (b3) when the first network module and the second network module are trained using the first data transmission rate specification and it is confirmed that the first network module and the second network module are not successfully connected, training is performed between the first network module and the second network module using the VLTV transmission specification; and (b4) when the first network module and the second network module are trained using the VLTV transmission specification and it is confirmed that the first network module and the second network module are successfully connected, data exchange is performed between the first network module and the second network module using the VLTV transmission specification.

[0022] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0023] Figure 1A This is a schematic diagram of an Ethernet network system.

[0024] Figure 1B This is a schematic diagram of an existing physical layer circuit (PHY);

[0025] Figure 1C A flowchart of the self-negotiation process for an existing network system;

[0026] Figure 2 This is a schematic diagram of the Ethernet network system of the present invention;

[0027] Figure 3 This is a flowchart of the self-negotiation process of the network system of the present invention;

[0028] Figure 4 This is a schematic diagram of the physical layer circuit (PHY) of the present invention; and

[0029] Figure 5A and Figure 5B This is a schematic diagram of the symbol synchronization circuit and related signals of the present invention.

[0030] The reference numerals in the attached figures are explained as follows:

[0031] 100, 200: Network system

[0032] 110, 120, 250, 260: Network modules

[0033] 112, 122, 200, 252, 262, 300: Physical layer circuits

[0034] 114, 124: Media-independent interfaces

[0035] 116, 126: Media access control circuit

[0036] 130: Transmission medium

[0037] 210, 310: Analog front-end circuit

[0038] 220, 320: Physical medium connection circuit

[0039] 222, 322: Physical medium connection element at the receiver end

[0040] 226, 326: Transmitter-side physical media connection elements

[0041] 230, 330: Physical coding sublayer circuits

[0042] 231: 10M receiver end physical coding sublayer element

[0043] 232: 100M receiver end physical coding sublayer element

[0044] 233, 333: Physical coding sublayer components at the 1000M receiver end

[0045] 237, 337: Physical coding sublayer elements at the 1000M transmitter end

[0046] 238: 100M transmitter end physical coding sublayer element

[0047] 239: 10M transmitter end physical coding sublayer element

[0048] 240, 340: Media-independent interfaces

[0049] 350: Symbol Synchronization Circuit

[0050] 352: Clock switching circuit

[0051] 510: Processing Group

[0052] 520: Computational Group

[0053] 530: Determines the circuit

[0054] 535: Judgment Circuit

[0055] 540: Selection Circuit Detailed Implementation

[0056] Essentially, in network systems, the operating mode when two network modules are connected via a transmission medium longer than 100 meters is not specified by the IEEE 802.3 standard. This invention discloses a network system and related control method for long-distance Ethernet networks, applicable to transmission media longer than 100 meters. For example, when the transmission medium is longer than 100 meters, it can be considered a network system with ultra-long-haul lines.

[0057] According to an embodiment of the present invention, a long reach transceiver specification (LVT) is additionally designed in the physical layer circuit (PHY) of the network module. In the network system, when both network modules support this LVT, it can be selectively used for data exchange during the auto-negotiation process. In other words, the present invention designs a unique hardware architecture in the physical layer circuit (PHY) of the network module. When both network modules in the network system include this unique hardware architecture, the LVT can be selectively used for data exchange during the auto-negotiation process.

[0058] For example, vendor A designs the unique hardware architecture of this invention in its network module products. If both network modules in the network system are designed by vendor A, the auto-negotiation process will confirm that both modules are capable of ultra-long-haul (ULWH) data transmission and reception. Therefore, this ULWHH specification can be selectively used for data exchange. Conversely, if network modules designed by vendor A and vendor B are connected to form a network system, the auto-negotiation process will confirm that one of the network modules does not possess the ULWHH specification capability of this invention. The network system auto-negotiation process will then be similar. Figure 1C This will prevent the use of the ultra-long-distance transceiver specifications disclosed in this invention for data exchange.

[0059] Please refer to Figure 2 The diagram illustrates the network system of the Ethernet of this invention. The network system 200 includes two network modules 250 and 260 and a transmission medium 130. The two network modules 250 and 260 are connected to the transmission medium 130, and the two network modules 250 and 260 exchange data via the transmission medium 130.

[0060] Network module 250 includes at least a physical layer circuit (PHY) 252 and a medium access control circuit (MAC) 116. Data is transmitted between the PHY 252 and the MAC 116 via a media independent interface (MII) 114. Similarly, network module 260 includes at least a physical layer circuit (PHY) 262 and a MAC 126. Data is transmitted between the PHY 262 and the MAC 126 via a media independent interface (MII) 124. The MII can be a gigabit media independent interface (GMII) or a reduced media independent interface (RMII). The PHYs 252 and 262 can be gigabit physical layer circuits (GPHYs).

[0061] Similarly, transmission medium 130 connects the two physical layer circuits (PHYs) 252 and 262. Transmission medium 130 can be a network cable, such as a network cable consisting of four pairs of twisted-pair cables. Of course, network modules 250 and 260 also include a controller (not shown) to provide parameters to set the corresponding physical layer circuits (PHYs) 252 and 262 and media access control circuits (MACs) 116 and 126.

[0062] Compared to Figure 1A In the existing network system 100, the present invention designs unique physical layer circuits (PHY) 252 and 262. That is, without modifying the media access control circuits (MAC) 116 and 126, the two circuit modules 250 and 260 can exchange data using 1000BASE-T, 100BASE-Tx X, and 10BASE-T / TE specifications, and can also exchange data using very long line transceiver specifications.

[0063] The following section first introduces the self-negotiation process of the network system of this invention. Then, it describes the physical layer circuit (PHY) of the network module within the network system of this invention.

[0064] Please refer to Figure 3 The diagram shown is a self-negotiation flowchart of the network system of the present invention. Figure 3 As shown, assuming both network modules 250 and 260 support the 1000BASE-T standard, auto-negotiation begins when the transmission medium 130 is connected to network modules 250 and 260 or when the network system 200 is powered on. First, it is determined whether the two network modules support the 1000BASE-T standard (step S202). After confirming that both network modules support the 1000BASE-T standard, it is further determined whether the two network modules support the ultra-long-haul (ULT) transceiver standard (step S204). The purpose of step S204 is to confirm whether the physical layer circuits (PHY) 252 and 262 in network modules 250 and 260 are products designed by vendor A.

[0065] According to an embodiment of the present invention, step S210 is performed when it is confirmed that one of the two network modules 250 and 260 does not support the 1000BASE-T specification (step S202) or when it is confirmed that one of the two network modules 250 and 260 does not support the Ultra Long Distance Transmit / Receive specification (step S204). The process of step 210 is similar to that of existing auto-negotiation. That is, one of the 1000BASE-T specification, 100BASE-Tx X specification, and 10BASE-T / TE specification is used as the training specification, and training is performed using the training specification (step S212). If the two network modules 250 and 260 cannot connect successfully (step S214), the process returns to step S202. If the two network modules 250 and 260 successfully connect (step S214), data exchange is performed using the training specification. That is, data exchange is performed using one of the following specifications: 1000BASE-T, 100BASE-Tx X, or 10BASE-T / TE (step S216). For detailed instructions on step 210, please refer to [link to relevant documentation]. Figure 1C The self-negotiation process.

[0066] Furthermore, upon confirming that both network modules 250 and 260 support the 1000BASE-T specification (step S202) and both support the ultra-long-haul transceiver specification (step S204), the two physical layer circuits 252 and 262 are trained using the 1000BASE-T specification (step S222). If it is confirmed that the two network modules 250 and 260 can be successfully linked (step S224), then the two network modules 250 and 260 exchange data using the 1000BASE-T specification (step S226).

[0067] If it is confirmed that the training in step 222 cannot be successfully linked (step S224), it means that the two network modules 250 and 260 are connected by a transmission medium 130 exceeding the specified length, that is, a transmission medium 130 with a length greater than 100 meters. At this time, the two physical layer circuits 252 and 262 will directly switch to training using the ultra-long-haul (ULWH) transceiver specification (step S232). If it is confirmed that the two network modules 250 and 260 can be successfully linked (step S234), then the two network modules 250 and 260 will exchange data using the ULWHH transceiver specification (step S226). Conversely, if it is confirmed that the training in step 232 cannot be successfully linked (step S224), then return to step S202.

[0068] Depend on Figure 3 According to the self-negotiation process of this invention, after confirming that the physical layer circuits (PHYs) 252 and 262 in network modules 250 and 260 are both products designed by vendor A (step S204) and training with the 1000BASE-T specification has failed (steps S222 and S224), the physical layer circuits (PHYs) 252 and 262 in network modules 250 and 260 are directly trained using the ultra-long-haul transceiver specification of this invention (step S232). After successful training (step S234), the two network modules 250 and 260 exchange data using the ultra-long-haul transceiver specification of this invention (step S236).

[0069] To enable network modules 250 and 260 to exchange data using the ultra-long-haul (ULWHM) transceiver specifications of this invention, a unique architecture is designed in the physical layer circuits (PHYs) 252 and 262 of network modules 250 and 260. This is described in detail below.

[0070] Please refer to Figure 4 The diagram shown is a schematic representation of the physical layer circuit (PHY) of this invention. This physical layer circuit (PHY) 300 can be used in... Figure 2 The two physical layer circuits (PHY) 252 and 262 are included, and the physical layer circuit (PHY) 300 is a gigabitant physical layer circuit (GPHY).

[0071] The physical layer circuit (PHY) 300 includes: an analog front-end circuit (AFE) 310, a physical media connection circuit (PMA) 320, a physical coding sublayer circuit (PCS) 330, and a media-independent interface (MII) 340. Furthermore, the physical layer circuit (PHY) 300 further includes: a symbol synchronization circuit 350 and a clock switching circuit 352.

[0072] Analog front-end circuitry (AFE) 310 is connected to a first end of transmission medium 130, while a second end of transmission medium 130 is connected to the physical layer circuitry (PHY) of another network module. Furthermore, media-independent interface (MII) 340 is connected to media access control circuitry (MAC).

[0073] The physical medium connection circuit (PMA) 320 includes: a receiver-side physical medium connection element (Rx PMA) 322 and a transmitter-side physical medium connection element (Tx PMA) 326.

[0074] The physical coding sublayer circuit (PCS) 330 includes: a 10M receiver-side physical coding sublayer element (10MRx PCS) 231, a 100M receiver-side physical coding sublayer element (100M Rx PCS) 232, a 1000M receiver-side physical coding sublayer element (1000M Rx PMA) 333, a 10M transmitter-side physical coding sublayer element (10M Tx PCS) 239, a 100M transmitter-side physical coding sublayer element (100M Tx PCS) 238, and a 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337. Here, 10M, 100M, and 1000M represent different data transmission rates (Mbps).

[0075] Furthermore, the symbol synchronization circuit 350 is connected between the receiver-side physical medium connection element (Rx PMA) 322 and the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333. The clock switching circuit 352 provides one of the clock signals CK1 and CK2 of different frequencies to the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326 according to the control signal Ctrl.

[0076] For example, the clock switching circuit 352 is a multiplexer, with two inputs receiving a 125MHz clock signal CK1 and a 12.5MHz clock signal CK2, respectively. When the physical layer circuit (PHY) 300 operates in 1000BASE-T specification, the clock switching circuit 352 provides the 125MHz clock signal CK1 to the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326. When the physical layer circuit (PHY) 300 is operating in the ultra-long line transceiver specification of the present invention, the clock switching circuit 352 provides a 12.5MHz clock signal CK2 to the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326.

[0077] certainly, Figure 4 The clock switching circuit 352 can also be modified appropriately. For example, the clock switching circuit 352 includes multiple multiplexers (e.g., three multiplexers) that operate according to the control signal Ctrl. The two inputs of the three multiplexers receive a 125MHz clock signal CK1 and a 12.5MHz clock signal CK2, respectively, and the outputs of the three multiplexers are connected to the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326, respectively.

[0078] In other words, when the physical layer circuit (PHY) 300 operates in the 1000BASE-T specification, the clock switching circuit 352 provides three clock signals of the same frequency (125MHz), which are transmitted to the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326, respectively. Conversely, when the physical layer circuit (PHY) 300 operates in the ultra-long-haul transceiver specification of this invention, the clock switching circuit 352 provides three clock signals of the same frequency (12.5MHz), which are transmitted to the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000MTx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326, respectively.

[0079] Compared to Figure 1B In addition to supporting 10BASE-T / TE, 100BASE-Tx X and 1000BASE-T specifications, the physical layer circuit (PHY) 300 of this invention supports ultra-long-distance transceiver specifications, as well as the existing physical layer circuit (PHY) 200.

[0080] When the physical layer circuit (PHY) 300 operates in 10BASE-T / TE specification, the receiver data path consists of the analog front-end circuit (AFE) 310, the 10M receiver-side physical coding sublayer element (10M Rx PCS) 231, and the media-independent interface (MII) 240. The transmitter data path consists of the media-independent interface (MII) 340, the 10M transmitter-side physical coding sublayer element (10MTx PCS) 239, and the analog front-end circuit (AFE) 310. Essentially, the physical layer circuit (PHY) 300 in 10BASE-T / TE specification is similar to existing... Figure 1B The physical layer circuit (PHY) 200 operates in the same manner as the 10BASE-T / TE specification.

[0081] When the physical layer circuit (PHY) 200 operates in 100BASE-Tx X specification, the receiver data path consists of analog front-end circuit (AFE) 310, receiver-side physical medium connection element (Rx PMA) 322, 100M receiver-side physical coding sublayer element (100M Rx PCS) 232, and media-independent interface (MII) 340. The transmitter data path consists of media-independent interface (MII) 340, 100M transmitter-side physical coding sublayer element (100M Tx PCS) 238, and analog front-end circuit (AFE) 310. Essentially, the physical layer circuit (PHY) 300 in 100BASE-Tx X specification is similar to existing... Figure 1B The physical layer circuit (PHY) 200 operates in the same manner as the 100BASE-Tx X specification.

[0082] When the physical layer circuit (PHY) 300 operates in 1000BASE-T specification, the clock switching circuit 352 provides a 125MHz clock signal CK1 to the 1000M receiver-side physical coding sublayer element (1000MRx PMA) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical media connection element (Tx PMA) 326. That is, when the physical layer circuit (PHY) 300 operates in 1000BASE-T specification, the clock signal CK1 for the receiver-side physical media connection element (RxPMA) 322, the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical media connection element (Tx PMA) 326 is 125MHz. Thus, in transmission medium 130, the data transmission rate of each twisted-pair cable is 250Mbps, and four twisted-pair cables can achieve a data transmission rate of 1000Mbps (1Gbps).

[0083] Furthermore, the receiver data path consists of an analog front-end circuit (AFE) 310, a receiver-side physical medium connection element (RxPMA) 322, a 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, and a media-independent interface (MII) 340. The transmitter data path consists of a media-independent interface (MII) 340, a 1000M transmitter-side physical coding sublayer element (1000M TxPCS) 337, a transmitter-side physical medium connection element (Tx PMA) 326, and an analog front-end circuit (AFE) 310. Therefore, by using the clock switching circuit 352 to provide a 125MHz clock signal CK1, the physical layer circuit (PHY) 300 can be made compatible with existing 1000BASE-T specifications. Figure 1B The physical layer circuit (PHY) 200 operates in the same manner as the 1000BASE-T specification.

[0084] According to an embodiment of the present invention, when the physical layer circuit (PHY) 300 is operating in the very long line transceiver specification, the clock switching circuit 352 provides a 12.5MHz clock signal CK2 to the 1000M receiver-side physical coding sublayer element (1000M RxPMA) 333, the 1000M transmitter-side physical coding sublayer element (1000MTx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326.

[0085] In other words, when the physical layer circuit (PHY) 300 operates in the VLTV (Very Long Distance) transceiver specification, only the receiver-side physical medium connection element (Rx PMA) 322 still operates according to a 125MHz clock signal. Although the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326 have sufficient capability to operate with a 125MHz clock signal CK1, in order to ensure the quality of transaction data and guarantee the correctness of data over VLTV, the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, and the transmitter-side physical medium connection element (Tx PMA) 326 will slow down and operate with a 12.5MHz clock signal CK2. In other words, the transmission medium 130 between network modules 250 and 260 actually exchanges data at a data transmission rate of 100Mbps (100Mbps).

[0086] like Figure 4 As shown, when the physical layer circuit (PHY) 300 operates in the VLTV (Very Long Line Transceiver) specification, the receiver data path consists of the analog front-end circuit (AFE) 310, the receiver-side physical medium connection element (Rx PMA) 322, the symbol synchronization circuit 350, the 1000M receiver-side physical coding sublayer element (1000M Rx PCS) 333, and the media-independent interface (MII) 340. The transmitter data path consists of the media-independent interface (MII) 340, the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337, the transmitter-side physical medium connection element (Tx PMA) 326, and the analog front-end circuit (AFE) 310.

[0087] In the transmitter data path, the media access control circuit (MAC) transmits data (D). T The data is transmitted via the media-independent interface 340 to the 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337. The 1000M transmitter-side physical coding sublayer element (1000M Tx PCS) 337 processes the transmitted data D according to a lower clock signal CK2. TThe data signal S1 is output to the transmitter-side physical medium connection element (Tx PMA) 326. Similarly, the transmitter-side physical medium connection element (Tx PMA) 326 processes the data signal S1 according to the lower clock signal CK2 and outputs the data signal S2 to the analog front-end circuit (AFE) 310 and transmits it to another network module via the transmission medium 130.

[0088] In the receiver data path, the data signal S3, transmitted to the network module via the transmission medium 130, is input to the receiver-side physical medium connection element (Rx PMA) 322. Since the clock signal of the receiver-side physical medium connection element (Rx PMA) 322 is 125MHz, ten times the clock signal CK2 (12.5MHz), each bit of data in the data signal S3 is sampled ten times by the receiver-side physical medium connection element (Rx PMA) 322, becoming the data signal S4, which is then transmitted to the symbol synchronization circuit 350. Furthermore, the symbol synchronization circuit 350 sums and averages the ten consecutive sampled values ​​in the data signal S4, obtaining multiple average signals, and then determines the optimal average signal from among these multiple average signals. In other words, the symbol synchronization circuit 350 continuously calculates multiple average signals from ten consecutive sampled values, and then selects the optimal average signal from these multiple average signals as the data signal S5, which is output to the 1000M receiver's physical coding sublayer element (1000M Rx PCS) 333. Since the symbol synchronization circuit 350 calculates the optimal average signal from ten consecutive sampled values ​​as the data signal S5, it means that the data rate of the data signal S5 has been reduced. Therefore, the 1000M receiver's physical coding sublayer element (1000M Rx PCS) 333 processes the data signal S5 according to the 12.5MHz clock signal CK2 and generates the received data D. R The signal is transmitted to the Media Access Control (MAC) circuit via the Media Independent Interface 340. The symbol synchronization circuit 350 is described in detail below.

[0089] Please refer to Figure 5A and Figure 5B The diagram illustrates the symbol synchronization circuit and related signals of the present invention. The symbol synchronization circuit 350 includes a processing group 510, a calculating group 520, and a judgment circuit 535. The judgment circuit includes a decision circuit 530 and a selection circuit 540.

[0090] Processing group 510 includes multiple processing devices. Each processing unit includes an adder, a first delay unit, a second delay unit, and an averaging unit. Basically, the number M of processing devices can be determined by the frequency ratio of clock signals CK1 and CK2. In an embodiment of the invention, M = 125MHz / 12.5MHz = 10, so processing group 510 includes 10 processing devices.

[0091] For example, in processing group 510, the topmost processing element 519 receives data signal S4 and generates processing signal X0. Data signal S4 is delayed by one time period via the first delay unit 511 before being passed to the next processing element. Furthermore, adder 513 continuously accumulates the consecutive sampled values ​​in data signal S4 and subtracts the sampled values ​​delayed by ten time periods via delay element 512. In other words, the topmost processing unit can sum ten consecutive sampled values ​​in data signal S4, and the averaging unit 514 averages the sum to generate processing signal X0. Similarly, each processing element receives ten different consecutive sampled values ​​and generates corresponding processing signals X0 to X9.

[0092] Furthermore, the computing group 520 includes multiple computing devices, such as ten computing devices. Each computing device includes an adder and a delay unit. Similarly, the number M of computing devices can be determined by the frequency ratio of clock signals CK1 and CK2.

[0093] For example, in the computational group 520, in the topmost computational element 529, the delay unit 524 delays the average signal AV0 by one unit time and then adds it to the processed signal X0 to obtain the average signal AV0. The computational element 529 operates like an integrator, eliminating large deviations in the processed signal X0 and calculating the average value.

[0094] Additionally, the multiple input terminals of the selection circuit 540 receive average signals AV0 to AV9. The determination circuit 530 receives all the average signals AV0 to AV9 and generates a selection signal SEL to the selection terminal of the selection circuit 540 to select one of the multiple average signals AV0 to AV9 as the data signal S5 to be transmitted to the 1000M receiver-side physical coding sublayer element (1000M RxPCS) 333. Basically, the determination circuit 530 generates the selection signal SEL based on the maximum value among the average signals AV0 to AV9. For example, if the average signal AV0 is the maximum value among the average signals AV0 to AV9, then the selection circuit 540 transmits the average signal AV0 as the data signal S5 to the 1000M receiver-side physical coding sublayer element (1000M RxPCS) 333 based on the selection signal SEL. That is, the determination circuit 535 can use the maximum value among the average signals AV0 to AV9 as the data signal S5.

[0095] Figure 5B The diagram shows the continuously sampled values ​​in the data signal S4. That is, the receiver-side physical medium connection element (Rx PMA) 322 samples each bit of the data signal S3 ten times, resulting in the data signal S4. In the symbol synchronization circuit 350, the ten processing elements of the processing group 510 continuously collect and process these ten consecutive sampled values, resulting in processing signals X0 to X9, which are then output to the computing group 520.

[0096] In addition, the ten computing elements in the computing group 520 respectively calculate and process signals X0 to X9, and generate average signals AV0 to AV9. The decision circuit 530 receives the average signals AV0 to AV9, and generates a selection signal SEL to the selection terminal of the selection circuit 540 to select the best average signal from the multiple average signals AV0 to AV9 as the data signal S5.

[0097] In summary, this invention proposes a network system and related control method for long-distance Ethernet networks. During the self-negotiation process of the network system, it is first confirmed whether both network modules possess the capability of the ultra-long-haul (ULW) transceiver specifications of this invention. When both network modules possess the capability of the ULWW transceiver specifications of this invention, and training with the 1000BASE-T specification fails, the two network modules directly train using the ULWW transceiver specifications of this invention. After successful training, the two network modules exchange data using the ULWW transceiver specifications of this invention.

[0098] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A network system, comprising: A first network module, a second network module, and a transmission medium are provided, wherein the first network module and the second network module are connected to the transmission medium; wherein the first network module includes: a first media access control circuit and a first physical layer circuit, and the first physical layer circuit includes: A first analog front-end circuit is connected to a first end of the transmission medium; A first physical medium connection circuit includes a first receiving end physical medium connection element and a first transmitting end physical medium connection element, wherein the first receiving end physical medium connection element operates according to a clock signal of a first frequency. A first physical coding sublayer circuit includes a first receiver-side physical coding sublayer element and a first transmitter-side physical coding sublayer element; A first symbol synchronization circuit; A first medium-independent interface is connected to the first medium access control circuit; and A first clock switching circuit; Wherein, when the first network module operates at a first data transmission rate specification, the first clock switching circuit provides a clock signal of the first frequency to the first receiver-side physical coding sublayer element, the first transmitter-side physical coding sublayer element, and the first transmitter-side physical medium connection element; a receiver data path of the first physical layer circuit includes the first analog front-end circuit, the first receiver-side physical medium connection element, the first receiver-side physical coding sublayer element, and the first media-independent interface; and a transmitter data path of the first physical layer circuit includes the first media-independent interface, the first transmitter-side physical coding sublayer element, the first transmitter-side physical medium connection element, and the first analog front-end circuit; When the first network module operates in an ultra-long-haul (ULWC) transceiver specification, the first clock switching circuit provides a second frequency clock signal to the first receiver-side physical coding sublayer element, the first transmitter-side physical coding sublayer element, and the first transmitter-side physical medium connection element, and the first frequency is greater than the second frequency; the receiver data path of the first physical layer circuit consists of the first analog front-end circuit, the first receiver-side physical medium connection element, the symbol synchronization circuit, the first receiver-side physical coding sublayer element, and the first medium-independent interface; and the transmitter data path of the first physical layer circuit consists of the first medium-independent interface, the first transmitter-side physical coding sublayer element, the first transmitter-side physical medium connection element, and the first analog front-end circuit.

2. The network system of claim 1, wherein the first clock switching circuit receives a clock signal of the first frequency and a clock signal of the second frequency, and provides the clock signal of the first frequency or the clock signal of the second frequency according to a control signal.

3. The network system of claim 1, wherein when the first network module operates in the VLTV (Very Long Over Long Distance) specification, in the transmitter data path, a transmission data of the first media access control circuit is transmitted to the first transmitter-side physical coding sublayer element via the first media-independent interface; the first transmitter-side physical coding sublayer element processes the transmission data according to the second frequency clock signal and outputs a first data signal to the first transmitter-side physical medium connection element; the first transmitter-side physical medium connection element processes the first data signal according to the second frequency clock signal and outputs a second data signal to the first analog front-end circuit and transmits it to the second network module via the transmission medium.

4. The network system of claim 3, wherein when the first network module operates in the VLTV (Very Long Over Long Distance) specification, in the receiver data path, the first analog front-end circuit transmits a third data line number to the first receiver physical medium connection element; the first receiver physical medium connection element processes the third data line number according to the clock signal of the first frequency and outputs a fourth data signal to the symbol synchronization circuit; the symbol synchronization circuit receives the fourth data signal and outputs a fifth data signal to the first receiver physical coding sublayer element; the first receiver physical coding sublayer element processes the fifth data line number according to the clock signal of the second frequency and outputs received data transmitted to the first medium access control circuit via the first medium-independent interface.

5. The network system of claim 4, wherein the symbol synchronization circuit receives continuous sample values ​​from the fourth data signal and obtains an optimal average signal as the fifth data signal.

6. The network system of claim 5, wherein the symbol synchronization circuit comprises: A processing group comprising M processing elements, each of which receives M different consecutive sample values ​​and obtains M processing signals. as well as A computing group, comprising M computing elements, calculates the M processed signals generated by the M processing elements and generates M average signals; as well as A judgment circuit receives the M average signals and selects the best average signal from the M average signals as the fifth data signal; Where M is equal to the frequency ratio of the first frequency clock signal to the second frequency clock signal.

7. The network system of claim 1, wherein the second network module comprises: A second media access control circuit and a second physical layer circuit, wherein the second physical layer circuit includes: A second analog front-end circuit is connected to a second end of the transmission medium; A second physical medium connection circuit includes a second receiving end physical medium connection element and a second transmitting end physical medium connection element, wherein the second receiving end physical medium connection element operates according to a clock signal of the first frequency; A second physical coding sublayer circuit includes a second receiver-side physical coding sublayer element and a second transmitter-side physical coding sublayer element; A second symbol synchronization circuit; A second media-independent interface is connected to the second media access control circuitry; and A second clock switching circuit; When the second network module operates at the first data transmission rate specification, the second clock switching circuit provides the first frequency clock signal to the second receiver end physical coding sublayer element, the second transmission end physical coding sublayer element and the second transmission end physical medium connection element. When the second network module operates in the ultra-long-haul (ULWH) transceiver specification, the second clock switching circuit provides the second frequency clock signal to the second receiver physical coding sublayer element, the second transmitter physical coding sublayer element, and the second transmitter physical medium connection element.

8. A self-negotiation method for the network system as described in claim 1, comprising the following steps: (b1) When it is confirmed that both the first network module and the second network module support the first data transmission rate specification and the ultra-long line transceiver specification, training is performed using the first data transmission rate specification; (b2) When the first network module and the second network module are trained with the first data transmission rate specification and it is confirmed that the first network module and the second network module are successfully connected, the first network module and the second network module exchange data with the first data transmission rate specification. (b3) When the first network module and the second network module are trained with the first data transmission rate specification, and it is confirmed that the first network module and the second network module have not been successfully connected, the first network module and the second network module are trained with the ultra-long line transceiver specification. as well as (b4) When the first network module and the second network module are trained using the ultra-long line transceiver specification and the connection between the first network module and the second network module is confirmed to be successful, the first network module and the second network module exchange data using the ultra-long line transceiver specification.

9. The self-negotiation method as described in claim 8 further comprises the following steps: (a1) Determine whether both the first network module and the second network module support the first data transmission rate specification; wherein... When both the first network module and the second network module support the first data transmission rate specification, step (a2) is performed; and when one of the first network module and the second network module does not support the first data transmission rate specification, step (c1) is performed. (a2) Determine whether both the first network module and the second network module support the ultra-long line transceiver specification; wherein, if both the first network module and the second network module support the ultra-long line transceiver specification, proceed to step (b1); and if one of the first network module and the second network module does not support the ultra-long line transceiver specification, proceed to step (c1). (c1) The first network module and the second network module use one of the first data transmission rate specification, a second data transmission rate specification or a third data transmission rate specification as a training specification, and are trained using the training specification. (c2) When the first network module and the second network module are trained with the training specifications, and the successful connection between the first network module and the second network module is confirmed, the first network module and the second network module exchange data with the training specifications; and (c2) When the first network module and the second network module are trained with the training specifications and it is confirmed that the first network module and the second network module are not successfully connected, proceed to step (a1).

10. The self-negotiation method as described in claim 8, further comprising the following steps: (b5) When the first network module and the second network module are trained with the ultra-long line transceiver specification, and it is confirmed that the first network module and the second network module have not been successfully connected, proceed to step (a1).

11. The auto-negotiation method as described in claim 9, wherein the first data transmission rate specification is a 1000BASE-T specification, the second data transmission rate specification is a 100BASE-TxX specification, and the third data transmission rate specification is a 10BASE-T / TE specification.

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