Semiconductor structure and integrated circuit

Abstract

According to the semiconductor structure and the integrated circuit provided by the invention, the resistance control electrode is arranged above the barrier layer, so that on one hand, the concentration of 2DEG can be adjusted by controlling positive and negative voltages loaded on the resistance control electrode, thereby obtaining a resistance-adjustable GaN-based integrated platform semiconductor structure; and on the other hand, the resistance control electrode can be controlled to be loaded with 0 potential or set to be a floating electrode, so that the resistance control electrode does not influence the channel resistance of the 2DEG, and the resistance control electrode can shield the influence of the upper layer wiring potential of the semiconductor structure on the 2DEG. Moreover, after tape-out of the semiconductor structure provided by the invention, the voltage loaded on the resistance control electrode can be changed in real time according to working requirements, so that the resistance value of the semiconductor structure is adjusted in real time, and the flexibility and functionality of circuit design are improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and integrated circuit. Background Technology

[0002] Gallium nitride (GaN) has a relatively low permittivity and a high saturation drift velocity, making it suitable for high-frequency applications. GaN can form high-electron-mobility channels through heterostructures, enabling the fabrication of high-electron-mobility transistors (HEMTs). The combination of high carrier concentration and high electron mobility achieves high current density and low channel resistance, which is particularly important for high-frequency operation and power switching applications. GaN utilizes a 2DEG channel for conduction, and its lateral structure facilitates monolithic integration. Compared to the board-level circuitry of discrete devices, monolithic integration reduces parasitic effects from interconnects, better leveraging the high-frequency characteristics of GaN.

[0003] In GaN monolithic integration, resistors are key passive components that implement circuit functions. In GaN integrated platforms, resistors mainly include 2DEG resistors and metal resistors. Metal resistors have very low sheet resistances, approximately tens of Ω / sq, suitable for circuits requiring fine resistance. 2DEG resistors typically have sheet resistances of several hundred Ω / sq. The sheet resistances of these two types of resistors differ significantly. Furthermore, the sheet resistance of 2DEG resistors is related to the device's layer hierarchy, thus the sheet resistance of resistors on a GaN integrated platform with a specific layer hierarchy is also determined accordingly, making it impossible to adjust the resistance value during operation / testing, which reduces the flexibility of circuit design. Different circuit designs require resistors of different resistance values. To achieve resistors of different sizes, one method is to connect multiple resistors in series or parallel, which requires a certain amount of chip area. Another method is to design and place variable resistors in the external circuitry of the integrated chip; however, this external circuitry PCB connection can introduce parasitic effects. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and integrated circuit that can adjust the resistance value of the semiconductor structure in real time as needed, increasing the flexibility and functionality of circuit design.

[0005] This disclosure provides a semiconductor structure, integrated circuit, and electronic device, the specific solutions of which are as follows: On one hand, embodiments of this disclosure provide a semiconductor structure, including: a substrate, a channel layer located on one side of the substrate, and a barrier layer located on the side of the channel layer away from the substrate; It also includes a first electrode and a second electrode disposed on both sides of the barrier layer, both of which are electrically connected to the channel layer; It also includes a resistance control electrode located on the side of the barrier layer away from the substrate, the resistance control electrode being located between the first electrode and the second electrode.

[0006] In some embodiments, in the semiconductor structure provided in this disclosure, the area of ​​the resistor control electrode accounts for more than 50% of the area between the first electrode and the second electrode.

[0007] In some embodiments, in the semiconductor structure provided in the present disclosure, the number of resistor control electrodes is one, the resistor control electrode is a floating electrode, or the resistor control electrode is configured to be loaded with voltages of different polarities and / or different magnitudes.

[0008] In some embodiments, in the semiconductor structure provided in the present disclosure, the direction from the first electrode to the second electrode is a first direction, and the direction perpendicular to the first direction is a second direction, wherein the first direction and the second direction are located in the same plane; The resistance control electrode covers the entire area of ​​the barrier layer between the first electrode and the second electrode extending along the second direction, or the resistance control electrode covers a portion of the area of ​​the barrier layer between the first electrode and the second electrode extending along the second direction.

[0009] In some embodiments, in the semiconductor structure provided in this disclosure, the number of resistor control electrodes along the direction from the first electrode to the second electrode is at least two that are spaced apart. Each of the resistor control electrodes is a floating electrode; or, each of the resistor control electrodes is connected to an external circuit via different leads, at least one of the resistor control electrodes is configured to be loaded with a voltage, and each of the resistor control electrodes is configured to be loaded with the same voltage.

[0010] In some embodiments, the semiconductor structure provided in this disclosure further includes a dielectric layer located on the side of the barrier layer away from the substrate, the resistance control electrode located on the side of the dielectric layer away from the substrate, and the first electrode and the second electrode located on the side of the dielectric layer away from the substrate and penetrating the dielectric layer.

[0011] In some embodiments, the semiconductor structure provided in this disclosure further includes a dielectric layer located on the side of the barrier layer away from the substrate, wherein the first electrode, the second electrode, and the resistance control electrode are located on the side of the dielectric layer away from the substrate and penetrate the dielectric layer.

[0012] In some embodiments, in the semiconductor structure provided in this disclosure, the first electrode and the second electrode are in contact with the surface of the barrier layer away from the substrate, or the first electrode and the second electrode also penetrate the barrier layer.

[0013] In some embodiments, the semiconductor structure provided in this disclosure further includes: a nucleation layer located between the substrate and the channel layer, a buffer layer located between the nucleation layer and the channel layer, and an isolation layer surrounding the first electrode and the second electrode.

[0014] On the other hand, this disclosure also provides an integrated circuit, including the semiconductor structure described above.

[0015] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor structure and integrated circuit. By placing a resistor control electrode above the barrier layer, the concentration of 2DEG can be adjusted by controlling the magnitude of the positive and negative voltage applied to it, thereby obtaining a GaN-based integrated platform semiconductor structure with adjustable resistance. Furthermore, the resistor control electrode can be controlled to have a zero potential or be set as a floating electrode, so that it does not affect the 2DEG channel resistance and can shield the influence of the upper layer trace potential on the 2DEG. Moreover, after tape-out, the semiconductor structure provided by this disclosure allows for real-time adjustment of the resistance value of the semiconductor structure by changing the voltage applied to the resistor control electrode according to operational needs, thereby increasing the flexibility and functionality of circuit design. Attached Figure Description

[0016] Figure 1 A cross-sectional structural schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 2 for Figure 1 A planar schematic diagram of the middle part of the structure; Figure 3 for Figure 1 Another planar schematic diagram of the middle part structure; Figure 4 Another cross-sectional structural schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 5 A schematic diagram illustrating the working principle of a semiconductor structure provided in this embodiment of the disclosure; Figure 6 This is another schematic diagram illustrating the working principle of a semiconductor structure provided in an embodiment of the present disclosure; Figure 7 This is a schematic diagram of a semiconductor structure simulated using TCAD; Figure 8 The curves show the variation of the 2DEG resistance (R) below G, between GS, and between GD as a function of the voltage (VG) of G; Figure 9 To adopt multiple lines Figure 2 The diagram shows the structure of the two-dimensional electron gas channel corresponding to the series connection of resistors. Figure 10 To adopt multiple lines Figure 2 The diagram shows the structure of the two-dimensional electron gas channel corresponding to the parallel connection of resistors. Figure 11 To adopt multiple lines Figure 2 The resistors shown are connected in parallel to form a parallel structure; Figure 12 To adopt multiple lines Figure 2 The resistors shown are connected in parallel to form another parallel structure; Figure 13 To adopt multiple lines Figure 2 The resistors shown are connected in parallel to form another parallel structure; Figure 14 Another cross-sectional structural schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 15 for Figure 14 A planar schematic diagram of the middle part of the structure; Figure 16 Another schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 17 for Figure 1 The diagram shows a schematic representation of the semiconductor structure during its fabrication process. Figure 18 for Figure 1 The diagram shows another possible structure of the semiconductor structure during the fabrication process. Figure 19 for Figure 1 The diagram shows another possible structure of the semiconductor structure during the fabrication process. Figure 20 for Figure 1 The diagram shows another possible structure of the semiconductor structure during the fabrication process. Figure 21 for Figure 1 The diagram shows another structural schematic of the semiconductor structure during the fabrication process. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0018] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0019] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0020] This disclosure provides a semiconductor structure, which can be a resistor, such as... Figure 1 As shown, it includes: a substrate 101, a channel layer 104 located on one side of the substrate 101, and a barrier layer 105 located on the side of the channel layer 104 away from the substrate 101; the channel layer 104 and the barrier layer 105 form a heterojunction, and a two-dimensional electron gas channel 106, i.e., a 2DEG channel, is formed on the side of the channel layer 104 near the barrier layer 105. It also includes a first electrode 109 and a second electrode 110 disposed on both sides of the barrier layer 105. Both the first electrode 109 and the second electrode 110 form an ohmic contact with the two-dimensional electron gas channel 106, that is, both the first electrode 109 and the second electrode 110 are electrically connected to the channel layer 104. In this way, the first electrode 109 and the second electrode 110 are located at the two ends of the semiconductor structure, and the unisolated resistance at both ends is the semiconductor structure resistance. Optionally, the first electrode 109 is the input electrode and the second electrode 110 is the output electrode; alternatively, the first electrode 109 can be the output electrode and the second electrode 110 can be the input electrode. It also includes a resistance control electrode 111 located on the side of the barrier layer 105 away from the substrate 101, the resistance control electrode 111 being located between the first electrode 109 and the second electrode 110; the resistance control electrode 111 is configured to control the voltage applied thereon to adjust the concentration of two-dimensional electron gas (2DEG) to obtain semiconductor structures with different resistance values.

[0021] The semiconductor structure provided in this disclosure includes a two-dimensional electron gas channel formed by 2DEGs at the interface between the channel layer and the barrier layer. The two-dimensional electron gas channel is electrically connected to the first and second electrodes and has a certain sheet resistance. By setting a resistor control electrode above the barrier layer, the concentration of 2DEGs can be adjusted by controlling the magnitude of the positive and negative voltage applied to it, thereby obtaining a GaN-based integrated platform semiconductor structure with adjustable resistance. Furthermore, the resistor control electrode can be controlled to have a zero potential or be set as a floating electrode, so that the resistor control electrode does not affect the 2DEG channel resistance, and it can shield the influence of the upper layer trace potential of the semiconductor structure on the 2DEGs. Moreover, after the semiconductor structure provided in this disclosure is fabricated, the voltage applied to the resistor control electrode can be changed in real time according to operational needs to adjust the resistance value of the semiconductor structure, thereby increasing the flexibility and functionality of the circuit design.

[0022] In some embodiments, the substrate 101 may be a Si, SiC, GaN, sapphire, diamond, SOI, QST composite substrate, etc., and this disclosure does not limit it.

[0023] In some embodiments, the material of the channel layer 104 may be unintentionally doped GaN.

[0024] In some embodiments, the material of the barrier layer 105 may be one or a combination of AlN and AlGaN.

[0025] Specifically, this disclosure uses GaN as the material for the channel layer 104 and AlGaN as the material for the barrier layer 105 as an example. AlGaN / GaN can form a heterojunction. The AlGaN / GaN heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects. This two-dimensional electron gas is spatially separated from ionized impurities, forming a semiconductor structure with a certain resistance.

[0026] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 1 As shown, it also includes a dielectric layer 107 located on the side of the barrier layer 105 away from the substrate 101, a resistance control electrode 111 located on the side of the dielectric layer 107 away from the substrate 101, and a first electrode 109 and a second electrode 110 located on the side of the dielectric layer 107 away from the substrate 101 and penetrating the dielectric layer 107. That is, the resistance control electrode 111 is deposited on top of the dielectric layer 107, and the material of the dielectric layer 107 can be SiO2, SiNx, AlN, etc.

[0027] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 1As shown, a resistance control electrode 111 is deposited above the barrier layer 105, and the 2DEG concentration can be controlled by potential to realize a 2DEG semiconductor structure with adjustable resistance. The resistance control electrode 111 and the dielectric layer 107 are Schottky contacts.

[0028] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 1 As shown, the first electrode 109 and the second electrode 110 both form ohmic contacts with the 2DEG channel. The first electrode 109 and the second electrode 110 can be metals formed on the plane of the barrier layer 105. That is, the first electrode 109 and the second electrode 110 both contact the surface of the barrier layer 105 away from the substrate 101 through the through hole penetrating the dielectric layer 107.

[0029] In some embodiments, the material of the first electrode 109 may be one or more combinations of Ti, Al, TiN, Si, and Au, and the material of the second electrode 110 may be one or more combinations of Ti, Al, TiN, Si, and Au.

[0030] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 1 As shown, it also includes: a nucleation layer 102 located between the substrate 101 and the channel layer 104, a buffer layer 103 located between the nucleation layer 102 and the channel layer 104, and an isolation layer 108 surrounding the first electrode 109 and the second electrode 110. The isolation layer 108 is used to isolate the 2DEG channel, achieving isolation between different device regions.

[0031] In some embodiments, the material of the nucleation layer 102 may be one or more combinations of AlN, GaN, and AlGaN.

[0032] In some embodiments, the buffer layer 103 may be a C-doped GaN layer with a C concentration between 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Between; the material of the buffer layer 103 can also be a superlattice structure composed of one or more of AlN, AlGaN, and GaN.

[0033] In some embodiments, the isolation layer 108 may be an ion implantation isolation layer, such as an F, B, or P ion implantation isolation layer; it may also be an etched trench isolation layer with an etching depth exceeding the 2DEG channel depth; or it may be a p-GaN cap layer isolation layer. This disclosure does not limit the structure of the isolation layer 108.

[0034] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 1As shown, the area of ​​the resistance control electrode 111 accounts for more than 50% of the area between the first electrode 109 and the second electrode 110. This allows the resistance control electrode 111 to cover most of the area of ​​the two-dimensional electron gas channel 106, which is beneficial for controlling the resistance value. Optionally, the area of ​​the resistance control electrode 111 can account for 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc.

[0035] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figures 1-3 As shown, Figure 2 for Figure 1 A planar schematic diagram of the middle part of the structure. Figure 3 for Figure 1 Another planar schematic diagram of the middle part structure shows that there is one resistor control electrode 111. The resistor control electrode 111 can be a floating electrode, that is, no voltage is applied. In this way, the resistor control electrode 111 does not affect the channel resistance of 2DEG, and the resistor control electrode 111 can shield the influence of the upper layer trace potential of the semiconductor structure on 2DEG.

[0036] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figures 1-3 As shown, the resistor control electrode 111 can be configured to apply voltages of different polarities and / or magnitudes. Specifically, the resistor control electrode 111 can be connected to an external circuit via leads, i.e., positive and negative voltages can be applied through the lead interface. In this way, the resistance value of the desired semiconductor structure can be adjusted by changing the magnitude of the positive or negative voltage applied to the resistor control electrode 111 by the external circuit. Alternatively, a zero bias voltage can be applied to the resistor control electrode 111, so that the resistor control electrode 111 does not affect the 2DEG channel resistance, and the resistor control electrode 111 can shield the influence of the upper layer trace potential of the semiconductor structure on the 2DEG.

[0037] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figures 1-3 As shown, the direction from the first electrode 109 to the second electrode 110 is the first direction X, and the direction perpendicular to the first direction X is the second direction Y. The first direction X and the second direction Y are located in the same plane. like Figure 2 As shown, the resistor control electrode 111 can cover the entire region of the barrier layer 105 extending along the second direction Y between the first electrode 109 and the second electrode 110, or, as... Figure 3 As shown, the resistor-controlled electrode 111 covers a portion of the barrier layer 105 extending along the second direction Y between the first electrode 109 and the second electrode 110. This allows for selection based on operational needs. Figure 2 or Figure 3 The structure shown controls the resistance value by controlling the magnitude of the positive and negative voltage applied to the resistor control electrode 111.

[0038] In some embodiments, the material of the resistance control electrode 111 can be a metal, a conductive semiconductor material, or a combination of a semiconductor material and a metal.

[0039] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 4 As shown, Figure 4 and Figure 1 The structures are basically the same; the difference between the two lies in: Figure 4 The resistance control electrode 111 is located on the side of the dielectric layer 107 away from the substrate 101 and penetrates the dielectric layer 107, that is, the resistance control electrode 111 is deposited directly above the barrier layer 105. The resistance control electrode 111 can be a Schottky contact or an ohmic contact.

[0040] Figure 1 and Figure 4 The working principle of the semiconductor structure shown is as follows: (1) When the voltage on the resistor control electrode 111 is zero bias or the resistor control electrode 111 is a floating electrode, the resistor control electrode 111 does not affect the resistance of the 2DEG channel, that is, the concentration of 2DEG is the initial concentration formed at the heterojunction interface, and the zero bias or floating metal can shield the influence of the upper layer trace potential of the semiconductor structure on 2DEG; (2) Applying a positive voltage to the resistor control electrode 111 can increase the concentration of 2DEG, such as Figure 5 As shown, the resistance of 2DEG is reduced; for resistors that need to be located between the metal resistor and the 2DEG resistor, this disclosure can reduce the area occupied by the series and parallel windings; and the resistance value can be adjusted as needed, increasing the flexibility and functionality of the circuit design; (3) Applying a negative voltage to the resistor control electrode 111 can deplete 2DEG, such as Figure 6 As shown, a 2DEG resistor is added. For scenarios where a large resistor is required for current limiting in the circuit, the prior art requires a 2DEG resistor to be connected in series and wound. However, the present disclosure uses a negative voltage control method on the resistor control electrode 111 above the barrier layer, which can effectively reduce the area waste of the resistor winding. Therefore, the present disclosure can adjust the resistance value in real time by controlling the polarity and magnitude of the voltage applied to the resistor control electrode 111 according to the working needs, which increases the flexibility and functionality of the circuit design.

[0041] The inventors of this disclosure also used TCAD simulation to... Figure 1 The working principle of the semiconductor structure shown was verified. TCAD simulation was performed on a semiconductor structure with a length of 4 μm, as shown... Figure 7As shown, S corresponds to the first electrode 109, and D corresponds to the second electrode 110, meaning the length between D and S is 4 μm. In the middle of the semiconductor structure, there is a 2 μm resistor control electrode 111 (G in the figure). The distance between G and S, and between G and D, is both 1 μm. Thus, the area of ​​the resistor control electrode 111 accounts for 50% of the area between the first electrode 109 and the second electrode 110. The barrier layer 105 has an Al composition of 0.18% and a thickness of 15 nm. The barrier layer 105 uses Al... 0.18 GaN is used as the designation. A 40 nm thick dielectric layer 107 (SiNx) exists between the barrier layer 105 and G. Below the barrier layer 105 is a 200 nm thick channel layer 104, represented by a GaN channel. (The text repeats itself here.) Figure 8 As shown, Figure 8 The curves showing the variation of the 2DEG resistance (R) under G, between GS, and between GD as a function of the voltage (VG) of G are recorded, represented by blue, red, and green lines, respectively. It can be seen that the 2DEG resistance in the area not covered by G does not change with the voltage of G. The 2DEG resistance under G decreases as a positive voltage is applied to VG. When VG increases from 0V to 20V, the resistance decreases by approximately 20%. The 2DEG resistance under G increases significantly as a negative voltage is applied to VG. When VG decreases from 0V to -20V, the resistance increases to five times its original value. Therefore, TCAD simulation verifies that applying a positive voltage to the resistor control electrode 111 can increase the concentration of 2DEG and decrease its resistance; applying a negative voltage to the resistor control electrode 111 can deplete the 2DEG and increase its resistance. This allows for flexible adjustment of the semiconductor structure's resistance value through voltage control, increasing the flexibility and functionality of the circuit design, and achieving high resistance without increasing the layout area, thus reducing the waste area of ​​the resistor winding.

[0042] Specifically, Figure 1 and Figure 4 Both methods control the area of ​​electrode 111 by fixing the resistor and obtain semiconductor structures with different resistance values ​​by changing the voltage on the resistor control electrode 111.

[0043] In some embodiments, in the semiconductor structure provided in the present disclosure, the present disclosure may select and employ the following based on circuit design requirements. Figure 2 The resistors shown can be connected in series or parallel. For example, to obtain a semiconductor structure with a large resistance value, multiple resistors can be used. Figure 2 The resistors shown are connected in series to form Figure 9The multi-resistor series structure shown can be used to isolate the two-dimensional electron gas channel into multiple strip regions using a structure similar to the isolation layer 108. The beginning and end of each strip region are connected sequentially through the first electrode 109 and the second electrode 110. In this way, a whole piece of resistor control electrode 111 can be deposited on the entire two-dimensional electron gas channel, or resistor control electrode 111 can be deposited separately on each strip region of the two-dimensional electron gas channel.

[0044] In some embodiments, in the semiconductor structure provided in the present disclosure, the present disclosure may select and employ the following based on circuit design requirements. Figure 2 The resistors shown can be connected in series or parallel. For example, to obtain a semiconductor structure with a low resistance value, multiple resistors can be used. Figure 2 The resistors shown are connected in parallel to form Figure 10 The diagram shows a parallel structure of multiple resistors. In this case, the two-dimensional electron gas channel can be divided into multiple strip-shaped regions using a structure similar to the isolation layer 108. One end of each strip-shaped region is electrically connected to the same first electrode 109, and the other end of each strip-shaped region is electrically connected to the same second electrode 110. Specifically, as shown... Figure 11 and Figure 12 As shown, a single resistive control electrode 111 can be deposited above the entire two-dimensional electron gas channel, i.e. Figure 11 and Figure 12 A resistor control electrode 111 is drawn out from the middle; such as Figure 13 As shown, metal electrodes can also be deposited individually on each strip region of the two-dimensional electron gas channel, i.e. Figure 13 Multiple metal electrodes are drawn out in parallel to form a resistance control electrode 111.

[0045] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 11 As shown, the resistor control electrode 111 can cover the entire area of ​​each strip region of the two-dimensional electron gas channel extending along the second direction Y; as Figure 12 As shown, the resistor control electrode 111 can cover a portion of the outermost two strip regions of the two-dimensional electron gas channel extending along the second direction Y.

[0046] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 14 and Figure 15 As shown, Figure 14 This is another cross-sectional schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 15 for Figure 14 A planar schematic diagram of the middle part of the structure. Figure 14 and Figure 1 The structures are basically the same; the difference between the two lies in: Figure 14In the direction from the first electrode 109 to the second electrode 110, that is, along the first direction X, the number of resistor control electrodes 111 is at least two that are spaced apart. Each resistor control electrode can be a floating electrode; or, each resistor control electrode can be connected to an external circuit through different leads, at least one resistor control electrode is configured to apply a voltage, and each resistor control electrode is configured to apply the same voltage.

[0047] Specifically, such as Figure 14 and Figure 15 As shown, this embodiment of the present disclosure takes a first resistance control electrode 111a and a second resistance control electrode 111b as an example. The first resistance control electrode 111a and the second resistance control electrode 111b are deposited above the dielectric layer 107. The areas of the first resistance control electrode 111a and the second resistance control electrode 111b can be the same or different. This embodiment of the present disclosure takes an example where the area of ​​the first resistance control electrode 111a is smaller than the area of ​​the second resistance control electrode 111b. When it is not necessary to adjust the resistance value of the device, the first resistance control electrode 111a and the second resistance control electrode 111b can be floating electrodes, i.e., no voltage is applied, or a zero bias voltage is applied to the first resistance control electrode 111a and the second resistance control electrode 111b. In this way, the first resistance control electrode 111a and the second resistance control electrode 111b do not affect the 2DEG channel resistance, and the first resistance control electrode 111a and the second resistance control electrode 111b can shield the influence of the upper layer trace potential of the semiconductor structure on the 2DEG. When it is necessary to adjust the resistance value of the device in real time, voltage can be applied only to the first resistance control electrode 111a, or only to the second resistance control electrode 111b, or the same voltage can be applied to both the first resistance control electrode 111a and the second resistance control electrode 111b, so that the area of ​​the resistance control electrode covering the barrier layer 105 is different, thereby obtaining different resistance values.

[0048] In some embodiments, in the semiconductor structure provided in the present disclosure, such as Figure 16 As shown, Figure 16 and Figure 14 The structures are basically the same; the difference between the two lies in: Figure 16 The first resistance control electrode 111a and the second resistance control electrode 111b are located on the side of the dielectric layer 107 away from the substrate 101 and penetrate the dielectric layer 107, that is, the first resistance control electrode 111a and the second resistance control electrode 111b are directly deposited above the barrier layer 105.

[0049] Specifically, Figure 14 and Figure 16Both methods involve fixing the voltage on each resistor control electrode and changing the number of resistor control electrodes by varying the applied voltage to obtain semiconductor structures with different resistance values.

[0050] In some embodiments, the first electrode 109 and the second electrode 110 in the semiconductor structure provided in this disclosure are not limited to... Figure 1 , Figure 4 , Figure 14 and Figure 16 The first electrode 109 and the second electrode 110 are in contact with the surface of the barrier layer 105. They can also be metals deposited in the grooves of the etched barrier layer 105, that is, the first electrode 109 and the second electrode 110 also penetrate the barrier layer 105.

[0051] To better understand the semiconductor structure provided in the embodiments of this disclosure, this disclosure uses... Figure 1 Taking the semiconductor structure shown as an example, the fabrication process of the semiconductor structure will be explained in detail.

[0052] In some embodiments, Figure 1 The fabrication process of the semiconductor structure shown may specifically include the following steps: (1) such as Figure 17 As shown, a nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105 are epitaxially grown on a substrate 101 using methods such as MOCVD.

[0053] (2) For example Figure 18 As shown, a medium layer 107 is deposited above the barrier layer 105.

[0054] (3) such as Figure 19 As shown, photolithography defines the first electrode and second electrode regions at both ends of the semiconductor structure, etching the dielectric layer 107 of the first electrode and second electrode regions, depositing metal and annealing to form the first electrode 109 and the second electrode 110 of the ohmic contact.

[0055] (4) such as Figure 20 As shown, an isolation layer 108 is formed around the first electrode 109 and the second electrode 110 by ion implantation, or by etching the dielectric layer 107, the barrier layer 105 and part of the channel layer 104 to form a groove, which is then filled to form the isolation layer 108 when other media are deposited later.

[0056] (5) such as Figure 21 As shown, photolithography defines the region and size of the resistance control electrode, and then metal is deposited in the region to form the resistance control electrode 111.

[0057] Therefore, through the above steps (1)-(5), a process is formed. Figure 1 The semiconductor structure shown.

[0058] Based on the same inventive concept, this disclosure provides an integrated circuit including the semiconductor structure described above. Since the principle by which this integrated circuit solves the problem is similar to that of the semiconductor structure described above, the implementation of the integrated circuit provided in this disclosure can refer to the implementation of the semiconductor structure described above, and repeated details will not be repeated.

[0059] In some embodiments, the integrated circuits provided in this disclosure may further include high electron mobility transistors, diodes, or capacitors, etc., and this disclosure does not limit them.

[0060] Based on the same inventive concept, this disclosure provides an electronic device including the integrated circuit described above. Since the principle by which this electronic device solves the problem is similar to that of the integrated circuit described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the integrated circuit described above, and repeated details will not be elaborated further.

[0061] In some embodiments, the electronic device provided in this disclosure may further include a circuit board, on which an integrated circuit is disposed.

[0062] In some embodiments, the electronic device provided in this disclosure can be different types of user equipment or terminal equipment such as a computer, mobile phone, tablet computer, wearable device, and vehicle-mounted device; the electronic device can also be a network device such as a base station. The disclosed embodiments do not impose special limitations on the specific form of the electronic device.

[0063] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0064] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, a channel layer located on one side of the substrate, and a barrier layer located on the side of the channel layer away from the substrate; It also includes a first electrode and a second electrode disposed on both sides of the barrier layer, both of which are electrically connected to the channel layer; It also includes a resistance control electrode located on the side of the barrier layer away from the substrate, the resistance control electrode being located between the first electrode and the second electrode.

2. The semiconductor structure as described in claim 1, characterized in that, The area of ​​the resistance control electrode accounts for more than 50% of the area between the first electrode and the second electrode.

3. The semiconductor structure as described in claim 1, characterized in that, The number of resistor control electrodes is one, the resistor control electrode is a floating electrode, or the resistor control electrode is configured to apply voltages of different polarities and / or different magnitudes.

4. The semiconductor structure as described in claim 3, characterized in that, The direction from the first electrode to the second electrode is the first direction, and the direction perpendicular to the first direction is the second direction. The first direction and the second direction are located in the same plane. The resistance control electrode covers the entire area of ​​the barrier layer between the first electrode and the second electrode extending along the second direction, or the resistance control electrode covers a portion of the area of ​​the barrier layer between the first electrode and the second electrode extending along the second direction.

5. The semiconductor structure as described in claim 1, characterized in that, Along the direction from the first electrode to the second electrode, the number of the resistance control electrodes is at least two that are spaced apart; Each of the resistor control electrodes is a floating electrode; or, each of the resistor control electrodes is connected to an external circuit via different leads, at least one of the resistor control electrodes is configured to be loaded with a voltage, and each of the resistor control electrodes is configured to be loaded with the same voltage.

6. The semiconductor structure as described in claim 1, characterized in that, It also includes a dielectric layer located on the side of the barrier layer away from the substrate, the resistance control electrode being located on the side of the dielectric layer away from the substrate, and the first electrode and the second electrode being located on the side of the dielectric layer away from the substrate and penetrating the dielectric layer.

7. The semiconductor structure as described in claim 1, characterized in that, It also includes a dielectric layer located on the side of the barrier layer away from the substrate, wherein the first electrode, the second electrode, and the resistance control electrode are located on the side of the dielectric layer away from the substrate and penetrate the dielectric layer.

8. The semiconductor structure as described in claim 6 or 7, characterized in that, The first electrode and the second electrode are in contact with the surface of the barrier layer away from the substrate, or the first electrode and the second electrode also penetrate the barrier layer.

9. The semiconductor structure as described in claim 1, characterized in that, Also includes: The nucleation layer is located between the substrate and the channel layer, the buffer layer is located between the nucleation layer and the channel layer, and the isolation layer is disposed around the periphery of the first electrode and the second electrode.

10. An integrated circuit, characterized in that, Including the semiconductor structure as described in any one of claims 1-9.

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