PMUT array ultrasonic transceiver circuit system

Abstract

The invention discloses a PMUT array ultrasonic transceiver circuit system, and relates to the technical field of electronic circuits and systems, and the system comprises a GPU processing module, an FPGA main control module and an ultrasonic analog circuit. The GPU processing module generates an optimal array element gating matrix by using an array element gating matrix generation model; the FPGA main control module drives the ultrasonic analog circuit to perform time-sharing gating on the transmitting array element and the receiving array element according to the optimal array element gating matrix; performing phase control excitation on the transmitting array element when the transmitting array element is gated; performing beam forming on the processed ultrasonic echo signal when the receiving array element is gated; the ultrasonic analog circuit performs time-sharing gating on the transmitting array element and the receiving array element, and generates a high-voltage pulse when the transmitting array element is gated; ultrasonic echo signals are collected and processed when the receiving array elements are gated; and the GPU processing module performs three-dimensional image reconstruction according to the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image. According to the invention, the imaging speed and resolution are improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuits and systems, and in particular to a PMUT array ultrasonic transceiver circuit system. Background Technology

[0002] With the emergence and rapid development of Micro-Electro-Mechanical Systems (MEMS), a new generation of piezoelectric micromachined ultrasonic transducers (PMUTs) has begun to appear. Compared with traditional piezoelectric transducers, PMUTs have advantages such as miniaturization, high sensitivity, no need for bias voltage, and ease of array integration. However, realizing real-time transmission and reception of two-dimensional multi-channel ultrasonic signals remains a major challenge in the research and application of PMUT devices. Most existing PMUT array ultrasonic transceiver circuits use row and column addressing scanning methods, which suffer from slow imaging speed and low image resolution.

[0003] Therefore, there is an urgent need for a PMUT array ultrasonic transceiver circuit system to solve the above problems. Summary of the Invention

[0004] The purpose of this application is to provide a PMUT array ultrasonic transceiver circuit system that improves imaging speed and resolution.

[0005] To achieve the above objectives, this application provides the following solution:

[0006] This application provides a PMUT array ultrasonic transceiver circuit system, which includes: a GPU processing module, an FPGA main control module, and an ultrasonic simulation circuit.

[0007] The GPU processing module and the ultrasonic simulation circuit are both connected to the FPGA main control module, and the ultrasonic simulation circuit is connected to the PMUT array.

[0008] The GPU processing module is used to generate an optimal element gating matrix based on the number of array elements required for imaging, using an element gating matrix generation model, and then send the optimal element gating matrix to the FPGA main control module. The element gating matrix generation model is obtained by training a neural network model using a training dataset. The training dataset includes: the number of sample array elements required for imaging and the corresponding optimal element gating matrix for the sample.

[0009] The FPGA main control module is used for:

[0010] Based on the optimal array element gating matrix, the ultrasonic analog circuit is driven to perform time-division gating of the transmitting and receiving array elements in the PMUT array;

[0011] When gating the transmitting array elements, phase-controlled excitation is performed on the transmitting array elements according to the optimal array element gating matrix;

[0012] When the receiving array element is selected, the processed ultrasonic echo signal is beamformed to obtain the synthesized ultrasonic echo signal.

[0013] The ultrasonic simulation circuit is used for:

[0014] Time-division gating is performed on the transmit and receive elements in the PMUT array;

[0015] When the transmitting element is selected, a high-voltage pulse is generated to excite the PMUT array to generate ultrasonic waves;

[0016] When the receiving array element is selected, the corresponding ultrasonic echo signal is collected and processed to obtain the processed ultrasonic echo signal.

[0017] The GPU processing module is also used to perform three-dimensional image reconstruction based on the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image.

[0018] Optionally, the GPU processing module includes: a neural network processing unit and a three-dimensional image reconstruction unit;

[0019] The neural network processing unit is connected to the FPGA main control module. The neural network processing unit is used to generate the optimal array element gating matrix according to the number of array elements required for imaging, using the array element gating matrix generation model, and send the optimal array element gating matrix to the FPGA main control module.

[0020] The three-dimensional image reconstruction unit is connected to the FPGA main control module. The three-dimensional image reconstruction unit is used to reconstruct a three-dimensional image based on the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image.

[0021] Optionally, the FPGA main control module includes: an array element selection control unit, a transmit beam combining unit, and a receive beam combining unit;

[0022] The array element selection control unit is connected to the neural network processing unit. The array element selection control unit is used to drive the ultrasonic simulation circuit to perform time-division gating of the transmitting array elements and receiving array elements in the PMUT array according to the optimal array element gating matrix.

[0023] The transmit beamforming unit is connected to the neural network processing unit. The transmit beamforming unit is used to perform phase-controlled excitation on the transmit array elements according to the optimal array element selection matrix when the transmit array elements are selected.

[0024] The receiving beamforming unit is connected to the ultrasonic analog circuit. The receiving beamforming unit is used to perform beamforming on the processed ultrasonic echo signal when the receiving array element is selected, so as to obtain the synthesized ultrasonic echo signal.

[0025] Optionally, the ultrasonic simulation circuit includes: a multiplexer, a transmitting circuit, and a receiving circuit;

[0026] The multiplexer is connected to the array element selection control unit and the PMUT array respectively. Under the control of the array element selection control unit, the multiplexer is used to connect the corresponding transmitting array element to the transmitting circuit to achieve the selection of the transmitting array element in the PMUT array, and to connect the corresponding receiving array element to the receiving circuit to achieve the selection of the receiving array element in the PMUT array.

[0027] The transmitting circuit is connected to the multiplexer and the transmitting beamforming unit respectively, and is used to generate a high voltage pulse when the transmitting array element is selected, so as to excite the PMUT array to generate ultrasonic waves.

[0028] The receiving circuit is connected to the multiplexer and the receiving beamforming unit respectively, and is used to acquire and process the corresponding ultrasonic echo signal when the receiving array element is selected, so as to obtain the processed ultrasonic echo signal.

[0029] Optionally, the transmitting circuit is a single-chip or multi-chip high-voltage pulse generator; the receiving circuit is an ultrasonic analog front-end chip.

[0030] Optionally, the receiving circuit includes: a low-noise amplifier, an analog low-pass filter, an attenuator, a digital time gain compensator, and an ADC;

[0031] The low-noise amplifier is connected to the multiplexer, and the low-noise amplifier is used to amplify the multiple ultrasonic echo signals to obtain amplified ultrasonic echo signals.

[0032] The analog low-pass filter is connected to the low-noise amplifier. The analog low-pass filter is used to perform low-pass filtering on the amplified ultrasonic echo signal to obtain the filtered ultrasonic echo signal.

[0033] The attenuator is connected to the analog low-pass filter, and the attenuator is used to attenuate the filtered ultrasonic echo signal to obtain the attenuated ultrasonic echo signal.

[0034] The digital time gain compensator is connected to the attenuator. The digital time gain compensator is used to perform time gain compensation on the attenuated ultrasonic echo signal to obtain the compensated ultrasonic echo signal.

[0035] The ADC is connected to the digital time gain compensator, and the ADC is used to sample the compensated ultrasonic echo signal to obtain the processed ultrasonic echo signal.

[0036] Optionally, the ultrasonic echo signal processed by the receiving circuit and the receiving beamforming unit is transmitted using a high-speed serial interface LVDS or the JEDEC JESD204B protocol.

[0037] Optionally, the FPGA main control module further includes: a power supply unit and a clock circuit;

[0038] The power supply unit is connected to the array element selection control unit, the transmit beamforming unit and the receive beamforming unit respectively, and is used to provide the required four independent power supplies to the array element selection control unit, the transmit beamforming unit and the receive beamforming unit;

[0039] The clock circuit is connected to the array element selection control unit, the transmit beamforming unit, the receive beamforming unit, and the receiving circuit, respectively, and is used to provide differential clock signals to the array element selection control unit, the transmit beamforming unit, the receive beamforming unit, and the receiving circuit.

[0040] Optionally, the FPGA main control module further includes: a DDR memory unit and a storage unit;

[0041] The DDR memory unit is connected to the array element selection control unit, the transmit beamforming unit and the receive beamforming unit respectively, and is used to provide data cache space for the operation of the array element selection control unit, the transmit beamforming unit and the receive beamforming unit;

[0042] The storage unit is connected to the receiving circuit and the receiving beamforming unit respectively, and is used to store the ultrasonic echo signal and the processed ultrasonic echo signal.

[0043] Optionally, the GPU processing module and the FPGA main control module are connected via a PCIe interface.

[0044] According to the specific embodiments provided in this application, this application has the following technical effects:

[0045] This application discloses a PMUT array ultrasonic transceiver circuit system, including a GPU processing module, an FPGA main control module, and an ultrasonic simulation circuit. The GPU processing module generates a transmit-receive sequence (i.e., the optimal element gating matrix) using an element gating matrix generation model to drive the gating of transmit and receive elements in the PMUT array, replacing row-column addressing element control and improving imaging speed and resolution. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the functional modules of a PMUT array ultrasonic transceiver circuit system in one embodiment of this application;

[0048] Figure 2 A neural network block diagram provided in one embodiment of this application;

[0049] Figure 3 This is a schematic diagram of the system algorithm processing flow provided in an embodiment of this application.

[0050] Figure label:

[0051] GPU processing module 1, neural network processing unit 11, 3D image reconstruction unit 12, FPGA main control module 2, array element selection control unit 21, transmit beamforming unit 22, receive beamforming unit 23, power supply unit 24, clock circuit 25, DDR memory unit 26, ultrasonic analog circuit 3, multiplexer 31, transmit circuit 32, receive circuit 33. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] In one exemplary embodiment, such as Figure 1As shown, a PMUT (Piezoelectric Micromachined Ultrasonic Transducers) array ultrasonic transceiver circuit system is provided, including: a GPU processing module 1, an FPGA main control module 2, and an ultrasonic simulation circuit 3.

[0055] Both the GPU processing module 1 and the ultrasonic simulation circuit 3 are connected to the FPGA main control module 2, and the ultrasonic simulation circuit 3 is connected to the PMUT array.

[0056] The GPU processing module 1 is used to generate the optimal array element gating matrix based on the number of array elements required for imaging using the array element gating matrix generation model, and send the optimal array element gating matrix to the FPGA main control module 2; the array element gating matrix generation model is obtained by training a neural network model using a training dataset; the training dataset includes: the number of sample array elements required for imaging and the corresponding optimal array element gating matrix for the sample.

[0057] Specifically, two-dimensional PMUT array transducers are used for three-dimensional volumetric imaging. Compared with traditional PZT linear probes, they are limited by the low sensitivity of a single PMUT element. Furthermore, the multi-element transmission and reception beamforming of the PMUT generates a large amount of echo signal data, posing a significant challenge to the system's computational performance and making real-time imaging difficult. To overcome these limitations, this application adopts a spatially coded transmission and reception scheme based on neural networks. Through extensive training data, the optimal ultrasonic transmission and reception sequence pattern under specific PMUT array and hardware conditions is learned. Compared with traditional physical model-based methods, neural networks can better adapt to complex and variable imaging, improving imaging quality and diagnostic accuracy.

[0058] like Figure 2 As shown, the input to the array element gating matrix generation model is the number of array elements required for imaging, ranging from 1 to L, for example, 1 to 256. The output is the optimal transmission and reception array element distribution for imaging (i.e., the optimal array element gating matrix), for example, an N*N two-dimensional Boolean matrix, where 0 represents an ungated array element and 1 represents a gated array element. Generating an N*N optimal array element gating matrix through the array element gating matrix generation model replaces the row-column addressing method for transmission and reception array element gating, improving imaging speed and the signal-to-noise ratio of the ultrasonic echo signal. Using Hadamard coefficients generated by a neural network to orthogonally constrain the encoding matrix output by the neural network, and using the encoding matrix to spatially encode the transmission array elements while spatially decoding the Hadamard coefficients of the reception array elements, can further improve the signal-to-noise ratio. Furthermore, the GPU processing module 1 transmits the optimal array element gating matrix to the FPGA main control module 2 via the PCIe bus.

[0059] The FPGA main control module 2 is used to: drive the ultrasonic analog circuit 3 to perform time-division gating of the transmitting array elements and receiving array elements in the PMUT array according to the optimal array element gating matrix; when the transmitting array elements are gating, perform phase-controlled excitation on the transmitting array elements according to the optimal array element gating matrix; when the receiving array elements are gating, perform beamforming on the processed ultrasonic echo signal to obtain the synthesized ultrasonic echo signal.

[0060] The ultrasonic simulation circuit 3 is used to: perform time-division multiplexing of the transmitting and receiving elements in the PMUT array; when the transmitting element is selected, a high-voltage pulse is generated to excite the PMUT array to generate ultrasonic waves; when the receiving element is selected, the corresponding ultrasonic echo signal is acquired and processed to obtain the processed ultrasonic echo signal.

[0061] The GPU processing module 1 is also used to perform three-dimensional image reconstruction based on the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image.

[0062] As an optional implementation method, such as Figure 1 As shown, the GPU processing module 1 includes a neural network processing unit 11 and a three-dimensional image reconstruction unit 12.

[0063] The neural network processing unit 11 is connected to the FPGA main control module 2. The neural network processing unit 11 is used to generate the optimal array element gating matrix according to the number of array elements required for imaging, using the array element gating matrix generation model, and send the optimal array element gating matrix to the FPGA main control module 2.

[0064] The three-dimensional image reconstruction unit 12 is connected to the FPGA main control module 2. The three-dimensional image reconstruction unit 12 is used to reconstruct a three-dimensional image based on the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image.

[0065] Specifically, the FPGA main control module 2 transmits the synthesized ultrasonic echo signal to the GPU processing module 1 via the PCIe bus. Digital beamforming is executed in parallel by the GPU's stream processing unit (i.e., the 3D image reconstruction unit 12), using a pipelined design to improve the real-time performance of the computation. Figure 3As shown, the 3D image reconstruction process includes: dynamic focusing, amplitude apodization, dynamic receiving aperture, and orthogonal demodulation detection. Dynamic focusing applies coarse and fine delays to the synthesized ultrasonic echo signal to achieve focused reception. Amplitude apodization assigns weighting coefficients to the synthesized ultrasonic echo signal of each receiving element to suppress sidelobes. Dynamic receiving aperture dynamically changes the number of receiving elements on both sides of the PMUT center element to ensure uniform main lobe widths in the near and far fields, achieving identical imaging resolution in both fields. Orthogonal demodulation detection copies the synthesized ultrasonic echo signal into two paths, multiplies them by a sine and a cosine signal with a 90-degree phase difference, respectively, and then applies an FIR low-pass filter to generate two baseband signals. These baseband signals are then obtained by summing the squares and taking the square root, resulting in the envelope signal corresponding to the synthesized ultrasonic echo signal. Finally, the envelope signal is scanned and transformed to obtain a 3D ultrasonic image, which is then transmitted to a host computer for display via PCIe.

[0066] As an optional implementation method, such as Figure 1 As shown, the FPGA main control module 2 includes: an array element selection control unit 21, a transmit beam combining unit 22, and a receive beam combining unit 23.

[0067] The array element selection control unit 21 is connected to the neural network processing unit 11. The array element selection control unit 21 is used to drive the ultrasonic simulation circuit 3 to perform time-division gating of the transmitting array elements and receiving array elements in the PMUT array according to the optimal array element gating matrix.

[0068] The transmit beamforming unit 22 is connected to the neural network processing unit 11. The transmit beamforming unit 22 is used to perform phase-controlled excitation on the transmit array elements according to the optimal array element selection matrix when the transmit array elements are selected.

[0069] The receiving beamforming unit 23 is connected to the ultrasonic analog circuit 3. The receiving beamforming unit 23 is used to perform beamforming on the processed ultrasonic echo signal when the receiving array element is selected, so as to obtain the synthesized ultrasonic echo signal.

[0070] As an optional implementation method, such as Figure 1 As shown, the FPGA main control module 2 also includes: a power supply unit 24, a clock circuit 25, a DDR (Double Data Rate SDRAM) memory unit 26, and a storage unit (not shown in the figure).

[0071] The power supply unit 24 is connected to the array element selection control unit 21, the transmit beamforming unit 22, and the receive beamforming unit 23, respectively, and is used to provide the array element selection control unit 21, the transmit beamforming unit 22, and the receive beamforming unit 23 with the required four independent power supplies, namely 1.0V, 1.5V, 1.8V, and 3.3V, respectively, and uses a high-efficiency DC / DC chip to meet the requirements of high current power supply.

[0072] The clock circuit 25 is connected to the array element selection control unit 21, the transmit beamforming unit 22, the receive beamforming unit 23 and the receive circuit 33 respectively, and is used to provide differential clock signals to the array element selection control unit 21, the transmit beamforming unit 22, the receive beamforming unit 23 and the receive circuit 33, that is, to provide a stable, low-jitter differential clock.

[0073] The DDR memory unit 26 is connected to the array element selection control unit 21, the transmit beamforming unit 22 and the receive beamforming unit 23 respectively, and is used to provide data cache space for the operation of the array element selection control unit 21, the transmit beamforming unit 22 and the receive beamforming unit 23.

[0074] The storage unit is connected to the receiving circuit 33 and the receiving beamforming unit 23, respectively, and is used to store ultrasonic echo signals and processed ultrasonic echo signals. The storage unit includes an SD card and a FLASH memory. The SD card provides a large storage capacity for local storage of the ultrasonic echo signals, and the FLASH memory is used for program storage of the FPGA.

[0075] As an optional implementation method, such as Figure 1 As shown, the ultrasonic simulation circuit 3 includes: a multiplexer 31, a transmitting circuit 32, and a receiving circuit 33.

[0076] The multiplexer 31 is connected to the array element selection control unit 21 and the PMUT array respectively. Under the control of the array element selection control unit 21, the multiplexer 31 is used to connect the corresponding transmitting array element to the transmitting circuit 32 to realize the selection of the transmitting array element in the PMUT array, and to connect the corresponding receiving array element to the receiving circuit 33 to realize the selection of the receiving array element in the PMUT array.

[0077] Specifically, the multiplexer 31 acts as a crucial switch, connecting the transmitting circuit 32 and the receiving circuit 33 to specific elements in the PMUT array based on control signals from the FPGA main control module 2. During the transmission phase, the multiplexer 31 connects the corresponding transmitting elements to the transmitting circuit 32 according to the transmission sequence provided by the FPGA. During the reception phase, the multiplexer 31 connects the elements receiving the ultrasonic echo to the receiving circuit 33 according to the reception sequence. This time-division multiplexing method ensures smooth transmission and reception while avoiding interference between the transmitted and received signals.

[0078] The transmitting circuit 32 is connected to both the multiplexer 31 and the transmitting beamforming unit 22, and is used to generate a high-voltage pulse when the transmitting array element is selected, so as to excite the PMUT array to generate ultrasonic waves. The transmitting circuit 32 is a single-chip or multi-chip high-voltage pulse generator.

[0079] The receiving circuit 33 is connected to both the multiplexer 31 and the receiving beamforming unit 23, and is used to acquire and process the corresponding ultrasonic echo signal when the receiving array element is selected, to obtain the processed ultrasonic echo signal. The receiving circuit 33 is an ultrasonic analog front end (AFE) chip.

[0080] Specifically, when the transmitting circuit 32 applies a voltage between the top and bottom electrodes of the PMUT piezoelectric film, the film bends and deforms due to the inverse piezoelectric effect, causing the PMUT to generate periodic alternating upward and downward bending vibrations, while simultaneously emitting ultrasonic waves. When the PMUT operates in receiving mode, the piezoelectric film bends and deforms under the drive of sound pressure, forming a potential difference between the top and bottom electrodes. The receiving circuit 33 samples and processes the electrical signal output by the PMUT to complete the reception of the ultrasonic echo signal.

[0081] As an optional implementation, the receiving circuit 33 includes: a low-noise amplifier, an analog low-pass filter, an attenuator, a digital time gain compensator, and an ADC.

[0082] The low-noise amplifier is connected to the multiplexer 31. The low-noise amplifier is used to amplify multiple ultrasonic echo signals to obtain amplified ultrasonic echo signals.

[0083] The analog low-pass filter is connected to the low-noise amplifier. The analog low-pass filter is used to perform low-pass filtering on the amplified ultrasonic echo signal to obtain the filtered ultrasonic echo signal.

[0084] The attenuator is connected to the analog low-pass filter, and the attenuator is used to attenuate the filtered ultrasonic echo signal to obtain the attenuated ultrasonic echo signal.

[0085] The digital time gain compensator is connected to the attenuator. The digital time gain compensator is used to perform time gain compensation on the attenuated ultrasonic echo signal to obtain the compensated ultrasonic echo signal.

[0086] The ADC is connected to the digital time gain compensator, and the ADC is used to sample the compensated ultrasonic echo signal to obtain the processed ultrasonic echo signal.

[0087] Specifically, the ultrasonic simulation circuit 3 uses a high-voltage pulse generator integrated chip based on the acoustic parameters (center frequency) and electrical parameters (impedance, excitation voltage) of the PMUT transducer. This chip integrates multiple channels of bipolar square wave pulses, supports on-chip beamforming, has a phase delay at the nanosecond level, a maximum peak-to-peak excitation voltage of ±100V, and a built-in transmit / receive switch (T / R), allowing for easy integration with the receiver circuit 33. Depending on the number of PMUT array elements, the transmitter circuit 32 selects a single or multiple high-voltage pulse generator. The output port of the transmitter circuit 32 is an SMA coaxial connector, connected to the PMUT array via a 50Ω coaxial cable. The FPGA main control module 2 initializes and configures the high-voltage pulse generator via the SPI bus, and uses the IO ports of the FPGA main control module 2 to control the nanosecond-level delay of the transmitted pulses.

[0088] The ultrasonic echo signal received by the receiving circuit 33 is relatively weak, typically in the range of μV to mV, and is easily affected by noise. Therefore, the receiving signal chain should include a low-noise amplifier, an anti-aliasing filter, and a high-precision ADC. Secondly, the ultrasonic echo attenuates with increasing propagation distance, resulting in lower amplitude echo signals at distant points. Therefore, depth-dependent signal amplification adjustment should be implemented using a time gain compensation (TGC) circuit. Furthermore, the receiving circuit 33 has an adjustable input impedance for impedance matching with the transducer. Finally, the ultrasonic echo signal is stronger near the transducer and has lower amplitude at distant points, resulting in a large dynamic range for the ultrasonic signal. The receiving circuit 33 should be able to handle echo signals with a high dynamic range.

[0089] Based on the echo signal amplitude, frequency, and imaging depth of the PMUT, the receiving circuit 33 uses an ultrasonic analog front-end chip, which integrates a low-noise amplifier, analog low-pass filter, attenuator, digital time gain compensator, and 14-bit ADC. This chip enables multi-channel parallel ultrasonic echo signal amplification, low-pass filtering, time gain compensation, and sampling. The analog front-end has a receiving signal bandwidth of 10kHz to 25MHz, making it ideal for acquiring echo signals from the PMUT array. The FPGA initializes and configures the ultrasonic AFE via the SPI bus. The FPGA main control module 2 and the AFE use a high-speed serial interface LVDS or the JEDEC JESD204B protocol for transmitting sampled data, achieving a single-channel data transmission rate of 1Gbps.

[0090] Multiplexer 31 controls the selection of array elements and transmit / receive channels of PMUT array, so that a pair of transmit / receive channels can connect to multiple array elements, realizing the function of driving two-dimensional PMUT array with a small number of transmit / receive channels.

[0091] The FPGA main control module 2 drives the multiplexer 31 to select the transmitting and receiving array elements. The FPGA main control module 2 controls the high-voltage pulse generator to perform phase-controlled excitation on the transmitting selected array element, and the FPGA main control module 2 controls the ultrasonic simulation front end to amplify, filter, compensate for time gain, and sample the ultrasonic echo signal of the receiving selected array element in multiple parallel channels. The echo data quantized by the ADC is transmitted to the FIFO of the FPGA (located in the receiving beamforming unit 23 of the FPGA) through a high-speed serial interface for further three-dimensional ultrasonic image reconstruction.

[0092] As an optional implementation, to meet the high-bandwidth data interaction requirements between the FPGA main control module 2 and the GPU processing module 1, the GPU processing module 1 and the FPGA main control module 2 are connected via a high-speed PCIe (Peripheral Component Interconnect Express) interface. The ultrasound imaging system transmits data to the host computer via wired and wireless communication interfaces, including Ethernet, USB 3.0, and Wi-Fi.

[0093] The beneficial effects of this application are:

[0094] To meet the control and computational requirements of multi-channel PMUT ultrasonic transceiver circuits, the PMUT array ultrasonic transceiver circuit system of this application has the advantages of high performance, high integration, and high signal-to-noise ratio.

[0095] 1) Use the FPGA main control module 2 to drive the receiving circuit 33 for high-speed signal acquisition and parallel ultrasonic signal processing, giving full play to the advantages of the FPGA's good real-time performance.

[0096] 2) The transmit / receive sequence is generated using the array element gating matrix generation model in GPU processing module 1 to drive the PMUT array, replacing the row-column addressing array element control and improving imaging speed and resolution. The transmit / receive sequence and 3D ultrasound image reconstruction and processing are generated using the array element gating matrix generation model, leveraging the advantages of GPU high-performance computing.

[0097] 3) A spatially encoded transmit-receive scheme using GPU processing module 1, through coherent composite algorithms, can improve the signal-to-noise ratio of the echo signal from the two-dimensional PMUT array and increase the imaging frame rate. Digital beamforming and high-resolution ultrasound image reconstruction are performed in GPU processing module 1 to achieve high frame rate and high-quality ultrasound imaging of the PMUT array.

[0098] 4) The use of an integrated chip with an integrated multi-channel ultrasonic signal chain improves the system's integration and signal-to-noise ratio.

[0099] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A PMUT array ultrasonic transceiver circuit system, characterized in that, The PMUT array ultrasonic transceiver circuit system includes: a GPU processing module, an FPGA main control module, and an ultrasonic simulation circuit. The GPU processing module and the ultrasonic simulation circuit are both connected to the FPGA main control module, and the ultrasonic simulation circuit is connected to the PMUT array. The GPU processing module is used to generate an optimal element gating matrix based on the number of array elements required for imaging, using an element gating matrix generation model, and then send the optimal element gating matrix to the FPGA main control module. The element gating matrix generation model is obtained by training a neural network model using a training dataset. The training dataset includes: the number of sample array elements required for imaging and the corresponding optimal element gating matrix for the sample. The FPGA main control module is used for: Based on the optimal array element gating matrix, the ultrasonic analog circuit is driven to perform time-division gating of the transmitting and receiving array elements in the PMUT array; When selecting the transmitting array elements, phase-controlled excitation is performed on the transmitting array elements according to the optimal array element selection matrix; When the receiving array element is selected, the processed ultrasonic echo signal is beamformed to obtain the synthesized ultrasonic echo signal. The ultrasonic simulation circuit is used for: Time-division gating is performed on the transmit and receive elements in the PMUT array; When the transmitting element is selected, a high-voltage pulse is generated to excite the PMUT array to generate ultrasonic waves; When the receiving array element is selected, the corresponding ultrasonic echo signal is acquired and processed to obtain the processed ultrasonic echo signal. The GPU processing module is also used to perform three-dimensional image reconstruction based on the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image.

2. The PMUT array ultrasonic transceiver circuit system according to claim 1, characterized in that, The GPU processing module includes: a neural network processing unit and a three-dimensional image reconstruction unit; The neural network processing unit is connected to the FPGA main control module. The neural network processing unit is used to generate the optimal array element gating matrix according to the number of array elements required for imaging, using the array element gating matrix generation model, and send the optimal array element gating matrix to the FPGA main control module. The three-dimensional image reconstruction unit is connected to the FPGA main control module. The three-dimensional image reconstruction unit is used to reconstruct a three-dimensional image based on the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image.

3. The PMUT array ultrasonic transceiver circuit system according to claim 2, characterized in that, The FPGA main control module includes: an array element selection control unit, a transmit beam combining unit, and a receive beam combining unit; The array element selection control unit is connected to the neural network processing unit. The array element selection control unit is used to drive the ultrasonic simulation circuit to perform time-division gating of the transmitting array elements and receiving array elements in the PMUT array according to the optimal array element gating matrix. The transmit beamforming unit is connected to the neural network processing unit. The transmit beamforming unit is used to perform phase-controlled excitation on the transmit array elements according to the optimal array element selection matrix when the transmit array elements are selected. The receiving beamforming unit is connected to the ultrasonic analog circuit. The receiving beamforming unit is used to perform beamforming on the processed ultrasonic echo signal when the receiving array element is selected, so as to obtain the synthesized ultrasonic echo signal.

4. The PMUT array ultrasonic transceiver circuit system according to claim 3, characterized in that, The ultrasonic simulation circuit includes: a multiplexer, a transmitting circuit, and a receiving circuit; The multiplexer is connected to the array element selection control unit and the PMUT array respectively. Under the control of the array element selection control unit, the multiplexer is used to connect the corresponding transmitting array element to the transmitting circuit to achieve the selection of the transmitting array element in the PMUT array, and to connect the corresponding receiving array element to the receiving circuit to achieve the selection of the receiving array element in the PMUT array. The transmitting circuit is connected to the multiplexer and the transmitting beamforming unit respectively, and is used to generate a high voltage pulse when the transmitting array element is selected, so as to excite the PMUT array to generate ultrasonic waves. The receiving circuit is connected to the multiplexer and the receiving beamforming unit respectively, and is used to acquire and process the corresponding ultrasonic echo signal when the receiving array element is selected, so as to obtain the processed ultrasonic echo signal.

5. The PMUT array ultrasonic transceiver circuit system according to claim 4, characterized in that, The transmitting circuit is a single or multiple high-voltage pulse generator; the receiving circuit is an ultrasonic analog front-end chip.

6. The PMUT array ultrasonic transceiver circuit system according to claim 5, characterized in that, The receiving circuit includes: a low-noise amplifier, an analog low-pass filter, an attenuator, a digital time gain compensator, and an ADC; The low-noise amplifier is connected to the multiplexer, and the low-noise amplifier is used to amplify the multiple ultrasonic echo signals to obtain the amplified ultrasonic echo signals. The analog low-pass filter is connected to the low-noise amplifier. The analog low-pass filter is used to perform low-pass filtering on the amplified ultrasonic echo signal to obtain the filtered ultrasonic echo signal. The attenuator is connected to the analog low-pass filter, and the attenuator is used to attenuate the filtered ultrasonic echo signal to obtain the attenuated ultrasonic echo signal. The digital time gain compensator is connected to the attenuator. The digital time gain compensator is used to perform time gain compensation on the attenuated ultrasonic echo signal to obtain the compensated ultrasonic echo signal. The ADC is connected to the digital time gain compensator, and the ADC is used to sample the compensated ultrasonic echo signal to obtain the processed ultrasonic echo signal.

7. The PMUT array ultrasonic transceiver circuit system according to claim 6, characterized in that, The ultrasonic echo signal is transmitted between the receiving circuit and the receiving beamforming unit using a high-speed serial interface LVDS or JEDEC JESD204B protocol.

8. The PMUT array ultrasonic transceiver circuit system according to claim 5, characterized in that, The FPGA main control module also includes: a power supply unit and a clock circuit; The power supply unit is connected to the array element selection control unit, the transmit beamforming unit and the receive beamforming unit respectively, and is used to provide the required four independent power supplies to the array element selection control unit, the transmit beamforming unit and the receive beamforming unit; The clock circuit is connected to the array element selection control unit, the transmit beamforming unit, the receive beamforming unit, and the receiving circuit, respectively, and is used to provide differential clock signals to the array element selection control unit, the transmit beamforming unit, the receive beamforming unit, and the receiving circuit.

9. The PMUT array ultrasonic transceiver circuit system according to claim 8, characterized in that, The FPGA main control module also includes: a DDR memory unit and a storage unit; The DDR memory unit is connected to the array element selection control unit, the transmit beamforming unit and the receive beamforming unit respectively, and is used to provide data cache space for the operation of the array element selection control unit, the transmit beamforming unit and the receive beamforming unit; The storage unit is connected to the receiving circuit and the receiving beamforming unit respectively, and is used to store the ultrasonic echo signal and the processed ultrasonic echo signal.

10. The PMUT array ultrasonic transceiver circuit system according to claim 1, characterized in that, The GPU processing module and the FPGA main control module are connected via a PCIe interface.

Images