Bandgap reference circuit, reference voltage source and reference voltage generation method

Abstract

The embodiment of the present application discloses a band gap reference circuit, a reference voltage source and a reference voltage generation method, the circuit comprising a current module, a differential input module, a limiting module, a feedback module and a voltage division module, the differential input module generating a first conduction current and a second conduction current in response to a first voltage signal and a second voltage signal of the voltage division module respectively, and then outputting a first output current and a second output current respectively; the limiting module outputting a driving signal to control the feedback module to adjust the first voltage signal and the second voltage signal in response to the first output current and the second output current, so that the first output current and the second output current are equal, and the differential input module outputs a reference voltage with zero temperature coefficient. The limiting module comprises a matching resistor or a low-transconductance switch tube to reduce the offset voltage. The present application sets a matching resistor or a low-transconductance switch tube in the limiting module to reduce the offset voltage of the limiting module and improve the accuracy of the reference voltage.

Description

[0001] This application is a divisional application. The parent application is Chinese patent application filed on July 29, 2024, with application number 202411024150.6 and entitled "Bandgap reference circuit, reference voltage source and reference voltage generation method". Technical Field

[0002] The embodiments of the present invention relate to the field of integrated circuit technology, and in particular to a bandgap reference circuit, a reference voltage source, and a reference voltage generation method. Background Technology

[0003] In analog and mixed-signal circuits, the bandgap reference circuit plays a crucial role as a fundamental unit. Its function is to generate a reference voltage that remains constant regardless of changes in temperature, power supply voltage, or manufacturing process parameters. The accuracy of the bandgap reference circuit directly affects many parameters of the chip in which it resides. Therefore, the design of the bandgap reference circuit is extremely important for the chip.

[0004] However, most existing technologies use a separate operational amplifier to control the bandgap reference circuit loop, which leads to a complex circuit structure. Furthermore, the offset voltage of the operational amplifier reduces the accuracy of the reference voltage output by the bandgap reference circuit. Summary of the Invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide a bandgap reference circuit, a reference voltage source, and a reference voltage generation method, which can reduce the impact of offset voltage on the accuracy of the reference voltage.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this invention is: providing a bandgap reference circuit, including: a current module, a differential input module, a limit module, a feedback module, and a voltage divider module. The current module is connected to an input power supply and the differential input module, and is used to provide current to the differential input module. The limit module is connected to the feedback module and the differential input module, and the feedback module is connected to the input power supply. The differential input module is configured to generate a first conduction current and a second conduction current in response to a first voltage signal and a second voltage signal from the voltage divider module, respectively. The first output current and the second output current are output respectively; the limiting module responds to the first output current and the second output current and outputs a drive signal to the feedback module to adjust the output current of the feedback module, and the output current causes the voltage divider module to generate the first voltage signal and the second voltage signal; when the first output current and the second output current are equal, the differential input module outputs a reference voltage with zero temperature coefficient; the limiting module includes a matching resistor or a low transconductance switch to reduce the offset voltage, and the transconductance of the low transconductance switch is less than the transconductance of the transistor in the differential input module.

[0007] In some embodiments, the limiting module includes switching transistors M1, M2, M3, and M5. The drain of switching transistor M1 is connected to the gate of switching transistor M3 and the first output terminal of the differential input module. The gate of switching transistor M1 is connected to the gate of switching transistor M2, the drain of switching transistor M2, and the second output terminal of the differential input module. The sources of switching transistors M1, M2, and M3 are grounded. The gate of switching transistor M3 is connected to the drain of switching transistor M5, the gate of switching transistor M5, and the controlled terminal of the feedback module. The source of switching transistor M5 is connected to the input power supply.

[0008] In some embodiments, the limiting module further includes resistors R6, R7, and R8. The first end of resistor R6 is connected to the source of the switching transistor M1, the first end of resistor R7 is connected to the source of the switching transistor M2, the first end of resistor R8 is connected to the source of the switching transistor M3, and the second ends of resistors R6, R7, and R8 are grounded.

[0009] In some embodiments, the current module includes a constant current source I1, the positive terminal of which is connected to the input power supply, and the negative terminal of which is connected to the input terminal of the differential input module. In some embodiments, the current module includes a switching transistor M6, the source of which is connected to the input power supply, the gate of which is connected to a bias voltage source, and the drain of which is connected to the input terminal of the differential input module.

[0010] In some embodiments, the current module includes a switching transistor M6, the gate of which is connected to the controlled terminal of the feedback module, the source of which is connected to the input power supply, and the drain of which is connected to the input terminal of the differential input module.

[0011] In some embodiments, the limiting module includes an operational amplifier U1, a resistor R4, and a resistor R5. The non-inverting input of the operational amplifier U1 is connected to the first output of the differential input module and the first terminal of the resistor R4. The inverting input of the operational amplifier U1 is connected to the second output of the differential input module and the first terminal of the resistor R5. The output of the operational amplifier U1 is connected to the controlled terminal of the feedback module. The second terminals of the resistor R4 and the second terminals of the resistor R5 are grounded.

[0012] In some embodiments, the feedback module includes a switching transistor M4, the gate of which is connected to the output terminal of the limiting module, the source of which is connected to the input power supply, and the drain of which is connected to the first terminal of the voltage divider module and the third output terminal of the differential input module.

[0013] In some embodiments, the differential input module includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the output terminal of the current module. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of the limit module. The collector of transistor Q2 is connected to the second input terminal of the limit module. The voltage divider module includes resistors R1 and R2. The first terminal of resistor R1 is connected to the second terminal of resistor R3 and the output terminal of the feedback module. The second terminal of resistor R1 is connected to the first terminal of resistor R2 and the base of transistor Q2. The second terminal of resistor R2 is grounded. The resistance of resistor R3 is equal to the resistance of resistor R1.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is to provide a reference voltage source, including a bandgap reference circuit as described above.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is: providing a reference voltage generation method, applied to a bandgap reference circuit as described above, comprising: under the action of a first voltage signal and a second voltage signal provided by a voltage divider module, controlling a differential input module to generate a first conduction current and a second conduction current respectively, thereby outputting a first output current and a second output current; under the action of the first output current and the second output current, controlling a limit module to output a drive signal; under the action of the drive signal, controlling a feedback module to adjust the first voltage signal and the second voltage signal to make the first conduction current and the second conduction current equal, thereby making the first output current and the second output current equal; when the first output current and the second output current are equal, controlling the differential input module to output a reference voltage with zero temperature coefficient; and causing the limit module to provide a matching resistor or a low transconductance switching transistor with a transconductance less than that of the differential input module to reduce the offset voltage.

[0016] The beneficial effects of the embodiments of the present invention are as follows: Unlike the prior art, the embodiments of the present invention use an isolation structure formed by a PNP transistor, and by setting a matching resistor in the limiting module to reduce offset, or by setting a low transconductance switching transistor with a transconductance much lower than that of the transistor, the injection of minority carriers is avoided, and the influence of the offset voltage of the limiting module is reduced, thereby improving the accuracy of the reference voltage. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of an existing bandgap reference circuit; Figure 2 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of the present invention; Figure 3 This is a circuit structure diagram of the first bandgap reference circuit provided in the embodiments of the present invention; Figure 4 This is a circuit structure diagram of the second bandgap reference circuit provided in the embodiments of the present invention; Figure 5 This is a circuit structure diagram of the third bandgap reference circuit provided in the embodiments of the present invention; Figure 6 This is a circuit structure diagram of the fourth bandgap reference circuit provided in the embodiments of the present invention; Figure 7 This is a circuit structure diagram of the fifth bandgap reference circuit provided in the embodiments of the present invention; Figure 8 This is a circuit structure diagram of the sixth bandgap reference circuit provided in the embodiments of the present invention; Figure 9 This is a schematic flowchart of a reference voltage generation method provided by an embodiment of the present invention. Detailed Implementation

[0018] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] The technical solutions in this application will be described below with reference to the accompanying drawings.

[0022] Figure 1 The circuit structure of an existing bandgap reference circuit is shown, which includes an operational amplifier U1, resistors R1 and R2, transistors Q1 and Q2.

[0023] The non-inverting input of operational amplifier U1 is connected to the second terminal of resistor R2 and the emitter of transistor Q2. The inverting input of operational amplifier U1 is connected to the second terminal of resistor R1 and the first terminal of resistor R0. The output of operational amplifier U1 is connected to the first terminal of resistor R2 and the first terminal of resistor R1. The second terminal of resistor R0 is connected to the emitter of transistor Q1. The base and collector of transistor Q1, the base and collector of transistor Q2 are grounded.

[0024] Among them, the resistance values ​​of resistor R1 and resistor R2 are equal, transistors Q1 and Q2 are both PNP transistors, and the ratio of the size of transistor Q1 to the size of transistor Q2 is m:1.

[0025] Because operational amplifier U1 forms negative feedback with resistors R1 and R2, the virtual short characteristic of the operational amplifier can be used to clamp the voltages at the second terminals of resistors R1 and R2, making them equal. Furthermore, since the resistances of R1 and R2 are equal, the current I1 flowing through resistor R1 is equal to the current I2 flowing through resistor R2.

[0026] Since the ratio of the dimensions of transistors Q1 and Q2 is m:1, the voltage across resistor R0 can be expressed by the following formula: ΔVBE=VBE1- VBE2=k*T*lnm / q, (1) Where k represents Boltzmann constant, q represents electron charge constant, T represents temperature, m represents the ratio between the dimensions of transistor Q1 and transistor Q2, VBE1 represents the voltage difference between the base and emitter of transistor Q1, and VBE2 represents the voltage difference between the base and emitter of transistor Q2.

[0027] As can be seen from equation (1), only temperature T is a variable, while other physical quantities are constants. Therefore, it is not difficult to understand that the voltage across resistor R0 is a voltage that is positively correlated with temperature, i.e., a positive temperature coefficient voltage.

[0028] It is known that the voltage difference VBE between the base and emitter of a transistor is negatively correlated with temperature, i.e., a negative temperature coefficient voltage. Therefore, by selecting appropriate resistors R1 and R0 and controlling the ratio of their values, the positive temperature coefficient corresponding to ΔVBE can be made equal to the negative temperature coefficient corresponding to VBE1. This yields a reference voltage with zero temperature coefficient, i.e., a voltage unaffected by temperature.

[0029] The reference voltage with zero temperature coefficient can be expressed by the following formula: VREF= VBE1+(R0+R) / R0*ΔVBE, Where VBE1 represents the voltage difference between the base and emitter of transistor Q1, R represents the resistance of resistor R1 and / or resistor R2, and ΔVBE represents the voltage across resistor R0.

[0030] However, the above bandgap reference circuit is affected by the offset voltage of the operational amplifier, and the actual reference voltage is as shown in the following formula: VREF= VBE1+(R0+R) / R0*(ΔVBE+Vos), Here, Vos is the offset voltage. It is easy to see that the offset voltage is amplified. The amplified offset voltage will bring about a higher temperature drift, which in turn will reduce the accuracy of the reference voltage output by the bandgap reference circuit.

[0031] To address the above problems, embodiments of the present invention provide a bandgap reference circuit, the schematic diagram of which is shown below. Figure 2 As shown, the bandgap reference circuit includes a current module 110, a differential input module 120, a limit module 130, a voltage divider module 140, and a feedback module 150.

[0032] The input terminal of the current module 110 is connected to the input power supply 20, the output terminal of the current module 110 is connected to the input terminal of the differential input module 120, the first output terminal of the differential input module 120 is connected to the first input terminal of the limit module 130, the second output terminal of the differential input module 120 is connected to the second input terminal of the limit module 130, the third output terminal of the differential input module 120 is connected to the first input terminal of the voltage divider module 140, and the fourth output terminal of the differential input module 120 is connected to the second input terminal of the voltage divider module 140.

[0033] The output of the limit module 130 is connected to the controlled terminal of the feedback module 150, the input of the feedback module 150 is connected to the input power supply 20, and the output of the feedback module 150 is connected to the first input terminal of the voltage divider module 140. The current module 110, the feedback module 150, the differential input module 120, the voltage divider module 140, and the limit module 130 constitute a negative feedback loop.

[0034] The current module 110 provides current to the differential input module 120. When the feedback module 150 is turned on, the input power supply 20 supplies power to the voltage divider module 140, causing the voltage divider module 140 to output a first voltage signal and a second voltage signal. The differential input module 120 is configured to generate a first conduction current and a second conduction current in response to the first voltage signal and the second voltage signal of the voltage divider module 140, respectively, and then output a first output current and a second output current, respectively.

[0035] The limit module 130 responds to the first output current and the second output current and outputs a drive signal to the feedback module 150 to adjust the output current of the feedback module 150, thereby adjusting the first voltage signal and the second voltage signal so that the first conduction current and the second conduction current are equal.

[0036] In this embodiment, the transistor used in the differential input module 120 is a PNP transistor.

[0037] It should be noted that the limit module 130 is equipped with a matching resistor or a low transconductance switch to reduce the offset voltage. The transconductance of the low transconductance switch is less than that of the transistor in the differential input module 120.

[0038] Unlike existing technologies, the embodiments of the present invention use an isolation structure formed by a PNP transistor. By setting a matching resistor in the limiting module to reduce offset, or by setting a low transconductance switching transistor with a transconductance much lower than that of the transistor, minority carrier injection is avoided, the influence of the offset voltage of the limiting module is reduced, and the accuracy of the reference voltage is improved.

[0039] In some embodiments of this application, a circuit diagram of a first bandgap reference circuit is provided, such as... Figure 3 As shown.

[0040] The current module 110 includes a constant current source I1, the positive terminal of which is connected to the input power supply VDD, and the negative terminal of which is connected to the input terminal of the differential input module 120.

[0041] The differential input module 120 includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the negative terminal of constant current source I1. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of limit module 140. The collector of transistor Q2 is connected to the second input terminal of limit module 140.

[0042] The limit module includes switching transistors M1, M2, M3, and M5. The drain of switching transistor M1 is connected to the gate of switching transistor M3 and the collector of transistor Q1. The gate of switching transistor M1 is connected to the gate of switching transistor M2, the drain of switching transistor M2, and the collector of transistor Q2. The sources of switching transistors M1, M2, and M3 are grounded. The gate of switching transistor M3 is connected to the drain of switching transistor M5, the gate of switching transistor M5, and the controlled terminal of feedback module 150. The source of switching transistor M5 is connected to the input power supply VDD.

[0043] In this embodiment, switch M1, switch M2 and switch M3 are N-channel MOSFETs, and switch M5 is a P-channel MOSFET.

[0044] The voltage divider module includes resistors R1 and R2. The first end of resistor R1 is connected to the second end of resistor R3 and the output terminal of feedback module 140. The second end of resistor R1 is connected to the first end of resistor R2 and the base of transistor Q2. The second end of resistor R2 is grounded.

[0045] In this embodiment, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0046] The feedback module includes a switching transistor M4, the gate of which is connected to the gate and drain of a switching transistor M5, the source of which is connected to the input power supply VDD, and the drain of which is connected to the first terminal of resistor R1 and the second terminal of resistor R3.

[0047] In this embodiment, the switching transistor M4 is a P-channel MOSFET.

[0048] Among them, the emitter output of transistor Q2 is the reference power supply VREF.

[0049] Specifically, the constant current source I1 provides a stable current to transistors Q1 and Q2. The source of switch M1 is connected to the source of switch M2, and the gate of switch M1 is connected to the gate of switch M2, so that switch M1 and switch M2 form a current mirror, allowing switch M1 to mirror the current of switch M2.

[0050] Transistor Q1 generates a first conducting current under the influence of a first voltage signal provided at the first terminal of resistor R1, and transistor Q2 generates a second conducting current under the influence of a second voltage signal provided at the second terminal of resistor R1, thereby outputting a first output current and a second output current, respectively. The currents of switching transistors M1 and M2 have a fixed proportional relationship, and the current amplification factors of transistors Q1 and Q2 are adjusted accordingly.

[0051] In some embodiments of this application, the size ratio of switch M1 to switch M2 is 1:1, meaning the first output current equals the second output current. Under the action of the current mirror formed by switch M1 and switch M2, the first and second output currents are compared. Switches M3 and M5 then generate drive signals based on this comparison result and output them to switch M4 to control the gate voltage of switch M4, thereby adjusting the on-state current of switch M4. This adjusts the voltage across resistor R1, i.e., the first voltage signal and the second voltage signal, so that the base current of transistor Q1 equals the base current of transistor Q2, i.e., the first on-state current equals the second on-state current.

[0052] When the base currents of transistors Q1 and Q2 are equal, the voltage difference between the voltage across the first terminal of resistor R3 and the voltage across the first terminal of resistor R2 is ΔVBE. Thus, ΔVBE is a positive temperature coefficient voltage. ΔVBE equals the voltage across resistor R1 plus the voltage across resistor R3, i.e., ΔVBE = I1 * R1 + I3 * R3.

[0053] I3 is the current flowing through resistor R3, which is the base current of transistor Q1, and I1 is the current flowing through resistor R1.

[0054] We can obtain I1 = (ΔVBE - I3 * R3) / R1. It is easy to understand that I1 is the positive temperature coefficient current.

[0055] Since the current flowing through resistor R2 is the sum of I1 and the base current of transistor Q2, it can be understood that the voltage across resistor R2 is a positive temperature coefficient voltage.

[0056] Since the voltage difference VBE2 between the base and emitter of transistor Q2 is a negative temperature coefficient voltage, the negative temperature coefficient voltage and the positive temperature coefficient voltage can be combined through the electrical connection of resistor R2 and transistor Q2 to obtain a zero temperature coefficient reference voltage VREF. In other words, the reference voltage VREF does not change with temperature.

[0057] Based on the above, we can obtain VREF = I²R² + VBE² I2 is the current flowing through resistor R2, i.e., I2 = I1 + I3.

[0058] Therefore, we can obtain VREF=((ΔVBE- I3*R3) / R1+I3)*R2+VBE2, Given R3=R1, then VREF=ΔVBE / R1*R2+VBE2.

[0059] However, due to the influence of offset voltage, the actual reference voltage is... VREF=(ΔVBE+Vos*gm1 / gm2) / R1*R2+VBE2, Where Vos is the offset voltage, gm1 is the transconductance of the switching transistor M1, and gm2 is the transconductance of the transistor Q1.

[0060] Therefore, by setting a switching transistor M1 with a transconductance much smaller than that of transistor Q1, the offset voltage Vos can be made close to 0, thereby reducing the impact of the offset voltage Vos.

[0061] In other embodiments of this application, circuit diagrams of a second bandgap reference circuit are provided, such as... Figure 4 As shown.

[0062] The current module 110 includes a switching transistor M6, the source of which is connected to the input power supply VDD, the gate of which is connected to the bias voltage source VEP, and the drain of which is connected to the input terminal of the differential input module 120.

[0063] In this embodiment, the switching transistor M6 is a P-channel MOS transistor.

[0064] The differential input module 120 includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the drain of switching transistor M6. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of limiting module 140. The collector of transistor Q2 is connected to the second input terminal of limiting module 140.

[0065] The limit module includes switching transistors M1, M2, M3, and M5. The drain of switching transistor M1 is connected to the gate of switching transistor M3 and the collector of transistor Q1. The gate of switching transistor M1 is connected to the gate of switching transistor M2, the drain of switching transistor M2, and the collector of transistor Q2. The sources of switching transistors M1, M2, and M3 are grounded. The gate of switching transistor M3 is connected to the drain of switching transistor M5, the gate of switching transistor M5, and the controlled terminal of feedback module 150. The source of switching transistor M5 is connected to the input power supply VDD.

[0066] In this embodiment, switch M1, switch M2 and switch M3 are N-channel MOSFETs, and switch M5 is a P-channel MOSFET.

[0067] The voltage divider module includes resistors R1 and R2. The first end of resistor R1 is connected to the second end of resistor R3 and the output terminal of feedback module 140. The second end of resistor R1 is connected to the first end of resistor R2 and the base of transistor Q2. The second end of resistor R2 is grounded.

[0068] In this embodiment, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0069] The feedback module includes a switching transistor M4, the gate of which is connected to the gate and drain of a switching transistor M5, the source of which is connected to the input power supply VDD, and the drain of which is connected to the first terminal of resistor R1 and the second terminal of resistor R3.

[0070] In this embodiment, the switching transistor M4 is a P-channel MOSFET.

[0071] Among them, the emitter output of transistor Q2 is the reference power supply VREF.

[0072] The specific working principle is the same as Figure 3 The bandgap reference circuit shown differs in that, in this embodiment, transistors Q1 and Q2 are supplied with current by the input power supply VDD.

[0073] In other embodiments of this application, circuit diagrams of a third bandgap reference circuit are provided, such as... Figure 5 As shown.

[0074] The current module 110 includes a switching transistor M6, the source of which is connected to the input power supply VDD, the gate of which is connected to the gate of the switching transistor M5 in the limit module 130, and the drain of which is connected to the input terminal of the differential input module 120.

[0075] In this embodiment, the switching transistor M6 is a P-channel MOS transistor.

[0076] The differential input module 120 includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the drain of switching transistor M6. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of limiting module 140. The collector of transistor Q2 is connected to the second input terminal of limiting module 140.

[0077] The limit module includes switching transistors M1, M2, M3, and M5. The drain of switching transistor M1 is connected to the gate of switching transistor M3 and the collector of transistor Q1. The gate of switching transistor M1 is connected to the gate of switching transistor M2, the drain of switching transistor M2, and the collector of transistor Q2. The sources of switching transistors M1, M2, and M3 are grounded. The gate of switching transistor M3 is connected to the drain of switching transistor M5, the gate of switching transistor M5, and the controlled terminal of feedback module 150. The source of switching transistor M5 is connected to the input power supply VDD.

[0078] In this embodiment, switch M1, switch M2 and switch M3 are N-channel MOSFETs, and switch M5 is a P-channel MOSFET.

[0079] The voltage divider module includes resistors R1 and R2. The first end of resistor R1 is connected to the second end of resistor R3 and the output terminal of feedback module 140. The second end of resistor R1 is connected to the first end of resistor R2 and the base of transistor Q2. The second end of resistor R2 is grounded.

[0080] In this embodiment, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0081] The feedback module includes a switching transistor M4, the gate of which is connected to the gate and drain of a switching transistor M5, the drain of which is connected to the input power supply VDD, and the source of which is connected to the first end of a resistor R1 and the second end of a resistor R3.

[0082] In this embodiment, the switching transistor M4 is an N-channel MOS transistor.

[0083] Among them, the emitter output of transistor Q2 is the reference power supply VREF.

[0084] The specific working principle is the same as Figure 4The bandgap reference circuit shown differs in that, in this embodiment, the bias voltage of switch M6 can be obtained from the drive voltage of switch M5. Unlike the two embodiments mentioned above, this embodiment does not require an additional constant current source or bias voltage source.

[0085] In other embodiments of this application, circuit diagrams of a fourth bandgap reference circuit are provided, such as... Figure 6 As shown.

[0086] The current module 110 includes a switching transistor M6, the source of which is connected to the input power supply VDD, the gate of which is connected to the gate of the switching transistor M5 in the limit module 130, and the drain of which is connected to the input terminal of the differential input module 120.

[0087] In this embodiment, the switching transistor M6 is a P-channel MOS transistor.

[0088] The differential input module 120 includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the drain of switching transistor M6. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of limiting module 140. The collector of transistor Q2 is connected to the second input terminal of limiting module 140.

[0089] The limit module includes switching transistors M1, M2, M3, and M5, resistors R6, R7, and R8. The drain of switching transistor M1 is connected to the gate of switching transistor M3 and the collector of transistor Q1. The gate of switching transistor M1 is connected to the gate of switching transistor M2, the drain of switching transistor M2, and the collector of transistor Q2. The source of switching transistor M3 is connected to the first terminal of resistor R3. The first terminal of resistor R6 is connected to the source of switching transistor M1. The first terminal of resistor R7 is connected to the source of switching transistor M2. The second terminals of resistors R6, R7, and R8 are grounded. The gate of switching transistor M3 is connected to the drain of switching transistor M5, the gate of switching transistor M5, and the controlled terminal of feedback module 150. The source of switching transistor M5 is connected to the input power supply VDD.

[0090] In this embodiment, switch M1, switch M2 and switch M3 are N-channel MOSFETs, and switch M5 is a P-channel MOSFET.

[0091] The voltage divider module includes resistors R1 and R2. The first end of resistor R1 is connected to the second end of resistor R3 and the output terminal of feedback module 140. The second end of resistor R1 is connected to the first end of resistor R2 and the base of transistor Q2. The second end of resistor R2 is grounded.

[0092] In this embodiment, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0093] The feedback module includes a switching transistor M4, the gate of which is connected to the gate and drain of a switching transistor M5, the source of which is connected to the input power supply VDD, and the drain of which is connected to the first terminal of resistor R1 and the second terminal of resistor R3.

[0094] In this embodiment, the switching transistor M4 is a P-channel MOSFET.

[0095] Among them, the emitter output of transistor Q2 is the reference power supply VREF.

[0096] The specific working principle is the same as Figure 5 The bandgap reference circuit shown differs in that, in this embodiment, matching resistors, namely resistors R6, R7, and R8, are further provided. Resistors R6 and R7 are used to reduce the impact of mismatch between switching transistors M1 and M2; resistor R8 is used to match the current of switching transistors M5 and M6.

[0097] In other embodiments of this application, circuit diagrams of a fifth bandgap reference circuit are provided, such as... Figure 7 As shown.

[0098] The current module 110 includes a constant current source I1, the positive terminal of which is connected to the input power supply VDD, and the negative terminal of which is connected to the input terminal of the differential input module 120.

[0099] The differential input module 120 includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the drain of switching transistor M6. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of limiting module 140. The collector of transistor Q2 is connected to the second input terminal of limiting module 140.

[0100] The limit module 130 includes an operational amplifier U1, a resistor R4, and a resistor R5. The non-inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q1 and the first terminal of the resistor R4. The inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q2 and the first terminal of the resistor R5. The output terminal of the operational amplifier U1 is connected to the controlled terminal of the feedback module 150. The second terminals of the resistor R4 and the second terminals of the resistor R5 are grounded.

[0101] The voltage divider module includes resistors R1 and R2. The first end of resistor R1 is connected to the second end of resistor R3 and the output terminal of feedback module 140. The second end of resistor R1 is connected to the first end of resistor R2 and the base of transistor Q2. The second end of resistor R2 is grounded.

[0102] In this embodiment, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0103] The feedback module includes a switching transistor M4. The gate of the switching transistor M4 is connected to the output terminal of the operational amplifier U1, the drain of the switching transistor M4 is connected to the input power supply VDD, and the source of the switching transistor M4 is connected to the first terminal of resistor R1 and the second terminal of resistor R3.

[0104] In this embodiment, the switching transistor M4 is an N-channel MOS transistor.

[0105] Among them, the emitter output of transistor Q2 is the reference power supply VREF.

[0106] Specifically, the constant current source I1 provides a stable current to transistors Q1 and Q2. The operational amplifier U1, the switching transistor M4, the constant current source I1, the resistor R1, the resistor R2, the transistors Q1 and Q2 form a negative feedback loop.

[0107] Transistor Q1 generates a first conducting current under the influence of a first voltage signal provided at the first terminal of resistor R1, and transistor Q2 generates a second conducting current under the influence of a second voltage signal provided at the second terminal of resistor R1, thereby outputting a first output current and a second output current, respectively. Operational amplifier U1 compares the first and second output currents and generates a drive signal based on this comparison result, which is then output to switch M4 to control the gate voltage of switch M4. This controls the conducting current of switch M4, thereby adjusting the voltage across resistor R1, i.e., the first and second voltage signals, so that the base current of transistor Q1 equals the base current of transistor Q2, i.e., the first conducting current equals the second conducting current.

[0108] When the base currents of transistors Q1 and Q2 are equal, the voltage difference between the voltage across the first terminal of resistor R3 and the voltage across the first terminal of resistor R2 is ΔVBE. Thus, ΔVBE is a positive temperature coefficient voltage. ΔVBE equals the voltage across resistor R1 plus the voltage across resistor R3, i.e., ΔVBE = I1 * R1 + I3 * R3.

[0109] I3 is the current flowing through resistor R3, which is the base current of transistor Q1, and I1 is the current flowing through resistor R1.

[0110] We can obtain I1 = (ΔVBE - I3 * R3) / R1. It is easy to understand that I1 is the positive temperature coefficient current.

[0111] Since the current flowing through resistor R2 is the sum of I1 and the base current of transistor Q2, it can be understood that the voltage across resistor R2 is a positive temperature coefficient voltage.

[0112] Since the voltage difference VBE2 between the base and emitter of transistor Q2 is a negative temperature coefficient voltage, the negative temperature coefficient voltage and the positive temperature coefficient voltage can be combined through the electrical connection of resistor R2 and transistor Q2 to obtain a zero temperature coefficient reference voltage VREF. In other words, the reference voltage VREF does not change with temperature.

[0113] Based on the above, we can obtain VREF = I²R² + VBE² I2 is the current flowing through resistor R2, i.e., I2 = I1 + I3.

[0114] Therefore, we can obtain VREF=((ΔVBE- I3*R3) / R1+I3)*R2+VBE2, Given R3=R1, then VREF=ΔVBE / R1*R2+VBE2.

[0115] Although in practice the reference voltage is affected by the offset voltage of the operational amplifier, this embodiment uses matching resistors, namely resistors R4 and R5, to limit the collector current of transistor Q1 and the collector current of transistor Q2, thereby avoiding the influence of the operational amplifier's offset voltage.

[0116] In other embodiments of this application, circuit diagrams of a sixth bandgap reference circuit are provided, such as... Figure 8 As shown.

[0117] The current module 110 includes a switching transistor M6, the source of which is connected to the input power supply VDD, the gate of which is connected to the gate of the switching transistor M4 in the feedback module 140, and the drain of which is connected to the input terminal of the differential input module 120.

[0118] The differential input module 120 includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the drain of switching transistor M6. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of limiting module 140. The collector of transistor Q2 is connected to the second input terminal of limiting module 140.

[0119] The limit module 130 includes an operational amplifier U1, a resistor R4, and a resistor R5. The inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q1 and the first terminal of the resistor R4. The non-inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q2 and the first terminal of the resistor R5. The output terminal of the operational amplifier U1 is connected to the controlled terminal of the feedback module 150. The second terminals of the resistor R4 and the second terminals of the resistor R5 are grounded.

[0120] The voltage divider module includes resistors R1 and R2. The first end of resistor R1 is connected to the second end of resistor R3 and the output terminal of feedback module 140. The second end of resistor R1 is connected to the first end of resistor R2 and the base of transistor Q2. The second end of resistor R2 is grounded.

[0121] In this embodiment, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0122] The feedback module includes a switching transistor M4. The gate of the switching transistor M4 is connected to the output terminal of the operational amplifier U1, the source of the switching transistor M4 is connected to the input power supply VDD, and the drain of the switching transistor M4 is connected to the first terminal of resistor R1 and the second terminal of resistor R3.

[0123] In this embodiment, the switching transistor M4 is a P-channel MOSFET.

[0124] Among them, the emitter output of transistor Q2 is the reference power supply VREF.

[0125] The specific working principle is the same as Figure 7 The bandgap reference circuit shown differs in that, in this embodiment, the bias voltage of switch M6 can be obtained from the drive voltage of switch M4. Unlike the embodiments described above, this embodiment does not require an additional constant current source or bias voltage source.

[0126] Unlike existing technologies, the embodiments of the present invention use an isolation structure formed by a PNP transistor. By setting a matching resistor in the limiting module to reduce offset, or by setting a low transconductance switching transistor with a transconductance much lower than that of the transistor, minority carrier injection is avoided, the influence of the offset voltage of the limiting module is reduced, and the accuracy of the reference voltage is improved.

[0127] based on Figure 2 The bandgap reference circuit provided in the illustrated embodiment is further provided by the present invention, which includes the bandgap reference circuit provided in any of the above embodiments.

[0128] based on Figure 2 The bandgap reference circuit provided in the illustrated embodiment also includes a reference voltage generation method, which is applied to the bandgap reference circuit provided in any of the above embodiments. A flowchart of this method is shown below. Figure 9 As shown, the specific steps include the following: Step S100: Under the action of the first voltage signal and the second voltage signal provided by the voltage divider module, the differential input module is controlled to generate the first conduction current and the second conduction current respectively, and then outputs the first output current and the second output current.

[0129] Specifically, when the feedback module is turned on, the input power supply powers the voltage divider module 1, causing the voltage divider module 140 to output a first voltage signal and a second voltage signal. Under the action of the first and second voltage signals provided by the voltage divider module, the differential input module generates a first conduction current and a second conduction current, respectively, and then outputs a first output current and a second output current.

[0130] Step S200: Under the action of the first output current and the second output current, control the limit module to output a drive signal.

[0131] Specifically, the limit module compares the first output current and the second output current, and further outputs the corresponding drive signal based on the comparison result.

[0132] Step S300: Under the action of the drive signal, the control feedback module adjusts the first voltage signal and the second voltage signal to make the first conduction current and the second conduction current equal, thereby making the first output current and the second output current equal.

[0133] Specifically, under the action of the drive signal, the feedback module adjusts its conduction current, and then adjusts the first voltage signal and the second voltage signal, so that the first conduction current and the second conduction current are equal, and thus the first output current and the second output current are equal.

[0134] Step S400: When the first output current and the second output current are equal, control the differential input module to output a reference voltage with zero temperature coefficient.

[0135] Specifically, when the first conduction current and the second conduction current are equal, the differential input module generates a current with a positive temperature coefficient. This current flows through the voltage divider module to generate a voltage with a positive temperature coefficient. This positive temperature coefficient voltage is combined with a negative temperature coefficient voltage of the differential input module itself to obtain a reference voltage with a zero temperature coefficient.

[0136] Step S500: The limit module provides a matching resistor or a low transconductance switch with a transconductance less than that of the transistor in the differential input module to reduce the offset voltage.

[0137] Specifically, the limit module introduces an offset voltage to the positive temperature coefficient voltage, which reduces the accuracy of the zero temperature coefficient reference voltage. Therefore, the limit module is further equipped with a matching resistor or a low transconductance switch with a transistor transconductance smaller than that of the differential input module to reduce the offset voltage and thus improve the accuracy of the zero temperature coefficient reference voltage.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A bandgap reference circuit, characterized in that, Includes: current module, differential input module, limit module, feedback module, and voltage divider module. The current module is connected to the input power supply and the differential input module, and the current module is used to provide current to the differential input module; the limit module is connected to the feedback module and the differential input module, and the feedback module is connected to the input power supply. The differential input module is configured to generate a first conduction current and a second conduction current in response to the first voltage signal and the second voltage signal of the voltage divider module, respectively, and then output a first output current and a second output current, respectively. The limiting module responds to the first output current and the second output current by outputting a drive signal to the feedback module to adjust the output current of the feedback module. The output current causes the voltage divider module to generate the first voltage signal and the second voltage signal. When the first output current and the second output current are equal, the differential input module outputs a reference voltage with zero temperature coefficient; The limiting module includes a matching resistor or a low transconductance switch to reduce offset voltage. The transconductance of the low transconductance switch is less than the transconductance of the transistor in the differential input module. The differential input module includes transistors Q1 and Q2 and resistor R3. The emitters of transistors Q1 and Q2 are connected to the output terminal of the current module. The base of transistor Q1 is connected to the first terminal of resistor R3. The collector of transistor Q1 is connected to the first input terminal of the limit module. The collector of transistor Q2 is connected to the second input terminal of the limit module.

2. The circuit according to claim 1, characterized in that, The limiting module includes switch M1, switch M2, switch M3, and switch M5. The drain of the switching transistor M1 is connected to the gate of the switching transistor M3 and the first output terminal of the differential input module. The gate of the switching transistor M1 is connected to the gate of the switching transistor M2, the drain of the switching transistor M2 and the second output terminal of the differential input module. The sources of the switching transistor M1, the sources of the switching transistor M2 and the sources of the switching transistor M3 are grounded. The gate of the switching transistor M3 is connected to the drain of the switching transistor M5, the gate of the switching transistor M5, and the controlled terminal of the feedback module, and the source of the switching transistor M5 is connected to the input power supply.

3. The circuit according to claim 2, characterized in that, The limiting module also includes resistors R6, R7, and R8. The first end of resistor R6 is connected to the source of the switching transistor M1, the first end of resistor R7 is connected to the source of the switching transistor M2, the first end of resistor R8 is connected to the source of the switching transistor M3, and the second ends of resistors R6, R7, and R8 are grounded.

4. The circuit according to claim 1, characterized in that, The current module includes a constant current source I1, the positive terminal of which is connected to the input power supply, and the negative terminal of which is connected to the input terminal of the differential input module.

5. The circuit according to claim 1, characterized in that, The current module includes a switching transistor M6, the source of which is connected to the input power supply, the gate of which is connected to a bias voltage source, and the drain of which is connected to the input terminal of the differential input module.

6. The circuit according to claim 1, characterized in that, The current module includes a switching transistor M6, the gate of which is connected to the controlled terminal of the feedback module, the source of which is connected to the input power supply, and the drain of which is connected to the input terminal of the differential input module.

7. The circuit according to claim 1, characterized in that, The limiting module includes an operational amplifier U1, resistor R4, and resistor R5. The non-inverting input terminal of the operational amplifier U1 is connected to the first output terminal of the differential input module and the first terminal of the resistor R4. The inverting input terminal of the operational amplifier U1 is connected to the second output terminal of the differential input module and the first terminal of the resistor R5. The output terminal of the operational amplifier U1 is connected to the controlled terminal of the feedback module. The second terminals of the resistor R4 and the second terminals of the resistor R5 are grounded.

8. The circuit according to claim 1, characterized in that, The feedback module includes a switching transistor M4, the gate of which is connected to the output terminal of the limit module, the source of which is connected to the input power supply, and the drain of which is connected to the first terminal of the voltage divider module and the third output terminal of the differential input module.

9. A reference voltage source, characterized in that, include: A bandgap reference circuit as described in any one of claims 1-8.

10. A method for generating a reference voltage, applied to a bandgap reference circuit as described in any one of claims 1-8, characterized in that, include: Under the action of the first voltage signal and the second voltage signal provided by the voltage divider module, the differential input module is controlled to generate the first conduction current and the second conduction current respectively, and then outputs the first output current and the second output current. Under the action of the first output current and the second output current, the control limit module outputs a drive signal; Under the action of the drive signal, the control feedback module adjusts the first voltage signal and the second voltage signal to make the first conduction current and the second conduction current equal, thereby making the first output current and the second output current equal; When the first output current and the second output current are equal, the differential input module is controlled to output a reference voltage with zero temperature coefficient. The limiting module provides a matching resistor or a low transconductance switch with a transconductance less than that of the transistor in the differential input module to reduce the offset voltage.

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