A signal intelligent regulation method and system of a multi-interface microcontroller

Abstract

This invention discloses a signal intelligent control method and system for a multi-interface microcontroller, relating to the field of intelligent interface scheduling technology. It includes: S1: Setting a corresponding interface resource configuration template according to the operational requirements of each test mode, and obtaining the conversion probability corresponding to each candidate module through a mode prediction model, generating a corresponding switching request; S2: Managing the switching data stream corresponding to the switching request through a dual-active data buffer, and simultaneously performing multiple verifications on the first frame data in the switching data stream through set real-time data verification points; S3: Setting a corresponding digital twin model according to the interface resource configuration template corresponding to the target mode, obtaining the expected KPI value, and performing adaptive parameter adjustment based on the comparison result between the expected KPI value and the actual KPI data. This invention can predict upcoming test mode transitions in advance and generate pre-scheduling instructions, pre-allocating and preparing interface resources for the target mode.

Description

Technical Field

[0001] This invention relates to the field of intelligent interface scheduling technology, specifically to a signal intelligent control method and system for a multi-interface microcontroller. Background Technology

[0002] Microcontroller units (MCUs), as the core control units of embedded systems, are widely used in industrial automation, smart homes, automotive electronics, medical devices, and IoT terminals. As system functions become increasingly complex, a single communication interface can no longer meet the demands of multi-device collaboration, multi-protocol interaction, and high real-time data transmission. Therefore, modern microcontrollers generally integrate multiple communication interfaces, such as Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface (SPI), I²C bus, Controller Area Network (CAN), USB, Ethernet, and even support wireless communication modules such as Wi-Fi and Bluetooth.

[0003] In recent years, some studies have attempted to introduce fuzzy control, finite state machines, or simple machine learning models to predict and optimize the communication behavior of microcontrollers. For example, the SPI transmission rate can be dynamically adjusted by monitoring the UART receive buffer fill rate, or low-power mode switching can be triggered by utilizing the CAN bus load rate. However, these methods are often limited to a single interface or specific application scenarios, lack a unified control framework for multi-interface collaboration, and have high computational overhead, making them difficult to deploy efficiently on resource-constrained 8 / 32-bit MCUs.

[0004] Chinese invention patent application CN120909193A discloses a method and system for intelligent start-stop predictive control of motors in distributed control systems. The method includes: determining an element matrix based on system control elements for the distributed control system; determining the series-parallel relationship of the distributed control system for the target control scenario, initializing the data interface on the acquisition side, encapsulating the element matrix, and transmitting it back to the controller; assisting the controller in executing cascaded control decisions under serial encapsulation, verifying and correcting deviations based on reliable start-stop and soft start-stop, determining the start-stop strategy, and responding to the motor set to execute start-stop control. This invention solves the technical problems of untimely motor start-stop response, inaccurate control decisions, and insufficient short-term shutdown transition management in existing distributed control systems. It improves the intelligence and reliability of motor start-stop prediction and control in distributed control systems, achieving the technical effects of smooth motor transition and optimized start-stop management under short-term shutdowns.

[0005] However, the above and similar technical solutions still have the following shortcomings: Different test modes of the MCU (such as extreme stress test mode, low-power characteristic test mode, and multi-protocol concurrent test mode) have different usage requirements, thus requiring dynamic switching between different control modes. Furthermore, each mode has different requirements for the microcontroller's interface resources (such as type, bandwidth, sampling rate, and priority). However, existing interfaces are prone to slow switching responses during reconstruction, and data corruption or transmission interruptions can easily occur during switching, resulting in a mismatch between the agile switching of control strategies and the rigid supply of interface services. Summary of the Invention

[0006] The purpose of this invention is to provide a method and system for intelligent signal control of a multi-interface microcontroller to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a signal intelligent control method for a multi-interface microcontroller, comprising:

[0008] S1: Predictive resource hierarchical switching: Based on the operational requirements of each test modality, set the corresponding interface resource configuration template, and obtain the conversion probability of each candidate module through the modality prediction model to generate the corresponding switching request;

[0009] S2: Interface resource hierarchical switching: The switching data stream corresponding to the switching request is managed through a dual-active data buffer. At the same time, the first frame data in the switching data stream is verified multiple times through the set real-time data verification points. The interface resource is switched through the switching data stream and the switching operation corresponding to the switching request.

[0010] S3: Digital Twin Optimization: Based on the interface resource configuration template corresponding to the target modality, set the corresponding digital twin model, obtain the expected KPI value, and based on the comparison result between the expected KPI value and the actual KPI data, perform adaptive parameter adjustment through the set fine-tuning strategy library.

[0011] Furthermore, a corresponding switching request is generated, including:

[0012] S1.1: Prediction Mapping: Generate corresponding pre-scheduling instructions through modal prediction models, and match the pre-scheduling instructions with interface resource configuration templates to obtain corresponding pre-scheduling configuration templates;

[0013] S1.2: Fusion Trigger: The system state variables, external command events, interface health information and high-confidence predicted target modes obtained from the industrial site are fused to obtain the corresponding fusion information. At the same time, the fusion information is used as the input of the mode arbitrator and the corresponding switching request is output.

[0014] S1.3: Hierarchical switching: Based on the interface resources of the industrial control system, set the interface hierarchy and perform multi-level parallel / sequential reconstruction processing within the hard real-time time window.

[0015] Furthermore, obtain the corresponding pre-scheduled configuration template, including:

[0016] S1.1.1: Template Construction: Based on the logical functions corresponding to the known control modes, set the corresponding interface resource configuration template, including mode ID, logical channel identifier, communication protocol, reserved bandwidth, exclusive time slice, data sampling rate / baud rate, priority of each data stream, control signal list, service quality indicators and maximum switching delay threshold;

[0017] S1.1.2: Model Construction: The rule inference engine, time-series pattern learner and external event interpreter are combined to construct the corresponding hybrid prediction model. The current state vector, short-term history sequence and external event stream are used as inputs to the hybrid prediction model, and the output is to obtain the corresponding high-confidence prediction target mode.

[0018] S1.1.3: Pre-scheduling determination: Based on all the interface resources actually occupied by the current running mode, set the corresponding active domain, based on the high-confidence predicted target mode, set the corresponding reserve domain, and combine the active domain, reserve domain and high-confidence predicted target mode to set the corresponding pre-scheduled task, and based on the target mode ID corresponding to the high-confidence predicted target mode, set the interface resource configuration template corresponding to the reserve domain.

[0019] Furthermore, the current state vector serves as the input to the rule inference engine, outputting a corresponding rule prediction candidate list; the short-term historical sequence serves as the input to the time-series pattern learner, outputting a corresponding time-series prediction candidate list; and the external event stream serves as the input to the external event interpreter, outputting a corresponding external prediction candidate list. Simultaneously, a prediction arbitrator performs multi-source information fusion and conflict resolution on the rule prediction candidate list, the time-series prediction candidate list, and the external prediction candidate list to determine the corresponding prediction target mode and the corresponding urgency level.

[0020] Furthermore, the interface layer includes an L1 security critical layer, an L2 real-time control layer, and an L3 monitoring and service layer. The L1 security critical layer is switched through a hardware redundancy channel, the L2 real-time control layer is reconfigured through an interface resource configuration template, and the L3 monitoring and service layer is migrated in an orderly manner through the remaining time window.

[0021] Furthermore, switching interface resources includes:

[0022] S2.1: Pre-switch guarantee: Based on the switching request, perform a conflict check on the current system resource status, determine the final switching scheme based on the conflict check results, and simultaneously save the interface-level resources in an orderly manner according to the interface level.

[0023] S2.2: Switching Management: Based on the interface resource level corresponding to the switching request, the switching request corresponding to the L1 security critical layer is switched with zero interruption, and the switching requests corresponding to the L2 real-time control layer and the L3 monitoring and service layer are reconstructed.

[0024] S2.3: Data Flow Control: Simultaneously, a dual-active data buffer is set up using both logical buffers and enhanced communication protocols. The application layer data flow is controlled through the dual-active data buffers. At the same time, the first frame of data after receiving and reassembling is verified using multiple verification rules. If the verification fails, data compensation is performed through the compensation logic of the driver layer.

[0025] Furthermore, the orderly preservation of interface-level resources includes:

[0026] S2.1.1: Conflict Detection: Based on the real-time occupancy of all physical and logical interface resources, obtain the corresponding current resource status snapshot, and compare the current resource status snapshot with the interface resource configuration template corresponding to the preparatory domain and the interface resource configuration template of the target modality corresponding to the switching request to determine the corresponding conflict detection result and the corresponding conflict type. At the same time, based on the conflict detection result and conflict type, determine the corresponding degradation switching plan through the preset degradation plan library.

[0027] S2.1.2: Current Interface Saving: Based on all logical interfaces corresponding to each interface level, determine the corresponding context saving list, and save the context saving list hierarchically according to the priority corresponding to the interface level, and save it to a dedicated rollback area.

[0028] Furthermore, the dedicated rollback area is located in non-volatile memory, and the physical memory range corresponding to the dedicated rollback area is marked so that only the context saving engine and the rollback recovery engine are allowed to perform write operations.

[0029] Furthermore, the switching requests corresponding to the L2 real-time control layer and the L3 monitoring and service layer are restructured, including:

[0030] S2.2.1: Zero-interruption switching: Based on the control signal corresponding to the L1 safety critical layer, two redundant channels are set up, and each of the redundant channels is equipped with a hardware comparator. At the same time, the signal level corresponding to the redundant channel is obtained through the hardware comparator, and the switching between the redundant channels is performed by comparing the signal levels.

[0031] S2.2.2: Reconstruction Verification: Based on the interface resource configuration templates of the target modal corresponding to the L2 real-time control layer and the L3 monitoring and service layer, the corresponding reconstruction task list is determined, and the reconstruction task list is used as the input of the parallel task scheduler to perform parameter configuration and driver initialization in parallel.

[0032] A signal intelligent control system for a multi-interface microcontroller uses any one of the above-described signal intelligent control methods for a multi-interface microcontroller.

[0033] Compared with the prior art, the beneficial effects of the present invention are:

[0034] Firstly, this invention constructs a hybrid prediction model that includes rule reasoning, temporal learning, and external event interpretation. This model can predict upcoming test mode transitions in advance, generate pre-scheduled instructions, pre-allocate and prepare interface resources for the target mode, and advance the resource preparation time, so that the actual switching process is completed instantly. Furthermore, the L1 safety critical layer signal achieves seamless physical layer takeover through hardware redundancy channels and zero-interruption switching technology, eliminating control interruptions caused by switching and improving the system's response speed to dynamic operating conditions.

[0035] Secondly, based on the criticality of interface resources, this invention divides them into an L1 safety critical layer, an L2 real-time control layer, and an L3 monitoring and service layer, and performs hierarchical parallel / sequential reconstruction, thereby optimizing the switching process. This ensures that critical tasks are not interfered with by non-critical tasks and meets the real-time requirements of complex industrial control systems for different levels of signals.

[0036] Thirdly, this invention uses a dual-active buffer to simultaneously copy data to the transmission queues of both the old and new physical channels, achieving uninterrupted transmission. The receiving side reads from the verified new channel and handles out-of-order packets and packet loss through a protocol with sequence numbers, timestamps, and forward error correction codes.

[0037] Fourthly, at the moment the switch is completed, the present invention sets a real-time data verification point to perform multiple verifications on the first frame of data for protocol compliance, business rationality and time sequence continuity. When the verification fails, it automatically corrects the error through compensation mechanisms such as data rollback, state interpolation or channel back-switching. This can prevent erroneous or hollow data from being injected into the application logic, realize seamless and highly reliable takeover of the data stream, and ensure business continuity.

[0038] Fifthly, by establishing a digital twin model for each target modality, this invention can pre-evaluate the performance of the interface resource configuration template in a simulation environment, output the expected KPI value, and collect the actual KPI data through a hardware performance counter and compare it with the expected value. When a performance deviation occurs, an early warning can be triggered, and the parameters can be adaptively adjusted using a fine-tuning strategy library. This allows for continuous optimization of resource configuration and improvement of overall energy efficiency and reliability. Attached Figure Description

[0039] Figure 1 This is a flowchart illustrating the intelligent signal control method of the present invention;

[0040] Figure 2 This is a schematic diagram illustrating the construction of the hybrid prediction model in this invention;

[0041] Figure 3 This is a schematic diagram of the hierarchical switching process for switching requests in this invention;

[0042] Figure 4 This is a schematic diagram illustrating the storage of interface-level resources in this invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] refer to Figure 1 This embodiment provides a method for intelligent signal control of a multi-interface microcontroller, which specifically includes the following steps:

[0045] Step S1: Predictive resource tiered switching. This involves setting corresponding interface resource configuration templates based on the operational requirements of each test modality, determining the required interface type, bandwidth, priority, and switching time limit for each test modality. Simultaneously, using a pre-defined modality prediction model, the conversion probability of each candidate module is obtained. Based on the conversion probability of each candidate module, the corresponding high-probability target conversion module is determined, and corresponding pre-scheduling instructions are generated.

[0046] Furthermore, the generated pre-scheduled instructions are combined with real-time acquired system status variables, external instructions, and interface health information, and compared with preset switching conditions to generate a switching request carrying the target modality identifier, emergency level, and pre-scheduled status.

[0047] Step S2: Tiered Switching of Interface Resources. This involves performing the corresponding switching operation based on the switching request generated in Step S1. Specifically, at the moment of switching, the switching data stream corresponding to the switching operation is managed through a set dual-active data buffer, and the first frame of data in the switching data stream undergoes multiple verifications through set real-time data verification points. Simultaneously, interface resources are switched based on the managed switching data stream and the switching operation corresponding to the switching request.

[0048] Step S3: Digital Twin Optimization. This involves processing the interface resource configuration template corresponding to the target mode through rule-based static analysis and simulation-based parameter extraction to set up the corresponding digital twin model, i.e., constructing a digital twin model of the MCU and peripheral interfaces. Specifically, a development toolchain (such as a configuration generator and timing analysis tool) is used to parse the parameters in the interface resource configuration template. The parsed parameters are then used as input to the communication stack simulation model or scheduling simulation tool, and the corresponding expected KPI values ​​(such as CPU utilization curves, bus utilization peaks, etc.) are output.

[0049] Furthermore, the corresponding actual KPI data is collected through the microcontroller's hardware performance counters (such as loop counting, cache hit / miss) and timers. The collected actual KPI data is then compared with the expected KPI values ​​output by the digital twin model to issue warnings based on the comparison results. At the same time, the parameters are adaptively adjusted through a set fine-tuning strategy library (which can be specifically set according to actual needs, so it is not specifically described in this embodiment).

[0050] Specifically, the actual KPI data obtained, the expected KPI values ​​obtained from the output, and the corresponding contextual information stream (such as the current additional status of the system, such as total CPU load, ambient temperature sensor readings, current operating mode identifier, and time information) are used as inputs to a preset rule set evaluator. The output is the corresponding event structure, which includes event type, warning level, source KPI, current value, expected upper limit, suggested action, and contextual information. For example, {Event type: performance deviation; Warning level: warning; Source KPI: communication delay; Current value: 1.5ms; Expected upper limit: 1.2ms; Suggested action: observe; Contextual information: system load = 85%}.

[0051] This embodiment also provides a signal intelligent control system for a multi-interface microcontroller, which uses the above-mentioned signal intelligent control method for a multi-interface microcontroller.

[0052] In this embodiment, the corresponding pre-scheduling instruction is determined by using the set interface resource configuration template and modal prediction model, and a corresponding switching request is generated. (See reference...) Figure 2 and Figure 3 This embodiment provides a method for tiered switching of predictive resources, which specifically includes the following steps:

[0053] Step S1.1: Prediction Mapping. This involves generating corresponding pre-scheduling instructions using the set modal prediction model, and then matching these pre-scheduling instructions with the set interface resource configuration template to obtain the corresponding pre-scheduling configuration template. Details are as follows:

[0054] Step S1.1.1: Template Construction. This involves setting up a corresponding interface resource configuration template based on the logical function of each known test mode (e.g., extreme stress test mode, low-power characteristic test mode, and multi-protocol concurrent test mode). This template includes the mode ID, logical channel identifier (e.g., "motor control bus"), communication protocol (e.g., SPI), predetermined bandwidth (e.g., 500kbps), dedicated time slice, data sampling rate / baud rate, priority of each data stream, list of key control signals (e.g., motor torque command, high-voltage interlock status), quality of service indicators (e.g., maximum latency, maximum jitter), and maximum switching latency threshold (e.g., fail-safe mode must be less than 1 millisecond).

[0055] In other words, the obtained modal ID, logical channel identifier, communication protocol, reserved bandwidth, exclusive time slice, data sampling rate / baud rate, priority of each data stream, control signal list, service quality indicators and maximum handover delay threshold are combined to construct the corresponding static template library (i.e., interface resource configuration template).

[0056] Step S1.1.2: Model Construction. This involves combining the rule inference engine, the temporal pattern learner, and the external event interpreter to construct a corresponding hybrid prediction model. Specifically, in this embodiment, the rule inference engine is a deterministic rule base obtained based on domain knowledge (such as system security specifications), the temporal pattern learner is a lightweight machine learning module (such as using a Hidden Markov Model (HMM) or a miniature Recurrent Neural Network (RNN), and the external event interpreter is a receiver that processes high-dimensional prediction or intent signals from other subsystems (such as the cloud).

[0057] Furthermore, in the real-time prediction process using the constructed hybrid prediction model, the current state vector (e.g., a fault code) is used as input to the rule inference engine, outputting a corresponding list of rule prediction candidates. Short-term historical sequences (e.g., modal sequences and key parameters from the past few seconds to minutes) are used as input to the time-series pattern learner, outputting a corresponding list of time-series prediction candidates. External event streams (e.g., cloud operation information and calendar schedules) are used as input to the external event interpreter, outputting a corresponding list of external prediction candidates. Simultaneously, the obtained rule prediction candidate lists, time-series prediction candidate lists, and external prediction candidate lists are combined, and multi-source information fusion and conflict resolution are performed through the prediction arbitrator in the hybrid prediction model, thereby obtaining the corresponding prediction target modality and its corresponding urgency level. It is worth noting that the prediction candidate list in this embodiment includes the prediction target modality, prediction start time, and internal confidence score.

[0058] Furthermore, when performing multi-source information fusion and conflict resolution using a predictive arbitrator, the predictive arbitrator weights and fuses the target modes from the rule-based prediction candidate list, the time-series prediction candidate list, and the external prediction candidate list based on the corresponding internal confidence scores in the prediction candidate list, to obtain a comprehensive confidence score for each target mode. Simultaneously, the comprehensive confidence scores for each target mode are compared, and the target modes are sorted in descending order according to their comprehensive confidence scores to determine the corresponding high-confidence target modes.

[0059] It is worth noting that when conflicting modes exist among the obtained target modality predictions, a preset priority strategy is used for mode determination. That is, the prediction target modality with higher priority is selected based on its priority level. Specifically, the preset priority strategy in this embodiment is as follows: the priority of the prediction target modality obtained by the rule inference engine is higher than the priority of the prediction target modality obtained by the temporal pattern learner, and the priority of the prediction target modality obtained by the temporal pattern learner is higher than the priority of the prediction target modality obtained by the external event interpreter.

[0060] Step S1.1.3: Pre-scheduling determination. This involves setting the corresponding active domain based on all interface resources actually used by the current operating mode (e.g., bus bandwidth, CPU time slice, DMA channels, and interrupt lines). Based on the high-confidence predicted target mode determined in step S1.1.2, the corresponding pre-scheduled domain is set. In other words, the set active domain, pre-scheduled domain, and the high-confidence predicted target mode determined in step S1.1.2 are combined to set the corresponding pre-scheduled task.

[0061] Furthermore, based on the target modality ID corresponding to the high-confidence predicted target modality, the corresponding interface resource configuration template is determined from the static template library constructed in step S1.1.1. Then, based on the determined interface resource configuration template, the interface resource configuration template corresponding to the preparatory domain is set. Simultaneously, based on the interface resource configuration template corresponding to the preparatory domain, the resource requirements corresponding to the preparatory domain (such as reserved bandwidth and exclusive time slices) are determined, and based on the determined resource requirements, the reserved resources corresponding to the scheduling kernel are set. Furthermore, based on the logical interfaces corresponding to the interface resource configuration templates of the preparatory domain, the driver context corresponding to each logical interface is set, including the pre-allocated buffer in memory, the parameter structure required for the initialization function, and the silent backup path corresponding to the critical signal channel.

[0062] Step S1.2: Fusion Trigger. This involves fusing the system state variables, external command events, interface health information obtained from the industrial site with the high-confidence predicted target mode determined in step S1.1.2 to obtain corresponding fusion information. Simultaneously, this fusion information is used as input to the configured mode arbitrator, which outputs a corresponding switching request.

[0063] Furthermore, the switching requests in this embodiment include event-triggered and predictive triggers. Event-triggered requests include event / safety triggers and status / planning triggers. Event / safety triggers are requests to switch modes when an emergency stop command is received, a safety interlock is triggered, or a fatal fault is detected. These requests are marked as the highest emergency level, and the highest priority requests can directly preempt any other process. Status / planning triggers are requests to switch modes when preset conditions are met or a planning command is received. Specifically, predictive triggers are requests corresponding to the pre-scheduled tasks set in step S1.1.3.

[0064] Step S1.3: Hierarchical Switching. Based on the switching request obtained in Step S1.2, hierarchical parallel / sequential reconstruction processing is performed within the set hard real-time time window. Specifically, in this embodiment, three interface levels are set according to the interface resources of the industrial control system, and multi-level parallel / sequential reconstruction processing is performed within the set hard real-time time window (i.e., the switching time window) based on these three interface levels. Specifically, the three interface levels in this embodiment include: L1 safety critical layer (i.e., signals related to personal and equipment safety, such as emergency stop circuits, safety door locks, safety torque shutdown signals, and combustible gas concentration exceeding limits interlocking), L2 real-time control layer (i.e., core production process control loops, such as servo axis position / speed loop control, PID adjustment loops, and synchronous motion control signals), and L3 monitoring and service layer (i.e., data acquisition (such as temperature and pressure historical records), parameter upload / download, diagnostic information, and non-real-time communication (such as HTTP)).

[0065] Furthermore, during the switching process, within the set hard real-time time window, the L1 safety-critical layer performs a hardware-level seamless switching. This means switching is done through hardware redundancy channels. For example, at the instant the switching command is issued, a hardware switching switch controlled by the safety PLC (such as a safety relay matrix or FPGA logic) switches the safety signal path from the old channel to a pre-established and verified backup channel. Simultaneously, the L2 real-time control layer performs deterministic reconstruction and verification. This means that, based on the interface resource configuration template determined in step S1.1.3, within the reserved CPU time slice and bus bandwidth, the corresponding interfaces are reconfigured in parallel and deterministically. For example, this includes reconfiguring the EtherCAT slave synchronization mode, setting the servo driver communication cycle, and establishing a new PID controller input / output mapping. Each control loop is independently verified after reconstruction (e.g., reading back configuration parameters and testing the communication of the first control cycle). Meanwhile, the L3 monitoring and service layer, based on the hardware-level seamless switching performed by the L1 safety-critical layer and the deterministic reconstruction and verification performed by the L2 real-time control layer, performs an orderly migration within the remaining time window of the hard real-time time window.

[0066] In this embodiment, interface resource switching is performed through the configured dual-active data buffer and the three interface levels corresponding to the switching request in step S1.3. (See reference...) Figure 4 This embodiment provides a method for hierarchical switching of interface resources, which specifically includes the following steps:

[0067] Step S2.1: Pre-switch guarantee. Based on the switch request obtained in Step S1.2, a conflict check is performed on the current system resource status, and the corresponding final switch plan is determined based on the conflict check results. Simultaneously, according to the three interface levels determined in Step S1.3, the resources corresponding to the current system resource status at the three interface levels are saved in an orderly manner. Specifically:

[0068] Step S2.1.1: Conflict Verification. This involves obtaining a snapshot of the current resource state based on the real-time occupancy of all physical and logical interface resources (e.g., CPU time slices, bus bandwidth, memory buffers, DMA channels). Simultaneously, this snapshot is compared with the interface resource configuration templates corresponding to the preparatory domain and the target modality corresponding to the switching request, as determined in Step S1.1.3, to identify the corresponding conflict detection results and conflict types. Specifically, the conflict types in this embodiment include exclusive resource conflicts, performance resource conflicts, and timing conflicts. An exclusive resource conflict occurs when the exclusive resource request corresponding to the target modality is already occupied in the current resource state snapshot. A performance resource conflict occurs when the minimum bandwidth or worst-case execution time corresponding to the target modality does not match the remaining available capacity in the current resource state snapshot (which can be specifically set based on idle time slices, bus utilization, etc., in the current resource state snapshot, and is therefore not specifically described in this embodiment). A timing conflict occurs when the switching time of the request corresponding to the target modality overlaps with the switching time in the interface resource configuration template corresponding to the preparatory domain, causing the total demand to exceed the physical limit.

[0069] Furthermore, when a conflict occurs during the comparison process, the corresponding degradation switching plan for the target mode is determined based on the conflict type and through a preset degradation plan library (which can be specifically set according to the actual target mode requirements, so it is not specifically described in this embodiment).

[0070] Step S2.1.2: Current Interface Saving. Based on the three interface levels determined in Step S1.3, identify all logical interfaces corresponding to the L1 security critical layer, L2 real-time control layer, and L3 monitoring and service layer. Then, based on the corresponding logical interface, determine the corresponding context saving list, including hardware register states (i.e., control registers, status registers, data registers, interrupt enable / status registers, etc.), runtime software states (i.e., the state machine inside the driver, read / write pointers of the circular buffer, incomplete DMA transfer descriptors, pending interrupt request queues, and protocol stack session states (e.g., TCP connection states)), and application layer associated states (i.e., intermediate calculation results of application tasks or control loops bound to the logical interface, filter historical data, etc.).

[0071] Furthermore, based on the priority levels of the L1 security critical layer, L2 real-time control layer, and L3 monitoring and service layer, the context save lists of all logical interfaces corresponding to each layer are saved hierarchically and stored in the corresponding dedicated rollback area. Specifically, in this embodiment, the priorities of the L1 security critical layer, L2 real-time control layer, and L3 monitoring and service layer are distributed in descending order. That is, during the hierarchical saving of the context save lists of logical interfaces, the context save lists of all logical interfaces corresponding to the L1 security critical layer are saved first, followed by the context save lists of all logical interfaces corresponding to the L2 real-time control layer, and finally the context save lists of all logical interfaces corresponding to the L3 monitoring and service layer.

[0072] It is worth noting that in this embodiment, the dedicated rollback area is located in non-volatile memory, and the physical memory range where the dedicated rollback area is located is marked so that only the context saving engine and the rollback recovery engine are allowed to perform write operations, while all other tasks (including the operating system kernel) only perform read operations on the physical memory range where the dedicated rollback area is located.

[0073] Step S2.2: Switchover Management. This involves performing a zero-disruption switchover for switchover requests corresponding to the L1 security-critical layer, and refactoring the switchover requests for the L2 real-time control layer and the L3 monitoring and service layer. Specifically:

[0074] Step S2.2.1: Zero-interruption switching. This involves setting up two redundant channels based on the control signals corresponding to the L1 safety-critical layer (e.g., emergency stop signals, safety interlocks), with both channels transmitting the same data simultaneously before switching. Specifically, each redundant channel is equipped with a hardware comparator to obtain the signal level corresponding to the redundant channel. The signal levels of each redundant channel are compared to ensure consistency. If the signal levels of the two redundant channels are inconsistent, a fault alarm will be triggered for manual verification.

[0075] Furthermore, the two redundant channels exchange information via control registers, and determine the corresponding switching command based on the input value of the control register. In other words, when the control signal corresponding to the L1 safety-critical layer requests a switching, the driver of one redundant channel is switched to the driver of the other redundant channel through the control register.

[0076] In other words, when monitoring the ADC sampling channel of the MCU core voltage, two redundant channels are set up: a main test channel and a backup channel. When the main test channel needs to be reconfigured due to test item switching, the backup channel can be seamlessly taken over by a hardware comparator, thereby ensuring uninterrupted voltage monitoring and preventing damage to the MCU under test during testing.

[0077] Step S2.2.2: Reconstruction Verification. Based on the interface resource configuration templates of the target modal corresponding to the L2 real-time control layer and the L3 monitoring and service layer, a corresponding reconstruction task list is determined. This list includes task grouping (grouping based on the physical independence and functional relevance of the interfaces), task dependencies (dependencies between tasks), and pre-loaded task markers (tasks that have completed resource pre-allocation and parameter pre-calculation during the prediction phase). Simultaneously, the determined reconstruction task list is used as input to the configured parallel task scheduler (i.e., functional logic components), performing parameter configuration and driver initialization on multiple independent peripheral control registers in parallel.

[0078] In other words, for tests requiring precise timing (such as PWM output accuracy testing), interface switching can be deterministically reconstructed within a reserved hard real-time window using interface resource configuration templates, and the configuration can be verified after reconstruction, thus ensuring that the timing accuracy of the next test pulse is not affected. Simultaneously, when printing test logs and reporting test progress, orderly migration can be carried out within the remaining time window after the switch between the L1 safety-critical layer and the L2 real-time control layer is completed, thus not affecting the execution of critical test tasks.

[0079] Step S2.3: Data Flow Control. During the handover critical period, the application layer data flow is controlled through a dual-active data buffer. Specifically, in this embodiment, the dual-active data buffer includes a logical buffer and an enhanced communication protocol. The logical buffer contains dual physical drivers, and the enhanced communication protocol uses a transmission mode with data packet sequence numbers, timestamps, and forward error correction codes. The application layer transmits data to be sent to the logical buffer. During the handover critical period, the dual physical drivers simultaneously copy and transmit the data sent by the application layer to the sending queues of two physical interfaces, including the target physical channel interface and the original physical channel interface. Simultaneously, the driver layer obtains the corresponding data through the receiving buffer of the target physical channel. It is worth noting that during the handover transmission process, data transmission is performed using a transmission mode with data packet sequence numbers, timestamps, and forward error correction codes (i.e., the enhanced communication protocol).

[0080] Furthermore, once the driver layer determines that the first frame of data in the target physical channel's receive buffer has been successfully received and reassembled, it verifies the received and reassembled first frame of data using various verification rules. If verification fails, the driver layer's compensation logic performs data compensation. Specifically, the verification rules in this embodiment include protocol compliance (i.e., checking CRC, frame format, etc.), business rationality (i.e., screening data content based on a predefined "reasonable value range" from the application layer (e.g., the rotational speed cannot jump instantaneously from 0 to the highest value), and temporal continuity (i.e., comparing the timestamp of this frame of data with the timestamp of the last valid frame of data received from the original physical channel interface to ensure the time interval is within the allowable jitter range). Simultaneously, the driver layer's compensation logic includes data rollback (i.e., determining the corresponding last frame of data based on the last buffered data of the original physical channel interface and using it as the corresponding "first frame of data"), state interpolation / prediction (i.e., generating the corresponding "virtual frame" based on the last few frames of data from the original physical channel interface using a prediction algorithm (e.g., linear extrapolation), and channel back-switching contingency plans (i.e., triggering a switchover manager alarm and initiating a back-switching evaluation).

[0081] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended embodiments and their equivalents.

Claims

1. A method for signal intelligent conditioning of a multi-interface microcontroller, comprising: Including: S1: Predictive resource hierarchical switching: Based on the operational requirements of each test modality, set the corresponding interface resource configuration template, and obtain the conversion probability of each candidate module through the modality prediction model to generate the corresponding switching request; S2: Interface resource hierarchical switching: The switching data stream corresponding to the switching request is managed through a dual-active data buffer. At the same time, the first frame data in the switching data stream is verified multiple times through the set real-time data verification points. The interface resource is switched through the switching data stream and the switching operation corresponding to the switching request. S3: Digital Twin Optimization: Based on the interface resource configuration template corresponding to the target modality, set the corresponding digital twin model, obtain the expected KPI value, and based on the comparison result between the expected KPI value and the actual KPI data, perform adaptive parameter adjustment through the set fine-tuning strategy library.

2. The method of claim 1, wherein, Generate the corresponding switching request, including: S1.1: Prediction Mapping: Generate corresponding pre-scheduling instructions through modal prediction models, and match the pre-scheduling instructions with interface resource configuration templates to obtain corresponding pre-scheduling configuration templates; S1.2: Fusion Trigger: The system state variables, external command events, interface health information and high-confidence predicted target modes obtained from the industrial site are fused to obtain the corresponding fusion information. At the same time, the fusion information is used as the input of the mode arbitrator and the corresponding switching request is output. S1.3: Hierarchical switching: Based on the interface resources of the industrial control system, set the interface hierarchy and perform multi-level parallel / sequential reconstruction processing within the hard real-time time window.

3. The intelligent signal control method for a multi-interface microcontroller according to claim 2, characterized in that, Obtain the corresponding pre-scheduled configuration template, including: S1.1.1: Template Construction: Based on the logical functions corresponding to the known control modes, set the corresponding interface resource configuration template, including mode ID, logical channel identifier, communication protocol, reserved bandwidth, exclusive time slice, data sampling rate / baud rate, priority of each data stream, control signal list, service quality indicators and maximum switching delay threshold; S1.1.2: Model Construction: The rule inference engine, time-series pattern learner and external event interpreter are combined to construct the corresponding hybrid prediction model. The current state vector, short-term history sequence and external event stream are used as inputs to the hybrid prediction model, and the output is to obtain the corresponding high-confidence prediction target mode. S1.1.3: Pre-scheduling determination: Based on all the interface resources actually occupied by the current running mode, set the corresponding active domain, based on the high-confidence predicted target mode, set the corresponding reserve domain, and combine the active domain, reserve domain and high-confidence predicted target mode to set the corresponding pre-scheduled task, and based on the target mode ID corresponding to the high-confidence predicted target mode, set the interface resource configuration template corresponding to the reserve domain.

4. The intelligent signal control method for a multi-interface microcontroller according to claim 3, characterized in that, The current state vector serves as the input to the rule inference engine, and the output obtains the corresponding rule prediction candidate list. The short-term historical sequence serves as the input to the time-series pattern learner, and the output obtains the corresponding time-series prediction candidate list. The external event stream serves as the input to the external event interpreter, and the output obtains the corresponding external prediction candidate list. At the same time, through the prediction arbitrator, multi-source information fusion and conflict resolution are performed on the rule prediction candidate list, the time-series prediction candidate list, and the external prediction candidate list to determine the corresponding prediction target mode and the corresponding urgency level.

5. The intelligent signal control method for a multi-interface microcontroller according to claim 2, characterized in that, The interface layer includes an L1 security critical layer, an L2 real-time control layer, and an L3 monitoring and service layer. The L1 security critical layer is switched through a hardware redundancy channel, the L2 real-time control layer is reconfigured through an interface resource configuration template, and the L3 monitoring and service layer is migrated in an orderly manner through the remaining time window.

6. The intelligent signal control method for a multi-interface microcontroller according to claim 1, characterized in that, Switching interface resources includes: S2.1: Pre-switch guarantee: Based on the switching request, perform a conflict check on the current system resource status, determine the final switching scheme based on the conflict check results, and simultaneously save the interface-level resources in an orderly manner according to the interface level. S2.2: Switching Management: Based on the interface resource level corresponding to the switching request, the switching request corresponding to the L1 security critical layer is switched with zero interruption, and the switching requests corresponding to the L2 real-time control layer and the L3 monitoring and service layer are reconstructed. S2.3: Data Flow Control: Simultaneously, a dual-active data buffer is set up using both logical buffers and enhanced communication protocols. The application layer data flow is controlled through the dual-active data buffers. At the same time, the first frame of data after receiving and reassembling is verified using multiple verification rules. If the verification fails, data compensation is performed through the compensation logic of the driver layer.

7. The intelligent signal control method for a multi-interface microcontroller according to claim 6, characterized in that, The orderly storage of interface-level resources includes: S2.1.1: Conflict Detection: Based on the real-time occupancy of all physical and logical interface resources, obtain the corresponding current resource status snapshot, and compare the current resource status snapshot with the interface resource configuration template corresponding to the preparatory domain and the interface resource configuration template of the target modality corresponding to the switching request to determine the corresponding conflict detection result and the corresponding conflict type. At the same time, based on the conflict detection result and conflict type, determine the corresponding degradation switching plan through the preset degradation plan library. S2.1.2: Current Interface Saving: Based on all logical interfaces corresponding to each interface level, determine the corresponding context saving list, and save the context saving list hierarchically according to the priority corresponding to the interface level, and save it to a dedicated rollback area.

8. The intelligent signal control method for a multi-interface microcontroller according to claim 7, characterized in that, The dedicated rollback area is located in non-volatile memory, and the physical memory range corresponding to the dedicated rollback area is marked so that only the context saving engine and the rollback recovery engine are allowed to perform write operations.

9. The intelligent signal control method for a multi-interface microcontroller according to claim 6, characterized in that, The switching requests corresponding to the L2 real-time control layer and the L3 monitoring and service layer will be restructured, including: S2.2.1: Zero-interruption switching: Based on the control signal corresponding to the L1 safety critical layer, two redundant channels are set up, and each of the redundant channels is equipped with a hardware comparator. At the same time, the signal level corresponding to the redundant channel is obtained through the hardware comparator, and the switching between the redundant channels is performed by comparing the signal levels. S2.2.2: Reconstruction Verification: Based on the interface resource configuration templates of the target modal corresponding to the L2 real-time control layer and the L3 monitoring and service layer, the corresponding reconstruction task list is determined, and the reconstruction task list is used as the input of the parallel task scheduler to perform parameter configuration and driver initialization in parallel.

10. A signal intelligent control system for a multi-interface microcontroller, characterized in that, The method for intelligent signal control of a multi-interface microcontroller as described in any one of claims 1-9 is used.

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