Data interaction method and device consistency circuit for computing fast link system

Abstract

The invention provides a data interaction method for computing a fast link (CXL) device. The data interaction method comprises the following steps: receiving a monitoring request or a writing request from a host by the CXL equipment; recording a target address pointed by the monitoring request or the writing request in a monitoring buffer of the CXL equipment by the CXL equipment; under the condition that the CXL equipment determines that the host has sent all monitoring requests or write requests or the monitoring buffer overflows, the CXL equipment sends a target address recorded in the monitoring buffer and a write pointer value corresponding to the target address to the host so as to request the host to send data in a host cache corresponding to the target address, therefore, the CXL equipment can receive the sent data; and when the CXL device determines that all the target addresses recorded in the listening buffer are sent to the host, the CXL device generates an emptying completion interrupt signal to indicate that data are received and written into the target addresses of the device memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and more particularly, to a data interaction method and a data processing method for a compute express link system. BACKGROUND

[0002] The compute express link (CXL) protocol is a cache-coherent interconnect protocol for processors, memory expansion, and accelerators. The CXL technology can achieve memory access consistency between the memory space of a host (e.g., a processor) and the memory space of an additional device, thereby allowing memory resource sharing to obtain better access and storage performance, reducing the complexity of the software stack, and reducing the cost of the computer system.

[0003] In order to achieve memory access consistency between the host and the additional device, the CXL.cache, a sub-protocol of CXL, adopts a device coherency engine (DCOH) technology or a hybrid coherency engine technology described in, for example, US2021 / 0200545A1. However, these coherency technologies have high design complexity, low efficiency, and can only actively initiate memory access from the additional device side (e.g., the accelerator side), which cannot be compatible with the business scenario of actively initiating memory access from the host side. In addition, the data interaction process between the host and the additional device in the existing CXL system also has reliability problems.

[0004] Therefore, it is necessary to provide an improved data interaction method and a data processing method for a CXL system. SUMMARY

[0005] An object of the present application is to provide an improved data interaction method and a data processing method for a CXL system to improve the efficiency and accuracy of data interaction between the CXL device and the host.

[0006] In one aspect of the present application, a data processing method for a compute express link (CXL) device is provided, the CXL device is coupled with a host through a CXL channel and has a device processor and a device memory, wherein the device memory and a host memory of the host are uniformly accessed by the host; the data processing method comprises: receiving, by the CXL device, a snoop request or a write request from the host, wherein each of the snoop request or the write request is directed to a target address in the device memory; recording, by the CXL device, the target address directed by the snoop request or the write request in a snoop buffer of the CXL device, wherein each of the recorded target addresses corresponds to a write pointer value of a write pointer of the snoop buffer; in a case where the CXL device determines that the host has sent all the snoop requests or the write requests or the snoop buffer is overflowed, the CXL device sends the target addresses recorded in the snoop buffer and the write pointer values corresponding thereto to the host to request the host to send data in a host cache corresponding to the target addresses, so that the CXL device can receive the sent data; and in a case where the CXL device determines that all the target addresses recorded in the snoop buffer are sent to the host, the CXL device generates an eviction completion interrupt signal to indicate that the data is received and written into the target addresses in the device memory.

[0007] In another aspect of the present application, there is also provided a data processing method for a computer system based on a Compute Express Link (CXL) protocol, the computer system comprising a host and a CXL device, the host and the CXL device being coupled to each other through a CXL channel, the host having a host processor and a host memory, the CXL device having a device processor and a device memory, wherein the device memory and the host memory are accessed uniformly by the host; the data processing method comprising: sending, by the host, snoop requests or write requests to the CXL device, wherein each of the snoop requests or write requests is directed to a target address in the device memory; recording, by the CXL device, the target addresses directed by the snoop requests or write requests in a snoop buffer of the CXL device, wherein each of the recorded target addresses corresponds to a write pointer value of a write pointer of the snoop buffer; in a case where the CXL device determines that the host has sent all of the snoop requests or write requests or the snoop buffer is full, the CXL device sending, to the host, the target addresses recorded in the snoop buffer and the write pointer values corresponding thereto, to request the host to send data in a host cache corresponding to the target addresses; sending, by the host, the data in the host cache corresponding to the target addresses to the CXL device, and receiving, by the CXL device, the data; and in a case where the CXL device determines that all of the target addresses recorded in the snoop buffer are sent to the host, the CXL device generating an eviction completion interrupt signal to indicate that the data is received and written into the target addresses in the device memory.

[0008] In another aspect of the present application, there is also provided a data processing method for a computer system based on a Compute Express Link (CXL) protocol, the computer system comprising a host and a CXL device, the host and the CXL device being coupled to each other through a CXL channel, the host having a host processor and a host memory, the CXL device having a device processor and a device memory, wherein the device memory and the host memory are accessed uniformly by the host; the data processing method comprising: sending, by the host, snoop requests or write requests to the CXL device, wherein each of the snoop requests or write requests is directed to a target address in the device memory; recording, by the CXL device, the target addresses directed by the snoop requests or write requests in a snoop buffer of the CXL device, wherein each of the recorded target addresses corresponds to a write pointer value of a write pointer of the snoop buffer; in a case where the CXL device determines that the host has sent all of the snoop requests or write requests or the snoop buffer is full, the CXL device sending, to the host, the target addresses recorded in the snoop buffer and the write pointer values corresponding thereto, to request the host to send data in a host cache corresponding to the target addresses; sending, by the host, the data in the host cache corresponding to the target addresses to the CXL device, and receiving, by the CXL device, the data; and in a case where the CXL device determines that all of the target addresses recorded in the snoop buffer are sent to the host, the CXL device generating an eviction completion interrupt signal to indicate that the data is received and written into the target addresses in the device memory.

[0009] In yet another aspect of the present application, there is also provided a device coherency circuit, comprising: a snoop buffer configured to receive and record snoop or write requests including target addresses, wherein the snoop buffer comprises a write pointer and a read pointer, and the snoop buffer is configured to update a value of the write pointer and a value of the read pointer according to a write condition of the requested target addresses and a read condition of the recorded target addresses; a reference write pointer value recording module coupled to the snoop buffer to receive a value of the write pointer from the snoop buffer as a reference write pointer value when the snoop buffer starts an eviction operation on the recorded target addresses; an address lookup module coupled to the snoop buffer to look up corresponding target addresses in the snoop buffer according to a current value of the read pointer in the snoop buffer; a request conversion module coupled to the address lookup module to convert the looked-up target addresses into RdOwnNoData requests defined by the CXL protocol, to send the RdOwnNoData requests and the corresponding target addresses to a host to allow receiving data from the host; a completion recording module configured to receive a completion flag from the host, the completion flag being used to indicate that a target address corresponding to a value of the read pointer corresponding to the RdOwnNoData request has completed data writing; wherein the completion recording module comprises a comparison pointer, and the completion recording module is further configured to update a value of the comparison pointer after each completion flag is completed; and a comparison module configured to compare the reference write pointer value with the comparison pointer value, and generate an eviction completion interrupt signal when they are equal to indicate that all the recorded target addresses in the snoop buffer have been processed.

[0010] The foregoing is a summary and may be simplified, generalized or omit details, therefore those skilled in the art should recognize that this section merely provides illustrative examples and is not intended to limit the scope of the present application in any way. This summary section is neither intended nor used to identify key or essential features of the claimed subject matter, nor used to build a base for determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other features of the present application will become more fully understood from the following detailed description and the accompanying drawings, wherein: It is to be understood that the drawings are only illustrative for several embodiments of the present application and they should not be considered limiting the scope of the present application. The present application will be described more fully with reference to the accompanying drawings, in which:

[0012] Figure 1 A computer system 100 based on the CXL protocol according to an embodiment of the present application is shown.

[0013] Figure 2 A computer system 100 based on the CXL protocol according to an embodiment of the present application is shown. Figure 1An exemplary process of the slave device 104 side performing data write operation steps in the computer system 100 shown.

[0014] Figure 3 An example of selective address recording by a snoop filter and snoop buffer according to one embodiment of the present application is shown.

[0015] Figure 4 A partial block diagram of a device coherency (DCOH) circuit according to one embodiment of the present application is shown. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and form part of this disclosure.

[0017] Figure 1 A computer system 100 based on CXL protocol according to one embodiment of the present application is shown. As shown, the computer system 100 includes a host 102 and a slave device 104, the host 102 and the slave device 104 are coupled to each other through a CXL channel 114 compliant with CXL protocol to enable data interaction between the two. In some embodiments, the slave device 104 can be a CXL Type 2 type of device, which can support all three CXL sub-protocols, CXL.io, CXL.cache, and CXL.mem, i.e., the slave device 104 can be referred to as a CXL device. Figure 1

[0018] ​The host 102 includes a host processor 106, which can be a special-purpose processor or a general-purpose processor (e.g., a CPU), and a host memory 108, which includes a host cache 107 with a plurality of cache lines. The slave device 104 can include a device processor 110, which can be any type of accelerator, such as an image processor, a tensor processor, a digital signal processor, etc., and a device memory 112. Through a CXL channel 114 between the host 102 and the slave device 104, the host 102 can access the device memory 112, such as writing data to the device memory 112 or reading data from the device memory 112. In some embodiments, the host 102 can access the device memory 112 in the slave device 104 through a CXL.mem channel compliant with the CXL.mem sub-protocol or interact with the slave device 104 through a CXL.cache channel compliant with the CXL.cache sub-protocol. In this case, the slave device 104, particularly in the example where the slave device 104 is an accelerator, has a device coherency engine DCOH internally, which can be used to handle coherency-related tasks, such as snooping the device cache of the slave device 104 with CXL.mem channel-based instructions.

[0019] The existing CXL.mem protocol specifies the implementation of the host 102 accessing the device memory 112 of the slave device 104. Specifically, according to the CXL.mem protocol, a transaction from the host 102 to the slave device 104 is referred to as an M2S transaction, and a transaction from the slave device 104 to the host 102 is referred to as an S2M transaction. The M2S transaction includes two types of messages, namely a request without data (Req) and a request with data (RwD), and the S2M transaction includes two types of messages, namely a response without data (NDR) and a response with data (DRS). Through these messages, the host 102 can directly access the device memory 112. However, the existing CXL protocol is complex for implementing device coherency, and in some cases, it can be desirable for the slave device 104 to perform more functions, so improvements can be made to the computer system 100.

[0020] For example, in some applications, the host 102 can need to offload an application running thereon or a part of the task in the application to the slave device 104 and run by the device processor 110 therein to take advantage of the data processing capability of the slave device 104. To address this need, the computer system 100 needs to map the storage space of the device memory 112 of the slave device 104 as a host-managed device memory (HDM) space, which is uniformly accessed by the host 102 together with the storage space of the host memory 108. Further, the task offloading of the application running and the access of the slave device 104 can be implemented based on the following interaction procedure.

[0021] Specifically, still referring to Figure 1 In step (1), the host processor 106 writes the data to be processed into the device memory 112 through the CXL channel 114 (specifically, through the CXL.mem channel). As aforementioned, the host 102 uniformly accesses the storage space of the host memory 108 and the device memory 112, thus the data to be processed written into the device memory 112 in step (1) can come from the host 102. Subsequently, the slave device 104 can notify the device processor 110 through an internal interaction procedure that the data to be processed has been written into the device memory 112, for example, the data required for performing a certain acceleration processing task has been written. In this way, in step (2), the device processor 110 can read out the data to be processed from the device memory 112 and perform corresponding processing on the data. In step (3), the device processor 110 writes the data processing result back into the device memory 112. Since steps (2) and (3) are internal operations of the slave device 104, they do not need the host 102 to participate in the execution. In step (4), the host processor 102 reads the data processing result from the device memory 112 through the CXL channel (specifically, through the CXL.mem channel) and optionally further processes the data processing result as needed. It should be noted that when the data processing result is written into the device memory 112 in step (3), the write address of the data processing result can partially overlap with the storage address of the data to be processed in the device memory 112, thereby affecting the write operation of the data processing result and further affecting the reading operation of the host in step (4). For this reason, when there is an overlap between the write address of the data processing result and the storage address of the data to be processed in the device memory 112, the overlapping address needs to be invalidated to ensure that the host can finally successfully read the data processing result generated by the device processor 110 from the device memory 112.

[0022] It can be seen that in the above operation, the slave device 104 can instruct the device processor 110 to perform the specified operation or operation with its internal interaction flow to realize the processing of data on the slave device 104. The internal interaction flow does not require the intervention of the host 102, so as to improve the operation efficiency of the computer system 100.

[0023] In order to realize Figure 1 In order to ensure that the data read out by the device processor 110 from the device memory 112 in step (2) is the latest written data when the host 102 serially writes a batch of data to the device memory 112 in the data write operation of step (1), the present application provides a method for data interaction between the host 102 and the slave device 104 based on the CXL protocol and the corresponding device in some embodiments.

[0024] Figure 2 An exemplary process of performing step (1) (i.e. data write operation) on the slave device 104 side in the computer system 100 shown is shown. Figure 1 It can be understood that although Figure 2 The host 102 side of the computer system 100 can perform corresponding responses and processing, although not shown in the present application. In some embodiments, the interaction between the host 102 and the slave device 104 can be realized by using the channel specified in the existing CXL protocol, that is, compatible with the existing CXL protocol. Next, the process of data interaction between the host 102 and the slave device 104 to realize the data write operation is described in detail in combination with Figure 1 and Figure 2 .

[0025] Specifically, in phase 1, the slave device 104 receives the monitoring request and the access request sent by the host 102, wherein the monitoring request and the access request respectively include the target address in the device memory 112 pointed to by the monitoring and access.

[0026] In some embodiments, the monitoring request can be a SnpData monitoring request specified in the CXL protocol, which is sent by the host 102 to the slave device 104 through the H2D request channel specified in the CXL.cache sub-protocol; and the access request can be a M2S transaction request specified in the CXL.mem sub-protocol, such as M2S Req request (no data required), which can include operation code MemWrFwd to indicate that the request is to perform a write operation.

[0027] The slave device 104 can include a snoop filter. The snoop filter can be provided in a device coherency engine (DCOH), for example, and can also include a snoop fifo and a snoop fifo controller (not shown in the figure). Through the snoop filter, snoop requests, access requests can be selectively buffered in the slave device 104. Specifically, a reference address range of a storage space in the device memory 112 can be preset in the snoop filter, and the snoop filter can determine whether a target address included in a received request is within the reference address range of the device memory 112 and whether the target address satisfies a coherency attribute. When the target address is within the reference address range of the device memory 112 and satisfies the coherency attribute, the target address is allowed to be buffered in the snoop fifo. The reference address range can be the address range of the device memory 112, for example. More details about the coherency attribute can be found in the relevant part of the CXL protocol, which will not be described in detail here.

[0028] In one embodiment, the snoop fifo can be a FIFO memory or a register, and the depth of the snoop fifo can be configured through a register. The snoop fifo includes a read pointer (Rd_ptr) and a write pointer (Wr_ptr), which respectively point to the current write-in and read-out positions (addresses of storage units of the snoop fifo) in the snoop fifo. After each write operation, the value of the write pointer can be automatically incremented by 1, i.e., moved to the next position to be written. After each read operation, the value of the read pointer can also be automatically incremented by 1, i.e., moved to the next position to be read. In this way, the addresses of the storage units currently written and currently read can be determined and recorded. The use of these pointers will be described in detail below.

[0029] The structure and principles of the present application are described below only with the access request as an example of a write request.

[0030] Specifically, during the process of receiving a listener request or write request in Phase 1, if the listener filter determines that the target address belongs to the reference address range, the slave device 104 can record the target address in the listener buffer. At this time, the current value of the write pointer of the listener buffer can correspond to the currently recorded target address, and the value of the write pointer can be automatically incremented by 1 to correspond to the next recorded target address. And so on. In some embodiments, the listener buffer only records the target address, so it does not distinguish whether the target address corresponds to a listener request or a write request. In addition, if multiple requests pointing to the same target address (e.g., a listener request and a write request, or two write requests) are received successively, the listener buffer will record the target address pointed to by these requests multiple times. That is, there will be multiple records in the listener buffer that include the same target address but correspond to different write pointer values. It should be noted that recording a target address multiple times does not affect the data being sent from the host 102 to the slave device 104, which will be further explained below.

[0031] Figure 3 An example of selective address recording using a listener filter and listener buffer according to one embodiment of this application is shown. Figure 3 As shown, multiple write requests 1-6 and multiple listen requests 1-2 are sent sequentially by the host to the slave device. Assuming the preset address range of the device memory in the listen filter is 0-15, then the target addresses of write requests 1-3 and listen requests 1-2 fall within this address range. If these target addresses also satisfy the consistency property, they can be recorded in the listen buffer through the listen filter. Write requests 4-6, whose target addresses do not fall within the address range, are filtered out by the listen filter. Furthermore, even if both write request 3 and listen request 1 point to target address 3, they will not be merged and recorded in the listen buffer. In this case, target address 3 will be recorded twice to indicate that the two corresponding requests from the host are recorded in the listen buffer, as recorded by write pointers 3 and 4 in the listen buffer.

[0032] Understandably, if the listening filter determines that the target address of the request is not within the reference address range, then the listening filter will not write the listening request into the listening buffer. In response to the listening request, the slave device can send, for example, an RspIHitI message to the host. In the CXL protocol, the RspIHitI message is used to indicate that the corresponding cache line has been cleared from the slave device.

[0033] Still referencing Figure 1 and Figure 2As shown, in some cases, particularly when the snoop buffer has a large depth or when the number of snoop requests and / or write requests that need to be buffered is small, the snoop buffer can be sufficient to record all of the target addresses that need to be sent to the slave device 104 without the snoop buffer overflowing. In such cases, the host 102 can send a request send completion notification to the slave device 104 to indicate that all of the snoop and access requests have been sent to completion by the host 102. Accordingly, upon receiving the completion notification, the slave device 104 can generate a flush enable command and enter stage 2. In one embodiment, the slave device 104 also includes a mailbox module that can be notified by the host 102 via memory mapped I / O (MMIO) to generate the flush enable command by the mailbox module.

[0034] The flush enable command can be provided to the snoop buffer, which determines and records the current value of the write pointer. It will be appreciated that the current value of the write pointer can be associated with the location of the last target address recorded in the snoop buffer, which can be used as a reference write pointer value for subsequent comparisons to determine whether all of the snoop and access requests for the recorded target addresses have been completed upon the slave device 104 generating the flush enable command.

[0035] Unlike the above case, in other cases, particularly when the number of requests to be buffered is large, the snoop buffer can overflow, i.e., the number of recorded target addresses has reached the maximum number of buffer entries of the snoop buffer, but not all of the snoop requests or write requests have been received and thus not all of the target addresses have been recorded. In such cases, the slave device 104 can generate the flush enable command and enter stage 2 upon the snoop buffer overflowing, and continue until the snoop buffer is not full or the slave device 104 generates an interrupt signal to subsequently receive new snoop requests or write requests and record new target addresses until all of the target addresses have been recorded. It will be appreciated that in cases where the number of target addresses to be recorded is large, the snoop buffer can generate the flush enable command multiple times to actively process the recorded requests in the snoop buffer.

[0036] In particular, still referring to Figure 1 and Figure 2 As shown, in stage 2, the slave device 104 sends the target addresses recorded in the snoop buffer in stage 1 to the host 102 along with the value of the read pointer corresponding to each target address. It will be appreciated that the value of the read pointer can be used to uniquely indicate the location of the corresponding target address in the snoop buffer, i.e., corresponding to the value of the write pointer.

[0037] In particular, when the amount of target addresses recorded in the snooping buffer has reached the depth of the snooping buffer (the maximum amount of data that can be recorded), i.e., the snooping buffer is full, or when the snooping buffer has recorded all the requested target addresses and is notified to empty the recorded target addresses, the snooping buffer can transfer the target addresses recorded therein, e.g., to the host 102. The slave device 104 (e.g., the snooping buffer controller) can read each record in the snooping buffer in order, and the value of the read pointer is automatically incremented by 1 each time a record is read until all records in the snooping buffer are read. The slave device 104 can convert the target address in each record read to a RdOwnNoData request for the cache line in the host cache 107 corresponding to the target address, and send the target address and the value of the read pointer at which the target address was read to the host as the ID of the RdOwnNoData request. For example, as shown in Figure 3 the read pointer initially points to the address at which the target address 1 is stored in the snooping buffer, and when the target address 1 is read, the current value of the read pointer (e.g., 1) can be sent to the host as the ID of the RdOwnNoData request corresponding to the target address 1, and the value of the read pointer is incremented by 1; at this time, the read pointer points to the address at which the target address 2 is stored, and when the target address 2 is read, the current value of the read pointer (e.g., 2) can be sent to the host as the ID of the RdOwnNoData request corresponding to the target address 2, and the value of the read pointer is again incremented by 1; and so on until all target addresses stored in the snooping buffer are read. It can be understood that Figure 3 the target address 3 stored twice in the snooping buffer can be sent to the host as two RdOwnNoData requests, and the two RdOwnNoData requests correspond to different IDs.

[0038] In some embodiments, the slave device 104 can send the RdOwnNoData request through the D2H request channel specified by the CXL.cache sub-protocol to request exclusive permission for the cache line in the host cache 107 corresponding to the target address.

[0039] The host 102 can match the target address in the received RdOwnNoData request with tags corresponding to cache lines in the host cache 107: if the target address matches a tag corresponding to a cache line in the host cache 107, it means that the host cache 107 has a cache line corresponding to the target address included in the RdOwnNoData request, i.e., a cache line hit; at this time, the slave device 104 receives a GO-E response message sent by the host 102 to indicate that the slave device 104 has obtained exclusive permission for the corresponding cache line, and the state of the corresponding cache line is set to exclusive (“Exclusive”) state, that is, the slave device 104 obtains exclusive ownership of the cache line. It can be understood that if there is no cache line corresponding to the requested target address in the host cache 107, the cache is not hit.

[0040] Next, at stage 3, after the slave device 104 obtains exclusive ownership of a cache line, the slave device 104 can continue to receive a write request sent by the host 102, and the write request can include a target address and write data; the slave device 104 can write the write data into the target address in the device memory 112 after receiving the write request. It can be understood that the write data is the data cached in the cache line in the host cache 107. In some embodiments, the host 102 can send a write request to the slave device through the CXL.mem channel. It can be understood that the write operation performed in stage 3 is the same as the write operation in the existing CXL.mem sub-protocol, and therefore more details thereof can be referred to the specific description in the CXL protocol, which will not be described here.

[0041] Since the response to the write request in this stage 3 includes the actual write operation, which is different from the step in stage 1 in which the buffered write request is only for subsequent processing reference or ordering without performing the write operation, the write request received by the slave device 104 in stage 3 can no longer be buffered into the listening buffer, but directly sent to the device memory 112. In other words, in stage 3, the listening buffer can be bypassed, so when the slave device 104 receives the write request at this time, the write request does not need to be received by the listening buffer. The bypassing of the listening buffer can be achieved by configuring a register, for example, configuring the register to be in the “no write to listening buffer” mode. In contrast, when the register is configured to be in the “write to listening buffer” mode, the listening buffer is enabled to receive and record the relevant request, just as the listening buffer performs in stage 1.

[0042] In phase 4, after receiving the write data, slave device 104 writes it to the corresponding target address in device memory 112 and sends a write response to host 102. This write response indicates that the data has been written to the corresponding target address in device memory 112. In this phase 4, the data in the corresponding cache line of host cache 107 is emptied and transferred to device memory 112. In some examples, slave device 104 can send a write response using an S2M message (e.g., a response without data, abbreviated as NDR) as specified in the CXL.mem sub-protocol. It can be understood that if multiple write requests are received in phase 3, slave device 104 can send multiple corresponding write responses to host 102 in this phase 4.

[0043] In phase 5, after receiving the write response, host 102 sends a completion flag to slave device 104. Along with the completion flag, the ID of the corresponding RdOwnNoData request is also sent; the ID is the value of the read pointer corresponding to the target address in the listener buffer. In some embodiments, host 102 can send the completion flag via an M2S message specified by the CXL.mem sub-protocol, such as the opcode MemRdFwd in the M2S message.

[0044] It should be noted that host 102 does not need to send write requests in the order they were received in phase 1 during phase 3. For example... Figure 3 As shown, for example, in stage 3, host 102 can first send a write request for target address 2 (whose corresponding read pointer is 2), and then send a write request for target address 4 (whose corresponding read pointer value is 5). That is, host 102 can send write requests "out of order" in stage 3. In stage 4, slave device 104 can perform write operations according to the order of the received write requests. For example, if slave device 104 receives a write request for target address 2 first, it will first perform the write operation corresponding to target address 2, and return a written response to host 102 after the write operation is completed. In stage 5, host 102 can send a completion flag and the corresponding ID according to the order of the received written responses.

[0045] It is noted that in stage 1, the host 102 can continuously send the snooping request and the access request to the slave 104, so as to record one or more target addresses in the snooping buffer. Therefore, during stages 2 to 5, the host 102 and the slave 104 can jointly complete the data write operation for at least one target address recorded in the snooping buffer in stage 1. The snooping buffer can also be further marked according to the completion flag received in stage 5, which will be further described below. It can be understood that in the case where multiple target addresses are included in the snooping buffer, the processes of stages 2 to 5 can be repeatedly executed multiple times to implement the processing of all target addresses recorded therein. In other words, in actual operation, it is not necessary to separately execute the operations of stages 2 to 5 for each target address or write / snoop request.

[0046] In some cases, the slave 104 can send the snooping or access request for the same target address to the host 102, for example Figure 3 The snooping buffer shown stores the target address 3 twice, but these same target addresses are recorded in the snooping buffer respectively and correspond to different IDs, i.e. the values of the write pointers. In some embodiments, when performing the write operation of stages 2 to 5, the two or more requests pointing to the same target address can be responded to by not repeatedly performing the write operation. Specifically, when the host 102 receives the first RdOwnNoData request including the target address 3, it can respond to the RdOwnNoData request for the target address 3 and, in the subsequent data interaction process, empty the data in the corresponding cache line of the host cache 107 to the slave 104 to store the data in the target address 3 of the slave 104. Then, the slave 102 sends the write completion response to the host 102, and the host 102 receives the write completion response and sends the completion flag and the corresponding ID to the slave 104. Unlike the processing of the first RdOwnNoData request, when the host 102 receives the second RdOwnNoData request including the target address 3, it can only send the completion response to the slave 104 (because the operation pointing to the target address 3 has been completed through the processing of the first request) without performing the corresponding write operation. In this way, each target address stored in the snooping buffer can be responded to and no conflict occurs.

[0047] In stage 6, upon receiving the completion tag and the corresponding ID sent by the host, the slave device 104 can determine the entry (i.e. the record corresponding to a target address) in the completion record module corresponding to the ID according to the ID, and mark the flag bit cmp_flag of the entry, for example, making cmp_flag = 1. If the entry corresponding to the currently marked flag bit cmp_flag is the same as the entry pointed to by the comparison pointer cmp_ptr, the comparison pointer is updated to point to the next entry, wherein the comparison pointer cmp_ptr is a read pointer in the completion record module. If the entry corresponding to the currently marked flag bit cmp_flag is not the same as the entry pointed to by the comparison pointer cmp_ptr, the comparison pointer cmp_ptr is not updated. If the entry pointed to by the updated comparison pointer cmp_ptr has been marked, the comparison pointer cmp_ptr is continuously updated to point to the next entry until the entry pointed to is not marked.

[0048] For example, assuming that 6 write requests are received in stage 1 and the 6 target addresses are stored in the listening buffer, when the completion tag and the ID corresponding to entry 3 are received by the slave device 104 for the first time in stage 6, the flag bit cmp_flag of entry 3 is marked, making cmp_flag = 1. Since the comparison pointer initially points to the position of entry 1, and the marked entry is not the same as the entry pointed to by the comparison pointer cmp_ptr, the comparison pointer cmp_ptr is not updated and still points to entry 1. When the completion tag and the ID corresponding to entry 1 are received by the slave device 104 for the second time, the flag bit cmp_flag of entry 1 is marked, and since the marked entry is the same as the entry pointed to by the comparison pointer cmp_ptr, the comparison pointer cmp_ptr is updated to point to entry 2. When the completion tag and the ID corresponding to entry 4 are received for the third time, the flag bit cmp_flag of entry 4 is marked and the comparison pointer cmp_ptr is not updated, and the comparison pointer cmp_ptr still points to entry 2. When the completion tag and the ID corresponding to entry 2 are received for the fourth time, the comparison pointer cmp_ptr is updated to point to entry 3, and since the flag bits cmp_flag of entries 3 and 4 have been marked, the comparison pointer cmp_ptr is continuously updated to point to entry 5, and so on, until the corresponding 6 entries are marked and the pointer is updated.

[0049] As indicated in stage 6, after each flagging of the cmp_flag in the entry, slave device 104 compares the current read pointer cmp_ptr with the write pointer (i.e., the reference write pointer value) recorded in stage 1 using the flush_en pulse. When the value of the comparison pointer increases to be equal to the reference write pointer value, a flush completion interrupt signal is generated to proceed with subsequent operations. This flush completion interrupt signal can be used to indicate that all target addresses recorded in the listen buffer have been processed.

[0050] Stage 6 allows the comparison pointer to be updated in the order the listener buffer receives requests, thus achieving "order-preserving" of instructions and serialization of writes. Therefore, even if the slave device 104 receives write requests from the host 102 out of order, it will not affect the data writing operation, which will proceed in the order the write requests were sent. Similarly, the slave device 104 can also perform order-preserving processing for other access requests issued by the host 102.

[0051] Figure 4 A partial module schematic diagram of a device conformance (DCOH) circuit according to one embodiment of this application is shown. In some embodiments, the device conformance circuit may be configured in... Figure 1 The device consistency engine DCOH is shown, and is used to perform... Figure 2 The data interaction processing is shown.

[0052] like Figure 4 As shown, the device consistency circuit may include a request receiving channel 402, which may include, for example, multiple sub-channels, to receive listen requests, read requests, and write requests from the host, respectively. Each request includes a corresponding target address, i.e., the address of the memory cell being accessed in the device memory. It is understood that in some embodiments, each sub-channel may be implemented in hardware, while in other embodiments, each sub-channel may be implemented in software.

[0053] Various access requests received by the request receiving channel 402 can be provided to the snoop filter 404 and processed by the snoop filter 404. Specifically, the snoop filter 404 can determine whether the target addresses included in the requests fall into the reference address range and satisfy the coherency properties, and only the requests falling into the reference address range and satisfying the coherency properties will be provided to the snoop buffer 406 and recorded by the snoop buffer 406. It can be appreciated that in some cases, the device coherency circuit can also forward the read requests and write requests received from the host to the downstream bus (e.g. the access bus of the device memory) and the device memory (not shown in the figure) without going through the snoop buffer 406, so that the slave device can access the device memory in response to these requests, and thus the request receiving channel 402 can also include an output interface coupled to the device memory to allow the read requests and write requests to be provided directly to the device memory bypassing the snoop filter 404 and the snoop buffer 406. In this way, the device memory can perform the access operations corresponding to the read requests or write requests in the normal processing flow and manner.

[0054] The structure and working principle of the device coherency circuit shown in Figure 4 It can be appreciated that more details about the circuit can be referred to the related description of the data interaction processing procedure shown in Figure 2 It can be appreciated that more details about the circuit can be referred to the related description of the data interaction processing procedure shown in

[0055] As described above in connection with Figure 2 The snoop buffer 406 can include a write pointer (wr_ptr) and a read pointer (rd_ptr) to update the value of the write pointer and the value of the read pointer according to the write cases of the requested target addresses and the read cases of the recorded target addresses. In some embodiments, the snoop buffer 406 can be a first-in-first-out buffer (FIFO). It should be noted that in the embodiments shown in Figure 4 In the embodiments shown in

[0056] In Figure 4In the illustrated embodiment, a flush enable (flush_en) command can be generated by the mailbox module 412 and provided to the reference write pointer value recording module 414. In some embodiments, the mailbox module 412 can be coupled to the host and receive a notification from the host indicating that all requests have been sent by the host; thus, the mailbox module 412 can generate a corresponding flush enable command. In addition, the mailbox module 412 can also be coupled to the snoop buffer 406 and receive an overflow notification from the snoop buffer 406 when the snoop buffer 406 overflows; thus, the mailbox module 412 can generate a corresponding flush enable command based on the overflow notification. As described in connection with the illustrated embodiment, when the number of requests to be buffered is large (e.g., exceeds the storage capacity of the snoop buffer 406), the snoop buffer 406 can overflow and generate an overflow notification to indicate to the mailbox module 412 to initiate a flush operation of the snoop buffer 406. Figure 2 As described in connection with the illustrated embodiment, when the number of requests to be buffered is large (e.g., exceeds the storage capacity of the snoop buffer 406), the snoop buffer 406 can overflow and generate an overflow notification to indicate to the mailbox module 412 to initiate a flush operation of the snoop buffer 406.

[0057] As another signal received by the comparison module 418, the comparison module 418 also receives updated values of the read pointer in the snoop buffer 406. Specifically, the device coherency circuit can include an address lookup module 408 that looks up a target address in the snoop buffer 406 based on a current value of the read pointer in the snoop buffer 406 (i.e., ID). After the target address is found, the device coherency circuit can convert the target address to a RdOwnNoData request through the request translation module 410 and subsequently send the RdOwnNoData request and the corresponding target address to the host through the D2H request channel. If there is a cache line in the host that corresponds to the target address included in the RdOwnNoData request, i.e., a cache line hit, the slave device can receive a GO-E response message from the host in response to the request to indicate that the slave device has obtained exclusive access to the corresponding cache line and the status of the corresponding cache line is set to exclusive. In this way, the slave device can receive write data from the host, which points to the corresponding target address in the device memory. As the slave device receives the write data, it can send a write done response to the host to indicate that the data has been written to the corresponding target address in the device memory; in this way, the host continues to send a completion tag to the slave device. The completion tag is sent together with the ID of the corresponding RdOwnNoData request. The completion tag can be received by the completion recording module 416 of the device coherency circuit, which records and updates the pointer value of the comparison pointer (cmp_ptr) based on the received completion tag and the corresponding ID. It can be appreciated that after each completion tag, both the comparison pointer and the read pointer in the snoop buffer 406 are incremented by one so that they can be updated to continue to read other target addresses.

[0058] Thus, the comparison module 418 in the snoop buffer can compare the reference write pointer value with the comparison pointer value: when the two values are equal, it means that all target addresses buffered in the snoop buffer 406 have been evicted, i.e., the emptying is completed. Accordingly, the comparison module 418 can generate an emptying completion interrupt signal at this time. The emptying completion interrupt signal can be provided to the device processor of the slave device, so that the device processor processes the data stored in the device memory, i.e., performs Figure 2 The processing operation of step (2) is shown.

[0059] It can be understood that the device coherency circuit can include an additional register for receiving configuration data to configure whether the data interaction method described in the embodiments of the present application needs to be implemented, i.e., whether the snoop request and the access request are buffered into the snoop buffer. In the case where the register is configured not to implement the data method described in the embodiments of the present application, the device coherency circuit can make the slave device work in the same way as the existing CXL.mem product and interact with the host.

[0060] It can be seen that the data interaction method of the CXL system, the data processing method, and the device coherency circuit of the present application have small hardware overhead, and are easy to design and implement. In addition, these methods and circuits can be well compatible with the existing CXL system and device, further reducing the application cost. In addition, by recording and marking the requests through the snoop buffer, the "order preservation" and write serialization of request processing can be achieved. Therefore, even if the requests are received from the host in disorder, it will not affect the operation of the data according to the order of the request, which greatly improves the stability and accuracy of data interaction.

[0061] In some embodiments, the present application also provides some computer program products, which include a non-transitory computer readable storage medium. The non-transitory computer readable storage medium includes computer executable code for performing the steps described in the above embodiments of the present application.

[0062] Embodiments of the application can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented by special logic; the software part can be stored in a memory and executed by a proper instruction execution system, such as a microprocessor or a specially designed hardware. A person of ordinary skill in the art can understand that the above-mentioned apparatus and method can be implemented by computer executable instructions and / or included in processor control code, for example, such code is provided on a carrier medium, such as a magnetic disk, CD or DVD-ROM, programmable memory, such as read-only memory (firmware), or data carrier, such as optical or electronic signal carrier. The apparatus of the application and its modules can be implemented by hardware circuit, such as very large scale integrated circuit or gate array, semiconductor, such as logic chip, transistor, or programmable hardware device, such as field programmable gate array, programmable logic device, or software executed by various types of processors, or a combination of the above-mentioned hardware circuit and software, such as firmware.

[0063] Although only the write request is taken as an example to introduce the circuit schematic structure and principle of the application, the application is not limited thereto, and can be applied to all requests, such as monitoring and access requests.

[0064] It should be noted that although several steps of the data interaction method and the data processing method for the CXL device and the computer system based on the CXL protocol and several modules of the device coherence circuit are mentioned in the above detailed description, such division is only exemplary and not mandatory. In fact, according to the embodiments of the application, the features and functions of two or more steps described above can be embodied in one step. Conversely, the features and functions of one step described above can be further divided into several steps.

[0065] Those of ordinary skill in the art can understand and implement other changes to the disclosed embodiments by studying the specification, disclosure content, and drawings and the appended claims. In the claims, the word "comprising" does not exclude other elements and steps, and the words "a" and "an" do not exclude a plurality. In the practical application of the present application, one part can perform the functions of multiple technical features referred to in the claims. Any reference signs in the claims should not be understood as limiting the scope.

Claims

1. A data interaction method for computing fast link (CXL) devices, characterized in that, The CXL device is coupled to the host via a CXL channel and has a device processor and a device memory, wherein the device memory and the host's host memory are accessed uniformly by the host. The data interaction method includes: The CXL device receives a listening request or a write request from the host, wherein each listening request or write request points to a target address in the device's memory; The CXL device records the target address pointed to by the listening request or write request in the listening buffer of the CXL device, wherein each recorded target address corresponds to a write pointer value of the write pointer of the listening buffer; If the CXL device determines that the host has sent all listen requests or write requests or the listen buffer has overflowed, the CXL device sends the target address recorded in the listen buffer and its corresponding write pointer value to the host to request the host to send the data in the host cache corresponding to the target address, so that the CXL device can receive the sent data. as well as When the CXL device determines that all target addresses recorded in the listening buffer have been sent to the host, the CXL device generates a drain completion interrupt signal to indicate that data has been received and written to the target address in the device memory.

2. The data interaction method according to claim 1, characterized in that, Prior to the step of the CXL device recording the target address pointed to by the listening request or write request in the listening buffer of the CXL device, the data method further includes: The steps include having the CXL device compare the target address with a predetermined reference address range using its monitoring filter, and, if the target address falls within the reference address range, continuing to record the target address in the monitoring buffer.

3. The data interaction method according to claim 1, characterized in that, The CXL device determines that all target addresses recorded in the listening buffer are sent to the host in the following manner: The CXL device will use the write pointer value corresponding to the last target address recorded in the listener buffer as the reference write pointer value; The listener buffer uses a read pointer to sequentially eject target addresses recorded therein for transmission to the host by the CXL device, wherein the read pointer is incremented by 1 each time a target address is ejected from the listener buffer and the CXL device determines that data has been written to the target address in the device memory; and When the read pointer value of the read pointer is equal to the reference write pointer value, the CXL device determines that all target addresses recorded in the listener buffer have been sent to the host.

4. The data interaction method according to claim 3, characterized in that, The CXL device determines that a target address in the device memory is to be written with data in the following manner: The CXL device receives write data from the host and writes the write data to the corresponding target address in the device's memory; The CXL device sends a write response to the host to indicate that the write data has been written to the target address; as well as The CXL device receives a completion flag from the host to indicate that the write operation for the target address has been completed.

5. The data interaction method according to claim 1, characterized in that, The step of the CXL device sending the target address recorded in the listening buffer and its corresponding write pointer value to the host includes: The CXL device uses the RdOwnNoData request specified in the CXL protocol to send the target address and the corresponding write pointer value.

6. A data interaction method for a computer system based on the Computational Fast Link (CXL) protocol, characterized in that, The computer system includes a host and a CXL device, the host and the CXL device are coupled to each other through a CXL channel, the host has a host processor and a host memory, and the CXL device has a device processor and a device memory, wherein the device memory and the host memory are accessed uniformly by the host. The data interaction method includes: The host sends a listen request or write request to the CXL device, wherein each listen request or write request points to a target address in the device's memory; The CXL device records the target address pointed to by the listening request or write request in the listening buffer of the CXL device, wherein each recorded target address corresponds to a write pointer value of the write pointer of the listening buffer; If the CXL device determines that the host has sent all listen requests or write requests or the listen buffer has overflowed, the CXL device sends the target address recorded in the listen buffer and its corresponding write pointer value to the host to request the host to send the data in the host cache corresponding to the target address. The host sends data from its host cache corresponding to the target address to the CXL device, and the CXL device receives the data; and When the CXL device determines that all target addresses recorded in the listening buffer have been sent to the host, the CXL device generates a drain completion interrupt signal to indicate that data has been received and written to the target address in the device memory.

7. The data interaction method according to claim 6, characterized in that, Prior to the step of the CXL device recording the target address pointed to by the listening request or write request in the listening buffer of the CXL device, the data method further includes: The steps include having the CXL device compare the target address with a predetermined reference address range using its monitoring filter, and, if the target address falls within the reference address range, continuing to record the target address in the monitoring buffer.

8. The data interaction method according to claim 6, characterized in that, The CXL device determines that all target addresses recorded in the listening buffer are sent to the host in the following manner: The CXL device will use the write pointer value corresponding to the last target address recorded in the listener buffer as the reference write pointer value; The listener buffer uses a read pointer to sequentially eject target addresses recorded therein for transmission to the host by the CXL device, wherein the read pointer is incremented by 1 each time a target address is ejected from the listener buffer and the CXL device determines that data has been written to the target address in the device memory; and When the read pointer value of the read pointer is equal to the reference write pointer value, the CXL device determines that all target addresses recorded in the listener buffer have been sent to the host.

9. The data interaction method according to claim 8, characterized in that, The CXL device determines that a target address in the device memory is to be written with data in the following manner: The CXL device receives write data from the host and writes the write data to the corresponding target address in the device's memory; The CXL device sends a write response to the host to indicate that the write data has been written to the target address; as well as The CXL device receives a completion flag from the host to indicate that the write operation for the target address has been completed.

10. The data interaction method according to claim 9, characterized in that, The step of the CXL device sending the target address recorded in the listening buffer and its corresponding write pointer value to the host includes: The CXL device uses the RdOwnNoData request specified in the CXL protocol to send the target address and the corresponding write pointer value.

11. A data processing method for a computer system based on the Computational Fast Link (CXL) protocol, characterized in that, The computer system includes a host and a CXL device, the host and the CXL device being coupled to each other via a CXL channel. The host has a host processor and a host memory, and the CXL device has a device processor and a device memory, wherein the device memory and the host memory are accessed uniformly by the host; the data processing method includes: The host writes data into the device memory of the CXL device through the CXL channel, wherein the data writing step is implemented by the data interaction method according to any one of claims 6 to 10; The CXL device reads the data from the device memory to the device processor, and the device processor processes the data. The CXL device writes the data processing results from the device processor back to the device memory; and The CXL device sends the data processing result to the host through the CXL channel.

12. A device consistency circuit, characterized in that, include: A listening buffer is used to receive and record listening or writing requests including a target address. The listening buffer includes a write pointer and a read pointer, and the listening buffer is used to update the values ​​of the write pointer and the read pointer according to the write status of the requested target address and the read status of the recorded target address. A reference write pointer value recording module is coupled to the listener buffer to receive the write pointer value from the listener buffer as a reference write pointer value when the listener buffer begins a drain operation on the recorded target address; The address lookup module is coupled to the listening buffer to look up the corresponding target address in the listening buffer based on the current value of the read pointer in the listening buffer; A request conversion module, coupled to the address lookup module, converts the target address to be looked up into an RdOwnNoData request as defined by the CXL protocol, and sends the RdOwnNoData request and the corresponding target address to the host, thereby allowing data to be received from the host; A completion recording module is configured to receive a completion flag from the host, the completion flag indicating that data writing has been completed at the target address corresponding to the value of the read pointer of the RdOwnNoData request; wherein, the completion recording module includes a comparison pointer, and the completion recording module is further configured to update the value of the comparison pointer after each completion flag is displayed; and The comparison module is used to compare the reference write pointer value with the comparison pointer value, and generate a drain completion interrupt signal when they are equal, to indicate that the target addresses recorded in the listening buffer have all been processed.

13. The device consistency circuit according to claim 12, characterized in that, Also includes: The mailbox module is used to receive notifications from the host and generate a drain enable command, thereby instructing the listening buffer to begin the drain operation.

14. The device consistency circuit according to claim 13, characterized in that, The mailbox module is also used to generate the drain enable command based on the overflow notification provided by the listening buffer.

15. The device consistency circuit according to claim 12, characterized in that, Also includes: A request receiving channel includes multiple sub-channels for receiving listen requests, read requests, and write requests from the host, respectively, wherein the request receiving channel is used to selectively provide the received requests to the listen buffer or the device memory coupled to the device coherence circuit.

16. The device consistency circuit according to claim 15, characterized in that, Also includes: A listening filter, coupled between the request receiving channel and the listening buffer, is used to filter received listening requests, read requests, and write requests, so as to provide the target address to the listening buffer if the target address included in the request falls within a predetermined reference address range.

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