JESD204B-oriented non-uniform-uniform data stream conversion system and operation method

Abstract

The invention provides a JESD204B-oriented non-uniform-uniform data stream conversion system and an operation method, belongs to the technical field of data conversion, and aims to solve the problem that data transmission between a PS end and a PL end of ZYNQ cannot meet a high-speed output scene, the conversion system comprises the PS end and the PL end, and the PS end is connected with the PL end through an AXIMM interface; the PS end comprises a DDR module, and the DDR module is used for storing waveform data to be transmitted; and the PL end comprises a DMA (Direct Memory Access) module, an asynchronous FIFO (First In First Out) module, a bit width conversion module and a JESD204B module which are connected in sequence. The operation method comprises the following steps: transmitting waveform data from the DDR module to the PL end through the data interface; the PL end carries out continuous reading, data stream buffering, data stream cross-clock processing and bit width conversion on the received waveform data, and finally the data is sent or received according to a JESD204B protocol specification after transmission layer framing, link layer processing and physical layer serialization are carried out by the JESD204B module.

Description

TECHNICAL FIELD

[0001] The application relates to a JESD204B-oriented non-uniform-uniform data stream conversion system and a running method, and belongs to the technical field of data conversion. BACKGROUND

[0002] With the continuous improvement of data transmission volume and data processing speed, serial communication gradually replaces parallel communication and becomes a development trend in the field of high-speed data transmission. The JESD204B (JEDEC Standard, JESD) protocol is a new generation of high-speed data converter interface standard, and is widely used for data transmission between a data converter and a signal processor due to its high bandwidth, low complexity and strong synchronization. However, the transmission rate of data between the PS end and the PL end of the ZYNQ is slow, and the data is a non-uniform data stream, which cannot meet the high-speed output scene. SUMMARY

[0003] The application is to solve the problem that the data transmission between the PS end and the PL end of the ZYNQ cannot meet the high-speed output scene, and further proposes a JESD204B-oriented non-uniform-uniform data stream conversion system and a running method.

[0004] The technical scheme adopted by the application to solve the above problem is that the JESD204B-oriented non-uniform-uniform data stream conversion system proposed by the application comprises: a PS end and a PL end, the PS end is connected with the PL end through an AXI_MM interface; the PS end comprises a DDR module, and the DDR module is used for storing waveform data to be transmitted; the PL end comprises a DMA module, an asynchronous FIFO module, a bit width conversion module and a JESD204B module connected in sequence; the DMA module is internally provided with an AXI DMA IP core, which is used for controlling the update of a descriptor chain table and reading internal parameters to indirectly control the continuous reading of the waveform data stored in the DDR, and outputting a non-uniform data stream; the asynchronous FIFO module is used for converting the non-uniform data stream into a uniform AXI-Streaming data stream and performing cross-clock domain processing; the bit width conversion module is internally provided with an AXI4-Stream Data Width Converter IP core, which is used for converting the bit width of the AXI-Streaming data stream processed in the cross-clock domain into a bit width required by the JESD204B module; the JESD204B module is used for transmitting or receiving data according to the JESD204B protocol.

[0005] Further, the AXI_MM interface has a bit width of one of 32 bits, 64 bits and 128 bits, and the AXI DMA IP core has a maximum data bit width of 1024 bits and supports a maximum clock of 240 MHz or above.

[0006] Further, the JESD204B module includes a transport layer, a link layer and a physical layer. When the JESD204B module is responsible for data transmission, it includes an AXI4-Stream data interface, TX transmission logic including scrambling logic, alignment character insertion logic and initialization link alignment sequence generation logic, a TX counter including control logic, a SYNC / SYSREF interface and state machine logic, a JESD204 PHY, an RPAT and a JSPAT test data generator, and an AXI4-lite configuration management interface. When the JESD204B module is responsible for data reception, it includes an AXI4-Stream data interface, RX transmission logic including ILA identification logic, descrambling logic, alignment character monitoring and replacement logic, a local multi-frame clock state machine and a SYNC / SYSREF interface, a JESD204 PHY, an error counter for monitoring data of each lane, and an AXI4-lite control management interface.

[0007] The operation method of the non-uniform-uniform data stream conversion system for JESD204B includes the following steps. Step 1: Store the waveform data to be transmitted in the DDR module of the PS end, and transmit the waveform data from the DDR module to the PL end through the data interface. Step 2: The DMA module of the PL end receives the waveform data, controls the automatic conversion of the data address through the configuration descriptor chain table, continuously reads the data in a loop mode, and outputs a non-uniform data stream. Step 3: Buffer the non-uniform data stream output by the DMA through the asynchronous FIFO module, convert it into a uniform data stream, and perform cross-clock domain processing. Step 4: Perform bit width conversion on the uniform data stream after cross-clock domain processing through the bit width conversion module. Step 5: Input the converted data stream into the JESD204B module, frame it through the transport layer, process it through the link layer, and serialize it through the physical layer, and then transmit or receive the data according to the JESD204B protocol specification.

[0008] Furthermore, in step 2, the DMA module is made to work in SGDMA mode by using the AXI DMA IP core of the DMA module. SGDMA mode enables continuous data reading by ignoring the completion status bit of the descriptor until an error occurs. The descriptor list contains the starting address of the data storage and the read length parameter.

[0009] Furthermore, step 5 involves sending or receiving data according to the JESD204B protocol specification, specifically including: When the JESD204B module sends data according to the JESD204B protocol specification, the transport layer frames the data stream output by the bit width conversion module. The framed data is then transmitted to the physical layer via the link layer. The physical layer sends the processed data to the serializer for serial data transmission. When the JESD204B module receives data according to the JESD204B protocol specification, the physical layer deserializes the data stream output by the bit width conversion module and sends it to the link layer. The link layer performs corresponding operations on the data and sends it to the transport layer. The transport layer deframes the data to obtain the received data and sends it to the data processing unit.

[0010] The beneficial effects of this invention are: 1. This invention realizes the data stream transmission from the DDR end to the PL end of the ZYNQ PS end, and the communication rate can reach 12.5Gbps by converting non-uniform to uniform data streams; 2. This invention realizes the clock domain conversion and bit width conversion functions between the front-end data processing module and the back-end data transmission module.

[0011] 3. The operation method of the non-uniform-uniform data stream conversion system for JESD204B proposed in this invention has certain universality with other types of serial communication protocols. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the non-uniform to uniform data stream conversion system for JESD204B provided by the present invention. Figure 2 This is a schematic diagram of the DMA loop provided by the present invention; Figure 3 This is a schematic diagram of the JESD204B protocol data flow provided by the present invention; Figure 4 A flowchart illustrating the operation method of the non-uniform to uniform data stream conversion system for JESD204B provided by this invention. Figure 5 For this embodiment, the Zynq UltraScale+ series XCZU7EV-2FFVC1156 chip was selected, according to the JESD204B protocol requirements and...Figure 4 The data flow direction, and a schematic diagram of the overall data flow conversion structure designed with AD9164; Figure 6 This is a schematic diagram of the clock wiring in an embodiment. Detailed Implementation

[0013] Specific Implementation Method 1: In this implementation method, DDR stands for Double Data Rate Synchronous Dynamic Random Access Memory, and DMA stands for Direct Memory Access Memory. Figure 1 and Figure 2 This implementation method is described as follows: Figure 1 As shown, the structure of the non-uniform to uniform data stream conversion system for JESD204B described in this embodiment includes: The ZYNQ platform includes a PS end and a PL end. The PS end includes a DDR module, which is used to store waveform data to be processed. It is connected to the PL end through the AXI_MM interface, and the bit width of the AXI_MM interface can be selected as 32bit, 64bit, or 128bit.

[0014] The PL side includes a DMA module, an asynchronous FIFO module, a bit-width conversion module, and a JESD204B module connected in sequence. Direct Memory Access (DMA) enables data exchange between memory and high-speed peripherals, greatly improving transmission speed. Based on this, the AXI DMA IP core can control high-bandwidth direct memory access between memory and AXI4-Stream type target peripherals. The AXI DMA IP core has a maximum data bit width of 1024 bits and supports a maximum clock speed of over 240MHz. The DMA loop is as follows... Figure 2 As shown. It has a built-in AXI DMA IP core, which can be configured to work in SGDMA mode. This mode indirectly controls the reading of DDR storage data by controlling the update and reading of internal parameters of the buffer descriptor (BD).

[0015] The asynchronous FIFO module has a built-in AXI4-Stream Data Width Converter IP core, which is used to convert non-uniform data streams into uniform AXI-Streaming data streams and perform cross-clock domain processing; The bit width conversion module is used to convert the bit width of the AXI-Streaming data stream after cross-clock domain processing to the bit width required by the JESD204B module; The JESD204B module is used to send or receive data according to the JESD204B protocol, and includes the transport layer, link layer, and physical layer. When the JESD204B module is responsible for data transmission, it includes the AXI4-Stream data interface; TX transmission logic, including scrambling logic, alignment character insertion logic, and initialization link alignment sequence generation logic; TX counter, including control logic, SYNC / SYSREF interface, and state machine logic; JESD204 PHY; RPAT and JSPAT test data generators; and AXI4-lite configuration management interface. When the JESD204B module is responsible for data reception, it includes the AXI4-Stream data interface; RX transmission logic, including ILA identification logic, descrambling logic, alignment character monitoring and replacement logic; local multi-frame clock state machine and SYNC / SYSREF interface; JESD204 PHY; error counter for monitoring data in each lane; and AXI4-lite control management interface.

[0016] The JESD204B module transmits data to the DAC connected to the peripheral device.

[0017] Specific Implementation Method Two: Combining Figure 3 and Figure 4 This embodiment will be described as follows: Figure 4 As shown, the steps of the operation method of the non-uniform-to-uniform data stream conversion system for JESD204B described in this embodiment include: S1: Store the waveform data to be transmitted in the DDR module of the PS end, and transmit the waveform data from the DDR module to the PL end through the data interface; S2: The DMA module at the PL end receives waveform data, enters SGDMA mode, and continuously reads data until an error occurs. The AXI DMA IP core can be configured to operate in SGDMA mode. This mode automatically adjusts the address according to user needs, requiring only one startup to read waveform data based on the given starting address and read length. Furthermore, the distributed DMA mode also provides a circular mode. Compared to the single-operation mode, which operates only once on the descriptor chain and stops after the last descriptor completes, the circular mode ignores the completion status bit of the descriptor itself and only stops DMA when a read error occurs. This invention uses the circular mode of the distributed DMA mode to complete data reading.

[0018] S3: The non-uniform data stream output by the DMA is buffered by the asynchronous FIFO module, converted into a uniform data stream, and processed across clock domains. To meet the data format requirements of the JESD204B protocol, the AXI_MM waveform data read from DDR needs to be converted into an AXI-Streaming data stream, thus requiring high-speed, high-bandwidth data format conversion. The clock of the JESD204B transmitter is provided by an external clock source, which is not the same clock source as the preceding data conversion module; therefore, cross-clock domain data processing is also necessary. This implementation uses an asynchronous FIFO module to convert the DDR clock to the transceiver clock of the JESD204B IP core, and then sends it to the data bit-width conversion module, ensuring that subsequent data can be continuously and accurately delivered to the JESD204B module.

[0019] S4: The bit width conversion module performs bit width conversion on the uniform data stream after cross-clock domain processing; The data width conversion is implemented by the AXI4-Stream Data Width Converter IP core, which converts the width from DDR to the width required by the JESD204B module.

[0020] S5: Input the converted data stream into the JESD204B module. After framing at the transport layer, processing at the link layer, and serialization at the physical layer, the data is sent or received in accordance with the JESD204B protocol specification.

[0021] The JESD204B module consists of a transport layer, a link layer, and a physical layer. At the transmitting end, the transport layer first frames the sample data. The framed data then passes through the link layer to the physical layer, where it is processed and sent to a serializer for serial data transmission. At the receiving end, the physical layer first deserializes the data from the data converter before sending it to the link layer. The link layer performs the necessary operations and sends the data to the transport layer. Upon receiving the data, the transport layer deframes it to obtain the received data and sends it to the data processing unit. The JESD204B protocol data flow is as follows: Figure 3 As shown.

[0022] This implementation uses the JESD204 and JESD204 PHY IP core provided by Xilinx for functional implementation. Each link (one JESD204 IP core) supports a maximum of 8 lanes, with a supported speed range of 1Gbps to 12.5Gbps. This IP core can be configured as a transmitter or receiver, but not for simultaneous transmission and reception. When the IP core is configured as a transmitter communicating with the DAC, it mainly includes the following modules: 1. AXI4-Stream data interface; 2. TX transmission logic: scrambling logic, alignment character insertion logic, and initialization link alignment sequence generation logic; 3. TX counter: control logic, SYNC / SYSREF interface, and state machine logic; 4. JESD204 PHY (mainly the MGT module); 5. RPAT and JSPAT test data generators; 6. AXI4-lite configuration management interface.

[0023] When the IP core is configured for receiver-ADC communication, it mainly includes the following modules: 1. AXI4-Stream data interface; 2. RX transmission logic: ILA identification logic, descrambling logic, alignment character monitoring and replacement logic; 3. Local Multi-Frame Clock (LMFC) state machine and SYNC / SYSREF interface; 4. JESD204 PHY (mainly for MGT module); 5. Error counter (monitors data for each lane); 6. AXI4-lite control and management interface.

[0024] Example This embodiment selects the Zynq UltraScale+ series XCZU7EV-2FFVC1156, whose high-speed serial transceiver is of type GTHE4. This is in accordance with the JESD204B protocol requirements and... Figure 4 The data flow at the transmitting end is designed in conjunction with the AD9164. The overall design architecture diagram is as follows. Figure 5 As shown, the ADF4355 is a clock generation chip that can perform frequency multiplication and other operations on the onboard 120MHz crystal oscillator or the external crystal oscillator. The AD9508 is a clock fan-out chip used to generate the device clock and the SYSREF reference signal. The HMC849A is used to select whether the DAC clock on the board is provided by the ADF4355 or by the external clock. The AD9164 is a 16-bit, 12GSPS digital-to-analog converter.

[0025] Clock connection as Figure 6 As shown, the DAC device clock, SYSREF signal, and reference clock of the high-speed transceiver GTHE4 need to be provided, while the operating clock of the data synchronization module required by the JESD204B transmitter FPGA is obtained from the reference clock of GTHE4.

[0026] The crystal oscillator uses a 120MHz clock, and a 5GHz clock is generated by the ADF4355. The 5GHz clock is the sampling clock of the AD9164, while the GTHE4 reference clock REF is 250MHz, and the clock of the transmitting device is also equal to 250MHz. The SYSREF signal is selected as a pulse periodic type, which is better for resynchronization or LMFC phase alignment design. The SYSREF signal provided for the DAC must meet the following design requirements: (1) Pulse width requirement: at least 4 device cycles. (2) SYSREF must satisfy the establishment and hold relationship with the device clock. Since the device clock and SYSREF are from the same source, the establishment and hold relationship is satisfied. According to the link parameters, SYSREF can be calculated to be 15.625MHz.

[0027] Figure 5 The overall architecture shown is operated as follows: 1) Clock design: Configure the clock according to the JESD204B protocol and the data transmission rate that it should achieve. The main components are the device clock, reference signal, synchronization signal and the sampling clock of the downstream device (AD9164 in this case). 2) Power on the board, perform hardware initialization and configure registers. The relevant registers can be configured through the PS terminal of the FPGA, mainly the clock chip, AD9164 and JESD204B protocol. 3) Data transmission design: Assemble the data to be transmitted into the data format required by the JESD204B protocol; 4) Descriptor design: Design descriptors based on the storage location of the data to be sent; 5) Start transmission: The Serdes transceiver on the PL end encodes the data and converts it into serial data. It outputs the data to the SFP through the differential output port using a local high-precision clock and then sends it out through the transmission medium.

[0028] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A non-uniform to uniform data stream conversion system for JESD204B, characterized in that, include: The PS terminal and the PL terminal are connected via an AXI_MM interface; The PS terminal includes a DDR module, which is used to store waveform data to be transmitted; The PL terminal includes a DMA module, an asynchronous FIFO module, a bit width conversion module, and a JESD204B module connected in sequence. The DMA module has a built-in AXI DMA IP core, which is used to control the update of the descriptor linked list and read internal parameters, thereby indirectly controlling the continuous reading of waveform data stored in DDR and outputting a non-uniform data stream. The asynchronous FIFO module is used to convert non-uniform data streams into uniform AXI-Streaming data streams and perform cross-clock domain processing. The bit width conversion module has a built-in AXI4-Stream Data Width Converter IP core, which is used to convert the bit width of the AXI-Streaming data stream after cross-clock domain processing into the bit width required by the JESD204B module; The JESD204B module is used to send or receive data according to the JESD204B protocol.

2. The non-uniform to uniform data stream conversion system for JESD204B according to claim 1, characterized in that, The AXI_MM interface has a bit width of 32bit, 64bit, and 128bit, and the AXI DMA IP core has a maximum data bit width of 1024 bits and a maximum clock speed of 240MHz or higher.

3. The non-uniform to uniform data stream conversion system for JESD204B according to claim 1, characterized in that, The JESD204B module includes a transport layer, a link layer, and a physical layer; When the JESD204B module is responsible for data transmission, it includes the AXI4-Stream data interface; TX transmission logic, including scrambling logic, alignment character insertion logic, and initialization link alignment sequence generation logic; TX counter, including control logic, SYNC / SYSREF interface, and state machine logic; JESD204 PHY; RPAT and JSPAT test data generators; and AXI4-lite configuration management interface. When the JESD204B module is responsible for data reception, it includes the AXI4 - Stream data interface; RX transmission logic, including ILA identification logic, descrambling logic, alignment character monitoring and replacement logic; local multi-frame clock state machine and SYNC / SYSREF interface; JESD204 PHY; error counter for monitoring data in each lane; and AXI4 - lite control and management interface.

4. A method for operating a non-uniform to uniform data stream conversion system for JESD204B, applied to the non-uniform to uniform data stream conversion system for JESD204B as described in any one of claims 1-3, characterized in that it includes: Step 1: Store the waveform data to be transmitted in the DDR module of the PS end, and transmit the waveform data from the DDR module to the PL end through the data interface; Step 2: The DMA module at the PL end receives waveform data, controls the automatic change of data address through the configuration descriptor linked list, continuously reads data in a loop mode, and outputs a non-uniform data stream; Step 3: Buffer the non-uniform data stream output by DMA through the asynchronous FIFO module, convert it into a uniform data stream, and perform cross-clock domain processing; Step 4: Perform bit width conversion on the uniform data stream after cross-clock domain processing using the bit width conversion module; Step 5: Input the converted data stream into the JESD204B module. After framing at the transport layer, processing at the link layer, and serialization at the physical layer, the data is sent or received in accordance with the JESD204B protocol specification.

5. The operation method of the non-uniform-to-uniform data stream conversion system for JESD204B according to claim 4, characterized in that, In step 2, the DMA module is made to work in SGDMA mode by using the AXI DMA IP core of the DMA module. SGDMA mode enables continuous data reading by ignoring the completion status bit of the descriptor until an error occurs. The descriptor list contains the starting address of the data storage and the read length parameter.

6. The operation method of the non-uniform-to-uniform data stream conversion system for JESD204B according to claim 4, characterized in that, Step 5 involves sending or receiving data according to the JESD204B protocol specification, specifically including: When the JESD204B module sends data according to the JESD204B protocol specification, the transport layer frames the data stream output by the bit width conversion module. The framed data is then transmitted to the physical layer via the link layer. The physical layer sends the processed data to the serializer for serial data transmission. When the JESD204B module receives data according to the JESD204B protocol specification, the physical layer deserializes the data stream output by the bit width conversion module and sends it to the link layer. The link layer performs corresponding operations on the data and sends it to the transport layer. The transport layer deframes the data to obtain the received data and sends it to the data processing unit.

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