NoC congestion control method based on redundant data merging

Abstract

The invention discloses an NoC congestion control method based on redundant data merging, and relates to the technical field of general parallel computing and network-on-chip. Aiming at NoC congestion caused by redundant data transmission in a general parallel computing architecture and a bottleneck problem of a memory controller caused by the NoC congestion, an adopted scheme comprises the following steps of: marking cache requests from different SMs and aiming at the same cache block by integrating a grouping and merging unit in the memory controller; and after the memory controller accesses and obtains the cache blocks, injecting the cache blocks into the NoC according to the request marks, combining the cache blocks shared by the plurality of SM into a single data packet by utilizing the NoC characteristics, and sending the single data packet to each SM initiating the request through multicast routing. The method is applied to a general parallel computing architecture, and transmission of redundant data in the NoC can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of general-purpose parallel computing and network-on-chip, in particular to a NoC congestion control method based on redundant data merging. BACKGROUND

[0002] General-purpose parallel computing architecture relies on tens of concurrent stream multiprocessors (full name: Streaming Multiprocessor, abbreviated as SM, which is the core computing unit in NVIDIA GPU architecture) to achieve high parallel computing, but a large number of parallel thread executions bring great pressure to the memory system, and the memory bandwidth becomes the key performance bottleneck, which further causes the memory access delay of the general-purpose parallel computing processor to increase. With the development of technology, the memory controller in the general-purpose parallel computing processor does not increase with the increase of the SM, which further aggravates the memory bottleneck; at the same time, due to the extension of the memory access time, the delay hiding effect of the thread bundle scheduling strategy becomes poor, which finally leads to the decline of the overall performance.

[0003] In the memory bottleneck, the memory controller bottleneck causes the increase of the access delay to a great extent. In the memory access process of the general-purpose parallel computing processor, even if the data is ready to be sent, due to the limited terminal bandwidth at the memory controller router, a large amount of data returned from the memory controller to the SM still cannot be injected into the network-on-chip (NoC). This situation is particularly serious when there is a large amount of redundant data, which refers to the data shared by multiple SMs - the sharing of these redundant data by multiple SMs will cause multiple access requests for the data in the access system, and these requests will all reach the memory controller through the NoC; after the memory controller obtains the cached data, the data will be sent to the requesting SM respectively, and the transmission of a large amount of redundant data further aggravates the memory access delay and network bandwidth pressure. SUMMARY

[0004] The present application provides a NoC congestion control method based on redundant data merging, aiming at the NoC congestion caused by the transmission of redundant data in the general-purpose parallel computing architecture and the memory controller bottleneck problem caused thereby.

[0005] The technical solution adopted by the NoC congestion control method based on redundant data merging of the present application to solve the above technical problems is as follows:

[0006] A NoC congestion control method based on redundant data merging is applied to a general-purpose parallel computing architecture, a packet merging unit is integrated in a memory controller to mark cache requests from different SMs and for the same cache block; after the memory controller accesses the cache block, the cache block is injected into the NoC according to the request mark, and the cache block shared by multiple SMs is merged into a single data packet by using the characteristics of the NoC, and then the cache block is sent to each SM that initiates the request by multicast routing.

[0007] Optionally, the general-purpose parallel computing architecture includes an SM, a NoC, a memory controller and a DRAM; wherein:

[0008] The SM is an operation core unit, which internally includes an instruction pipeline and an L1 cache unit; the instruction pipeline is a core path of thread execution, and in an execution phase, a plurality of threads in a thread bundle are distributed to respective SPs for execution; meanwhile, the instruction pipeline internally integrates a thread bundle scheduling unit for implementing thread bundle scheduling and branch jump control, a register file unit for caching data and intermediate calculation results in an operation process, and a shared memory unit for data exchange between thread bundles and threads; the L1 cache unit is connected to the NoC, and is used to save data and instructions obtained from the L2 cache unit;

[0009] The memory controller internally integrates a packet merging unit and an L2 cache unit; the packet merging unit is used to merge and process cache requests from different SMs and for the same cache block, and to merge the cache block obtained based on the request into a single data packet; the L2 cache unit is used to prefetch data in a global memory by a merging access mode, and each memory controller is connected to a plurality of L2 cache units to implement access to an external DRAM;

[0010] The NoC connects the L2 cache unit and the L1 cache unit of each SM to realize efficient transmission of data.

[0011] Further optionally, the packet merging unit processes cache requests from different SMs and for the same cache block by packet merging, and specifically includes two stages of request grouping and reply merging;

[0012] In the request grouping stage, the packet merging unit aggregates access requests for the same cache block from multiple SMs into a request group within a preset time window, retains only the first request and marks all related SMs as destination ends, and discards repeated requests for the cache block from the remaining SMs;

[0013] In the reply merging stage, when the cache block based on the same access request is returned from the memory system, the packet merging unit associates the cache block with all marked destination SMs in the request group, and synchronously sends the cache block to all destination SMs by NoC multicast routing.

[0014] Further alternatively, the request grouping phase specifically includes the following processes:

[0015] When a request for cache block a from a certain SM reaches the memory controller, if there is no active request group for cache block a at present, the grouping and merging unit sends the request to the memory system and creates a request group A, and marks the SM that initiates the request as one of the destination SMs of the request group A;

[0016] Within the time window of the request group A, all subsequent requests from other SMs for cache block a are included in the request group A, the corresponding SMs are marked as destination SMs, and the corresponding subsequent requests are discarded;

[0017] The time window of the request group A lasts until the first request for cache block a returns from the memory system, at which time the request group A terminates and no longer receives new requests for cache block a.

[0018] Further alternatively, the reply merging phase specifically includes the following processes:

[0019] When cache block a returns to the grouping and merging unit from the memory system, the grouping and merging unit extracts all the marked destination SM information in the request group A corresponding to cache block a to obtain a destination SM list, and then sends cache block a associated with the destination SM list to the NoC sending queue;

[0020] The NoC sending queue generates a multicast data packet containing cache block a according to the destination SM list,

[0021] Then, through the multicast routing mechanism of the NoC, the data packet is transmitted in parallel to all destination SMs in the destination SM list, ensuring that each participating SM in the request group A can obtain the required cache block a, achieving efficient interaction that meets the needs of multiple SMs with one data transmission.

[0022] Alternatively, the grouping and merging unit implements grouping and merging of requests for accessing the same cache block by different SMs through a request grouping register, specifically including two stages of request grouping and reply merging;

[0023] The request grouping register is composed of a valid bit, an address field, and a destination SM identification field; wherein: the valid bit indicates whether the register is enabled; the address field stores the cache block address; the destination SM identification field is m bits, m is equal to the number of SMs, and each bit corresponds to the access state of an SM, 1 indicating that the SM accesses the cache block and 0 indicating that it does not;

[0024] The number n of request grouping registers determines the maximum groupable number.

[0025] Further, in the request grouping phase, the request grouping register aggregates the requests accessing the same cache block into a request group by storing the cache block address and the ID of the SM accessing the cache block within a preset time window, only retains the first request and marks all related SMs as the destination; this process specifically includes:

[0026] When the grouping and merging unit receives the cache request of the SM, it parses the cache block address and the ID of the SM in the request:

[0027] If there is a request grouping register with the valid bit being 1 and the address field matching, the bit corresponding to the ID of the SM is set to 1 in the destination SM identification field, i.e. the SM is added to the request group, and the current repeated request is discarded;

[0028] If there is no request grouping register with the valid bit being 1 and the address field matching, a new request grouping register is enabled, the cache block address is stored in the address field of the new request grouping register, the bit corresponding to the ID of the SM is set to 1, and the first request is retained as the representative of the new request group.

[0029] Further, in the reply grouping phase, when the cache block returns from the memory system, the grouping and merging unit obtains the IDs of all destination SMs by accessing the corresponding request grouping register, associates the cache block with all the obtained destination SMs, and then sends the cache block to the destination SMs through NoC multicast routing synchronization and releases the request grouping register resource; this process specifically includes:

[0030] When the cache block returns from the L2 cache unit, the grouping and merging unit obtains the IDs of all SMs with the bit being 1 in the destination SM identification field by accessing the corresponding request grouping register;

[0031] The cache block and the IDs of all destination SMs are sent to the memory controller response queue, and the valid bit of the request grouping register is cleared to release the request grouping register resource;

[0032] When the NoC sending queue is idle, the grouping and merging unit takes out the cache block and the IDs of all destination SMs from the memory controller response queue and sends them to the NoC sending queue; the NoC sending queue packs the cache block into a data packet, identifies the IDs of all destination SMs in the packet header, and then injects the data packet into the NoC and sends it to each corresponding SM through multicast routing synchronization.

[0033] Further, a NoC congestion control method based on redundant data merging is involved, and the specific implementation process is as follows:

[0034] 1) When the cache request of the SM to the L2 cache unit reaches the memory controller through the NoC, the cache request is put into the NoC receiving queue;

[0035] 2) The packet merging unit checks whether there is an available request packet register, that is, whether there is a request packet register with a valid bit of 0;

[0036] 3) If no available request packet register exists, the packet merging unit does not process any cached requests and continues to wait for an available request packet register;

[0037] 4) If an available request packet register exists, the packet merging unit retrieves a cached request from the NoC receive queue and determines whether the cached request is a write request or a read request;

[0038] 5) If the cache request is a write request, then write it along with the data to be written to the write buffer;

[0039] 6) If the cache request is a read request, then access all currently valid request block registers in sequence and determine whether the cache block address of the read request is the same as the cache block address in the valid request block register.

[0040] 7) If the cache block address of the read request is different from the cache block addresses in all valid request block registers, then write the request and the cache block address into an empty request block register, set the valid bits of the request block register to 1, and set the bit corresponding to the SM ID in the destination SM identifier field to 1.

[0041] 8) If the cache block address of the read request is the same as the cache block address in a valid request block register, then set the bit corresponding to the SMID of the read request in the destination SM identifier field of the request block register to 1, and discard the read request;

[0042] 9) The group merging unit processes the buffered requests in the NoC receive queue sequentially according to steps 2)-8) to achieve request grouping;

[0043] 10) The group merging unit checks whether there are free resources in the memory controller request queue. If so, it initiates read and write requests in a loop, and the read and write requests enter the memory controller request queue.

[0044] When a write request is initiated, the group merging unit retrieves the write request and the write data from the write buffer, and then sends the write request and the write data to the memory controller request queue to wait for scheduling; when the memory controller schedules the write request, it retrieves the write request and the corresponding write data from the memory controller request queue and completes the write operation in the L2 cache unit.

[0045] 11) If the packet merging unit initiates a read request, it will check the valid bits of all request packet registers in sequence, and send the request and cache block address of the first valid request packet register to the L2 cache unit for memory access, and wait for the cache block to return;

[0046] 12) When the requested cache block is returned from the L2 cache unit, the packet merging unit accesses the request packet register corresponding to the request, obtains the IDs of all SMs requesting the cache block, and sends them to the memory controller response queue together with the cache block;

[0047] 13) The packet merging unit releases the valid position 0 of the request packet register corresponding to the request, releasing the request packet register resource;

[0048] 14) The packet merging unit detects whether the NoC sending queue is idle, and if the NoC sending queue has idle resources, the cache block and the IDs of all destination SMs are taken out from the memory controller response queue and sent to the NoC sending queue;

[0049] 15) The NoC sending queue packs the cache block into a data packet, and identifies the data packet header according to the IDs of all SMs requesting the cache block;

[0050] 16) The NoC sends the data packet to the SMs identified in the header by multicast routing, completing the response return of the cache request;

[0051] 17) The packet merging unit processes the read request in the request packet register and the write request in the write buffer according to steps 10)-16), and realizes reply merging.

[0052] The NoC congestion control method based on redundant data merging of the application has the beneficial effects compared with the prior art:

[0053] The application is applied to a general parallel computing architecture, marks cache requests from different SMs for the same cache block through a packet merging unit, and after the memory controller access completes to obtain the cache block, injects the cache block into the NoC according to the request mark, and sends it to the requesting SMs by multicast routing, avoiding the transmission of redundant data in the NoC, improving the bandwidth utilization of the NoC, reducing energy consumption and congestion, and solving the NoC congestion caused by redundant data transmission in the general parallel computing architecture and the resulting memory controller bottleneck problem. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a control method implementation architecture diagram of the application; Figure 1 Figure 2 is a control method implementation flowchart of the application.

[0055] Figure 1 is a control method implementation architecture diagram of the application; Figure 2 Figure 2 is a control method implementation flowchart of the application. DETAILED DESCRIPTION

[0056] In order to make the technical solutions, technical problems solved and technical effects of the application clearer, the technical solutions of the application are described clearly and completely in combination with specific embodiments.

[0057] Embodiment one:

[0058] In combination with the accompanying Figure 1 , the embodiment proposes a NoC congestion control method based on redundant data merging, which is applied to a general parallel computing architecture. A packet merging unit is integrated in a memory controller to mark cache requests from different SMs and for the same cache block. After the memory controller accesses the cache block, the request is injected into the NoC according to the request mark, and the cache block shared by multiple SMs is merged into a single data packet using the characteristics of the NoC, and then sent to each requesting SM through multicast routing.

[0059] Specifically, the general parallel computing architecture involved in the embodiment includes SMs, a NoC, a memory controller, and a DRAM. Wherein:

[0060] The SM is the operation core unit, which internally includes an instruction pipeline and an L1 cache unit. The instruction pipeline is the core path of thread execution, which will allocate several threads in a thread bundle to each SP for execution in the execution phase. Meanwhile, the instruction pipeline also integrates a thread bundle scheduling unit for implementing thread bundle scheduling and branch jump control, a register file unit for caching data and intermediate calculation results in the operation process, and a shared memory unit for data exchange between thread bundles and threads. The L1 cache unit is connected to the NoC and is used to save data and instructions obtained from the L2 cache unit.

[0061] The memory controller integrates a packet merging unit and an L2 cache unit. The packet merging unit merges cache requests from different SMs and for the same cache block on one hand, and merges the cache block obtained based on the request into a single data packet on the other hand. The L2 cache unit pre-fetches data in the global memory through the merged access mode, and each memory controller is connected to multiple L2 cache units to access the external DRAM.

[0062] The NoC connects the L2 cache unit with the L1 cache unit of each SM to realize efficient data transmission.

[0063] The packet merging unit processes cache requests from different SMs and for the same cache block through packet merging, which includes two stages of request grouping and reply merging.

[0064] (1) In the request grouping stage, the packet merging unit aggregates multiple access requests for the same cache block from multiple SMs into a request group within a preset time window, retains only the first request and marks all related SMs as the destination, and discards the repeated requests for the cache block from the remaining SMs. The specific process includes the following steps:

[0065] When a request of a certain SM to cache block a arrives at the memory controller, if there is no active request group for cache block a at present, the grouping and merging unit sends the request to the memory system and creates request group A, and marks the SM initiating the request as one of the destination SMs of request group A;

[0066] Within the time window of request group A (determined by the memory access time, such as the L2 cache unit access time or the total time of L2 cache unit access + global DRAM access), all subsequent requests from other SMs and to cache block a are included in request group A, the corresponding SM is marked as a destination SM, and the corresponding subsequent request itself is discarded;

[0067] The time window of request group A continues until the cache block a of the first request is returned from the memory system, at which time request group A is terminated and no longer receives new requests for cache block a.

[0068] (ii) In the reply merging phase, when the cache block (based on the access request of the request group) is returned from the memory system, the grouping and merging unit associates the cache block with all the marked destination SMs in the request group and sends it to all the destination SMs through the NoC multicast routing. Specifically, the following processes are included:

[0069] When cache block a is returned from the memory system to the grouping and merging unit, the grouping and merging unit extracts all the marked destination SM information in request group A corresponding to cache block a to obtain a destination SM list, and then associates cache block a with the destination SM list and sends it to the NoC sending queue;

[0070] The NoC sending queue generates a multicast data packet containing cache block a according to the destination SM list,

[0071] Then, through the multicast routing mechanism of the NoC, the data packet is transmitted in parallel to all the destination SMs in the destination SM list, ensuring that each SM participating in request group A can obtain the required cache block a, realizing efficient interaction that meets the needs of multiple SMs in one data transmission.

[0072] It should be noted that the grouping and merging unit of the present embodiment realizes grouping and merging of requests of different SMs to access the same cache block through a request grouping register (RGR).

[0073] The request grouping register (RGR) is composed of a valid bit (valid), an address field (addr), and a destination SM identification field (SM ID Flag). Among them: the valid bit (valid) indicates whether the register is enabled; the address field (addr) stores the cache block address; the destination SM identification field (SM ID Flag) is m bits, m is equal to the number of SMs, and each bit corresponds to the access state of an SM, 1 indicates that the SM accesses this cache block, and 0 indicates that it does not access;

[0074] The number n of the request group register (RGR) determines the maximum number of groups.

[0075] Based on the request group register (RGR), the packet merging unit implements the two-stage process of request packet and reply merging as follows.

[0076] In the request packet stage, the request group register (RGR) aggregates the related requests accessing the same cache block into a request group within a preset time window by storing the cache block address and the ID of the SM accessing the cache block, and only retains the first request and marks all related SMs as the destination; this process specifically includes:

[0077] I. When the packet merging unit receives the cache request of the SM, it parses the cache block address and the ID of the SM in the request:

[0078] If there is a request group register (RGR) with valid bit (valid) being 1 and address field (addr) matching, the bit corresponding to the ID of the SM is set to 1 in the destination SM identification field (SM ID Flag), i.e., the SM is added to the request group, and the current duplicate request is discarded;

[0079] If there is no request group register (RGR) with valid bit (valid) being 1 and address field (addr) matching, a new request group register (RGR) is enabled, the cache block address is stored in the address field (addr) of the new request group register (RGR), the bit corresponding to the ID of the SM is set to 1, and the first request is retained as the representative of the new request group.

[0080] II. In the reply merging stage, when the cache block returns from the memory system, the packet merging unit obtains the IDs of all destination SMs by accessing the corresponding request group register (RGR), associates the cache block with all the obtained destination SMs, and then sends the cache block to each destination SM through NoC multicast routing synchronization, and releases the request group register (RGR) resource; this process specifically includes:

[0081] When the cache block returns from the L2 cache unit, the packet merging unit obtains the IDs of all SMs with bit set to 1 in the destination SM identification field (SM ID Flag) by accessing the corresponding request group register (RGR);

[0082] The cache block and the IDs of all destination SMs are sent to the memory controller response queue, and the valid bit (valid) of the request group register (RGR) is cleared to release the request group register (RGR) resource;

[0083] When the NoC sending queue is idle, the packet merging unit takes out the cache block and the IDs of all destination SMs from the memory controller response queue, and sends them into the NoC sending queue; the NoC sending queue packs the cache block into a data packet, identifies the IDs of all destination SMs in the packet header, and then injects the data packet into the NoC and synchronously sends it to each corresponding SM through multicast routing.

[0084] Based on the above description, combined with the accompanying Figure 2 The NoC congestion control method based on redundant data merging proposed in the embodiment has the following implementation process:

[0085] 1) When a cache request of an SM to the L2 cache unit arrives at the memory controller (MC) through the NoC, the cache request is put into the NoC receiving queue.

[0086] 2) The packet merging unit detects whether there is an available request packet register (RGR), i.e., whether there is a request packet register (RGR) with a valid bit of 0.

[0087] 3) If there is no available request packet register (RGR), the packet merging unit does not process any cache request and continues to wait for an available request packet register (RGR).

[0088] 4) If there is an available request packet register (RGR), the packet merging unit takes out one cache request from the NoC receiving queue, and judges whether the cache request is a write request or a read request.

[0089] 5) If the cache request is a write request, it is written into the write buffer together with the write data.

[0090] 6) If the cache request is a read request, all currently valid request packet registers (RGRs) are accessed in sequence, and it is judged whether the cache block address of the read request is the same as the cache block address in the valid request packet register (RGR).

[0091] 7) If the cache block address of the read request is different from the cache block addresses in all valid request packet registers (RGRs), the request and the cache block address are written into an empty request packet register (RGR), the valid bit (valid) of the request packet register (RGR) is set to 1, and the bit corresponding to the SM ID in the destination SM identification field (SM ID Flag) is set to 1.

[0092] 8) If the cache block address of the read request is the same as the cache block address in a valid request packet register (RGR), the bit corresponding to the read request SM ID in the destination SM identification field (SM ID Flag) of the request packet register (RGR) is set to 1, and the read request is discarded.

[0093] 9) The packet merging unit processes the buffered requests in the NoC receive queue in sequence according to steps 2)-8) to implement the request packet.

[0094] 10) The packet merging unit detects whether there is a free resource in the memory controller request queue, and if so, initiates a read request and a write request in a loop, and the read request and the write request enter the memory controller request queue.

[0095] When initiating the write request, the packet merging unit obtains the write request and the write data from the write buffer, and then sends the write request and the write data into the memory controller request queue for waiting for scheduling; when the memory controller schedules the write request, the write request and the corresponding write data are taken out from the memory controller request queue, and the write operation is completed in the L2 cache unit.

[0096] 11) The packet merging unit initiates the read request, then detects the valid bits of all request packet registers (RGRs) in sequence, and sends the request and the cache block address of the first valid request packet register (RGR) to the L2 cache unit for memory access, and waits for the cache block to return. This step is independent of and does not interfere with steps 1)-9).

[0097] 12) When the requested cache block returns from the L2 cache unit, the packet merging unit accesses the request packet register (RGR) corresponding to the request, obtains the IDs of all SMs requesting the cache block, and sends the cache block and the IDs to the memory controller response queue.

[0098] 13) The packet merging unit sets the valid bit of the request packet register (RGR) corresponding to the request to 0 to release the request packet register (RGR) resource.

[0099] 14) The packet merging unit detects whether the NoC sending queue is free, and if the NoC sending queue has a free resource, takes out the cache block and the IDs of all destination SMs from the memory controller response queue and sends them into the NoC sending queue.

[0100] 15) The NoC sending queue packs the cache block into a data packet, and identifies all SMs requesting the cache block in the data packet header according to the IDs.

[0101] 16) The NoC sends the data packet to the SMs identified in the header by multicast routing to complete the response return of the cache request.

[0102] 17) The packet merging unit processes the read request in the request packet register (RGR) and the write request in the write buffer according to steps 10)-16) to implement the reply merging.

[0103] In conclusion, the NoC congestion control method based on redundant data merging is applied to the general parallel computing architecture, the cache request from different SMs and aiming at the same cache block is marked by the grouping merging unit, and after the cache block is obtained by the memory controller access, the cache block is injected into the NoC according to the request mark and is sent to the SM initiating the request by the multicast routing mode, the transmission of the redundant data in the NoC is avoided, the bandwidth utilization of the NoC is improved, the energy consumption and congestion are reduced, the NoC congestion caused by the redundant data transmission in the general parallel computing architecture and the memory controller bottleneck problem caused thereby are solved.

[0104] The principles and implementation manners of the application are described in detail by using the above application specific examples, and the examples are only used to help understand the core technical content of the application. Based on the above specific examples of the application, any improvement and modification of the application made by the person skilled in the art without departing from the principles of the application shall fall within the patent protection scope of the application.

Claims

1. A NoC congestion control method based on redundant data merge, characterized by, The method is applied to a general parallel computing architecture, and a grouping and merging unit is integrated in a memory controller to mark cache requests from different SMs and for the same cache block; After the memory controller accesses the cache block, the cache block is injected into a NoC according to the request mark, and the cache block shared by multiple SMs is merged into a single data packet using the characteristics of the NoC, and then the cache block is sent to each SM initiating the request through multicast routing.

2. The NoC congestion control method based on redundant data merging according to claim 1, wherein, The general parallel computing architecture comprises SMs, a NoC, memory controllers and DRAMs; wherein: The SM is an operation core unit, and comprises an instruction pipeline and an L1 cache unit; the instruction pipeline is a core path of thread execution, and a plurality of threads in a thread bundle are allocated to the SPs for execution in an execution stage; meanwhile, the instruction pipeline further comprises a thread bundle scheduling unit for implementing thread bundle scheduling and branch jump control, a register file unit for caching data and intermediate calculation results in the operation process, and a shared memory unit for data exchange between thread bundles and threads; the L1 cache unit is connected to the NoC, and is used to save data and instructions obtained from the L2 cache unit; The memory controller comprises a grouping and merging unit and an L2 cache unit; the grouping and merging unit is used to merge cache requests from different SMs and for the same cache block, and to merge the cache block obtained based on the request into a single data packet; the L2 cache unit is used to prefetch data in the global memory through merged access, and each memory controller is connected to a plurality of L2 cache units to access the external DRAM; The NoC connects the L2 cache unit and the L1 cache unit of each SM to realize efficient data transmission.

3. The NoC congestion control method based on redundant data merging according to claim 2, characterized in that, The grouping and merging unit processes cache requests from different SMs and for the same cache block through grouping and merging, and specifically comprises two stages of request grouping and reply merging; In the request grouping stage, the grouping and merging unit aggregates access requests of the same cache block from multiple SMs into a request group within a preset time window, retains only the first request and marks all related SMs as destination ends, and discards the repeated requests of the SMs for the cache block; In the reply merging stage, when the cache block based on the same access request is returned from the memory system, the grouping and merging unit associates the cache block with all the marked destination SMs in the request group, and synchronously sends the cache block to all the destination SMs through NoC multicast routing.

4. The NoC congestion control method based on redundant data merging according to claim 3, characterized in that, The request grouping stage specifically comprises the following processes: When a request of a SM for a cache block a reaches the memory controller, if there is no active request group for the cache block a, the grouping and merging unit sends the request to the memory system, creates a request group A, and marks the SM initiating the request as one of the destination SMs of the request group A; Within the time window of the request group A, all subsequent requests from other SMs for the cache block a are included in the request group A, the corresponding SMs are marked as destination SMs, and the corresponding subsequent requests are discarded. The time window of the request group A lasts until the first requested cache block a is returned from the memory system, at which time the request group A is terminated and no new request for the cache block a is accepted.

5. The NoC congestion control method based on redundant data merging according to claim 4, characterized in that, The reply merging stage specifically includes the following process: When the cache block a is returned from the memory system to the group merging unit, the group merging unit extracts all the marked destination SM information in the request group A corresponding to the cache block a to obtain a destination SM list, and then sends the cache block a associated with the destination SM list to the NoC sending queue; The NoC sending queue generates a multicast data packet containing the cache block a according to the destination SM list, and then transmits the data packet in parallel to all the destination SMs in the destination SM list through the multicast routing mechanism of the NoC, so as to ensure that each participating SM in the request group A can obtain the required cache block a, and realize efficient interaction that meets the needs of multiple SMs in one data transmission.

6. The NoC congestion control method based on redundant data merging according to claim 3, wherein, The group merging unit realizes the grouping and merging of the requests of different SMs accessing the same cache block through the request grouping register, specifically including two stages of request grouping and reply merging; The request grouping register is composed of a valid bit, an address field and a destination SM identification field; wherein: the valid bit indicates whether the register is enabled; the address field stores the cache block address; the destination SM identification field is m bits, m is equal to the number of SMs, and each bit corresponds to the access state of an SM, 1 indicating that the SM accesses the cache block and 0 indicating that the SM does not access the cache block; The number n of the request grouping register determines the maximum groupable number.

7. The NoC congestion control method based on redundant data merging according to claim 6, characterized in that, In the request grouping stage, the request grouping register aggregates the related requests accessing the same cache block into a request group within a preset time window by storing the cache block address and the ID of the SM accessing the cache block, and only retains the first request and marks all the related SMs as destination ends; This process specifically includes: When the group merging unit receives the cache request of an SM, the cache block address and the ID of the SM in the request are parsed: If there is a request grouping register with the valid bit being 1 and the address field matching, the bit corresponding to the ID of the SM in the destination SM identification field is set to 1, that is, the SM is added to the request group, and the current repeated request is discarded; If there is no request grouping register with the valid bit being 1 and the address field matching, a new request grouping register is enabled, the cache block address is stored in the address field of the new request grouping register, the bit corresponding to the ID of the SM is set to 1, and the first request is retained as the representative of the new request group.

8. The NoC congestion control method based on redundant data merging according to claim 7, characterized in that, In the reply merging stage, when the cache block is returned from the memory system, the group merging unit obtains the IDs of all the destination SMs by accessing the corresponding grouping register, associates the cache block with all the destination SMs, sends the cache block to each destination SM through the NoC multicast routing, and releases the request grouping register resource; This process specifically includes: When the cache block is returned from the L2 cache unit, the group merging unit obtains the IDs of all the SMs with the bit being 1 in the destination SM identification field by accessing the corresponding request grouping register; The cache block and the IDs of all the destination SMs are sent to the memory controller response queue, and the valid bit of the request grouping register is cleared to release the request grouping register resource; When the NoC sending queue is idle, the packet merging unit takes out the cache block and the IDs of all destination SMs from the memory controller response queue and sends them into the NoC sending queue; the NoC sending queue packs the cache block into a data packet, identifies the IDs of all destination SMs in the packet header, and then injects the data packet into the NoC and synchronously sends it to each corresponding SM through multicast routing.

9. The NoC congestion control method based on redundant data merging according to claim 8, characterized in that, The specific implementation process of the control method is as follows: 1) When a cache request of the SM to the L2 cache unit arrives at the memory controller through the NoC, the cache request is put into the NoC receiving queue; 2) The packet merging unit detects whether there is an available request packet register, that is, whether there is a request packet register with an effective bit of 0; 3) If there is no available request packet register, the packet merging unit does not process any cache request and continues to wait for an available request packet register; 4) If there is an available request packet register, the packet merging unit takes out a cache request from the NoC receiving queue and judges whether the cache request is a write request or a read request; 5) If the cache request is a write request, it is written into the write buffer together with the write data; 6) If the cache request is a read request, all currently valid request packet registers are accessed in sequence, and it is judged whether the cache block address of the read request is the same as the cache block address in the valid request packet register; 7) If the cache block address of the read request is different from the cache block addresses in all valid request packet registers, the request and the cache block address are written into an empty request packet register, the effective bit of the request packet register is set to 1, and the bit corresponding to the SM ID in the destination SM identification field is set to 1; 8) If the cache block address of the read request is the same as the cache block address in a valid request packet register, the bit corresponding to the read request SM ID in the destination SM identification field of the request packet register is set to 1, and the read request is discarded; 9) The packet merging unit processes the cache requests in the NoC receiving queue in sequence according to steps 2)-8) to realize request grouping; 10) The packet merging unit detects whether there is an idle resource in the memory controller request queue, and if so, it repeatedly initiates read requests and write requests, and the read requests and write requests enter the memory controller request queue; When initiating a write request, the packet merging unit obtains the write request and the write data from the write buffer, and then sends the write request and the write data into the memory controller request queue and waits for scheduling; When the memory controller schedules the write request, the write request and the corresponding write data are taken out from the memory controller request queue, and the write operation is completed in the L2 cache unit; 11) The packet merging unit initiates a read request, detects the effective bits of all request packet registers in sequence, and sends the request and the cache block address of the first valid request packet register to the L2 cache unit for memory access, and waits for the cache block to return; 12) When the requested cache block returns from the L2 cache unit, the packet merging unit accesses the request packet register corresponding to the request, obtains the IDs of all SMs requesting the cache block, and sends them together with the cache block to the memory controller response queue; 13) The packet merging unit releases the request packet register resource corresponding to the request at valid position 0 of the request packet register; 14) The packet merging unit detects whether the NoC sending queue is idle. If the NoC sending queue has idle resources, the cache block and the IDs of all destination SMs are taken out from the memory controller response queue and sent into the NoC sending queue; 15) The NoC sending queue packs the cache block into a data packet and identifies the IDs of all SMs requesting the cache block in the data packet header; 16) The NoC sends the data packet to the SMs identified in the header by means of multicast routing, and returns the response of the cache request; 17) The packet merging unit processes the read request in the request packet register and the write request in the write buffer according to steps 10)-16), and realizes reply merging.

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