Power distribution control circuit and power distribution circuit

Abstract

The invention relates to the technical field of power supplies, and discloses a power distribution control circuit and a power distribution circuit, a first switch circuit can orderly receive and transmit a reset signal and a preset signal, and provides an accurate input basis for subsequent signal processing; and the signal holding circuit can maintain the current level for preset time when the preset signal and the reset signal have level changes, so that circuit misoperation caused by instantaneous fluctuation of the input signal can be avoided, the continuity and the stability of the power supply state of the load are further ensured, and power supply interruption or abnormal starting of the load caused by sudden signal change is prevented. And the second switching circuit is connected with the load by accessing the first power supply voltage, so that ordered on-off control of power supply of the load can be realized under the synergistic effect of the signal holding circuit, and the power supply state of the load can be accurately adjusted according to actual requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply, in particular to a power distribution control circuit and a power distribution circuit. BACKGROUND

[0002] In the scene of missile-borne power distribution, there is a key requirement of state retention function, specifically, when the CPU appears abnormal conditions such as runaway or machine cutting, the relay needs to maintain the original working state to ensure the stability of power supply. Based on this demand, the magnetic latching relay is generally used in the missile-borne power distribution circuit. The control mode of the magnetic latching relay has specific characteristics, and its state switching depends on the pulse signal output by the CPU. After the pulse signal is output, the state of the relay will be reversed, and in order to ensure that the state of the relay can be reliably switched, the holding time of the pulse signal needs to be greater than 100ms. However, the missile-borne power distribution circuit using the magnetic latching relay has many shortcomings. In the application scene of spacecraft, volume and weight are extremely valuable resources, which directly affect the launch cost of the spacecraft. However, the magnetic latching relay itself has the problems of large volume and heavy weight, and its price is also relatively high. When facing the demand of large current load, the selection range of the magnetic latching relay is limited, and the overcurrent capacity is obviously smaller compared with the MOS tube. In addition, the magnetic latching relay has mechanical life limit, and is easily affected by environmental factors such as temperature change, humidity fluctuation and vibration impact during use, thereby affecting its working stability and service life. SUMMARY

[0003] Therefore, the present application provides a power distribution control circuit and a power distribution circuit to solve the problem of how to maintain the stability of power distribution.

[0004] In a first aspect, the present application provides a power distribution control circuit, comprising: a first switching circuit, a second switching circuit and a signal holding circuit, wherein the first input end and the second input end of the first switching circuit receive a clear signal and a preset signal respectively, the first output end and the second output end of the first switching circuit are connected with the first input end and the second input end of the signal holding circuit respectively, the output end of the signal holding circuit is connected with the first input end of the second switching circuit, and the signal holding circuit is used for maintaining the current level for a preset time when the level of the preset signal and the clear signal changes; the second input end of the second switching circuit is connected with a first power supply voltage, and the output end of the second switching circuit is connected with a load.

[0005] In an optional implementation, the first switching circuit comprises: a first switching sub-circuit and a second switching sub-circuit, wherein the input end of the first switching sub-circuit is connected with the clear signal, the output end of the first switching sub-circuit is connected with the first input end of the signal holding circuit; the input end of the second switching sub-circuit is connected with the preset signal, and the output end of the second switching sub-circuit is connected with the second input end of the signal holding circuit.

[0006] In an alternative embodiment, the first switch sub-circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a first transistor, wherein the control end of the first transistor is connected with the first end of the second resistor and the first end of the third resistor, the first end of the first transistor is connected with the first input end of the signal holding circuit and the first end of the fourth resistor, the second end of the first transistor is connected with the second end of the third resistor and then grounded; the first end of the first resistor is connected with the second end of the second resistor, the first end of the first resistor is connected with the clear signal, and the second end of the first resistor is grounded; the second end of the fourth resistor is connected with the second supply voltage.

[0007] In an alternative embodiment, the second switch sub-circuit comprises a fifth resistor, a sixth resistor, a seventh resistor and a second transistor, wherein the control end of the second transistor is connected with the first end of the sixth resistor and the first end of the seventh resistor, the first end of the second transistor is connected with the second input end of the signal holding circuit, the second end of the second transistor is connected with the second end of the seventh resistor and then grounded; the first end of the fifth resistor is connected with the first end of the sixth resistor, the first end of the fifth resistor is connected with the preset signal, and the second end of the fifth resistor is grounded.

[0008] In an alternative embodiment, the second switch circuit comprises a third switch sub-circuit and a fourth switch sub-circuit, wherein the first end of the third switch sub-circuit is connected with the output end of the signal holding circuit, the second end of the third switch sub-circuit is connected with the first end of the fourth switch sub-circuit; the second end of the fourth switch sub-circuit is connected with the first supply voltage, and the third end of the fourth switch sub-circuit is connected with the load.

[0009] In an alternative embodiment, the third switch sub-circuit comprises an eleventh resistor, a twelfth resistor, a thirteenth resistor and a third transistor, wherein the control end of the third transistor is connected with the first end of the eleventh resistor and the first end of the twelfth resistor, the first end of the third transistor is connected with the first end of the thirteenth resistor, the second end of the third transistor is connected with the second end of the twelfth resistor and then grounded; the first end of the eleventh resistor is connected with the output end of the signal holding circuit; the second end of the thirteenth resistor is connected with the first end of the fourth switch sub-circuit.

[0010] In an alternative embodiment, the fourth switch sub-circuit comprises a fourteenth resistor, a first capacitor, a first diode and a fourth transistor, wherein the control end of the fourth transistor is connected with the second end of the third switch sub-circuit, the first end of the fourteenth resistor, the first end of the first capacitor and the anode of the first diode, the first end of the fourth transistor is connected with the second end of the fourteenth resistor, the second end of the first capacitor and the cathode of the first diode, the first end of the fourth transistor is connected with the first supply voltage, and the second end of the fourth transistor is connected with the load.

[0011] In an alternative embodiment, the signal holding circuit comprises a D flip-flop, wherein a clock input pin of the D flip-flop is connected to the first output end of the first switch circuit, a set pin of the D flip-flop is connected to the second output end of the first switch circuit, and a positive output pin of the D flip-flop is connected to the first input end of the second switch circuit.

[0012] In an alternative embodiment, the power distribution control circuit further comprises a controller, wherein the controller is configured to output the preset signal and the clear signal.

[0013] In a second aspect, the present application provides a power distribution circuit, comprising the power distribution control circuit and a relay, wherein the first input end and the second input end of the first switch circuit receive the preset signal and the clear signal respectively, the first output end and the second output end of the first switch circuit are connected to the first input end and the second input end of the signal holding circuit respectively, the output end of the signal holding circuit is connected to the first input end of the second switch circuit, the signal holding circuit is configured to maintain the current level for a preset time when the level of the preset signal and the clear signal changes, and the second input end of the second switch circuit is connected to the first supply voltage, and the output end of the second switch circuit is connected to the relay.

[0014] The power distribution control circuit of the present application can effectively realize stable and precise control of load power distribution through the coordinated operation of the first switch circuit, the second switch circuit and the signal holding circuit. The first switch circuit can orderly receive and transmit the clear signal and the preset signal, providing an accurate input basis for subsequent signal processing. The signal holding circuit can maintain the current level for a preset time when the level of the preset signal and the clear signal changes, which can avoid circuit malfunctions caused by instantaneous fluctuations in the input signal, thereby ensuring the continuity and stability of the load power supply state and preventing the load power supply from being interrupted or abnormally started due to signal mutations. Meanwhile, the second switch circuit, connected to the first supply voltage and the load, can orderly control the on-off of the load power supply under the coordinated action of the signal holding circuit, which can accurately adjust the power supply state of the load according to actual needs, reduce unnecessary power consumption, effectively protect the load from damage caused by sudden voltage changes or frequent on-off, and significantly improve the operation reliability and control accuracy of the entire power distribution system, which is suitable for various power consumption scenarios with high requirements for power supply stability.

[0015] The application realizes the MOS transistor by the D flip-flop with the clear and preset functions, can meet the requirement of power distribution state keeping without changing the input pulse control signal, has multiple advantages: the D flip-flop and the MOS transistor have the characteristics of small size, light weight and low cost, can significantly reduce the development and application cost of the power distribution circuit; the pure digital circuit design is adopted, not only the type selection is flexible and rich, can adapt to diversified application requirements, but also there is no life limitation caused by mechanical wear, has stronger environmental adaptability, and can work stably under complex working conditions. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0017] Figure 1 is a composition diagram of a power distribution control circuit according to an embodiment of the present application;

[0018] Figure 2 is a composition diagram of another power distribution control circuit according to an embodiment of the present application;

[0019] Figure 3 is a specific circuit structure diagram of the composition diagram of the power distribution control circuit according to an embodiment of the present application;

[0020] Figure 4 is a composition diagram of another power distribution control circuit according to an embodiment of the present application;

[0021] Figure 5 is a composition diagram of another power distribution control circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0023] In the present embodiment, a power distribution control circuit is provided, as shown in Figure 1 , comprising: a first switching circuit 1, a second switching circuit 2 and a signal holding circuit 3.

[0024] As shown in Figure 1As shown, the first input end and the second input end of the first switch circuit 1 receive the clear signal CLR and the preset signal PRE respectively, and the first output end and the second output end of the first switch circuit 1 are connected with the first input end and the second input end of the signal holding circuit 3 respectively.

[0025] Specifically, the first switch circuit 1 is configured in a double-signal receiving mode, the first input end is used to receive the preset signal PRE, i.e. the enable signal, and the second input end is used to receive the clear signal CLR, i.e. the reset signal. The PRE signal is the core control trigger signal of the circuit, which is usually a digital level signal (such as high level active or low level active, which can be set according to the system control logic), used to send the preset instruction of "allowing the load to be powered" to the circuit. The CLR signal is the fault or reset control signal of the circuit, which is also a digital level signal, used to send the "reset clear" instruction when it is necessary to cut off the power supply of the load or the circuit is abnormal.

[0026] Specifically, the core function of the first switch circuit 1 is to logically integrate and signal gate the PRE signal and the CLR signal. For example, when the CLR signal is invalid, the circuit responds to the level change of the PRE signal preferentially and outputs a control signal logically matched with the PRE signal. When the CLR signal is valid, the circuit ignores the PRE signal and outputs a reset signal for cutting off the power supply of the load. Finally, the first output end and the second output end of the first switch circuit 1 transmit the two processed control signals to the first input end and the second input end of the signal holding circuit 3 respectively, providing a basis for subsequent signal stable control.

[0027] As shown, Figure 1 the output end of the signal holding circuit 3 is connected with the first input end of the second switch circuit 2. The signal holding circuit 3 is used to maintain the current level for a preset time when the level of the preset signal PRE or the clear signal CLR changes.

[0028] Specifically, the signal holding circuit 3 is the "signal stable core" of the circuit, and its core function is to eliminate the transient level jump of the PRE signal or the CLR signal caused by external interference (such as electromagnetic interference and voltage fluctuation), so as to avoid the misoperation of the circuit. Specifically, when the control signal output by the first switch circuit 1 (i.e. the level signal obtained by processing the PRE signal and the CLR signal) changes (such as switching from low level to high level or from high level to low level), the signal holding circuit 3 maintains the current stable level state for a preset time. Through this design, even if the PRE signal or the CLR signal appears a short-term transient fluctuation (such as interference jump lasting less than 1 ms), the signal holding circuit 3 can still output a stable level signal, which provides a guarantee for the reliable on-off of the second switch circuit 2. The output end of the signal holding circuit 3 is directly connected with the first input end of the second switch circuit 2, and transmits the stable control signal to the second switch circuit 2.

[0029] As shown in Figure 1 , the second input end of the second switch circuit 2 is connected to the first supply voltage VDD1, and the output end of the second switch circuit 2 is connected to the load.

[0030] Specifically, the second switch circuit 2 as the "power execution unit" of the circuit undertakes the core task of delivering the supply voltage to the load, and its input end is divided into two paths: the second input end is used to connect the first supply voltage VDD1, which is the working power supply for the load, usually a direct current voltage; the first input end receives a stable control signal from the signal holding circuit 3, and the on-off control of the power supply loop is realized through the control signal.

[0031] Specifically, when the signal holding circuit 3 outputs a "conduction control level" (such as a high level), the semiconductor switching element inside the second switch circuit 2 is turned on, so that the first supply voltage VDD1 is transmitted to the output end through the power path inside the circuit; when the signal holding circuit 3 outputs a "turn-off control level" (such as a low level), the semiconductor switching element is turned off, cutting off the power supply loop. The output end of the second switch circuit 2 is directly electrically connected to the load, and finally realizes precise and reliable control of the power supply state of the load, ensuring that the load can be stably powered when needed, and reliably powered off when abnormal or not needed.

[0032] In some optional embodiments, the first switch circuit 1 as the "signal fine processing module" in the power distribution control circuit, its core is through two functionally independent and logically cooperative sub-circuits, the first switch sub-circuit 11 and the second switch sub-circuit 12, respectively, to clear the signal CLR and the preset signal PRE for targeted processing, to ensure that the two types of control signals have stable level characteristics, clear logic properties and anti-interference ability before entering the signal holding circuit 3, and lay a reliable foundation for subsequent signal holding and load power supply control.

[0033] As shown in Figure 2 , the input end of the first switch sub-circuit 11 is connected to the clear signal CLR, and the output end of the first switch sub-circuit 11 is connected to the first input end of the signal holding circuit 3; the input end of the second switch sub-circuit 12 is connected to the preset signal PRE, and the output end of the second switch sub-circuit 12 is connected to the second input end of the signal holding circuit 3.

[0034] Specifically, the second switch sub-circuit 12 focuses on the processing and transmission of the preset signal PRE. The PRE signal connected to its input terminal is the core enable signal for the circuit to trigger the load power supply: this signal is usually a digital control signal from the CPU or control unit, and can be designed as a "pulse trigger" or "continuous level trigger" mode according to the load requirements (for example, for loads that require continuous power supply, PRE is a continuous high level; for loads that work intermittently, PRE is a pulse signal of a specific frequency). The level threshold of the signal needs to match the input characteristics of the sub-circuit to avoid signal recognition errors.

[0035] Specifically, the first switch sub-circuit 11 is specifically responsible for receiving and preprocessing the clear signal CLR. Its input terminal is directly connected to the clear signal CLR issued by the system. It is mainly used for circuit fault diagnosis, emergency power cut-off of the load, or reset control during system initialization. For example, when the CPU detects overcurrent, overvoltage, or abnormal operation of the load, it will output a valid CLR signal to trigger the circuit to cut off the power supply to the load.

[0036] In some alternative implementations, such as Figure 3 As shown, the first switching sub-circuit 11 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first transistor Q1. The control terminal of the first transistor is connected to the first terminals of the second resistor R2 and the third resistor R3. The first terminal of the first transistor Q1 is connected to the first input terminal of the signal holding circuit 3 (i.e., U1). The first terminal of the first transistor Q1 is connected to the second terminal of the third resistor R3 and then grounded; the first terminal of the first resistor R1 is connected to the second terminal of the second resistor R2, the first terminal of the first resistor R1 is connected to the clear signal CLR, and the second terminal of the first resistor R1 is grounded; the second terminal of the fourth resistor R4 is connected to the second power supply voltage.

[0037] Specifically, the control end of the first triode Q1 is a signal input end, forms a common node with the first end of the second resistor R2 and the first end of the third resistor R3, receives an external CLR signal through R2, and establishes an emitter current negative feedback path through R3; the first end of the first triode Q1 is a signal output end, is connected with the first input end of the signal retention circuit 3 and the first end of the fourth resistor R4, and the level state of this output node directly determines whether the signal retention circuit 3 receives a reset command, and the second supply voltage is obtained through R4; the second end of the first triode Q1 is connected with the second end of the third resistor R3 and then grounded, forming a negative electrode of the current loop of the triode, and R3 is connected in series between the emitter and the ground, constituting a current negative feedback path; the first resistor R1 is a "pull-down protection resistor", the first end of which is connected with the second end of R2 and the CLR signal input end, and the second end is directly grounded, and this resistor is used to prevent the "level instability" problem caused by line suspension or electromagnetic interference during CLR signal transmission; the fourth resistor R4 is an "up-pull load resistor", the second end of which is connected to the second supply voltage, and the first end is connected to the collector of Q1, and the role of this resistor is to pull the output node level to VDD2 when Q1 is cut off, ensuring the stability of the output high level.

[0038] Specifically, when the CLR signal is not input (such as signal disconnection caused by front-end circuit failure) or is at a low level, the first resistor R1 can pull the base potential of Q1 to the ground potential (0V) stably, avoiding the Q1 mis-conduction caused by the suspended base; at the same time, R1 and R2 form a voltage division relationship, which can weaken the high-frequency interference burr in the CLR signal and improve the signal anti-interference ability; the second resistor R2 is a "base limiting resistor" of Q1, and its core role is to limit the current flowing into the base of Q1 to prevent IB from being too large to burn the triode; the third resistor R3 is a "emitter negative feedback resistor" of Q1, and its core function is to stabilize the working point of Q1, resist the influence of temperature fluctuations in the missile-borne environment on the circuit, realize current stability, and avoid misoperation of the circuit due to temperature drift; the fourth resistor R4 is a pull-up resistor, and its resistance value needs to balance the "output level stability" and "power consumption", and a too small resistance value will cause R4 to have too large power consumption when Q1 is turned on, and a too large resistance value will easily cause the output level to jump due to external interference, so the value of VDD2 is combined.

[0039] Specifically, referring to Figure 3 , the first switch sub-circuit 11 switches through the "off-on" state of Q1 to realize level conversion of the CLR signal:

[0040] (1) When the CLR signal is "valid level", the CLR signal is added to the base of Q1 through R2, the base voltage of Q1 is raised to VB≥VBE (about 0.7V), Q1 is saturated and turned on, the collector (output end) potential approaches the emitter potential (ground), the low level is transmitted to the first input end of the signal holding circuit 3, and the signal holding circuit 3 is triggered to perform the reset logic.

[0041] (2) When the CLR signal is "invalid level" (such as low level 0V), the base of Q1 is pulled down to the ground through R1, VB≈0V<VBE, Q1 is cut off, the collector is connected to VDD2 through R4, the output high level is obtained, at this time, the first input end of the signal holding circuit 3 receives the high level, the reset logic is not triggered, and the circuit maintains the normal working state.

[0042] In some optional embodiments, as shown in FIG. 2, the second switch sub-circuit 12 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a second triode Q2. Figure 3 The control end of the second triode Q2 is connected with the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the first end of the second triode Q2 is connected with the second input end (i.e. the pin of U2) of the signal holding circuit 3, and the second end of the second triode Q2 is connected with the second end of the seventh resistor R7 and then grounded. The first end of the fifth resistor R5 is connected with the first end of the sixth resistor R6, the first end of the fifth resistor R5 is connected with the preset signal PRE, and the second end of the fifth resistor R5 is grounded.

[0043] Specifically, the control end (base B) of the second triode Q2 is a signal receiving core, which is connected with the first end of the sixth resistor R6 and the first end of the seventh resistor R7 to form a "base signal node", which receives the PRE signal inputted from outside through R6 on one hand, and forms a negative feedback path with the emitter on the other hand to balance the base current stability; the first end (collector C) of the second triode Q2 is a signal output end, which is directly connected with the second input end of the signal holding circuit 3, and the output level state (high / low) thereof directly determines whether the signal holding circuit 3 starts the "load power supply holding" logic; and the second end (emitter E) of the second triode Q2 is connected with the second end of the seventh resistor R7 and then grounded (GND), which constitutes the negative electrode of the current loop of the triode, and at the same time makes R7 series connected between the emitter and the ground to form a current negative feedback path.

[0044] Specifically, the fifth resistor R5 is a "PRE signal pull-down protection resistor", a first end of which is connected with a first end of R6 and a PRE signal input end, and a second end of which is directly grounded. The resistor is used to solve the "level uncertainty" problem when the PRE signal is disconnected, suspended or disturbed, and to ensure that the Q2 base potential is stable when there is no effective signal input. The sixth resistor R6 is a "Q2 base current limiting resistor", which is connected in series between the PRE signal and the Q2 base. The core function is to limit the current flowing into the base to avoid Q2 burning due to excessive current. The seventh resistor R7 is an "emitter negative feedback resistor", which stabilizes the Q2 collector current through voltage feedback to resist the influence of temperature fluctuations on the circuit performance.

[0045] Specifically, referring to Figure 3 , the second switch subcircuit 12 switches through the "off-saturated conduction" state of Q2 to realize effective conversion of the PRE signal, which is specifically divided into two working conditions:

[0046] (1) When the PRE signal is an "effective level" (assuming it is a high level, which is unified with the effective level of the clear signal CLR to avoid control logic conflict), the PRE signal is transmitted to the Q2 base through R6, so that the base potential VB is greater than or equal to VBE (about 0.7V), and Q2 enters a saturated conduction state. At this time, the Q2 collector (output end) potential is close to the emitter potential (ground), and a low level is output, which is transmitted to the second input end of the signal retention circuit 3 to trigger the signal retention circuit 3 to start the "load power supply retention" logic, laying a foundation for the subsequent conduction of the second switch circuit 2 and the power-on of the load.

[0047] (2) When the PRE signal is an "invalid level" (such as a low level of 0V), the Q2 base is pulled down to the ground potential through R5, so that VB is less than VBE, and Q2 enters an off state. At this time, there is no current path for the Q2 collector, and the internal pull-up structure of the input stage of the signal retention circuit 3 pulls the collector potential to a high level consistent with the self-supply voltage, and the "load power supply retention" logic of the signal retention circuit 3 is not triggered, and the circuit maintains the load power-off state.

[0048] In some optional embodiments, as shown in Figure 4 , the second switch circuit 2 includes a third switch subcircuit 21 and a fourth switch subcircuit 22, wherein a first end of the third switch subcircuit 21 is connected with an output end of the signal retention circuit 3, a second end of the third switch subcircuit 21 is connected with a first end of the fourth switch subcircuit 22, and a second end of the fourth switch subcircuit 22 is connected with the first power supply voltage VDD1, and a third end of the fourth switch subcircuit 22 is connected with the load.

[0049] In some optional embodiments, as shown in Figure 3As shown, the third switch subcircuit 21 includes: an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a third triode Q3, wherein the control end of the third triode Q3 is connected with the first end of the eleventh resistor R11 and the first end of the twelfth resistor R12, the first end of the third triode Q3 is connected with the first end of the thirteenth resistor R13, and the second end of the third triode Q3 is connected with the second end of the twelfth resistor R12 and then grounded; the first end of the eleventh resistor R11 is connected with the output end of the signal holding circuit 3 (i.e. the Q+ pin of U2); and the second end of the thirteenth resistor R13 is connected with the first end of the fourth switch subcircuit 22 (i.e. R14).

[0050] Specifically, the control end (base B) of the third triode Q3 is a signal input end, which is connected with the first end of the eleventh resistor R11 and the first end of the twelfth resistor R12 to form a "base signal node", which is a receiving core of weak signals; the output signal of the signal holding circuit 3 is obtained through R11, and an emitter negative feedback path is established through R12; the first end (collector C) of the third triode Q3 is a signal output end, which is connected with the first end of the thirteenth resistor R13, and the output driving signal is directly transmitted to the control end of the fourth switch subcircuit 22; the second end (emitter E) of the third triode Q3 is connected with the second end of the twelfth resistor R12 and then grounded (GND), thereby constituting a negative electrode of a current loop and making R12 be connected in series between the emitter and the ground, thereby forming a working point stabilization mechanism; the first end of the eleventh resistor R11 is directly connected with the output end of the signal holding circuit 3, and the second end is connected with the base of Q3, thereby being a "current limiting barrier" for weak signal transmission; and the second end of the thirteenth resistor R13 needs to be connected with a driving power supply voltage, thereby constituting a collector pull-up loop.

[0051] Specifically, the third switch subcircuit 21 realizes the conversion of weak signals to driving signals through the "off-saturation conduction" state switching of Q3, and specifically includes two working conditions:

[0052] (1) When the signal holding circuit 3 outputs an "effective control level" (assuming a high level), the signal is transmitted to the base of Q3 through R11, so that VB≥VBE (about 0.7V), Q3 is saturated and conducted, the collector (output end) potential is close to the emitter potential (ground), and a low level is output. The low level is transmitted to the control end (such as the gate of a PMOS tube) of the fourth switch subcircuit 22, thereby laying a foundation for the conduction of the power stage.

[0053] (2) When the signal holding circuit 3 outputs an "invalid control level" (such as a low level of 0V), the base of Q3 receives a low level through R11, so that VB≈0V<VBE, Q3 is cut off, and the collector outputs a high level (≈12V). The high level is transmitted to the control end of the fourth switch subcircuit 22, so that the power device is cut off and the load power supply circuit is cut off.

[0054] In some alternative embodiments, as shown in FIG. 2, the fourth switch sub-circuit 22 comprises a fourteenth resistor R14, a first capacitor C1, a first diode D1 and a fourth transistor Q4. The control terminal of the fourth transistor Q4 is connected with the second end (i.e. R14) of the third switch sub-circuit 21, the first end of the fourteenth resistor R14, the first end of the first capacitor C1 and the anode of the first diode D1. The first end of the fourth transistor Q4 is connected with the second end of the fourteenth resistor R14, the second end of the first capacitor C1 and the cathode of the first diode D1. The first end of the fourth transistor Q4 is connected with the first supply voltage VDD1. The second end of the fourth transistor Q4 is connected with the load. Figure 3

[0055] Specifically, the control terminal of the fourth transistor Q4 is the driving signal receiving terminal. The control terminal of the fourth transistor Q4 is connected with the second end (i.e. the driving signal output terminal) of the third switch sub-circuit 21, the first end of the fourteenth resistor R14, the first end of the first capacitor C1 and the anode of the first diode D1 to form a “base driving node”. The node is the integration core of the driving signal. The node receives the level signal of the third switch sub-circuit 21 and realizes current limiting, acceleration and protection through the R14, C1 and D1. The first end of the fourth transistor Q4 is the power input terminal. The first end of the fourth transistor Q4 is connected with the second end of the fourteenth resistor R14, the second end of the first capacitor C1 and the cathode of the first diode D1 and then directly connected with the first supply voltage VDD1. The second end of the fourth transistor Q4 is the power output terminal. The second end of the fourth transistor Q4 is directly connected with the power input terminal of the load (such as a motor or a heating module) to form a main power supply loop of “VCC1→Q4(C→E)→load→ground”.

[0056] In some alternative embodiments, as shown in FIG. 2, the fourth switch sub-circuit 22 comprises a fourteenth resistor R14, a first capacitor C1, a first diode D1 and a fourth transistor Q4. The control terminal of the fourth transistor Q4 is connected with the second end (i.e. R14) of the third switch sub-circuit 21, the first end of the fourteenth resistor R14, the first end of the first capacitor C1 and the anode of the first diode D1. The first end of the fourth transistor Q4 is connected with the second end of the fourteenth resistor R14, the second end of the first capacitor C1 and the cathode of the first diode D1. The first end of the fourth transistor Q4 is connected with the first supply voltage VDD1. The second end of the fourth transistor Q4 is connected with the load. Figure 3

[0057] Optionally, the power distribution control circuit further comprises a controller. The controller is configured to output the preset signal PRE and the clear signal CLR.

[0058] Specifically, the D flip-flop U1 with the clear and preset functions is selected to realize the following functions:

[0059] ​​​​(1) When the preset signal PRE of the D flip-flop U1 is valid (active low), the positive electrode (Q+) output of the D flip-flop U1 is high, and the negative electrode (Q-) output of the D flip-flop U1 is low. When the preset signal PRE of the D flip-flop U1 is invalid, the positive and negative electrode outputs of the D flip-flop U1 remain unchanged.

[0060] (2) When the clear signal CLR of the D flip-flop U1 is valid (active low), the positive electrode output of the D flip-flop U1 is low, and the negative electrode output of the D flip-flop U1 is high. When the clear signal CLR of the D flip-flop U1 is invalid, the positive and negative electrode outputs of the D flip-flop U1 remain unchanged.

[0061] In this way, when a pulse signal (low pulse) is input to the clear signal CLR or the preset signal PRE of the D flip-flop U1, the change of the positive and negative electrode output signals of the D flip-flop U1 can be controlled without the need to continuously maintain the valid signal.

[0062] Reference Figure 3 When the D flip-flop U1 controls the PMOS tube, the positive and negative electrode outputs of the D flip-flop U1 are connected to the triode, and the triode is controlled to control the on-off of the PMOS tube. When the D flip-flop U1 controls the NMOS tube, the positive and negative electrode outputs of the D flip-flop U1 can be directly connected to the NMOS to control the on-off of the NMOS tube. In this way, the on-off of the MOS tube is controlled by the pulse signal, and the power distribution of the aircraft is also controlled by the pulse signal.

[0063] In an actual application, reference Figure 3 is made to the controller, and the CPU with the model number STM32H743 IIT6 is selected. When the circuit is powered on and works, the PB14 and PB15 pins of the STM32H743 IIT6 need to be configured as a pull-down output mode, and the initial state outputs low.

[0064] At T0, the PB14 outputs a 3.3V high level, which makes the second triode Q2 at the back end conduct, and further pulls the preset signal PRE of U1 low. Since the PRE signal is low and valid, when it takes effect, the positive electrode (Q+) output of U1 outputs a 5V high level. This high level makes the third triode Q3 at the back end conduct, and at this time, the GS voltage of the PMOS tube is half of the input voltage. When the input voltage is 28V, the GS voltage is -14V, which is lower than the conduction voltage (-3V) of the PMOS tube, so the PMOS tube is turned on, and the 28V voltage is output externally. At T1, the PB14 is controlled to return to a low level, the second triode Q2 is cut off, and the PRE signal of U1 is pulled high. At this time, the Q+ end of U1 remains unchanged (T1-T0≥100ms is required).

[0065] When it is needed to turn off the power output, the control PB15 outputs 3.3V high level at T2, which makes the first transistor Q1 conduct, and the clear signal CLR of U1 is pulled low. Since the CLR signal is low active, when it takes effect, the Q+ end of U1 outputs 0V low level. This low level makes the third transistor Q3 cut off, and the GS voltage of the PMOS transistor is equal (0V), which is higher than the conduction voltage (-3.4V) of the PMOS transistor, so the PMOS transistor is cut off, and the 28V voltage output is turned off. Similarly, at T4, the control PB15 returns to low level, the first transistor Q1 is cut off, the CLR signal of U1 is pulled high, and the Q+ end remains the current output state unchanged (T4-T3≥100ms is required).

[0066] The above pulse signal can be output to control the power distribution circuit. In addition, when the STM32H743IIT6 has a program runaway fault or a master-slave switching, the power distribution circuit can still maintain the current state unchanged.

[0067] In the embodiment, a power distribution circuit is provided, as shown in the figure, comprising the power distribution control circuit, a relay 4, wherein, Figure 5

[0068] The first input end and the second input end of the first switch circuit 1 receive preset signals PRE and clear signals CLR respectively, and the first output end and the second output end of the first switch circuit 1 are connected with the first input end and the second input end of the signal maintaining circuit 3 respectively.

[0069] The output end of the signal maintaining circuit 3 is connected with the first input end of the second switch circuit 2, and the signal maintaining circuit 3 is used to maintain the current level for a preset time when the levels of the preset signals PRE and the clear signals CLR change.

[0070] The second input end of the second switch circuit 2 is connected with the first power supply voltage VDD1, and the output end of the second switch circuit 2 is connected with the relay.

[0071] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.​

Claims

1. A power distribution control circuit, characterized in that, include: The circuit comprises a first switching circuit, a second switching circuit, and a signal holding circuit, wherein... The first input terminal and the second input terminal of the first switching circuit receive a clear signal and a preset signal, respectively, and the first output terminal and the second output terminal of the first switching circuit are respectively connected to the first input terminal and the second input terminal of the signal holding circuit. The output terminal of the signal holding circuit is connected to the first input terminal of the second switching circuit. The signal holding circuit is used to maintain the current level for a preset time when the levels of the preset signal and the clear signal change. The second input terminal of the second switching circuit is connected to the first power supply voltage, and the output terminal of the second switching circuit is connected to the load.

2. The power distribution control circuit according to claim 1, characterized in that, The first switching circuit includes: a first switching sub-circuit and a second switching sub-circuit, wherein, The input terminal of the first switching sub-circuit is connected to the reset signal, and the output terminal of the first switching sub-circuit is connected to the first input terminal of the signal holding circuit; The input terminal of the second switching sub-circuit is connected to the preset signal, and the output terminal of the second switching sub-circuit is connected to the second input terminal of the signal holding circuit.

3. The power distribution control circuit according to claim 2, characterized in that, The first switching sub-circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a first transistor, wherein, The control terminal of the first transistor is connected to the first terminal of the second resistor and the first terminal of the third resistor. The first terminal of the first transistor is connected to the first input terminal of the signal holding circuit and the first terminal of the fourth resistor. The second terminal of the first transistor is connected to the second terminal of the third resistor and then grounded. The first end of the first resistor is connected to the second end of the second resistor, the first end of the first resistor is connected to the zeroing signal, and the second end of the first resistor is grounded. The second terminal of the fourth resistor is connected to the second power supply voltage.

4. The power distribution control circuit according to claim 2, characterized in that, The second switching sub-circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, and a second transistor, wherein, The control terminal of the second transistor is connected to the first terminal of the sixth resistor and the first terminal of the seventh resistor. The first terminal of the second transistor is connected to the second input terminal of the signal holding circuit. The second terminal of the second transistor is connected to the second terminal of the seventh resistor and then grounded. The first end of the fifth resistor is connected to the first end of the sixth resistor, the first end of the fifth resistor is connected to the preset signal, and the second end of the fifth resistor is grounded.

5. The power distribution control circuit according to claim 1, characterized in that, The second switching circuit includes: a third switching sub-circuit and a fourth switching sub-circuit, wherein, The first terminal of the third switch sub-circuit is connected to the output terminal of the signal holding circuit, and the second terminal of the third switch sub-circuit is connected to the first terminal of the fourth switch sub-circuit. The second terminal of the fourth switch sub-circuit is connected to the first power supply voltage, and the third terminal of the fourth switch sub-circuit is connected to the load.

6. The power distribution control circuit according to claim 5, characterized in that, The third switching sub-circuit includes: an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a third transistor, wherein, The control terminal of the third transistor is connected to the first terminal of the eleventh resistor and the first terminal of the twelfth resistor. The first terminal of the third transistor is connected to the first terminal of the thirteenth resistor. The second terminal of the third transistor is connected to the second terminal of the twelfth resistor and then grounded. The first end of the eleventh resistor is connected to the output end of the signal holding circuit; The second end of the thirteenth resistor is connected to the first end of the fourth switch sub-circuit.

7. The power distribution control circuit according to claim 5, characterized in that, The fourth switching sub-circuit includes: a fourteenth resistor, a first capacitor, a first diode, and a fourth transistor, wherein, The control terminal of the fourth transistor is connected to the second terminal of the third switch sub-circuit, the first terminal of the fourteenth resistor, the first terminal of the first capacitor, and the anode of the first diode. The first terminal of the fourth transistor is connected to the second terminal of the fourteenth resistor, the second terminal of the first capacitor, and the cathode of the first diode. The first terminal of the fourth transistor is connected to the first power supply voltage, and the second terminal of the fourth transistor is connected to the load.

8. The power distribution control circuit according to claim 1, characterized in that, The signal holding circuit includes: a D flip-flop, wherein, The clock input pin of the D flip-flop is connected to the first output terminal of the first switching circuit, the set pin of the D flip-flop is connected to the second output terminal of the first switching circuit, and the positive output pin of the D flip-flop is connected to the first input terminal of the second switching circuit.

9. The power distribution control circuit according to claim 1, characterized in that, Also includes: A controller, wherein the controller is used to output the preset signal and the reset signal.

10. A power distribution circuit, characterized in that, include: The power distribution control circuit and relay according to any one of claims 1-9, wherein, The first input terminal and the second input terminal of the first switching circuit receive a preset signal and a clear signal, respectively. The first output terminal and the second output terminal of the first switching circuit are connected to the first input terminal and the second input terminal of the signal holding circuit, respectively. The output terminal of the signal holding circuit is connected to the first input terminal of the second switching circuit. The signal holding circuit is used to maintain the current level for a preset time when the levels of the preset signal and the reset signal change. The second input terminal of the second switching circuit is connected to the first power supply voltage, and the output terminal of the second switching circuit is connected to the relay.

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