Chip selection transmitter for multiple signal levels

Abstract

A signal drive circuit (400) includes a first transmit circuit (410) having an input (402) coupled to a source of a chip select signal and an output configured to switch within a first voltage range (406, 408) having a first amplitude; a second transmit circuit (420) having an input (412) coupled to a source of the chip select signal and an output configured to switch within a second voltage range (416, 408) having a second amplitude; and an output node (422) coupled to an output of the first transmit circuit (410) and an output of the second transmit circuit (420). The first amplitude may be lower than the second amplitude.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. non-provisional application No. 18 / 301,769, filed April 17, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This disclosure relates in its entirety to the transition between low-power states and active states in integrated circuits, and more specifically to techniques for adjusting the voltage of signals supplied to memory devices during the transition between low-power states and active states. Background Technology

[0004] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0005] IC devices may include a memory interface having physical layer circuitry configured to read from and write to a double-data-rate random access memory device. The increasing demand for higher data rates necessitates tight timing between the circuits within this memory interface. Therefore, there is a continuous need for new technologies that provide reliable training and calibration techniques for components used to receive clock signals over high-speed data links.

[0006] Some devices constrained by power consumption budgets may operate at different clock speeds and / or voltage levels in different operating states. For example, battery-powered mobile phones typically support full-power, low-power, and sleep operating modes, which can be selected based on the phone's operating state, internal temperature level, and remaining battery capacity or the availability of an external power source. Transitions between active, full-power modes and low-power, idle, and / or sleep modes may require changes to the voltage supplying power to certain circuitry. Transitions between active, full-power modes and low-power, idle, and / or sleep modes may require changes to the voltage range of certain signals. There is a continuous need to improve interface circuitry that operates at multiple signaling voltage levels. Summary of the Invention

[0007] Some aspects of this disclosure relate to systems, apparatuses, methods, and techniques for implementing and calibrating memory interface circuits that can be used with clock signals that can have frequencies varying over a wide range.

[0008] In various aspects of this disclosure, a signal driving circuit includes: a first transmitting circuit having an input portion coupled to a source of a chip select signal and an output portion configured to switch within a first voltage range having a first amplitude; a second transmitting circuit having an input portion coupled to the source of the chip select signal and an output portion configured to switch within a second voltage range having a second amplitude; and an output node coupled to the output portion of the first transmitting circuit and the output portion of the second transmitting circuit. The first amplitude may be lower than the second amplitude.

[0009] In various aspects of this disclosure, a method for driving a chip select signal includes: coupling an input portion of a first transmitting circuit to a source of the chip select signal; coupling an output portion of the first transmitting circuit to an output node; coupling an input portion of a second transmitting circuit to the source of the chip select signal; and coupling an output portion of the second transmitting circuit to the output node. The first transmitting circuit may be configured to drive the output node within a first voltage range having a first amplitude. The second transmitting circuit may be configured to drive the output node within a second voltage range having a second amplitude. The first amplitude may be lower than the second amplitude.

[0010] In various aspects of this disclosure, an apparatus includes: components for generating a first output representing a chip select signal, the components including a first transmitting circuit having an output configured to switch within a first voltage range having a first amplitude; components for generating a second output representing the chip select signal, the components including a second transmitting circuit having an output configured to switch within a second voltage range having a second amplitude; and an output node coupled to the output of the first transmitting circuit and the output of the second transmitting circuit. The first amplitude may be lower than the second amplitude.

[0011] In some aspects, the first transmitting circuit is configured to receive a first enable signal. When the first enable signal is asserted, the output of the first transmitting circuit can actively drive the output node. When the first enable signal is not asserted, the output of the first transmitting circuit can be placed in a high-impedance state. The second transmitting circuit can be configured to receive a second enable signal. When the second enable signal is asserted, the output of the second transmitting circuit can actively drive the output node. When the second enable signal is not asserted, the output of the second transmitting circuit can be placed in a high-impedance state. In one example, when operating in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted. In another example, when operating in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted. During the transition from the first operating mode to the second operating mode, the second enable signal can be asserted, and then the first enable signal is deasserted. When transitioning from the second operating mode to the first operating mode, the first enable signal can be asserted, and then the second enable signal is deasserted.

[0012] In some respects, this output node is configured to be coupled to a memory device via a chip-select channel. In one example, the memory device is LPDDR SDRAM. Attached Figure Description

[0013] Figure 1 Example components and interconnects in a system-on-a-chip (SoC) that may be adapted to implement certain aspects of this disclosure are illustrated.

[0014] Figure 2 This illustrates various aspects of the physical layer circuitry used to read data from a memory device via a data communication link.

[0015] Figure 3 A typical chip select signal driver in a conventional dynamic memory interface circuit is illustrated.

[0016] Figure 4 Chip selection signal drive circuits that can be adapted or configured according to certain aspects of this disclosure are illustrated.

[0017] Figure 5 This is an example Figure 4 The timing diagram illustrates certain aspects of the operation of the chip select signal drive circuit.

[0018] Figure 6 This is a flowchart illustrating an example of a method for selecting a signal for a driver chip according to certain aspects of this disclosure. Detailed Implementation

[0019] The detailed description below, illustrated with reference to the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0020] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any or all of the following: servers, personal computers, smartphones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, handheld computers, personal data assistants (PDAs), wireless email receivers, cellular phones with multimedia internet support, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While these aspects are particularly useful in mobile devices (e.g., smartphones, laptops, etc.) with limited resources (e.g., processing power, battery, size, etc.), they are generally useful in any computing device that can benefit from improved processor performance and reduced power consumption.

[0022] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package containing two or more independent processing units or cores (e.g., CPU cores) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device comprising two or more processing units configured to read and execute program instructions.

[0023] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), blocks of memory (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, regulators, oscillators, etc.), any one or all of which may be included in one or more cores.

[0024] The memory technologies described or referenced herein are suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless specifically stated in the language of the claims. The complexity of mobile computing device architectures has increased and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or structures), and many other resources for executing complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0025] Certain aspects of this disclosure apply to input / output (I / O) circuitry that provides an interface between core circuitry and memory devices. Many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate SDRAM, which may be referred to as low-power DDR SDRAM (LPDDR SDRAM), or in some instances as LPDDRx, where x describes the technology generation of the LPDDR SDRAM. Later-generation LPDDR SDRAMs designed to operate at higher operating frequencies may employ lower voltage levels in the core of the SoC or memory device to mitigate the power increase associated with higher operating frequencies.

[0026] The process technologies used to manufacture semiconductor devices (including IC devices) are constantly being improved. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of the circuitry in an IC device can be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" are used to characterize a specific semiconductor manufacturing process and its corresponding design rules. By using smaller feature sizes to produce smaller transistors that enable the manufacture of higher-density ICs, faster and more efficient technology nodes are continuously being developed.

[0027] Figure 1Example components and interconnects in a System-on-Chip (SoC) 100 suitable for implementing certain aspects of this disclosure are illustrated. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), allowing the processors to operate at much higher frequencies / clock rates than would be possible with off-chip signal propagation. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails), and allows for more coordinated cooperation between the cores.

[0028] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations such as decoding high-definition video, video processing, etc. System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on computing devices. System components and resources 110 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0029] SoC 100 may also include a Universal Serial Bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a Centralized Resource Manager (CRM) 116. SoC 100 may also include input / output modules (not illustrated) for communicating with resources outside the SoC, each of which may be shared by two or more internal SoC components.

[0030] Processors 102, 104, 106, and 108 can be interconnected via interconnect / bus module 122 to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components. This interconnect / bus module may include reconfigurable gate arrays and / or implement a bus architecture. Communication may also be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0031] Interconnect / bus module 122 may include or provide a bus master system configured to grant exclusive control of the bus to SoC components (e.g., processors, peripherals, etc.) (e.g., data transfer in burst mode, block transfer mode, etc.) to achieve set durations, number of operations, number of bytes, etc. In some cases, interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. Memory controller 114 may be a dedicated hardware module configured to manage data flows to and from memory 124 via memory interface / bus 126.

[0032] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic units, discrete hardware circuitry, and other suitable hardware configured to perform various functionalities described throughout this disclosure. In some aspects, the memory 124 may be part of a SoC 100.

[0033] Figure 2 This illustrates some aspects of the physical layer (PHY) circuitry that enables SoC 200 to read data from memory device 240 via data communication link 250. Figure 2 The example shown illustrates data channel 254, data select channel 252, and chip select channel 256. Channels 252, 254, and 256 may include wires, metal traces, pads, pins, and other interconnects or elements of interconnects. Data channel 254 provides a signal path between a data pin (DQ) in data transceiver 204 in SoC 200 and a corresponding data pin (DQ) in data transceiver 244 in memory device 240. Data select channel 252 provides a signal path to data transceiver 202 in SoC 200 for components (RDQS_t and RDQS_c) of differential receive data strobe signals 218 received from data strobe transceiver 242 in memory device 240. Edges or transitions in the data strobe signals 218 received through data select channel 254 provide timing information that can be used to capture data bits from data signals transmitted through data channel 252.

[0034] The inputs of differential gating receiver 212 are configured to receive differential gating signals transmitted via data gating channel 252. The output of differential gating receiver 212 is a single-ended gating signal 220, representing the data gating signal, and is provided to the read capture window circuitry (RCW 210). In one example, RCW 210 is configured to provide a pass signal 222 by aligning an edge (transition) in the single-ended gating signal 220 with a transition in the received data signal 226 output by a pseudo-differential receiver 214, which receives the data signal from data channel 254 at one input and a reference voltage level (Vref 232) at a second input. As used herein, the term pseudo-differential receiver may refer to a differential receiver whose one of its pair of inputs is coupled to a reference voltage source. In the illustrated example, a calibration delay circuit (CDC 208) receives the pass signal 222 and can be configured to generate a read clock signal 224, where an edge occurs after a transition between bits in the received data signal 226. The illustrated example also includes a duty cycle correction circuit (DCC 216) that can be configured to maximize the time available for sampling each bit in the received data signal 226. In this example, the output 228 of DCC 216 can be sampled by a data capture circuit 206 timing via a read clock signal 224 to provide a data output 230. The data capture circuit 206 may include latches, flip-flops, shift registers, combinational logic, and other circuitry.

[0035] Chip select channel 256 provides one or more signal paths for single-ended or differential chip select (CS) signals used to select a region of a memory device or memory device, module, or subsystem for reading data, writing data, or receiving commands. CS signal transmitter 234 in SoC 200 generates CS signals to be transmitted via chip select channel 256 to CS receiver 246 in memory device 240. The depicted channels 252, 254, and 256 exemplify channels that provide signal paths, for example, for multi-bit address signals, multi-bit command and control signals (including control signals for distinguishing read and write operations), indicate that a command will be received by the memory device, and define timing signals for capturing address and command bits.

[0036] Multiple signaling schemes can be defined for interface circuitry supporting certain types of memory devices. For example, interface circuitry supporting LPDDR SDRAM devices can use multiple voltage rails to save power and reduce heat generation during battery-powered mobile operation. Voltage rails are used to distribute power within the IC device, and can be configured to provide power at voltage levels defined by process technology and configured to conform to industry standards for one or more operating modes. Some voltage rails can be configured to provide power at one voltage level in sleep mode and can be reconfigured to provide power at another level in active mode. The amplitudes of control signals, data signals, and / or address signals can conform to the voltage levels defined for power supply in each operating mode. In one example, LPDDR5 SDRAM and LPDDR6 SDRAM drive the CS signal at different signal levels in different operating modes to wake up the SDRAM in a power-down state, thereby saving power consumption when used for battery operation or power-constrained applications such as mobile communications, mobile computing, low-power sensor systems, automotive, and artificial intelligence systems.

[0037] Figure 3 This example illustrates a typical CS signal driver 300 in a conventional LPDDR SDRAM interface circuit. The CS signal driver 300 is connected via a pair of voltage rails (V... DDA Rail 306 and V SS The CS signal driver 300 is powered by a pair of voltage rails 308, which can support the highest signaling amplitude for the CS signal 304, corresponding to the maximum signaling amplitude of the CS signal 304 driving a power-down exit signal. During normal high-speed operation, for example, the CS signal 304 is driven with a lower signaling amplitude to reduce power and switching time. The CS signal driver 300 may include internal circuitry that provides a voltage rise from a low-voltage input signal (IN signal 302) to a higher-voltage CS signal 304. Using driver circuitry that supports higher-voltage power-down mode signaling may affect switching speed and latency during normal high-speed operation.

[0038] Figure 3 Table 310 includes examples illustrating signaling voltages defined for the CS signal in an LPDDR5 interface. The CS signal driver 300 in a typical LPDDR5 interface can be designed to support a power-down mode signaling amplitude (ViH_PD) for power-down exit signal driving, which is higher than the normal mode signaling amplitude (VCS). In the example shown, ViH_PD is greater than twice the VCS. The voltage level of the signaling amplitude in normal mode can correspond to or be compatible with the voltage level of the DRAM input / output (I / O) power supply, which may be referred to herein as V... DDQThe voltage level is measurable relative to a common or reference voltage level, which may correspond to or be referred to as V. SS Voltage level.

[0039] Figure 3 Timing diagram 320 illustrates certain aspects of CS signaling used to control the LPDDR SDRAM device before and after the transition between normal mode and power-down mode 340. Timing is measured or controlled using clock signal 322. In the illustrated example, in normal mode and V... DDQ At the specified voltage level, a first pulse 332 is transmitted via CS channel 326. The first pulse 332 causes the LPDDR SDRAM device to load a power-down command 328 transmitted by the memory controller via command (CA) channel 324. After a delay, the LPDDR SDRAM device enters power-down mode 340. The LPDDR SDRAM device can be configured to exit power-down mode 340 in response to a pulse transmitted via CS channel 326 at a higher nominal ViH_PD voltage level 342 relative to a reference or ground voltage level (nominally ViL_PD voltage level 344). The specification of the LPDDR SDRAM device may define a minimum latching period (t) during which CS is not asserted. CSLCK 330). t CSLCK The duration of 330 corresponds to the time required for the LPDDR SDRAM device to enter power-down mode 340. After exiting power-down mode 340, the memory controller sends a second pulse 334 via CS channel 326. The second pulse 334 is sent at a higher ViH_PD voltage level 342 and is configured to cause the LPDDR SDRAM device to exit power-down mode 340.

[0040] The memory controller can send a No Operation (NOP) code via CA channel 324, and simultaneously send a second pulse 334 via CS channel 326. Then, when CS channel 326 is idle, the memory controller can send a Device Deselection code (DES code 348) via CA channel 324. When the memory subsystem has resumed normal operation, a third pulse 336 is sent along with a valid command via CS channel 326, which is then sent via CA channel 324.

[0041] The LPDDR5 specification defines a slower switching rate for CS signaling to accommodate designs commonly used with conventional CS signal drivers (300). This slower switching rate reduces the design complexity required for optimizing for both normal and power-down modes in circuits powered at the ViH_PD voltage level. By comparison, the data rate achievable using a conventional CS signal driver (300) is likely limited to 1.07 gigabits per second (Gbps), while the data rate achievable using a command / address driver is 2.14 Gbps, and the expected data rate achievable using a DQ driver is approximately 8.53 Gbps.

[0042] Some aspects of this disclosure relate to a low-complexity driver circuit that can be used to drive a variable voltage CS signal without compromising switching rates at different voltage levels. The CS signal driving circuit disclosed herein can be configured to support all signaling voltage levels defined for the CS signal in LPDDR5 and LPDDR6 SDRAM. In one aspect, a CS signal driving circuit is disclosed that can be configured independently for each signaling amplitude to accommodate variations in the rise and fall times of a specified CS signal for LPDDR5 and LPDDR6 SDRAM, as well as later-generation LPDDR SDRAM. In one example, the CS signal driving circuit disclosed herein can be configured to support LPDDR6 SDRAM devices, wherein the CS signal rate can be increased to 3.2 Gbps or higher in normal and / or power-down modes.

[0043] Figure 4 Examples of CS signal drive circuitry 400 adapted or configured according to certain aspects of this disclosure are illustrated. In one example, CS signal drive circuitry 400 is used in a memory subsystem including LPDDR5 SDRAM devices, and in which CS signal drive circuitry 400 may need to operate at a switching frequency of 1.07 Gbps in normal mode. In another example, CS signal drive circuitry 400 is used in a memory subsystem including LPDDR6 SDRAM devices, and in which CS signal drive circuitry 400 may need to operate at a switching frequency of 3.2 Gbps in normal mode. In yet another example, CS signal drive circuitry 400 is used in a memory subsystem including later-generation LPDDR SDRAM devices, and in which CS signal drive circuitry 400 may need to operate at a switching frequency greater than 3.2 Gbps in normal mode.

[0044] The CS signal driving circuit 400 includes a TX-1 transmitter 410 and a TX-2 transmitter 420, which have outputs coupled to the CS channel 430 via an output node 422. For example, the output node 422 may be an I / O pad. Each of the transmitters 410, 420 is powered using at least two power rails. The TX-1 transmitter 410 operates at a higher voltage level and is coupled herein to a voltage level referred to as V. DDA Rail and V at voltage level 406 SS Between rails at voltage level 408. The TX-2 transmitter 420 operates at a lower voltage level and is coupled to V. DDQ rails and V at voltage levels SS Between rails at voltage levels. Each of the transmitters 410 and 420 is controlled by enable signals 404 and 414, which determine when the corresponding transmitter 410 or 420 actively drives the CS channel 430.

[0045] In the illustrated example, TX-1 transmitter 410 can be configured or optimized for a power-down exit mode requiring high-voltage, low-frequency operation, while TX-2 transmitter 420 can be configured or optimized for a normal mode requiring low-voltage and high-frequency operation. In one example, optimization may involve selecting the type of transistors or process technology used to construct transmitters 410, 420. In another example, optimization may involve the number of sequential amplification stages required to sufficiently and effectively amplify input signals 402 or 412 to generate a CS signal with desired voltage amplitude, desired switching speed, and / or desired load drive capability. In another example, optimization may involve the number of transistors required in each amplification stage to span the desired voltage difference between the input and output of transmitters 410 or 420. In another example, optimization may involve the level of bias current required to sufficiently and effectively amplify input signals 402 or 412 to generate a CS signal with desired voltage amplitude, desired switching speed, and / or desired load drive capability. In another example, optimization may involve selecting the voltage rails supplied to transmitters 410 or 420.

[0046] Each transmitter 410, 420 receives an input signal 402 or 412 (IN-1 or IN-2). The input signal 402 or 412 may be derived from a common source of the CS signal and may differ in the type and number of intervening circuits between the common source and the transmitters 410, 420. In one example, the TX-1 transmitter 410 may be fed by circuitry that switches between intermediate voltage levels higher than the circuitry feeding the TX-2 transmitter 420. In another example, the TX-2 transmitter 420 may be fed by circuitry including transistors capable of faster switching times than the circuitry feeding the TX-1 transmitter 410, despite a lower operating voltage level.

[0047] Input signals 402 and 412 can be provided as differential signals. When TX-1 transmitter 410 is enabled, IN-1 input signal 402 drives CS channel 430. When TX-2 transmitter 420 is enabled, IN-2 input signal 412 drives CS channel 430. Each transmitter is enabled or disabled based on the signaling state of the corresponding enable signal 404 or 414 (EN-1 or EN-2). When EN-1 enable signal 404 is asserted, TX-1 transmitter 410 is enabled, and when EN-2 enable signal 414 is asserted, TX-2 transmitter 420 is enabled. When EN-1 enable signal 404 is not asserted, the output of TX-1 transmitter 410 is in a high-impedance state, and when EN-2 enable signal 414 is not asserted, the output of TX-2 transmitter 420 is in a high-impedance state. In the first example, the enable signal is asserted when enable signals 404 and 414 are driven to a high signaling state. In the second example, the enable signal is asserted when enable signals 404 and 414 are driven to a low signaling state. In the third example, the enable signal is asserted when one of enable signals 404 or 414 is driven to a high signaling state, and the other enable signal is asserted when the other enable signal 414 or 404 is driven to a low signaling state.

[0048] The CS signal driving circuit 400 can be configured to enable the TX-2 transmitter 420 during normal operation mode. The CS signal driving circuit 400 can be further configured to enable the TX-1 transmitter 410 during power-down operation mode to transmit a pulse via the CS channel 430, which is configured to cause the LPDDR SDRAM device to exit power-down mode and enter normal mode. Both enable signals 404 and 414 can be asserted during the overlapping period provided at the mode transition to prevent short-duration pulse interference or unexpected transitions in the CS signal transmitted via the CS channel 430.

[0049] Figure 5 This is an example Figure 4 Timing diagram 500 illustrates certain aspects of the operation of the CS signal drive circuit 400. Timing diagram 500 provides an example where the CS signal drive circuit 400 in the memory subsystem generates CS signaling used to control the LPDDR SDRAM device before and after the transition between normal mode and power-down mode 340. Timing is measured or controlled using clock signal 502.

[0050] In the illustrated example, when the memory subsystem operates in normal mode, a first pulse 512 is transmitted via CS channel 506. When the memory subsystem operates in normal mode, the EN-2 signal 414 is asserted, and the first pulse 512 is generated by the TX-2 transmitter 420 in response to a corresponding pulse 522 on the input signal 412 received by the TX-2 transmitter 420. The TX-2 transmitter 420 is powered by V... DDQ Rail 416 is powered and generates a voltage with V DDQ The first pulse 512 defines the nominal voltage amplitude of the voltage level. The first pulse 512 causes the LPDDR SDRAM device to load the power-down command 508 sent by the memory controller through CA channel 504.

[0051] In which t can be corresponding CSLCK 330 (see also) Figure 3 After a delay, the LPDDR SDRAM device enters power-down mode 520 and is configured to exit power-down mode 520 in response to a pulse at a higher ViH_PD voltage level 518 on CS channel 506. After exiting power-down mode 520, the memory controller sends a second pulse 514 on CS channel 506. The second pulse 514 is sent at a higher ViH_PD voltage level 518 and causes the LPDDR SDRAM device to exit power-down mode 520. When the memory subsystem operates in power-down mode 520, the EN-1 signal 404 is asserted, and the second pulse 514 is generated by the TX-1 transmitter 410 in response to a corresponding pulse 524 on the input signal 402 received by the TX-1 transmitter 410. The TX-1 transmitter 410 is powered by V... DDA A voltage level 406 is supplied, and a first pulse 512 with a voltage amplitude satisfying the nominal ViH_PD voltage level 518 defined by the specification is generated. The memory controller can send a NOP code via CA channel 504, and simultaneously send a second pulse 514 via CS channel 506. Then, when CS channel 506 is idle, the memory controller can send a device deselect code (DES code 510) via CA channel 504. A third pulse 516 sent via CS channel 506 is generated by TX-2 transmitter 420 in response to a corresponding pulse 526 on the input signal 412 received by TX-1 transmitter 420. The third pulse 516 is sent concurrently with a valid command that can be sent via CA channel 324 when the memory subsystem has resumed normal operation.

[0052] In some implementations, when the memory subsystem enters and exits power-down mode 520, the EN-1 signal 404 and the EN-2 signal 414 are asserted concurrently. The illustrated example shows a first transition zone 528 and a second transition zone 530, in which the EN-1 signal 404 is asserted and then the EN-2 signal 414 is deasserted, and in the second transition zone, the EN-2 signal 414 is asserted and then the EN-1 signal 404 is deasserted. The simultaneous assertion of the EN-1 signal 404 and the EN-2 signal 414 prevents short-term pulse interference or undetermined signaling states on channel 506 during transitions between operating modes. Transition zones 528 and 530 can be configured to avoid collisions between transmitters 410 and 420. The duration of transition zones 528 and 530 can be selected to ensure that the CS signal is inactive and in a low signaling state during the duration of each transition zone 528 and 530, and that both transmitters 410 and 420 actively drive the CS channel 506 to the same signaling state or the same voltage level.

[0053] In some implementations, when transmitter 410 or 420 is powered, transmitter 410 or 420 actively drives CS channel 506, and the output of transmitter 410 or 420 follows its input by either sourcing or absorbing the current flowing through output node 422. In some implementations, when transmitter 410 or 420 is not actively driving CS channel 506, its output may be in a high-impedance state. The high-impedance output of transmitter 410 or 420 nominally does not source or absorb the current flowing through output node 422, or source or absorb the leakage current flowing through output node 422.

[0054] Figure 6 This is a flowchart illustrating an example of a method 600 for driving a chip selection signal according to certain aspects of this disclosure. In one example, method 600 may use... Figure 4 The CS signal driving circuit 400 illustrated herein is used to implement this, and can be corresponding to Figure 5 This relates to certain aspects of the timing diagram provided. At block 602, the input of the first transmitting circuit can be coupled to the source of the chip select signal. At block 604, the output of the first transmitting circuit can be coupled to the output node. The first transmitting circuit can be configured to drive the output node within a first voltage range having a first amplitude. At block 606, the input of the second transmitting circuit can be coupled to the source of the chip select signal. At block 608, the output of the second transmitting circuit can be coupled to the output node. The second transmitting circuit can be configured to drive the output node within a second voltage range having a second amplitude. The first amplitude may be lower than the second amplitude.

[0055] In some implementations, a first transmitting circuit is configured to receive a first enable signal. When the first enable signal is asserted, the output of the first transmitting circuit can actively drive the output node. When the first enable signal is not asserted, the output of the first transmitting circuit can be placed in a high-impedance state. A second transmitting circuit can be configured to receive a second enable signal. When the second enable signal is asserted, the output of the second transmitting circuit can actively drive the output node. When the second enable signal is not asserted, the output of the second transmitting circuit can be placed in a high-impedance state. In one example, when operating in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted. In another example, when operating in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted. During the transition from the first operating mode to the second operating mode, the second enable signal can be asserted, and then the first enable signal is deasserted. During the transition from the second operating mode to the first operating mode, the first enable signal can be asserted, and then the second enable signal is deasserted.

[0056] In some implementations, the output node is coupled to a memory device via a chip-select channel. In one example, the memory device is LPDDR SDRAM.

[0057] The apparatuses and methods described herein and illustrated in the accompanying drawings can be implemented using various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0058] According to certain aspects of this disclosure, an apparatus configured to operate as a memory interface circuit includes: circuitry or modules configured to generate a first output representing a chip select signal, the circuitry or modules including a first transmitting circuit having an output configured to switch within a first voltage range having a first amplitude; circuitry or modules configured to generate a second output representing the chip select signal, the circuitry or modules including a second transmitting circuit having an output configured to switch within a second voltage range having a second amplitude; and an output node. The output node may be coupled to the output of the first transmitting circuit and the output of the second transmitting circuit. The first amplitude may be lower than the second amplitude.

[0059] In some implementations, a first transmitting circuit is configured to receive a first enable signal. When the first enable signal is asserted, the output of the first transmitting circuit can actively drive the output node. When the first enable signal is not asserted, the output of the first transmitting circuit can be placed in a high-impedance state. A second transmitting circuit can be configured to receive a second enable signal. When the second enable signal is asserted, the output of the second transmitting circuit can actively drive the output node. When the second enable signal is not asserted, the output of the second transmitting circuit can be placed in a high-impedance state. In one example, when the device operates in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted. In another example, when the device operates in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted. During the transition from the first operating mode to the second operating mode, the second enable signal can be asserted, and then the first enable signal is deasserted. During the transition from the second operating mode to the first operating mode, the first enable signal can be asserted, and then the second enable signal is deasserted.

[0060] In some implementations, the output node is configured to be coupled to a memory device via a chip-select channel. In one example, the memory device is LPDDR SDRAM.

[0061] According to at least one example described herein, a signal driving circuit has a first transmitting circuit and a second transmitting circuit coupled to an output node. The first transmitting circuit has an input coupled to a chip select signal source and an output configured to switch within a first voltage range having a first amplitude. The second transmitting circuit has an input coupled to a source of the chip select signal and an output configured to switch within a second voltage range having a second amplitude. The output node may be coupled to the outputs of the first transmitting circuit and the second transmitting circuit. The first amplitude may be lower than the second amplitude.

[0062] In some implementations, a first transmitting circuit is configured to receive a first enable signal. When the first enable signal is asserted, the output of the first transmitting circuit can actively drive the output node. When the first enable signal is not asserted, the output of the first transmitting circuit can be placed in a high-impedance state. A second transmitting circuit can be configured to receive a second enable signal. When the second enable signal is asserted, the output of the second transmitting circuit can actively drive the output node. When the second enable signal is not asserted, the output of the second transmitting circuit can be placed in a high-impedance state. In one example, when the signal driving circuit operates in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted. In another example, when the signal driving circuit operates in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted. During the transition from the first operating mode to the second operating mode, the second enable signal can be asserted, and then the first enable signal is deasserted. During the transition from the second operating mode to the first operating mode, the first enable signal can be asserted, and then the second enable signal is deasserted.

[0063] In some implementations, the output node is configured to be coupled to a memory device via a chip-select channel. In one example, the memory device is LPDDR SDRAM.

[0064] In some implementations, certain functions or portions thereof may be implemented using software residing in a computer-readable form on a storage device or other computer-readable medium. Computer-readable media may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer.

[0065] In some implementations, computer-readable media maintain instructions and information, wherein these instructions are configured to cause one or more processors or controllers to perform certain functions and processes.

[0066] In one example, a processor-readable storage medium stores or maintains code for performing the following operations: coupling an input of a first transmitting circuit to a source of a chip select signal; coupling an output of the first transmitting circuit to an output node, the first transmitting circuit being configured to drive the output node within a first voltage range having a first amplitude; coupling an input of a second transmitting circuit to the source of the chip select signal; and coupling an output of the second transmitting circuit to the output node, the second transmitting circuit being configured to drive the output node within a second voltage range having a second amplitude. The first amplitude may be lower than the second amplitude.

[0067] In some implementations, a first transmitting circuit is configured to receive a first enable signal. When the first enable signal is asserted, the output of the first transmitting circuit can actively drive the output node. When the first enable signal is not asserted, the output of the first transmitting circuit can be placed in a high-impedance state. A second transmitting circuit can be configured to receive a second enable signal. When the second enable signal is asserted, the output of the second transmitting circuit can actively drive the output node. When the second enable signal is not asserted, the output of the second transmitting circuit can be placed in a high-impedance state. In one example, when operating in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted. In another example, when operating in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted. During the transition from the first operating mode to the second operating mode, the second enable signal can be asserted, and then the first enable signal is deasserted. During the transition from the second operating mode to the first operating mode, the first enable signal can be asserted, and then the second enable signal is deasserted.

[0068] In some implementations, the output node is configured to be coupled to a memory device via a chip-select channel. In one example, the memory device is LPDDR SDRAM.

[0069] Some specific implementation examples are described in the following numbered clauses:

[0070] 1. A signal driving circuit, the signal driving circuit comprising: a first transmitting circuit having an input portion coupled to a source of a chip select signal and an output portion configured to switch within a first voltage range having a first amplitude; a second transmitting circuit having an input portion coupled to the source of the chip select signal and an output portion configured to switch within a second voltage range having a second amplitude; and an output node coupled to the output portion of the first transmitting circuit and the output portion of the second transmitting circuit, wherein...

[0071] The first amplitude is lower than the second amplitude.

[0072] 2. The signal driving circuit according to Clause 1, wherein the first transmitting circuit is configured to receive a first enable signal, wherein when the first enable signal is asserted, the output of the first transmitting circuit actively drives the output node, and

[0073] When the first enable signal is not asserted, the output of the first transmitting circuit is in a high-impedance state.

[0074] 3. The signal driving circuit according to Clause 2, wherein the second transmitting circuit is configured to receive a second enable signal, wherein when the second enable signal is asserted, the output of the second transmitting circuit actively drives the output node, and

[0075] When the second enable signal is not asserted, the output of the second transmitting circuit is in a high-impedance state.

[0076] 4. The signal driving circuit according to Clause 3, wherein when the signal driving circuit operates in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted, wherein when the signal driving circuit operates in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted.

[0077] 5. The signal driving circuit according to Clause 4, wherein when transitioning from the first operating mode to the second operating mode, the second enable signal is asserted, and then the first enable signal is deasserted.

[0078] 6. The signal driving circuit according to Clause 4 or Clause 5, wherein, upon transition from the second operating mode to the first operating mode, the first enable signal is asserted, and then the second enable signal is deasserted.

[0079] 7. The signal driving circuit according to any one of Clauses 1 to 6, wherein the output node is configured to be coupled to a memory device via a chip-select channel.

[0080] 8. The signal driving circuit according to Clause 7, wherein the memory device includes low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

[0081] 9. A method for driving a chip select signal, the method comprising: coupling an input portion of a first transmitting circuit to a source of the chip select signal; coupling an output portion of the first transmitting circuit to an output node, the first transmitting circuit being configured to drive the output node within a first voltage range having a first amplitude; coupling an input portion of a second transmitting circuit to the source of the chip select signal; and coupling an output portion of the second transmitting circuit to the output node, the second transmitting circuit being configured to drive the output node within a second voltage range having a second amplitude, wherein the first amplitude is lower than the second amplitude.

[0082] 10. The method according to Clause 9, wherein the first transmitting circuit is configured to receive a first enable signal, wherein when the first enable signal is asserted, the output of the first transmitting circuit actively drives the output node, and wherein when the first enable signal is not asserted, the output of the first transmitting circuit is in a high-impedance state.

[0083] 11. The method according to Clause 10, wherein the second transmitting circuit is configured to receive a second enable signal, wherein when the second enable signal is asserted, the output of the second transmitting circuit actively drives the output node, and wherein when the second enable signal is not asserted, the output of the second transmitting circuit is in a high-impedance state.

[0084] 12. The method according to Clause 11, wherein when operating in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted, and wherein when operating in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted.

[0085] 13. The method according to Clause 12, wherein during the transition from the first operating mode to the second operating mode, the second enable signal is asserted, and then the first enable signal is deasserted.

[0086] 14. The method according to Clause 12 or Clause 13, wherein, upon transition from the second operating mode to the first operating mode, the first enable signal is asserted, and then the second enable signal is deasserted.

[0087] 15. The method according to any one of clauses 9 to 14, the method further comprising: coupling the output node to a memory device via a chip selection channel.

[0088] 16. The method according to Clause 15, wherein the memory device includes low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

[0089] 17. An apparatus comprising: means for generating a first output representing a chip select signal, the means including a first transmitting circuit having an output configured to switch within a first voltage range having a first amplitude; means for generating a second output representing the chip select signal, the means including a second transmitting circuit having an output configured to switch within a second voltage range having a second amplitude; and an output node coupled to the output of the first transmitting circuit and the output of the second transmitting circuit, wherein the first amplitude is lower than the second amplitude.

[0090] 18. The apparatus according to Clause 17, wherein the first transmitting circuit is configured to receive a first enable signal, wherein when the first enable signal is asserted, the output of the first transmitting circuit actively drives the output node, and wherein when the first enable signal is not asserted, the output of the first transmitting circuit is in a high-impedance state.

[0091] 19. The apparatus according to Clause 18, wherein the second transmitting circuit is configured to receive a second enable signal, wherein when the second enable signal is asserted, the output of the second transmitting circuit actively drives the output node, and wherein when the second enable signal is not asserted, the output of the second transmitting circuit is in a high-impedance state.

[0092] 20. The apparatus according to Clause 19, wherein when the apparatus operates in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted, wherein when the apparatus operates in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted.

[0093] 21. The apparatus according to Clause 20, wherein during the transition from the first operating mode to the second operating mode, the second enable signal is asserted, and then the first enable signal is deasserted.

[0094] 22. The apparatus according to Clause 20 or Clause 21, wherein, during the transition from the second operating mode to the first operating mode, the first enable signal is asserted, and then the second enable signal is deasserted.

[0095] 23. The apparatus according to any one of clauses 17 to 22, wherein the output node is configured to be coupled to a memory device via a chip-select channel.

[0096] 24. The apparatus according to Clause 23, wherein the memory device includes low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

[0097] As used herein, the phrase “at least one of” in a list of entries refers to any combination of those entries, including a single member. For example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0098] This disclosure is provided so that any person skilled in the art can make or use various aspects of it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A signal driving circuit, the signal driving circuit comprising: A first transmitting circuit has an input section coupled to a source of a chip selection signal and an output section configured to switch within a first voltage range having a first amplitude. The second transmitting circuit has an input section coupled to the source of the chip selection signal and an output section configured to switch within a second voltage range having a second amplitude. and An output node, which is coupled to the output section of the first transmitting circuit and the output section of the second transmitting circuit. The first amplitude is lower than the second amplitude.

2. The signal driving circuit according to claim 1, wherein the first transmitting circuit is configured to receive a first enable signal, wherein when the first enable signal is asserted, the output of the first transmitting circuit actively drives the output node, and wherein when the first enable signal is not asserted, the output of the first transmitting circuit is in a high impedance state.

3. The signal driving circuit according to claim 2, wherein the second transmitting circuit is configured to receive a second enable signal, wherein when the second enable signal is asserted, the output of the second transmitting circuit actively drives the output node, and wherein when the second enable signal is not asserted, the output of the second transmitting circuit is in a high impedance state.

4. The signal driving circuit according to claim 3, wherein when the signal driving circuit operates in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted, wherein when the signal driving circuit operates in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted.

5. The signal driving circuit of claim 4, wherein when transitioning from the first operating mode to the second operating mode, the second enable signal is asserted, and then the first enable signal is deasserted.

6. The signal driving circuit of claim 4, wherein when transitioning from the second operating mode to the first operating mode, the first enable signal is asserted, and then the second enable signal is deasserted.

7. The signal driving circuit of claim 1, wherein the output node is configured to be coupled to a memory device via a chip-selected channel.

8. The signal driving circuit of claim 7, wherein the memory device comprises low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

9. A method for driving a chip selection signal, the method comprising: The input section of the first transmitting circuit is coupled to the source of the chip selection signal; The output of the first transmitting circuit is coupled to the output node, and the first transmitting circuit is configured to drive the output node within a first voltage range having a first amplitude. The input section of the second transmitting circuit is coupled to the source of the chip selection signal; as well as The output of the second transmitting circuit is coupled to the output node, and the second transmitting circuit is configured to drive the output node within a second voltage range having a second amplitude, wherein the first amplitude is lower than the second amplitude.

10. The method of claim 9, wherein the first transmitting circuit is configured to receive a first enable signal, wherein when the first enable signal is asserted, the output of the first transmitting circuit actively drives the output node, and wherein when the first enable signal is not asserted, the output of the first transmitting circuit is in a high-impedance state.

11. The method of claim 10, wherein the second transmitting circuit is configured to receive a second enable signal, wherein when the second enable signal is asserted, the output of the second transmitting circuit actively drives the output node, and wherein when the second enable signal is not asserted, the output of the second transmitting circuit is in a high-impedance state.

12. The method of claim 11, wherein when operating in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted, and wherein when operating in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted.

13. The method of claim 12, wherein during the transition from the first operating mode to the second operating mode, the second enable signal is asserted, and then the first enable signal is deasserted.

14. The method of claim 12, wherein during the transition from the second operating mode to the first operating mode, the first enable signal is asserted, and then the second enable signal is deasserted.

15. The method according to claim 9, further comprising: The output node is coupled to the memory device via a chip-selected channel.

16. The method of claim 15, wherein the memory device comprises low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

17. An apparatus comprising: A component for generating a first output representing a chip selection signal, the component including a first transmitting circuit having an output configured to switch within a first voltage range having a first amplitude; A component for generating a second output representing the chip selection signal, the component including a second transmitting circuit having an output configured to switch within a second voltage range having a second amplitude; and An output node coupled to the output section of the first transmitting circuit and the output section of the second transmitting circuit, wherein the first amplitude is lower than the second amplitude.

18. The apparatus of claim 17, wherein the first transmitting circuit is configured to receive a first enable signal, wherein when the first enable signal is asserted, the output of the first transmitting circuit actively drives the output node, and wherein when the first enable signal is not asserted, the output of the first transmitting circuit is in a high-impedance state.

19. The apparatus of claim 18, wherein the second transmitting circuit is configured to receive a second enable signal, wherein when the second enable signal is asserted, the output of the second transmitting circuit actively drives the output node, and wherein when the second enable signal is not asserted, the output of the second transmitting circuit is in a high-impedance state.

20. The apparatus of claim 19, wherein when the apparatus operates in a first operating mode, the first enable signal is asserted and the second enable signal is not asserted, wherein when the apparatus operates in a second operating mode, the first enable signal is not asserted and the second enable signal is asserted.

21. The apparatus of claim 20, wherein during the transition from the first operating mode to the second operating mode, the second enable signal is asserted, and then the first enable signal is deasserted.

22. The apparatus of claim 20, wherein during the transition from the second operating mode to the first operating mode, the first enable signal is asserted, and then the second enable signal is deasserted.

23. The apparatus of claim 17, wherein the output node is configured to be coupled to a memory device via a chip-select channel.

24. The apparatus of claim 23, wherein the memory device comprises low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

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