Single-register multiplexing circuit for parameter configuration and parameter configuration method

Abstract

The invention discloses a single-register multiplexing circuit for parameter configuration and a parameter configuration method, and relates to the technical field of parameter configuration.The circuit comprises a set of configuration registers used for storing and providing calibration parameters for an analog IP, and the configuration registers are multiplexed in a test mode and a normal working mode; the multipath selection module is coupled to the data input end of the configuration register and is used for selecting one path of data from a plurality of configuration data sources according to a preset priority strategy and writing the selected path of data into the configuration register; wherein the plurality of configuration data sources at least comprise a default initial value, a nonvolatile memory loading value and a test interface write-in value. The problem that parameters cannot take effect in real time due to the fact that a test register and a working register are separated in a traditional double-register architecture is effectively solved, the calibration parameters written in through an interface in the test stage can directly act on the simulation IP, power-on verification is not needed after a memory is burnt, and the calibration efficiency is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of parameter configuration technology, and in particular to a single-register multiplexing circuit and parameter configuration method for parameter configuration. Background Technology

[0002] Currently, in existing chip designs, the calibration of analog IPs (such as ADCs, PLLs, LDOs, etc.) typically relies on a dual-register architecture: one set is used during the calibration testing phase, allowing calibration parameters to be dynamically written through the test interface; the other set is used for normal operation, with its value loaded from non-volatile memory and write-protected upon power-up. The two sets of registers are switched via a multiplexer based on the mode signal to achieve a balance between testing flexibility and operational stability. However, under this architecture, the parameters written during the testing phase only affect the dedicated test registers and cannot directly drive the actual operating analog IP. This necessitates that the parameters be burned into memory and the system be powered on again after each calibration adjustment to verify the calibration effect, severely limiting testing efficiency. Summary of the Invention

[0003] In view of this, the present invention proposes a single-register multiplexing circuit and a parameter configuration method for parameter configuration, which can realize the instantaneous mapping and verification of calibration parameters. The present invention provides the following technical solution: A single-register multiplexing circuit for parameter configuration includes: A set of configuration registers is used to store and provide calibration parameters to the analog IP, and the configuration registers are multiplexed in test mode and normal operation mode; A multiplexing module, coupled to the data input terminal of the configuration register, is used to select one data source from multiple configuration data sources and write it to the configuration register according to a preset priority strategy; The plurality of configuration data sources include at least: default initial values, non-volatile memory load values, and test interface write values.

[0004] Optionally, the multiplexing module is configured to select data according to a three-level priority strategy: The highest priority is the default initial value, which is forcibly selected when the chip is powered on or reset; The second highest priority is the non-volatile memory load value, which is selected when the non-volatile memory data is ready and the chip is in normal operating mode; The lowest priority is the value written to the test interface, which is selected when the chip is in test mode and has write permissions.

[0005] Optionally, the output of the configuration register is mapped to the control terminal of the analog IP in real time; When an abnormal configuration register value, invalid write permission, or abnormal input source switching is detected, the configuration register value is automatically rolled back to the default initial value to drive the simulated IP into a preset secure working state.

[0006] Optionally, the write operation to the configuration register is subject to permission and exception control logic, including: When the chip is in test mode and receives a high-privilege write command, modification of the configuration register is allowed through the test interface; When the chip is in the secure boot phase and the non-volatile memory data is ready, the high-privilege mode is automatically enabled, and the non-volatile memory load value is written to the configuration register.

[0007] Optionally, the output of the configuration register is coupled to the control input of the analog IP, and after receiving valid write data, the output value of the configuration register is updated to the analog IP in the current clock cycle or the next clock cycle, without relying on a reset signal or power restart operation.

[0008] Optionally, the configuration register is a multi-bit register, where each bit corresponds to a different adjustable parameter in the analog IP. The value of the configuration register directly controls at least one analog characteristic of the analog IP, such as bias current, gain, bandwidth, or timing, through bit mapping.

[0009] This invention further discloses a parameter configuration method applied to the aforementioned single-register multiplexing circuit, comprising the following steps: Calibration parameters are stored and provided to the analog IP through a set of configuration registers, which are reused in test mode and normal operation mode. The multiplexing module coupled to the data input terminal of the configuration register selects one data source from multiple configuration data sources and writes it to the configuration register according to a preset priority strategy. The multiple configuration data sources include at least a default initial value, a non-volatile memory load value, and a test interface write value; The output value of the configuration register is mapped to the control terminal of the analog IP to control its analog characteristics.

[0010] Optionally, selecting one data source from multiple configuration data sources and writing it to the configuration register according to a preset priority strategy includes: When the chip is powered on or reset, the default initial value is forcibly written into the configuration register; When the non-volatile memory data is ready and the chip is in normal operating mode, the non-volatile memory load value is selected and written to the configuration register; When the chip is in test mode and has write permissions, select the test interface to write the value to the configuration register.

[0011] Optionally, it also includes: When an abnormal configuration register value, invalid write permission, or abnormal input source switching is detected, the value of the configuration register is rolled back to the default initial value to drive the simulated IP into a preset secure working state.

[0012] Optionally, the write operation to the configuration register is subject to permission and exception control logic, including: When the chip is in test mode and receives a high-privilege write command, modification of the configuration register is allowed through the test interface; When the chip is in the secure boot phase and the non-volatile memory data is ready, the high-privilege mode is automatically enabled, and the non-volatile memory load value is written to the configuration register.

[0013] According to the technical solution of the present invention, by setting only one set of configuration registers shared in both test mode and normal operation mode, and having the multiplexing module dynamically select the input source from the default initial value, the non-volatile memory load value, and the test interface write value according to a preset priority strategy, the problem of parameters not taking effect in real time due to the separation of test registers and working registers in the traditional dual-register architecture is effectively eliminated. This allows the calibration parameters written through the interface during the test phase to be directly applied to the analog IP without the need to burn the memory and then power on again for verification, significantly improving calibration efficiency. At the same time, this solution eliminates a whole set of redundant registers and their control logic, greatly saving chip area and reducing manufacturing costs while ensuring functional integrity and system security. Attached Figure Description

[0014] For illustrative and not limiting purposes, the present invention will now be described in conjunction with embodiments and accompanying drawings, wherein: Figure 1 This is a schematic diagram of the single-register multiplexing circuit for parameter configuration in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the parameter configuration method in an embodiment of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0016] It should be noted that, where there is no conflict, the embodiments and features of the embodiments in this application can be combined with each other. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0017] refer to Figure 1 This embodiment discloses a single register multiplexing circuit for parameter configuration, including a set of configuration registers 100, a multiplexing module 200, a non-volatile memory 300, a test interface 400, and permission and exception control logic 500.

[0018] The configuration register 100 is a multi-bit register, such as 8-bit, 12-bit, or 16-bit, with the specific bit width determined according to the requirements of the controlled analog IP. Its output is directly coupled to the control input of the analog IP 600. The configuration register 100 is multiplexed in both the chip's test mode and normal operation mode, used both to receive debugging parameters during the CP testing phase and to provide the final calibration value to the analog IP 600 during normal operation. This single-register multiplexing structure eliminates the redundant second set of registers and its switching MUX found in traditional solutions, significantly saving chip area.

[0019] The data input terminal of configuration register 100 is connected to multiplexing module 200. Multiplexing module 200 selects one of the three configuration data sources and writes it to configuration register 100 according to a preset priority strategy. (1) Default initial value, usually the security startup value simulating IP 600, is stored in hardwired logic or read-only register; (2) Memory Load Value, which comes from non-volatile memory 300 (such as eFuse, OTP or Flash). This value is the final calibration parameter burned after the test is completed; (3) Test Interface Write Value: The value is written by an external test device through the test interface 400 (such as I²C, JTAG or dedicated debug bus).

[0020] The multiplexing module 200 employs a three-level priority arbitration mechanism: The highest priority is the default initial value, which is forcibly selected when the chip is powered on or when the reset signal (RST) is valid, ensuring that the system can enter a safe operating point under any abnormal startup state; The second highest priority is the non-volatile memory load value, which is selected when the chip completes power-on initialization, the non-volatile memory 300 data ready signal (MEM_RDY) is valid, and the chip is in normal operating mode (TEST_MODE=0). The lowest priority is the value written to the test interface, which is only selected when TEST_MODE=1 (test mode) and the permission and exception control logic 500 determine that writing is allowed. This three-level priority can be uniformly arbitrated by a lightweight state machine to avoid metastability risks caused by multiple signal contention and improve system robustness.

[0021] Write operations to configuration register 100 are strictly constrained by permission and exception control logic 500. Permission and exception control logic 500 monitors the chip's operating mode, memory status, and write instruction permission bits in real time. A write operation to configuration register 100 is only permitted if any of the following conditions are met: When the chip is in test mode (TEST_MODE=1) and the received write command contains a high-privilege identifier (such as a specific key or privileged address), the write value of test interface 400 can be accepted. When the chip is in the secure boot phase (i.e., a brief window after power-on and before the normal operating mode is enabled), and the MEM_RDY signal of the non-volatile memory 300 is valid, the high-privilege mode is automatically enabled, and the memory load value is written to the configuration register 100. This privilege mechanism effectively prevents unauthorized tampering or misoperation from causing the analog IP to malfunction.

[0022] After valid data is written to the configuration register 100, the output value is updated to the control terminal of the analog IP 600 within the current clock cycle or the next clock cycle, without relying on a reset signal or power restart. For example, in a synchronous digital system, the configuration register 100 can be implemented using an edge-triggered D flip-flop, whose Q output directly drives the analog IP 600's digital-to-analog conversion control unit. This real-time mapping mechanism allows testers to immediately observe the performance response of the analog IP (such as output spectrum, settling time, etc.) after writing new parameters via I²C, without repeated power cycles, significantly shortening the calibration cycle.

[0023] Furthermore, each bit or bit field of the configuration register 100 has a predefined bit mapping relationship with different adjustable parameters in the analog IP 600. For example, bits [7:4] control the bias current intensity, bits [3:2] set the gain level, and bits [1:0] adjust the bandwidth compensation. This structured coding allows a single register to precisely control multiple analog characteristics, avoiding the resource waste of configuring a separate register for each parameter in traditional schemes.

[0024] Furthermore, anomaly detection and rollback mechanisms are integrated into the permission and anomaly control logic 500. When any of the following anomalies are detected: the configuration register 100 value exceeds the valid range, write permission is invalid, a conflict occurs during input source switching, or the non-volatile memory 300 verification fails, the permission and anomaly control logic 500 will immediately force the multiplexer module 200 to switch to its default initial value and lock the output of the configuration register 100, driving the analog IP 600 into a preset safe operating state. This mechanism ensures that even under extreme conditions such as test misoperation or memory damage, the chip can still maintain basic functionality, significantly improving product reliability.

[0025] In summary, this embodiment achieves efficient, secure, and flexible configuration of analog IP parameters while saving area through collaborative design such as single register reuse, three-level priority selection, access control, real-time mapping, and exception rollback, thus overcoming the fundamental defects of existing dual-register architectures.

[0026] refer to Figure 2 This embodiment further discloses a parameter configuration method for analog IP. This method can be executed in a single register multiplexing circuit as described in the foregoing embodiment, and can also be applied to other chip systems with multi-source input selection and register multiplexing capabilities.

[0027] The method in this embodiment includes the following steps: S100: Calibration parameters are stored and provided to the analog IP through a configuration register, which is reused in test mode and normal operation mode. Unlike the traditional dual-register scheme, this method relies on a single register as the sole carrier of parameter configuration, thereby avoiding the verification delay problem caused by the separation of test parameters and operating parameters.

[0028] S200: A multiplexer module coupled to the data input terminal of the configuration register selects one data source from multiple configuration data sources and writes it to the configuration register according to a preset priority strategy. The multiple configuration data sources include at least: a default initial value, a non-volatile memory load value, and a test interface write value. The default initial value is the security boot baseline value for the simulated IP, typically fixed during the chip design phase; the non-volatile memory load value is the final calibration parameter burned after testing; and the test interface write value is sent in real-time by external test equipment during the debugging phase via communication interfaces such as I²C and JTAG.

[0029] The specific execution logic of the priority strategy is as follows: When the chip is powered on or the reset signal is valid, regardless of the current mode, the default initial value is forcibly written to the configuration register to ensure that the analog IP can enter a controllable state under any abnormal startup scenario. When the chip completes power-on initialization, the non-volatile memory data ready signal (MEM_RDY) is valid, and the chip is in normal operating mode (TEST_MODE=0), the non-volatile memory load value is automatically selected and written to the configuration register, so that the analog IP runs in the optimal calibration state. When the chip is in test mode (TEST_MODE=1) and the permission and exception control logic determines that the current write instruction has a high-privilege identifier (such as a specific address, key, or privilege bit), the test interface write value is allowed to be written to the configuration register.

[0030] The three-level priority can be uniformly arbitrated by a lightweight state machine, avoiding logical conflicts or metastability risks caused by concurrent judgments of multiple conditions, and improving the reliability of method execution.

[0031] S300: After a write operation is complete, the output value of the configuration register is mapped to the control terminal of the analog IP within the current clock cycle or the next clock cycle. No reset or power-on waiting is required. For example, in a synchronous system, the configuration register can be implemented using an edge-triggered register, whose output directly drives the analog IP's internal digital-to-analog converter or bias control unit. This real-time mapping mechanism allows testers to immediately observe the analog IP's performance response, such as output spectrum, settling time, and phase noise, through ATE equipment after sending a write command, significantly improving calibration iteration efficiency.

[0032] Furthermore, to ensure system security, this method also includes an anomaly detection and rollback mechanism: during parameter writing or source switching, if an anomaly is detected such as the configuration register value exceeding the legal range, invalid write permission, input source switching conflict, or non-volatile memory verification failure, the current write operation will be immediately aborted, and the configuration register value will be forcibly rolled back to the default initial value. Simultaneously, the simulated IP will be driven into a preset safe operating state. This rollback action is triggered by the hardware anomaly detection module, with a response delay of no more than one clock cycle, ensuring that the simulated IP will not fail due to illegal parameters.

[0033] Furthermore, write operations to configuration registers are strictly constrained by permission and exception control logic. Writes are only permitted if any of the following conditions are met: The chip is in test mode and the received write command contains a high-privilege identifier, which allows modification of the configuration register through the test interface; When the chip is in the secure boot phase (a brief window after power-on and before normal operation mode is enabled), and the non-volatile memory data is ready, the system automatically enables high-privilege mode and writes the memory load value into the configuration register. The privilege identifier and mode signal must be verified together; a single signal is invalid, effectively preventing accidental triggering or malicious tampering.

[0034] In summary, this method achieves efficient, secure, and real-time configuration of simulated IP parameters without relying on additional hardware redundancy, through mechanisms such as single register reuse, three-level priority dynamic selection, permission collaborative verification, and rapid rollback in case of anomalies. This solves the problem of low testing efficiency caused by the inability of parameters to take effect immediately in traditional methods.

[0035] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can occur depending on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A single-register multiplexing circuit for parameter configuration, characterized in that, include: A set of configuration registers is used to store and provide calibration parameters to the analog IP, and the configuration registers are multiplexed in test mode and normal operation mode; A multiplexing module, coupled to the data input terminal of the configuration register, is used to select one data source from multiple configuration data sources and write it to the configuration register according to a preset priority strategy.

2. The single-register multiplexing circuit for parameter configuration according to claim 1, characterized in that, The multiple configuration data sources include at least: default initial values, non-volatile memory load values, and test interface write values; The multiplexing module is configured to select data according to a three-level priority strategy: The highest priority is the default initial value, which is forcibly selected when the chip is powered on or reset; The second highest priority is the non-volatile memory load value, which is selected when the non-volatile memory data is ready and the chip is in normal operating mode; The lowest priority is the value written to the test interface, which is selected when the chip is in test mode and has write permissions.

3. The single-register multiplexing circuit for parameter configuration according to claim 2, characterized in that, The output of the configuration register is mapped to the control terminal of the analog IP in real time. When an abnormal configuration register value, invalid write permission, or abnormal input source switching is detected, the configuration register value is automatically rolled back to the default initial value to drive the simulated IP into a preset secure working state.

4. The single-register multiplexing circuit for parameter configuration according to claim 2, characterized in that, The write operation to the configuration register is subject to permission and exception control logic, including: When the chip is in test mode and receives a high-privilege write command, modification of the configuration register is allowed through the test interface; When the chip is in the secure boot phase and the non-volatile memory data is ready, the high-privilege mode is automatically enabled, and the non-volatile memory load value is written to the configuration register.

5. The single-register multiplexing circuit for parameter configuration according to claim 4, characterized in that, The output of the configuration register is coupled to the control input of the analog IP. After receiving valid write data, the output value of the configuration register is updated to the analog IP in the current clock cycle or the next clock cycle, without relying on a reset signal or power restart operation.

6. The single-register multiplexing circuit for parameter configuration according to claim 1, characterized in that, The configuration register is a multi-bit register, with each bit corresponding to a different adjustable parameter in the analog IP. The value of the configuration register directly controls at least one analog characteristic of the analog IP, such as bias current, gain, bandwidth, or timing, through bit mapping.

7. A parameter configuration method, applied to a single-register multiplexing circuit as described in any one of claims 1-6, characterized in that, Includes the following steps: Calibration parameters are stored and provided to the analog IP through a set of configuration registers, which are reused in test mode and normal operation mode. The multiplexing module coupled to the data input terminal of the configuration register selects one data source from multiple configuration data sources and writes it to the configuration register according to a preset priority strategy. The multiple configuration data sources include at least a default initial value, a non-volatile memory load value, and a test interface write value; The output value of the configuration register is mapped to the control terminal of the analog IP to control its analog characteristics.

8. The parameter configuration method according to claim 7, characterized in that, The step of selecting one data source from multiple configuration data sources and writing it to the configuration register according to a preset priority strategy includes: When the chip is powered on or reset, the default initial value is forcibly written into the configuration register; When the non-volatile memory data is ready and the chip is in normal operating mode, the non-volatile memory load value is selected and written to the configuration register; When the chip is in test mode and has write permissions, select the test interface to write the value to the configuration register.

9. The parameter configuration method according to claim 7, characterized in that, Also includes: When an abnormal configuration register value, invalid write permission, or abnormal input source switching is detected, the value of the configuration register is rolled back to the default initial value to drive the simulated IP into a preset secure working state.

10. The parameter configuration method according to claim 7, characterized in that, The write operation to the configuration register is subject to permission and exception control logic, including: When the chip is in test mode and receives a high-privilege write command, modification of the configuration register is allowed through the test interface; When the chip is in the secure boot phase and the non-volatile memory data is ready, the high-privilege mode is automatically enabled, and the non-volatile memory load value is written to the configuration register.

Images