A CRC check code generation circuit

Abstract

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a CRC check code generation circuit. BACKGROUND

[0002] Cycle Redundancy Check (CRC) is one of the data transmission check methods, which uses polynomial division and remainder as the detection of possible errors after data transmission. In the field of computer networks, communication networks and most high-speed interface transmission protocols, CRC field is defined for data error check, so CRC implementation is a widely used channel coding technology.

[0003] With the development of technology, the system processing data throughput is getting larger and larger, and the bit width of data in the CRC implementation circuit is getting larger and larger, and the working frequency is also required to be higher and higher. However, according to the characteristics of CRC coding, if the CRC calculation result of large bit width is obtained in one clock cycle, the combinational logic will be very large, which will affect the working frequency of the CRC circuit and thus affect the performance of the whole system. In addition, under the design mode of large bit width, the data length to be calculated is often not an integer multiple of the data bit width, resulting in the need to calculate CRC circuits of different bit widths. It can be seen that the traditional CRC implementation method not only occupies a large amount of combinational logic resources, but also has a low running working frequency. Therefore, how to reduce the combinational logic resources occupied by the CRC check code generation circuit and improve the running working frequency of the CRC check code generation circuit has become a technical problem to be solved. SUMMARY

[0004] The present application aims to provide a CRC check code generation circuit, which can reduce the combinational logic resources occupied by the CRC check code generation circuit and improve the running working frequency of the CRC check code generation circuit.

[0005] According to the first aspect of the present application, a CRC check code generation circuit is provided, which comprises J first calculation units, J second calculation units, J XOR units and a J-way selector.

[0006] The first input end of the jth first calculation unit is used to receive the jth data block of the current data to be processed, the jth data block is the data from the (j-1)xi bit to the jxi-1 bit of the current data to be processed, i is the bit width of the data block received by the second input end of the first calculation unit, the length X of the current data to be processed is less than or equal to jxi, and X can be divided by i, and the value range of j is 1 to J.

[0007] The second input end of the jth first calculation unit is configured to receive data 0 when j = 1, and the first input end of the jth first calculation unit is configured to receive output data of a (j-1)th first calculation unit when j > 1.

[0008] The jth first calculation unit is configured to generate output data corresponding to the jth first calculation unit based on data of the first input end and data of the second input end by performing first calculation unit operation logic, and transmit the output data corresponding to the jth first calculation unit to a second input end of a (j+1)th first calculation unit and a first input end of a jth exclusive or unit, the first calculation unit operation logic being configured to generate the output data corresponding to the first calculation unit by performing a modulo-2 addition operation based on the data of the first input end and the data of the second input end.

[0009] The jth second calculation unit is configured to generate output data corresponding to the jth second calculation unit based on a current initial value and data 0 by performing jth second calculation unit operation logic, and transmit the output data corresponding to the jth second calculation unit to a second input end of the jth exclusive or unit, the jth second calculation unit operation logic being configured to be simplified based on preset component circuits of the jth second calculation unit.

[0010] The jth exclusive or unit is configured to perform an exclusive or operation based on the output data corresponding to the jth first calculation unit and the output data corresponding to the jth second calculation unit to generate output data corresponding to the jth exclusive or unit, and transmit the output data corresponding to the jth exclusive or unit to a jth input port of the J-way selector.

[0011] The J-way selector is configured to gate the kth input port, and determine input data of the kth input port as the CRC check code of the current to-be-processed data for output, k being an integer quotient of X / i.

[0012] Further, the preset component circuits of the jth second calculation unit include j basic calculation units connected in sequence, wherein an input of a first basic calculation unit is the current initial value and the data 0, an input of a kth basic calculation unit is output data of a (k-1)th basic calculation unit and the data 0, output data of a jth basic calculation unit is the output data of the jth second calculation unit, k ranges from 2 to j, and each basic calculation unit performs a modulo-2 addition operation based on two inputs.

[0013] Further, if a target data bit width Y is less than or equal to j×i, the target data is directly taken as the current to-be-processed data, an operation is performed by the CRC check code generation circuit, and output data of the J-way selector is determined as the CRC check code of the target data.

[0014] Further, the output end of the jth first calculation unit is connected with the second input end of the j+1th first unit and the first input end of the jth exclusive OR unit respectively;

[0015] The output end of the jth second calculation unit is connected with the second input end of the jth exclusive OR unit;

[0016] The output end of the jth exclusive OR unit is connected with the jth input port of the J-way selector.

[0017] Further, each first calculation unit, each second calculation unit and each exclusive OR unit can perform corresponding operation once per cycle, and the J-way selector selects the kth input port in the k+1th cycle when the CRC check code generation circuit processes the current to-be-processed data.

[0018] Further, if the target data bit width Y>j×i, the target data is divided into R to-be-processed data, if r

[0019] In the order of r from small to large, each to-be-processed data is taken as the current to-be-processed data in turn with an interval of one cycle, and the corresponding CRC check code is obtained through the CRC check code generation circuit;

[0020] When r

[0021] When r=R, the CRC check code corresponding to the Rth to-be-processed data is determined as the CRC check code of the target data.

[0022] Further, i is set as 8 and j is set as 128.

[0023] Further, the output end of the jth first calculation unit is connected with the second input end of the j+1th first unit and the first input end of the jth exclusive OR unit respectively,

[0024] The output end of the jth second calculation unit is connected with the second input end of the jth exclusive OR unit;

[0025] The output end of the jth exclusive OR unit is connected with the jth input port of the J-way selector.

[0026] The output port of the J-way selector is connected with the input port of each jth second calculation unit.

[0027] Compared with the prior art, the present application has obvious advantages and beneficial effects. By means of the above technical scheme, the CRC check code generation circuit provided by the present application can achieve considerable technical progress and practicability, and has wide industrial utilization value, and at least has the following beneficial effects:

[0028] The CRC check code generation circuit provided by the present application can realize pipeline technology, and can realize CRC check code generation of data with different lengths without setting CRC calculation circuits with different bit widths, thereby reducing the combination logic resources of the CRC check code generation circuit and greatly improving the working frequency of the CRC check code generation circuit due to the pipeline design. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0030] Figure 1 The CRC check code generation circuit structure diagram provided by the present application is shown. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0032] The present application provides a CRC check code generation circuit, as shown in Figure 1 including J first calculation units, J second calculation units, J XOR units and a J-way selector.

[0033] The first input end of the jth first calculation unit is configured to receive a jth data block of the current to-be-processed data, the jth data block is data from a (j-1)xi bit to a jxi-1 bit of the current to-be-processed data, i is a bit width of a data block received by the second input end of the first calculation unit, a length X of the current to-be-processed data is less than or equal to jxi, and X is divisible by i, that is, a result of dividing X by i is an integer, and j is in a range of 1 to J. As a preferred example, i is set to 8, and j is set to 128.

[0034] It should be noted that the current to-be-processed data is divided into g(X) data blocks, g(X) is the result of dividing X by i. If g(X) is less than J, the (g(X)+1)th to Jth first calculation unit, the (g(X)+1)th to Jth second calculation unit, and the (g(X)+1)th to Jth exclusive or unit can be set not to perform operations when processing the current to-be-processed data.

[0035] When j is 1, the second input end of the jth first calculation unit is configured to receive data 0, and when j is greater than 1, the first input end of the jth first calculation unit is configured to receive output data of a (j-1)th first calculation unit.

[0036] The jth first calculation unit is configured to generate output data corresponding to the jth first calculation unit based on data of the first input end and data of the second input end by performing first calculation unit operation logic, and transmit the output data corresponding to the jth first calculation unit to the second input end of a (j+1)th first calculation unit and the first input end of a jth exclusive or unit.

[0037] The first calculation unit operation logic is to generate output data corresponding to the first calculation unit by performing a modulo-2 addition operation based on data of the first input end and data of the second input end. It should be noted that, during processing of the current to-be-processed data, the J first calculation units collectively implement obtaining a result of performing a modulo-2 addition operation based on 0 and the current to-be-processed data.

[0038] The jth second calculation unit is configured to generate output data corresponding to the jth second calculation unit based on a current initial value and data 0 by performing jth second calculation unit operation logic, and transmit the output data corresponding to the jth second calculation unit to the second input end of the jth exclusive or unit.

[0039] The operation logic corresponding to the jth second calculation unit is operation logic generated based on a preset composition circuit of the jth second calculation unit, the preset composition circuit of the jth second calculation unit includes j sequentially connected basic calculation units, the input of the first basic calculation unit is the current initial value and data 0, the input of the kth basic calculation unit is the output data of the (k-1)th basic calculation unit and data 0, the output data of the jth basic calculation unit is the output data of the jth second calculation unit, the value range of k is 2 to j, and each basic calculation unit performs a modulo-2 addition operation based on two input data. It should be noted that the second calculation unit is used to perform a modulo-2 addition operation based on the current initial value and data 0. In the initial state, the current initial value of the second calculation unit is set to a preset CRC initial value.

[0040] The jth exclusive OR unit is used to perform an exclusive OR operation based on the output data corresponding to the jth first calculation unit and the output data corresponding to the jth second calculation unit, generate output data corresponding to the jth exclusive OR unit, and transmit the output data corresponding to the jth exclusive OR unit to the jth input port of the J-way selector.

[0041] The J-way selector is used to gate the kth input port, determine the input data of the kth input port as the CRC check code of the current to-be-processed data, and output the CRC check code, and k is the quotient of X / i.

[0042] It should be noted that only one of the J exclusive OR units is used to obtain the CRC check code of the current to-be-processed data, that is, the kth exclusive OR unit. Specifically, it can be set that when the data of the two input ends of the kth exclusive OR unit are input during the process of processing the current to-be-processed data, the kth exclusive OR unit is started to perform the corresponding exclusive OR operation, and the other exclusive OR units do not run. Alternatively, each exclusive OR unit can be normally run, and the J-way selector can subsequently select the output data corresponding to the kth exclusive OR unit as the CRC check code of the current to-be-processed data for output.

[0043] The CRC check code generation circuit described in the embodiment of the application can be specifically applied in application scenarios such as CRC generation and CRC check.

[0044] It should be noted that the existing CRC check code is generated based on the following formula:

[0045] C(1)=f(C init ,d1)

[0046] C(2)=f(C(1),d2) ...

[0047] C(n)=f(f(...f(C init ,d1),d2)...),dn ) ...

[0048] C(N) = f(f(...f(C init ,d1),d2),...),d N )

[0049] Among them, C init d is the preset CRC initial value. n Let N be the nth bit of the current data to be processed, C(n) be the CRC checksum generated based on the first n bits of the current data to be processed, and f() be a function that performs modulo-2 addition based on the corresponding input data. In the prior art, when N takes different values, different CRC checksum generation circuits need to be set up to obtain and generate the corresponding CRC checksums. It is necessary to select the CRC checksum generation circuit from N sets of circuits according to the valid bit indication, which is resource-intensive and has a low operating frequency.

[0050] In this embodiment of the invention, C(N) = f(f(...f(C) is first set to f(f(...f(C)). init ,d1),d2),...),d N It can be transformed into C(N) = F(C) init D n ), D n For the set {d1,d2,...,d... n ,...,d N In the data in}, n ranges from 1 to N. F() is a function that performs modulo-2 addition based on the corresponding input data. It can be understood that f() and F() are different functions because they take different inputs. When only K bits of N data are valid for CRC checksum generation, the following equation is obtained: C(K) = F(C init D K ), D k For the set {d1,d2,...,d... k ,...,d K In the value}, k ranges from 1 to K, where K <N。

[0051] Existing technologies acquire CRC checksums within a single cycle, making direct pipelined implementation impossible. Therefore, this invention further refines C(N) = F(C init D n The function F() performs transformations and splits because its operations are based on modulo-2 addition, and the modulo-2 addition of any number and the data 0 results in itself. Therefore, C(N) = F(C). init D n This can be transformed into C(N) = F(0, D) n )⊕F(C init,0), after deformation, D can be n and C init Implement them separately, and you can use D n After splitting, based on pipeline design, D n It can be further divided into multiple data blocks of length i. F(0,D) n The calculation of the ) part is implemented through j first calculation units in the CRC check code generation circuit, F(C init The operation of F(0,D) is implemented through j second calculation units in the CRC checksum generation circuit. n )⊕F(C init The final result of (0) is obtained based on the outputs of the first computing unit, the second computing unit, j XOR units, and J-way selector.

[0052] Example 1

[0053] The output of the j-th first calculation unit is connected to the second input of the (j+1)-th first unit and the first input of the j-th XOR unit, respectively; the output of the j-th second calculation unit is connected to the second input of the j-th XOR unit; the output of the j-th XOR unit is connected to the j-th input port of the J-way selector.

[0054] Each first computing unit, each second computing unit, and each XOR unit can perform a corresponding operation once in each cycle. The J-channel selector selects the k-th input port in the (k+1)-th cycle of the CRC checksum generation circuit when it processes the current data to be processed.

[0055] If the target data bit width Y ≤ j × i, the target data is directly used as the current data to be processed. The CRC checksum generation circuit performs calculations to determine the output data of the J-channel selector as the CRC checksum of the target data. The target data is the data for which a CRC checksum needs to be generated. It can be understood that when the target data bit width Y ≤ j × i, the CRC checksum generation circuit only needs to perform one round of calculations to obtain the CRC checksum of the target data. Furthermore, the CRC checksum generation circuit can obtain the CRC checksum of target data with any bit width less than or equal to j × i.

[0056] Example 2

[0057] The output of the j-th first calculation unit is connected to the second input of the (j+1)-th first unit and the first input of the j-th XOR unit, respectively; the output of the j-th second calculation unit is connected to the second input of the j-th XOR unit.

[0058] The output end of the jth exclusive OR unit is connected with the jth input port of the J-way selector; and the output port of the J-way selector is connected with the input port of each jth second calculation unit.

[0059] Each first calculation unit, each second calculation unit and each exclusive OR unit can perform a corresponding operation once per cycle; and the J-way selector selects the kth input port in the k+1th cycle of processing the current to-be-processed data.

[0060] If the target data bit width Y > j×i, the target data is first divided into R pieces of to-be-processed data; if r < R, the length of the rth piece of to-be-processed data is equal to j×i; if r = R, the length of the rth piece of to-be-processed data is ≤ j×i; and the value range of r is 1 to R. It should be noted that when the target data bit width Y > j×i, the CRC check code generation circuit performs multiple rounds of operations to obtain the CRC check code of the target data, and therefore the target data needs to be first divided into multiple pieces of to-be-processed data.

[0061] In the order of r from small to large, each piece of to-be-processed data is sequentially taken as the current to-be-processed data at intervals of one cycle to obtain a corresponding CRC check code through the CRC check code generation circuit. It should be noted that the time when the rth piece of to-be-processed data starts to be processed through the CRC check code generation circuit and the time when the r+1th piece of to-be-processed data starts to be processed through the CRC check code generation circuit are at intervals of one cycle, so that the CRC check code generation circuit can be reused to process each piece of to-be-processed data in parallel, and the accuracy of the CRC check code of the final output target data can be ensured.

[0062] When r < R, after the CRC check code corresponding to the rth piece of to-be-processed data is generated, the J-way selector transmits the CRC check code corresponding to the rth piece of to-be-processed data to the input port of each jth second calculation unit, and each jth second calculation unit updates the current initial value to the CRC check code corresponding to the rth piece of to-be-processed data, so that the current initial value used in the second calculation unit during the generation of the CRC check code corresponding to the r+1th piece of to-be-processed data is the CRC check code corresponding to the rth piece of to-be-processed data; and when r = R, the CRC check code corresponding to the Rth piece of to-be-processed data is determined as the CRC check code of the target data.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0064] It is to be understood that some of the example embodiments are described in terms of a process or method depicted as a flowchart. Although a flowchart can describe operations as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations can be re-arranged. A process is terminated when its operations are completed, but could also terminate without completing its operations due to, for example, a system shutdown. A process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0065] An electronic device is also provided, including: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to perform the method according to the embodiments of the application.

[0066] A computer readable storage medium is also provided, storing computer executable instructions, and the computer executable instructions are configured to perform the method according to the embodiments of the application.

[0067] The CRC code generation circuit provided by the embodiments of the application can implement pipeline technology, and can generate CRC codes of data of different lengths without setting CRC calculation circuits of different bit widths, thereby reducing the combination logic resources of the CRC code generation circuit and greatly improving the working frequency of the CRC code generation circuit due to the pipeline design.

[0068] The above merely describes the preferred embodiments of the present application, but not any form of limitation to the present application. Although the present application has been disclosed as the above preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some minor changes or modifications to the above disclosed technical contents to make equivalent embodiments with equivalent changes, but as long as the changes or modifications do not deviate from the technical solution of the present application, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application shall still fall within the scope of the technical solution of the present application.

Claims

1. A CRC check code generation circuit, Characterized in that, It comprises J first computing units, J second computing units, J XOR units and a J-way selector; The first input end of the jth first computing unit is configured to receive the jth data block of the current data to be processed, the jth data block being data from the (j-1)xi bit to the jxi-1 bit of the current data to be processed, i being the bit width of the data block received by the second input end of the first computing unit, the length X of the current data to be processed being less than or equal to jxi, and X being divisible by i, the value of j being in the range of 1 to J; When j=1, the second input end of the jth first computing unit is configured to receive data 0, and when j>1, the first input end of the jth first computing unit is configured to receive the output data of the (j-1)th first computing unit; The jth first computing unit is configured to perform first computing unit operation logic based on the data of the first input end and the data of the second input end to generate the output data corresponding to the jth first computing unit, and transmit the output data corresponding to the jth first computing unit to the second input end of the (j+1)th first computing unit and the first input end of the jth XOR unit, the first computing unit operation logic being a binary addition operation based on the data of the first input end and the data of the second input end to generate the output data corresponding to the first computing unit; The jth second computing unit is configured to perform the operation logic corresponding to the jth second computing unit based on the current initial value and data 0 to generate the output data corresponding to the jth second computing unit, and transmit the output data corresponding to the jth second computing unit to the second input end of the jth XOR unit, the operation logic corresponding to the jth second computing unit being an operation logic generated by simplifying a preset composition circuit of the jth second computing unit; The jth XOR unit is configured to perform XOR operation based on the output data corresponding to the jth first computing unit and the output data corresponding to the jth second computing unit to generate the output data corresponding to the jth XOR unit, and transmit the output data corresponding to the jth XOR unit to the jth input port of the J-way selector; The J-way selector is configured to select the kth input port, determine the input data of the kth input port as the CRC check code of the current data to be processed, and output the CRC check code, k being the quotient of X / i.

2. The CRC check code generation circuit according to claim 1, characterized in that, The preset composition circuit of the jth second computing unit comprises j basic computing units connected in sequence, wherein the input of the first basic computing unit is the current initial value and data 0, the input of the kth basic computing unit is the output data of the (k-1)th basic computing unit and data 0, the output data of the jth basic computing unit being the output data of the jth second computing unit, the value of k being in the range of 2 to j, and each basic computing unit performing binary addition operation based on two input data.

3. The CRC check code generation circuit according to claim 1, characterized in that, If the target data bit width Y≤j×i, the target data is directly taken as the current data to be processed, and the CRC check code is generated by the CRC check code generation circuit, and the output data of the J-way selector is determined as the CRC check code of the target data.

4. The CRC check code generation circuit of claim 3, wherein, the output end of the jth first calculation unit is connected with the second input end of the j+1th first calculation unit and the first input end of the jth exclusive OR unit respectively; the output end of the jth second calculation unit is connected with the second input end of the jth exclusive OR unit; the output end of the jth exclusive OR unit is connected with the jth input port of the J-way selector.

5. The CRC check code generation circuit of claim 1, wherein, each first calculation unit, each second calculation unit and each exclusive OR unit can perform corresponding operation once in each cycle, and the J-way selector selects the kth input port in the k+1th cycle when the CRC check code generation circuit processes the current data to be processed.

6. The CRC check code generation circuit of claim 5, wherein, if the target data bit width Y>j×i, the target data is first divided into R pieces of data to be processed, the length of the rth piece of data to be processed is equal to j×i when r in the order of r from small to large, each piece of data to be processed is taken as the current data to be processed in turn at an interval of one cycle, and the corresponding CRC check code is obtained by the CRC check code generation circuit; when r when r=R, the CRC check code corresponding to the Rth piece of data to be processed is determined as the CRC check code of the target data.

7. The CRC check code generation circuit of claim 6, wherein, the output end of the jth first calculation unit is connected with the second input end of the j+1th first calculation unit and the first input end of the jth exclusive OR unit respectively, the output end of the jth second calculation unit is connected with the second input end of the jth exclusive OR unit; the output end of the jth exclusive OR unit is connected with the jth input port of the J-way selector; the output port of the J-way selector is connected with the input port of each jth second calculation unit.

8. The CRC check code generation circuit of claim 1, wherein, i is set to 8, and j is set to 128.

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