A heterogeneous phototransistor based on a double ferroelectric layer, its fabrication method and application

Abstract

This invention provides a heterogeneous phototransistor based on a double ferroelectric layer, its fabrication method, and its applications, belonging to the field of high-performance sensing and integrated sensing-memory-computing technology. The heterogeneous phototransistor includes a bottom gate substrate, a bottom gate dielectric layer, and a heterostructure stacked thereon. The heterostructure consists of a ferroelectric semiconductor bismuth oxide selenide layer, a bismuth selenite oxide dielectric layer, and a ferroelectric semiconductor α-phase indium selenide layer. Source and drain electrodes are provided on both sides of the ferroelectric semiconductor α-phase indium selenide layer. This invention utilizes the structural symmetry breaking characteristic of the ferroelectric semiconductor in the double ferroelectric layer structure to achieve a direction-sensitive response to linearly polarized light. Simultaneously, through the polarization coupling between the two ferroelectric semiconductor layers, supplemented by the suppression of electrostatic energy and the blocking of carrier migration by the intermediate bismuth selenite oxide dielectric layer, the polarization state is effectively stabilized, giving the device significant non-volatile electrical characteristics. This invention can achieve in-situ encryption of optical information at the sensing end.

Description

Technical Field

[0001] This invention belongs to the field of high-performance sensing and integrated sensing-storage-computing technology, and relates to in-situ encryption of image information based on ferroelectric-photoelectric multiplepolarization devices with in-situ heterostructure phototransistors. Specifically, it relates to a heterostructure phototransistor based on a double ferroelectric layer, its fabrication method, and its application. Background Technology

[0002] The Internet of Things (IoT) era has brought severe challenges to the data security of edge sensors, and sensing data encryption technology has become a key barrier to protect privacy. As the most important form of sensing data, image data, due to its rich spatial and feature information, places higher demands on encryption technology. Current mainstream image encryption technologies can be divided into two methods: optical and electrical. Optical encryption utilizes lens combinations and surface microstructures on metasurfaces to effectively convert image information for encryption. Although it can fully utilize various dimensions of optical information (light intensity, wavelength, polarization direction, etc.), it faces problems such as the large size of optical components and difficulties in key changes / reconfiguration. Electrical encryption achieves image encryption by converting optical signals collected by remote CMOS sensors into a data stream through analog-to-digital conversion, and then executing complex encryption algorithms such as AES and RSA in a dedicated encryption engine. Although it provides a reconfigurable and rich key space, it requires data transmission and complex calculations between the sensor and the encryption unit, leading to increased latency and energy consumption. Furthermore, the data remains exposed at the sensing end, making it vulnerable to theft and attacks. In-sensor encryption based on phototransistors can simultaneously perform sensing operations and utilize device characteristics to encrypt optical information, thereby improving data encryption security while reducing complex hardware footprint and data latency. However, existing solutions still have significant limitations in terms of key space dimension and multidimensional optical information processing capabilities, restricting their practical application scope. Therefore, there is an urgent need to explore new device structures and operating methods to design an in-situ image encryption hardware with high key space and multidimensional optical information response capabilities. Summary of the Invention

[0003] To achieve in-situ sensing and storage of image information within a device, this invention provides a heterojunction phototransistor based on a double ferroelectric layer and its fabrication method. This device can perform in-situ transformation and storage of optical information within the device based on the polarization direction of the incident light and the initial conductivity state of the device. It also expands the device's memory window, effectively increasing the available key space, thereby achieving in-situ encryption of optical information. This ensures that the sensed data remains in a non-exposed state during acquisition, significantly improving the overall security of information sensing and transmission.

[0004] The technical solution provided by this invention is as follows:

[0005] A heterogeneous phototransistor based on a double ferroelectric layer has a structure comprising a bottom gate substrate, a bottom gate dielectric layer, and a heterogeneous structure stacked thereon. The heterogeneous structure consists of a ferroelectric semiconductor bismuth oxy selenide layer (Bi2O2Se), a bismuth oxy selenite (β-Bi2SeO5) dielectric layer, and a ferroelectric semiconductor α-phase indium selenide layer (α-In2Se3) from bottom to top. Source and drain electrodes are provided on both sides of the ferroelectric semiconductor α-phase indium selenide layer.

[0006] Furthermore, the bottom gate substrate is a silicon substrate, the bottom gate dielectric layer is hafnium oxide with a thickness in the range of 10-20 nm, the thickness of the ferroelectric semiconductor bismuth oxide selenide layer is in the range of 5-15 nm, the thickness of the bismuth selenite oxide dielectric layer is in the range of 2-5 nm, the thickness of the ferroelectric semiconductor α-phase indium selenide layer is in the range of 20-40 nm, and the source / drain electrode material is a Ti / Au electrode with a thickness not exceeding 90 nm.

[0007] This invention further provides a method for fabricating a heterogeneous phototransistor based on a double ferroelectric layer, comprising the following steps:

[0008] 1) Define the gate electrode region on the silicon substrate using electron beam exposure;

[0009] 2) A metal layer is prepared by electron beam evaporation deposition and then stripped with acetone solution to form a gate electrode;

[0010] 3) Electron beam exposure defines the gate dielectric region of the array;

[0011] 4) Atomic layer deposition and stripping with acetone solution to form the bottom gate dielectric layer;

[0012] 5) Two-dimensional bismuth oxy selenide and indium selenide single-crystal nanosheets were synthesized on mica substrates by chemical vapor deposition.

[0013] 6) Two-dimensional bismuth-oxygen selenide single-crystal nanosheets were transferred onto the bottom gate dielectric layer using polymethyl methacrylate (PMMA);

[0014] 7) Bismuth oxyselenium is partially oxidized using an oxygen plasma treatment method to generate a bismuth oxyselenite dielectric layer;

[0015] 8) Two-dimensional indium selenide single-crystal nanosheets were transferred onto a bismuth selenite dielectric layer using polymethyl methacrylate (PMMA) to form a heterostructure;

[0016] 9) Locate the heterostructure, and use electron beam exposure to define the source and drain electrode regions sequentially;

[0017] 10) Electron beam evaporation was used to prepare Ti / Au metal layers, and acetone was used for peeling to form source and drain electrodes;

[0018] Furthermore, the specific parameters for the treatment method in step 7) are: oxygen flow rate of 20-30 sccm, power of 25-30 watts, and treatment time of 5-8 minutes.

[0019] The present invention further provides a method for implementing an on-chip sensing-storage-computing integrated chip, characterized in that the sensing-storage-computing integrated chip includes an array of heterogeneous phototransistors arranged periodically based on a double ferroelectric layer. The devices in the array are programmed to different conductance states by a gate voltage pulse as an electrical key. After receiving illumination from an optical pattern, the sensing-storage-computing integrated chip filters the input optical image information through a light polarization-sensitive effect, so that the light signal containing the correct polarization state is mapped into the devices in the array. An electrical signal is output through the photoelectric coupling effect within the device, completing the in-situ sensing and encryption operation of the optical image information.

[0020] This invention's heterogeneous phototransistor utilizes the structural symmetry breaking characteristic of the ferroelectric semiconductors in a double ferroelectric layer structure to achieve a direction-sensitive response to linearly polarized light, serving as the first layer of optical encryption and decryption. Simultaneously, through the polarization coupling between the two ferroelectric semiconductor layers, supplemented by the suppression of electrostatic energy and the obstruction of carrier migration by the intermediate bismuth selenite dielectric layer, the polarization state is effectively stabilized, giving the device significant non-volatile electrical characteristics. Under optical signal excitation, relying on the photoinduced ferroelectric polarization reversal effect, the device's output current exhibits a non-volatile differentiated response according to the initial polarization state, serving as the second layer of electrical encryption. This achieves in-situ encryption of optical information at the sensing end.

[0021] The advantages of this invention are as follows:

[0022] 1) Using a double ferroelectric semiconductor layer bismuth oxy selenide and an α-phase indium selenide, with the primary oxide layer of bismuth oxy selenide as the intermediate dielectric layer, this structure was designed for the first time and achieved an increased hysteresis window, i.e. an expanded storage space and a larger anisotropy ratio of linearly polarized light.

[0023] 2) By introducing an intermediate dielectric layer of bismuth oxyselenite, the device effectively suppresses interlayer charge injection and leakage, stabilizes the ferroelectric polarization state, and maintains stable performance even under repeated read / write operations, ensuring the long-term reliability of the encryption function. Utilizing the unique photo-induced polarization reversal characteristics of ferroelectric semiconductor materials, the device current is influenced by both the initial polarization state and optical information, laying the foundation for the device's characteristics in ferroelectric-optoelectronic encryption.

[0024] 3) The device can integrate optical sensing, non-volatile storage and encryption functions into one. While sensing optical signals, it can directly complete the encryption transformation using physical mechanisms, so that the original data is in ciphertext state at the acquisition end, which fundamentally avoids the risk of leakage during transmission and greatly improves information security.

[0025] 4) The device innovatively combines optical (polarization direction) and electrical (conductivity state programmed by gate voltage) physical variables as encryption keys, significantly increasing the key space. Furthermore, the encryption mechanism based on ferroelectric-optocoupler coupling is highly complex, difficult to derive from external measurements, and possesses excellent anti-cracking capabilities. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the heterogeneous phototransistor based on a double ferroelectric layer according to the present invention;

[0027] Figures 2-6 This is a schematic diagram of the fabrication process steps for a heterogeneous phototransistor with a double ferroelectric layer in a specific embodiment of the present invention, wherein:

[0028] Figure 2 This refers to the steps involved in growing hafnium oxide on a p++ silicon substrate via atomic layer deposition.

[0029] Figure 3 A step-by-step method for transferring bismuth selenide grown on a mica substrate using hydrofluoric acid and PMMA wet-assisted transfer;

[0030] Figure 4 The steps involve treating the surface of bismuth oxyselenide with an oxygen plasma cleaner to partially generate bismuth oxyselenite.

[0031] Figure 5 A method for transferring α-phase indium selenide grown on a mica substrate using hydrofluoric acid and PMMA wet-assisted transfer;

[0032] Figure 6 The steps include defining the source and drain regions for electron beam exposure, depositing Ti / Au via electron beam evaporation, and then immersing the area in acetone solution overnight for stripping.

[0033] Figure 7A schematic diagram of a planar structure of a periodically arranged device array fabricated for repeated use of the above-mentioned multiple exposure overlay process; the structure of each individual device is consistent with that described above.

[0034] Figure 8 The electrical hysteresis characteristic curves of the device of the present invention and other comparative structural devices are shown.

[0035] Figure 9 This is a comparison of the memory window values ​​of the device of the present invention with those of other comparative structural devices;

[0036] Figure 10 This invention provides a gate-voltage programmable multi-conductance state characteristic for the device.

[0037] Figure 11 The current of the device of the present invention changes over time under illumination by linearly polarized light in different directions;

[0038] Figure 12 This describes the response behavior of the device of the present invention to optical signals with the same incident direction and optical power under different initial conductivity states;

[0039] Figure 13 This is the current distribution of the device of the present invention under different initial conductance states for different optical powers in the same incident direction;

[0040] Figure 14 This invention provides an encrypted electrical information current mapping diagram output by the device array after simultaneously receiving inputs containing 90-degree polarized light information (target information) and 0-degree polarized light information (interference information) and after photoelectric conversion encoding of the ferroelectric key within the device.

[0041] Figure 15 This is a flowchart illustrating the process of in-situ character encryption and decryption within a sensor using the device array of the present invention.

[0042] Figure 16 The curves showing the change in recognition accuracy of the encryption device with polarization sensitivity and the device without polarization sensitivity in character recognition tasks are compared with the number of training iterations.

[0043] In the figure: 1—Heavily doped silicon bottom gate substrate; 2—Hafnium oxide bottom gate dielectric layer; 3—Bismuth oxy selenide ferroelectric semiconductor layer; 4—Bismuth oxy selenide intermediate dielectric layer; 5—α-phase indium selenide ferroelectric semiconductor layer; 6—Drain electrode; 7—Source electrode; 8—Heterogeneous phototransistor in the array. Detailed Implementation

[0044] The following description, in conjunction with the accompanying drawings, uses examples to illustrate the ferroelectric-optocoupler device with a double ferroelectric layer proposed in this invention and its application in in-situ image information encryption.

[0045] like Figure 1As shown, the heterogeneous phototransistor based on a double ferroelectric layer of the present invention includes a bottom gate substrate, a bottom gate dielectric layer and a heterostructure located on the bottom gate dielectric layer. The heterostructure consists of a ferroelectric semiconductor bismuth oxy selenide layer, a bismuth selenite oxy dielectric layer and a ferroelectric semiconductor α-phase indium selenide layer from bottom to top. Source and drain electrodes are provided on both sides of the ferroelectric semiconductor α-phase indium selenide layer.

[0046] The specific embodiment of this invention provides the following fabrication process for a heterogeneous phototransistor based on a double ferroelectric layer:

[0047] 1) Using water and tetra(dicarboxymethyl)hafnium as precursors, a 20 nm hafnium oxide bottom gate dielectric was grown by atomic layer deposition at 90 °C on a p++ silicon substrate, such as... Figure 2 As shown;

[0048] 2) Using bismuth oxide and bismuth selenide as precursors, 10 nm thick two-dimensional bismuth oxide selenide single-crystal nanosheets were synthesized on a fluorophlogopite substrate via chemical vapor deposition. Using indium selenide as a precursor, 40 nm thick two-dimensional indium selenide single-crystal nanosheets were synthesized on a fluorophlogopite substrate via chemical vapor deposition.

[0049] 3) A PMMA layer was spin-coated onto the mica substrate with two-dimensional bismuth-oxygen-selenium nanosheets. The specific process was as follows: spin-coating at 500 rpm for 5 seconds, then at 3000 rpm for 55 seconds, followed by drying on a 170°C hot plate for 3 minutes; then immersing in hydrofluoric acid solution for selective etching of the mica for 8 hours; transferring the PMMA film with the two-dimensional bismuth-oxygen-selenium nanosheets onto a Si / HfO2 substrate using ultrapure water, followed by drying on a 75°C hot plate for 1 minute to remove moisture from the film; immersing in acetone solution for 1 hour to remove PMMA, then drying as described above. Figure 3 As shown;

[0050] 4) The surface bismuth-oxygen selenium layer was oxidized using a plasma cleaner at a power of 20 W and an oxygen flow rate of 30 sccm for 7 minutes. Figure 4 As shown;

[0051] 5) Spin-coat a layer of PMMA onto the mica substrate with grown two-dimensional indium selenide nanosheets. The specific process is as follows: spin-coat at 500 rpm for 5 seconds, then at 3000 rpm for 55 seconds, followed by drying on a 180°C hot plate for 3 minutes; then immerse in hydrofluoric acid solution for selective etching of the mica for 30 minutes; use ultrapure water to flip the PMMA film with the two-dimensional indium selenide nanosheets onto polydimethylsiloxane (PDMS); use a two-dimensional transfer alignment platform to transfer it over the bismuth oxyselenosilane / bismuth oxyselenosemate structure, heat to 80°C for 20 minutes, then lift out the PDMS; immerse the film in acetone solution for 1 hour to remove the PMMA, then blow dry. Figure 5 As shown;

[0052] 6) Using electron beam lithography, source and drain electrodes are sequentially defined on the heterostructure. Then, an electron beam evaporation deposition technique is used to prepare a metal layer Ti / Au = 5 / 45nm. Subsequently, acetone is used to remove excess photoresist, forming the source and drain electrodes. Figure 6 As shown.

[0053] like Figure 7 As shown, the device is expanded into a device array composed of periodically arranged individual devices to achieve encryption of multi-pixel images. The top view illustrates the construction method of the device array, with the structure of each individual device consistent with that described earlier.

[0054] The heterogeneous phototransistor device of this invention exhibits excellent crystal anisotropy, with varying response current magnitudes for polarized light at different angles, laying the foundation for optical encryption. Due to the existence of the photoinduced ferroelectric polarization reversal mechanism, the device's photoresponse current is non-volatile, meaning that the encrypted data and ciphertext can be stored in situ at the sensing end, reducing data transmission, improving data security, and facilitating the construction of edge-segment security sensing systems.

[0055] An array of periodically arranged heterogeneous phototransistors with double ferroelectric layers forms an on-chip sensing, storage, and computing integrated chip. A gate voltage pulse presets the heterogeneous phototransistors in the array to different conductance states, serving as an electrical key. Each pixel of the image information is converted into an optocoupled optical signal. After receiving the optical pulse, the array uses polarization filtering to map the optical signal onto the heterogeneous phototransistor, completing in-situ encryption of the image information. This achieves direct encryption, reduces data exposure, and constructs a secure edge sensing device.

[0056] This invention compares indium selenide (ISS) channel devices, bismuth oxy selenide (BOS) channel devices, and indium selenide / bismuth oxy selenide (ISS / BOS) heterojunction devices without a bismuth selenite oxide dielectric layer. Electrical tests were performed on the device using a chip test bench and a 1500A semiconductor parameter analyzer. Different amplitude electrical pulse signals were applied, and the device's characteristics were verified by applying optical signals with different polarization directions and illumination intensities using devices such as polarizers, half-wave plates, lasers, and random signal generators. The electrical hysteresis characteristics of the heterojunction phototransistor device based on a double ferroelectric layer are as follows: Figure 8 As shown, compared to a single ferroelectric layer transistor, the double ferroelectric layer heterotransistor of the present invention has a significantly expanded hysteresis window. Figure 9 As shown, the hysteresis window of the heterogeneous phototransistor in a specific embodiment of the present invention is 5.6 volts, which is much larger than the hysteresis window of other comparative structures, and in particular, it achieves a significant improvement of 87% compared to single indium selenide transistor devices.

[0057] The multi-conductance state gate piezoelectric programming capability of the heterogeneous phototransistor in a specific embodiment of the present invention was tested, such as... Figure 10 As shown, by adjusting the amplitude of the write and erase voltage pulse sequences, the device can achieve gradually increasing and decreasing conductance states, with a total of 128 conductance states. This verifies that it has increased memory capacity and can be programmed into different initial conductance states by gate voltage pulses. When used in subsequent image encryption applications, this increased key space effectively improves the security of encryption.

[0058] like Figure 11 As shown, the photocurrent of the heterogeneous phototransistor of this invention after being irradiated by incident light pulses at different polarization angles was tested according to a specific embodiment of the invention. The experimental results show that the photoresponse current of the device under linearly polarized light in different directions has significant differences, reflecting the polarization-sensitive characteristics of the device due to the anisotropy of the material. Among them, the ratio of the linearly polarized photocurrent perpendicular to the two polarization directions (i.e., 90 degrees and 0 degrees) reached 3.4, laying the foundation for the optical encryption and decryption capabilities of the device.

[0059] like Figure 12 As shown, in a specific embodiment of the present invention, a heterogeneous phototransistor is irradiated with a light pulse signal of the same polarization direction and intensity under different initial conductance states (i.e., different initial polarization states), and the changes in the source and drain current of the device over time are recorded. The different source and drain current values ​​after irradiation indicate that the device responds differently to the same light information under different conductance states. Therefore, when a gate piezoelectric pulse of different amplitude writes the key into the initial conductance state of the device, the conversion of the light signal (image plaintext) can be completed inside the device, and the conductance becomes ciphertext after the device responds. Furthermore, the non-volatile response current of the device indicates that not only photoconductivity exists inside the device, but also photoinduced ferroelectric polarization reversal. The free electron-hole pairs generated by the incident light in the device will separate under the combined action of the built-in electric field and the depolarization field within the device, neutralizing some of the polarization charge, thereby changing the polarization intensity of the device.

[0060] like Figure 13 As shown, the post-conductance of the heterogeneous phototransistor in a specific embodiment of the present invention is statistically analyzed under different initial conductance states (i.e., different initial polarization states) and light pulse signals with different illumination intensities and the same polarization direction. Due to photoconductivity and photoinduced ferropolar polarization reversal, the device output conductance exhibits a nonlinear relationship with light intensity and initial conductance state. This enhances the security of the device's internal encryption, making it difficult for external systems to crack.

[0061] like Figure 14As shown, the device array of this invention is simultaneously input with light pattern information containing different polarization directions. The "CH" input on the left, representing the 90-degree polarization direction, is the target pattern information to be encrypted, while the "25" input on the 0-degree polarization direction represents the interfering erroneous light pattern information. The color of each pixel in the pattern represents the intensity of the input light. This mixed optical pattern is then irradiated onto the device array, and a mixed optical information encryption process is performed. Specifically, because the ferroelectric heterojunction device has polarization-sensitive characteristics, it can selectively enhance information in specific polarization directions during the encryption process, i.e., it identifies the pattern information "CH" with the "correct" 90-degree polarization direction. Before performing the encryption operation, a gate piezoelectric pulse is first input to program each device unit in the array to a different conductance state. Thus, upon receiving light information, the device array can generate different electrical signal responses to the light information based on different conductance states. The output conductance mapping is the in-situ encryption result of the optical image information. The color of each pixel in the image represents the magnitude of the output conductance. As shown on the far right, the encrypted ciphertext information significantly confuses the original image information, thus achieving the in-situ optical image encryption function.

[0062] like Figure 15 The diagram illustrates the implementation process of in-situ encryption and decryption of real handwritten character images using a large-scale array based on the device of this invention. The left side shows the "correct" image information (character "8") input with 90-degree polarization, while simultaneously inputting erroneous interference information (character "9") with 0-degree polarization. Under normal circumstances, it is difficult to distinguish the correct information from this mixed image. If traditional photodiode chips are used for image encryption, the output photoresponse current must first be converted into a digital signal via an analog-to-digital circuit, and then encrypted using encryption algorithms such as AES and RSA to obtain the ciphertext information. However, because such devices lack physical encryption capabilities sensitive to polarized light, as shown in the right figure, the decrypted information is a confused optical image, which cannot be accurately restored to the correct image information. In contrast, using the device of this invention, the initial conductance state of the device array can be used as the key, and the image encryption process is completed directly within the device, with the device conductance change as the primary manifestation. Meanwhile, due to the polarization-sensitive characteristics of the device of the present invention, as shown in the right figure, it can accurately decrypt and extract the correct image information, demonstrating the innovation and effectiveness of the ferroelectric-photoelectric coupling response capability of the device of the present invention for in-situ optical image perception-encryption computing integration.

[0063] like Figure 16As shown, by comparing the decryption accuracy of the device with optical signal polarization direction sensitivity provided by this invention with that without such sensitivity in encrypted images containing interfering characters, the results show that introducing polarization sensitivity significantly improves the character recognition accuracy of the decrypted image from 70% to 98%. This comparison demonstrates that in complex interference scenarios, relying solely on electrical encryption and decryption mechanisms has limitations, while combining encryption and decryption capabilities with optical dimensions can substantially enhance data security. This verifies that this invention is suitable for edge-end sensing data security hardware systems with stringent reliability requirements.

[0064] The embodiments described above are not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A hetero-phototransistor based on two ferroelectric layers, characterized in that, The hetero-optoelectron transistor comprises a bottom gate substrate, a bottom gate dielectric layer and a heterostructure stacked thereon, the heterostructure is composed of a ferroelectric semiconductor bismuth oxyselenide layer, a bismuth oxyselenide selenite dielectric layer and a ferroelectric semiconductor alpha phase indium selenide layer from bottom to top, source-drain electrodes are arranged on both sides of the ferroelectric semiconductor alpha phase indium selenide layer, the thickness of the ferroelectric semiconductor bismuth oxyselenide layer is in the range of 5-15 nm, the thickness of the bismuth oxyselenide selenite dielectric layer is in the range of 2-5 nm, and the thickness of the ferroelectric semiconductor alpha phase indium selenide layer is in the range of 20-40 nm.

2. The dual ferroelectric layer based hetero-phototransistor of claim 1, wherein, The bottom gate substrate is a silicon substrate.

3. The dual ferroelectric layer based hetero-phototransistor of claim 1, wherein, The bottom gate dielectric layer is hafnium oxide, and the thickness is in the range of 10-20 nm.

4. The dual ferroelectric layer based hetero-phototransistor of claim 1, wherein, The material of the source-drain electrode is Ti / Au, and the thickness is not more than 90 nm.

5. The preparation method of the double ferroelectric layer based hetero-optoelectron transistor according to claim 1, comprising the following steps: 1) Electron beam exposure is performed on the silicon substrate to define the gate electrode area; 2) A metal layer is prepared by electron beam evaporation and is stripped using acetone solution to form the gate electrode; 3) Electron beam exposure is performed to define the gate dielectric area of the array; 4) Atomic layer deposition is performed and acetone solution is used for stripping to form the bottom gate dielectric layer; 5) Two-dimensional bismuth oxyselenide and indium selenide monocrystal nanosheets are synthesized on the mica substrate by chemical vapor deposition method; 6) The two-dimensional bismuth oxyselenide monocrystal nanosheets are transferred to the bottom gate dielectric layer by using polymethyl methacrylate; 7) The bismuth oxyselenide is partially oxidized by using oxygen plasma treatment method to form a bismuth oxyselenide selenite dielectric layer; 8) The two-dimensional indium selenide monocrystal nanosheets are transferred to the bismuth oxyselenide selenite dielectric layer by using polymethyl methacrylate to form a heterostructure; 9) The heterostructure is positioned, and the source electrode and the drain electrode areas are defined by electron beam exposure in sequence; 10) Ti / Au metal layer is prepared by electron beam evaporation, and is stripped using acetone solution to form the source electrode and the drain electrode.

6. The method of fabricating a hetero-photo-transistor according to claim 5, wherein The specific parameters of the treatment method of step 7) are as follows: the oxygen flow is 20-30 sccm, the power is 25-30 watts, and the treatment time is 5-8 minutes.

7. An on-chip perception-storage-computation integrated implementation method, characterized in that, The perception-storage-computation integrated chip comprises an array of the double ferroelectric layer based hetero-optoelectron transistor according to claim 1, and the devices in the array are programmed to different conductance states by gate voltage pulses as electrical keys, after the perception-storage-computation integrated chip receives optical pattern irradiation, the input optical image information is screened by light polarization sensitive effect, so that the optical signals containing correct polarization states are mapped into the devices in the array, and the electrical signals are output by the photoelectric coupling effect in the devices, thereby completing the in-situ perception and encryption operation of the optical image information.

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