Memory testing method and electronic equipment

Abstract

The invention discloses a memory testing method and electronic equipment, and relates to the technical field of memory testing, and the memory testing method comprises the steps that a testing environment is dynamically configured according to serial existence detection parameters of a to-be-tested memory, so that a testing criterion is accurately matched with a memory specification, and the testing accuracy and pertinence are remarkably improved; meanwhile, dynamic adjustment of the protection threshold is achieved by comparing the power supply parameters with the serial existence detection parameters in real time, mistaken interruption is avoided, the test continuity is guaranteed, response can be made in time when real abnormity occurs, the test efficiency is effectively improved, and the memory damage risk is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory testing, and in particular to a memory testing method and an electronic device. BACKGROUND

[0002] In the related art, memory testing usually needs to monitor the signal waveform of the memory during operation with the help of an oscilloscope or other external devices, and by analyzing the amplitude, frequency, phase and other characteristics of the signal, it is determined whether there is an abnormality in the memory data transmission, clock synchronization and the like, but it is difficult to analyze in depth in the face of complex faults such as data transmission abnormalities, internal defects of memory chips and the like; in addition, in order to protect the electrical performance of the memory, the memory testing fixture is equipped with an overvoltage and overcurrent protection circuit, but the overvoltage and overcurrent protection circuit is mostly set with a fixed threshold value, which cannot match the complex and diverse working voltage and current range of different memories, and the fixed threshold value either leads to misjudgment, frequently cutting off normal power supply and interfering with the testing process, or is slow to react when a real abnormality occurs, and cannot protect the memory in time, increasing the risk of memory damage. SUMMARY

[0003] The present application provides a memory testing method and an electronic device to at least solve the problem of insufficient diagnostic depth and rigid protection strategy in the face of complex faults in the related art, which leads to the problem that the testing efficiency and protection reliability are difficult to be balanced.

[0004] The present application provides a memory testing method, which comprises: collecting a serial presence detect parameter of a memory to be tested; sending an initialization instruction to the memory to be tested and receiving response information of the memory to be tested, and in the case that it is determined that the initialization of the memory to be tested is successful according to the response information, testing the memory to be tested based on the serial presence detect parameter to obtain a test result; and in the process of testing the memory to be tested, collecting an actual power supply parameter of the memory to be tested based on a preset time interval, and performing a corresponding protection operation based on the actual power supply parameter and the serial presence detect parameter.

[0005] The present application also provides an electronic device, which comprises: a memory, a processor and a memory testing program stored in the memory and executable on the processor, and when the processor executes the memory testing program, the memory testing method described above is realized.

[0006] The memory testing method of the present application dynamically configures the test environment according to the serial presence detect parameter of the memory to be tested, so that the test criterion is accurately matched with the memory specification, which significantly improves the accuracy and pertinence of the test; at the same time, the dynamic adjustment of the protection threshold value is realized by real-time comparison of the power supply parameter and the serial presence detect parameter, which not only avoids false interruption and ensures the continuity of the test, but also responds in time when a real abnormality occurs, effectively improving the testing efficiency and reducing the risk of memory damage. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0008] Figure 1 The flow chart of the memory testing method according to some embodiments of the present application; Figure 2 The structural schematic diagram of the memory testing system according to some embodiments of the present application; Figure 3 The structural schematic diagram of the mechanical adaptation unit according to some embodiments of the present application; Figure 4 The flow chart of the memory testing method according to some other embodiments of the present application; Figure 5 The block schematic diagram of the electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0009] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0010] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are applicable to distinguish similar objects, and are not used to describe a specific order or sequence.

[0011] In order to make the skilled in the art better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0012] In combination with the specific application environment architecture or specific hardware architecture on which the memory testing method is executed, the specific application environment architecture or specific hardware architecture is described here.

[0013] The embodiments of the present application provide a memory testing method, and the method is described in detail in combination with the execution flow of the memory testing method.

[0014] Figure 1 A flowchart of a memory testing method according to some embodiments of the present application. Referring to Figure 1 The memory testing method of the embodiments of the present application can include the following steps: S110, collecting serial presence detection parameters of the memory to be tested.

[0015] Specifically, after the memory to be tested is installed into the memory testing fixture, the memory testing fixture reads the JEDEC (Joint Electron Device Engineering Council) standard information in the SPD (Serial Presence Detect) chip of the memory to be tested through the SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit) communication interface integrated thereon, i.e., reads the serial presence detection parameters, which include the type, capacity, reference power supply parameters (such as reference power supply voltage and reference power supply current), reference amplitude parameters and reference timing parameters of the memory data signal, address signal and clock signal of the memory to be tested, etc.

[0016] S120, sending an initialization instruction to the memory to be tested and receiving response information of the memory to be tested, and in the case that it is determined according to the response information that the initialization of the memory to be tested is successful, testing the memory to be tested based on the serial presence detection parameters to obtain a test result.

[0017] Specifically, after the serial presence detection parameters of the memory to be tested are collected, the memory testing fixture sends an initialization instruction, such as the MRS (Mode Register Set) and EMRS (Extended Mode Register Set) instruction of DDR5 (Double Data Rate 5 Synchronous Dynamic Random-Access Memory), to the memory to be tested and receives the response information of the memory to be tested; then, the response information is matched with the expected value, and in the case that the response information is consistent with the expected value, it is determined that the initialization of the memory to be tested is successful; then, the memory testing fixture sends a test instruction to the memory to be tested, the memory to be tested executes corresponding test operations based on the test instruction to obtain corresponding test data, and returns the test data to the memory testing fixture, and the memory testing fixture matches the test data with the serial presence detection parameters to obtain a test result.

[0018] S130, during the testing of the to-be-tested memory, collecting actual power supply parameters of the to-be-tested memory based on a preset time interval, and performing corresponding protection operations based on the actual power supply parameters and the serial existence detection parameters. The preset time interval can be determined according to actual conditions, for example, the preset time interval can be 1 minute, which is not limited here.

[0019] Specifically, during the testing of the to-be-tested memory, the memory test fixture collects the actual power supply parameters of the to-be-tested memory every preset time interval, compares the actual power supply parameters with the serial existence detection parameters, determines whether protection operations need to be performed according to the comparison result, and performs specific protection operations in the case of determining that protection operations need to be performed. For example, if it is determined according to the comparison result that the actual power supply parameters are relatively large, it is determined that protection operations need to be performed, for example, the power supply to the to-be-tested memory is stopped.

[0020] The memory test method of the present application dynamically configures the test environment according to the serial existence detection parameters of the to-be-tested memory, so that the test criteria are accurately matched with the memory specifications, which significantly improves the accuracy and pertinence of the test. At the same time, by comparing the power supply parameters with the serial existence detection parameters in real time, the dynamic adjustment of the protection threshold is realized, which not only avoids false interruption and ensures the continuity of the test, but also responds in time when there is a real exception, effectively improves the test efficiency and reduces the risk of memory damage.

[0021] In some embodiments, the serial existence detection parameters include a reference power supply voltage and a reference power supply current of the to-be-tested memory, the actual power supply parameters include an actual power supply voltage and an actual power supply current, and performing corresponding protection operations based on the actual power supply parameters and the serial existence detection parameters includes: determining a voltage protection threshold based on the product of the reference power supply voltage and a preset protection coefficient; determining a current protection threshold based on the product of the reference power supply current and the preset protection coefficient; and performing corresponding protection operations according to the voltage protection threshold, the current protection threshold, the actual power supply voltage and the actual power supply current. The preset protection coefficient can be calibrated according to actual conditions, for example, the preset protection coefficient can be 0.95, which is not limited here.

[0022] Specifically, after the memory to be tested is installed to the memory test fixture, the memory test fixture collects the serial presence detect parameters of the memory to be tested through the communication interface, the serial presence detect parameters of the memory to be tested including a reference supply voltage of the memory to be tested and a reference supply current of the memory to be tested, wherein the reference supply voltage is used to represent the maximum supply voltage that the memory to be tested can bear, and the reference supply current is used to represent the maximum supply current that the memory to be tested can bear; then, the voltage protection threshold is determined based on the product of the reference supply voltage and a preset protection coefficient, and the current protection threshold is determined based on the product of the reference supply current and the preset protection coefficient, thereby realizing the individual customization of the protection threshold; finally, during the testing process of the memory to be tested by the memory test fixture, the actual supply voltage and the actual supply current are collected every preset time interval, and it is determined whether the protection operation needs to be performed according to the voltage protection threshold, the current protection threshold, the actual supply voltage and the actual supply current, for example, the actual supply voltage is compared with the voltage protection threshold, and at the same time, the actual supply current is compared with the current protection threshold, if the difference between the voltage protection threshold and the actual supply voltage is large, and the difference between the current protection threshold and the actual supply current is also large, it is determined that the protection operation does not need to be performed; if the difference between the current protection threshold and the actual supply current is large, but the difference between the voltage protection threshold and the actual supply voltage is small, it is determined that the protection operation needs to be performed, for example, the memory test fixture issues an alarm prompt; if the actual supply current exceeds the current protection threshold or the actual supply voltage exceeds the voltage protection threshold, it is determined that the protection operation needs to be performed, for example, the memory test fixture directly cuts off the power supply.

[0023] In some embodiments, the corresponding protection operation is performed according to the voltage protection threshold, the current protection threshold, the actual supply voltage and the actual supply current, including: in the case that the actual supply current is less than or equal to the current protection threshold, the actual supply voltage is greater than or equal to the product of the voltage protection threshold and a preset percentage and less than the voltage protection threshold, it is determined that the protection operation is to issue a power supply protection warning action; in the case that the actual supply current is greater than the current protection threshold or the actual supply voltage is greater than or equal to the voltage protection threshold, it is determined that the protection operation is to cut off the power supply circuit of the memory to be tested. Wherein, the preset percentage can be calibrated according to the actual situation, for example, the preset percentage can be 90%, which is not limited here.

[0024] For example, assuming that the current protection threshold is 2A, the voltage protection threshold is 1.21V, the product of the voltage protection threshold and the preset percentage is 1.089V, if the detected actual supply voltage is 1V and the actual supply current is 1.6A, it is indicated that the actual supply voltage is less than the product of the voltage protection threshold and the preset percentage, and the actual supply current is less than the current protection threshold, so it is determined that no protection operation is needed, and the green display lamp of the memory test fixture is on; if the detected actual supply voltage is 1.1V and the actual supply current is 1.6A, it is indicated that the actual supply current is less than the current protection threshold, and the actual supply voltage is greater than or equal to the product of the voltage protection threshold and the preset percentage and less than the voltage protection threshold, so it is determined that the protection operation is to issue a power supply protection warning action, for example, the yellow display lamp of the memory test fixture is on; if the detected actual supply current is 2.1A, it is indicated that the actual supply current is greater than or equal to the current protection threshold, or if the detected actual supply voltage is 1.22V, it is indicated that the actual supply voltage is greater than or equal to the voltage protection threshold, so it is determined that the protection operation is to cut off the power supply loop of the memory to be tested, for example, an NMOS (N-type Metal-Oxide-Semiconductor) tube is used as a main switching device (on-resistance < 10 mΩ), and a high-speed gate driver (response time < 50 ns) is used in cooperation, when an abnormality is detected, the memory power supply can be cut off within 1 μs, which is much faster than a traditional relay (millisecond level), and the red display lamp of the memory test fixture is on, which needs to be manually reset.

[0025] The present application compares the actual supply parameters with the dynamic threshold in real time, provides a buffer intervention opportunity for the system when the parameters are close to the threshold, and cuts off the power supply immediately when the parameters exceed the safety limit, so as to ensure the timeliness of protection. In this way, the continuity of the test can be ensured, and the safety and reliability of the memory test process can be significantly improved.

[0026] In some embodiments, the serial presence detection parameters include reference amplitude parameters and reference timing parameters of memory data signals, address signals and clock signals of the memory to be tested, and the test result includes a signal integrity state, and the test on the memory to be tested based on the serial presence detection parameters to obtain the test result includes: sending a preset data test sequence to the memory to be tested at a plurality of test frequencies to collect actual amplitude parameters and actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested; determining the signal integrity state of the memory to be tested according to the reference amplitude parameters and the reference timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested and the actual amplitude parameters and the actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested.

[0027] Specifically, after the memory under test is installed into the memory test fixture, the fixture acquires the serial presence detection parameters of the memory under test through a communication interface. These parameters include reference amplitude parameters and reference timing parameters for the memory data signal, address signal, and clock signal. Then, the fixture sends test commands to the memory under test, for example, sending a preset data test sequence at a test frequency (e.g., 3200MHz). It then captures the corresponding memory data signal, address signal, and clock signal. The actual amplitude parameters and timing parameters are determined by analyzing the voltage trajectories of each signal waveform. Specifically, the actual amplitude parameter is calculated by statistically analyzing the voltage extremes of high and low levels to obtain the signal swing. The actual timing parameter is based on the clock edge, measuring the setup and hold times of the data signal before and after transitions to quantify the actual state of the signal. The fixture acquires the memory data of the memory under test. After determining the actual amplitude and timing parameters of the memory data, address, and clock signals, the actual amplitude and timing parameters of the memory data, address, and clock signals under test are compared with their corresponding reference amplitude and timing parameters. Specifically, the actual amplitude parameters of the memory data signals are compared with their reference amplitude parameters, the actual timing parameters of the memory data signals are compared with their reference timing parameters, the actual amplitude parameters of the address signals are compared with their reference amplitude parameters, the actual timing parameters of the address signals are compared with their reference timing parameters, the actual amplitude parameters of the clock signals are compared with their reference amplitude parameters, and the actual timing parameters of the clock signals are compared with their reference timing parameters. Based on the comparison results, the signal integrity status of the memory under test is determined.

[0028] After the current test frequency is completed, switch to the next test frequency (e.g., 2666MHz) and send a preset data test sequence to the memory under test to retest the signal integrity status of the memory under test at the next test frequency.

[0029] In some embodiments, determining the signal integrity status of the memory under test based on reference amplitude parameters and reference timing parameters of the memory data signal, address signal, and clock signal of the memory under test, as well as the actual amplitude parameters and actual timing parameters of the memory data signal, address signal, and clock signal of the memory under test, includes: determining the amplitude deviation value of the memory data signal, the amplitude deviation value of the address signal, and the amplitude deviation value of the clock signal of the memory under test based on the difference between the actual amplitude parameters of the memory data signal, address signal, and clock signal of the memory under test and the corresponding reference amplitude parameters; and determining the amplitude deviation value of the memory data signal, address signal, and clock signal of the memory under test based on the difference between the actual amplitude parameters of the memory data signal, address signal, and clock signal of the memory under test. The difference between the actual timing parameters of the memory under test and the corresponding reference timing parameters determines the timing deviation values ​​of the memory data signal, address signal, and clock signal of the memory under test. If at least one of the absolute values ​​of the amplitude deviation values ​​of the memory data signal, address signal, and clock signal, as well as the absolute values ​​of the timing deviation values ​​of the memory data signal, address signal, and clock signal of the memory under test, is greater than the corresponding preset tolerance threshold, the signal integrity state of the memory under test is determined to be abnormal.

[0030] For example, the amplitude deviation between the actual amplitude parameter of the memory data signal and the reference amplitude parameter of the memory data signal is calculated; the amplitude deviation between the actual amplitude parameter of the address signal and the reference amplitude parameter of the address signal is calculated; the amplitude deviation between the actual amplitude parameter of the clock signal and the reference amplitude parameter of the clock signal is calculated; the timing deviation between the actual timing parameter of the memory data signal and the reference timing parameter of the memory data signal is calculated; the timing deviation between the actual timing parameter of the address signal and the reference timing parameter of the address signal is calculated; the timing deviation between the actual timing parameter of the clock signal and the reference timing parameter of the clock signal is calculated; the absolute value of the above amplitude deviation value is compared with the corresponding preset tolerance threshold, and the absolute value of the above timing deviation value is compared with the corresponding preset tolerance threshold. If one or more of the absolute values ​​of the above amplitude deviation value and the absolute values ​​of the above timing deviation value are greater than the corresponding preset tolerance threshold, the signal integrity status of the memory under test is abnormal; if the absolute values ​​of the above amplitude deviation value and the absolute values ​​of the above timing deviation value are both less than or equal to the corresponding preset tolerance threshold, the signal integrity status of the memory under test is normal. The preset tolerance threshold can be calibrated according to the actual situation, and no specific restrictions are imposed here.

[0031] This application achieves accurate assessment of signal integrity by testing the actual parameters of memory signals at multiple frequencies and comparing them quantitatively with reference standards in serial presence detection parameters. Thus, by calculating the deviation values ​​of amplitude and timing and performing automated judgment based on preset tolerances, signal degradation caused by physical links or high-frequency interference can be effectively detected, thereby comprehensively evaluating the electrical performance and stability of memory under high loads and at different operating frequencies.

[0032] In some embodiments, the test result includes the test power consumption stability status, and the method further includes: sending a continuous refresh operation instruction to the memory under test, and collecting the test power consumption of the memory under test during the execution of the continuous refresh operation instruction; if the test power consumption is greater than a preset test power consumption threshold, the test power consumption stability status is determined to be an abnormal state. The preset test power consumption threshold can be calibrated according to actual conditions, and no specific limitation is made here.

[0033] Specifically, the memory testing fixture sends test commands to the memory under test, such as a continuous refresh operation command. During the execution of the continuous refresh operation command, the current and voltage in the memory power supply circuit are collected, and the test power consumption of the memory under test is determined based on the product of the current and voltage. Then, the test power consumption of the memory under test is compared with a preset test power consumption threshold. If the test power consumption is greater than the preset test power consumption threshold, the test power consumption stability state of the memory under test is determined to be abnormal; if the test power consumption is less than or equal to the preset test power consumption threshold, the test power consumption stability state of the memory under test is determined to be normal.

[0034] This application monitors the dynamic power consumption of the memory during continuous refresh operations, which can effectively identify abnormal power consumption phenomena caused by increased internal leakage current or circuit failure, thereby accurately judging the stability of memory power consumption and providing a direct basis for detecting potential defects and preventing reliability risks caused by overheating or over-consumption.

[0035] In some embodiments, the test result includes bad blocks in the memory under test, including: writing corresponding reference data to the access address of the memory under test, and accessing the access address of the memory under test one by one to read the corresponding target data; matching the reference data with the target data, and determining the bad blocks in the memory under test based on the matching result.

[0036] Specifically, the memory testing fixture sends test instructions to the memory under test, such as writing corresponding reference data to the access address of the memory under test, and accessing the access address of the memory under test one by one to read the corresponding target data. By matching the read-back target data with the originally written reference data bit by bit, if any bit of the target data is found to be inconsistent with the reference data, it can be determined that the storage unit or storage block where the bit is located is a bad block, thereby accurately identifying the physical defect area in the memory.

[0037] This application achieves precise location of physical defects in storage units by writing preset reference data to memory addresses and comparing and reading back data bit by bit. In this way, unreliable storage bits are directly exposed through data consistency verification, effectively identifying bad block regions in memory and providing a direct basis for memory quality and reliability assessment.

[0038] In some embodiments, the response information includes the response time and return code. Determining that the memory to be tested has been successfully initialized based on the response information includes: determining that the memory to be tested has been successfully initialized if the response time is less than or equal to a preset response time threshold and the return code is a preset return code. The preset response time threshold can be set according to actual conditions; for example, the preset response time threshold can be 1 second, and no specific limitation is made here.

[0039] Specifically, after collecting the serial presence detection parameters of the memory under test, the memory test fixture will send an initialization command to the memory under test and receive the response information from the memory under test. The response information includes the response time and the return code. If the response time is less than or equal to the preset response time threshold and the return code is the preset return code (indicating successful initialization), then the memory under test is determined to have been successfully initialized. If the response time is greater than the preset response time threshold, or the return code is not the preset return code, or the response time is greater than the preset response time threshold and the return code is not the preset return code, then the memory under test is determined to have failed to initialize.

[0040] In this way, the reliability of successful initialization is ensured in both timing and state dimensions, effectively avoiding test process errors caused by misjudgment of a single condition, and improving the accuracy of initialization state detection and the confidence level of test results.

[0041] In some embodiments, acquiring serial presence detection parameters of the memory under test includes: obtaining physical parameters and configuration information of the gold fingers of the memory under test; adjusting the spacing of the retractable slot assembly based on the physical parameters of the gold fingers to adapt to the physical size of the memory under test; dynamically adjusting the conduction logic between electrical contacts based on the configuration information of the memory under test to adapt to the pin definition of the memory under test; and after completing the mechanical and electrical adaptation of the memory under test, reading the serial presence detection parameters of the memory under test in response to the acquisition enable signal.

[0042] Specifically, memory test fixtures typically use a fixed slot design, which can only accommodate memory of a specific specification. In today's world of frequent memory upgrades, this incompatibility limitation is glaringly obvious. For example, when transitioning from DDR3 (Double Data Rate 3 Synchronous Dynamic Random-Access Memory) memory to DDR4 (Double Data Rate 4 Synchronous Dynamic Random-Access Memory) memory, the memory test fixtures become incompatible due to significant changes in the gold finger spacing, pin count, and electrical characteristics. Based on this, after the memory under test is installed into the memory test fixture, the memory test fixture will collect the physical parameters of the gold fingers of the memory under test (such as length and pin spacing) through the built-in sensors, and obtain configuration information (such as voltage type and pin definition) through the communication interface of the memory test fixture. Then, the memory test fixture automatically adjusts the mechanical spacing of the retractable slot to ensure reliable physical contact, and dynamically configures the connection logic of the electrical contacts to match different signal definitions. After completing these two adaptive matchings, and in response to the acquisition enable signal, it reads the serial presence detection parameters of the memory under test.

[0043] Alternatively, after installing the memory under test into the memory test fixture, the fixture will collect the physical parameters of the memory's gold fingers (such as length and pin spacing) through its built-in sensors. Based on these physical parameters, the spacing of the retractable slot assembly will be adjusted to fit the physical size of the memory under test. After successful connection, the fixture will read the serial presence detection parameters of the memory under test through the SPI / I2C communication interface. These parameters include the configuration information of the memory under test. Then, based on the configuration information, the fixture will dynamically adjust the conduction logic between the electrical contacts to match the pin definitions of the memory under test. After completing the mechanical and electrical adaptation of the memory under test, initialization and subsequent testing will be performed.

[0044] This application achieves mechanical self-adaptation of the slot spacing and dynamic configuration of the electrical contact conduction logic of the test fixture by automatically acquiring the physical parameters and configuration information of the memory gold fingers, effectively overcoming the compatibility bottleneck of traditional fixed slot designs during memory specification iterations. This allows a single test fixture to automatically adapt to memory modules of different generations and specifications, ensuring physical connection reliability and electrical interface compatibility while safely and accurately reading serial presence detection parameters, significantly improving the versatility of testing and equipment utilization.

[0045] As a concrete example, refer to Figure 2The memory testing system 1 includes: an adjustable connection module 11, a testing module 12, a protection module 13, and a display module 14.

[0046] The adjustable connection module 11 includes a mechanical adapter unit, an electrical adapter unit, and a parameter identification unit. The mechanical adapter unit, for example... Figure 3 As shown, the device includes a retractable slot assembly, a displacement detection assembly (e.g., laser sensor 0, laser sensor 1, laser sensor 2, and laser sensor 3), and a motor drive assembly. The mechanical adapter unit is configured to acquire the physical parameters of the gold fingers of the memory under test through the displacement detection assembly (e.g., detecting the width, spacing, and thickness parameters of the gold fingers), and control the motor drive assembly to adjust the spacing of the retractable slot assembly based on the gold finger physical parameters (e.g., the adjustment range covers the entire series of DDR3 to DDR5 and LPDDR memory) to adapt to the physical size of the memory under test.

[0047] The electrical adapter unit includes a spring probe array and a programmable switch matrix. The spring probe array forms electrical contact with the gold fingers of the memory under test (a single pin can withstand 0-5V voltage and a maximum current of 3A). The programmable switch matrix dynamically adjusts the conduction logic between the electrical contacts based on the configuration information of the memory under test to adapt to the pin definition of the memory under test (e.g., the 288 pins of DDR4 and the 288 pins of DDR5 have different signal definitions).

[0048] The parameter identification unit (integrated with an SPI / I2C communication interface) is configured to receive the acquisition enable signal sent by the test module 12 after the mechanical adapter unit completes the mechanical and electrical adaptation of the memory under test. In response to the acquisition enable signal, it reads the JEDEC standard information in the SPD chip of the memory under test, that is, reads the serial presence detection parameters. The serial presence detection parameters include the type, capacity, reference power supply parameters (such as reference power supply voltage and reference power supply current), reference amplitude parameters and reference timing parameters of memory data signals, address signals and clock signals, etc., and transmits the serial presence detection parameters to the test module 12 and the protection module 13.

[0049] For example, the mechanical adapter unit uses a retractable slot assembly with a manually adjustable knob. The knob can be used to slide the side plates to accommodate the length differences of DDR3 (133.35mm gold finger length), DDR4 (133.35mm gold finger length), and DDR5 (139.7mm gold finger length), with an adjustment range of 130-140mm. The inner side of the plate is lined with a wear-resistant rubber pad to ensure stable fixation after the memory to be tested is inserted. The electrical adapter unit uses a 288-pin gold-plated pogo pin (spring probe) array with a pin pitch of 1mm, covering the gold finger pin distribution of mainstream memory. The probe travel is 0.5mm to ensure reliable contact with the gold fingers. The contacts are connected to the test module 12 via a ribbon cable. The parameter recognition unit integrates a simple I2C card reader, which reads the basic information of the memory SPD chip (memory type, operating voltage), completes the recognition within 200ms, and indicates whether the recognition is successful via LED indicator (red / green).

[0050] The core processor of test module 12 can be an STM32F103C8T6 microprocessor, which has high-speed data processing capabilities and can run memory initialization detection, signal analysis, and protection control algorithms in parallel. Test module 12 is configured to test the memory under test based on serial presence detection parameters to obtain test results. Based on the test results, the fault signal of the memory under test is determined. For example, the test data is matched with a preset fault feature library (containing 100+ typical fault modes, such as VDD overvoltage, DQ signal open circuit, initialization timeout, etc.) to determine the fault signal of the memory under test, and the fault signal is sent to the status display module 14. Specifically, the test module 12 includes a basic test unit, a signal test unit, a stress test unit, and an initialization unit. The initialization unit is configured to send an initialization command to the memory under test, receive the response information from the memory under test, and determine whether the memory under test has been successfully initialized based on the response information. If initialization is successful, the memory under test is tested. The basic test unit is configured to write corresponding reference data to the access addresses of the memory under test, access the access addresses of the memory under test one by one to read the corresponding target data, match the reference data with the target data, and determine bad blocks in the memory under test based on the matching result. The signal test unit is configured to send a preset data test sequence to the memory under test at multiple test frequencies to collect the amplitude and timing parameters of the data signal, address signal, and clock signal of the memory under test, and determine the signal integrity status of the memory under test based on the amplitude parameters, timing parameters, reference amplitude parameters, and reference timing parameters. The stress test unit is configured to send a continuous refresh operation command to the memory under test, and collect the test power consumption of the memory under test during the execution of the continuous refresh operation command, and determine the test power consumption stability status based on the test power consumption.

[0051] Test module 12 is also configured to collect power supply parameters of the memory under test during the test. For example, it can collect power supply voltage (accuracy ±1mV) and power supply current (accuracy ±1mA) in real time through a 16-bit ADC (Analog-to-Digital Converter) chip (sampling rate 1MSPS). The monitoring points cover key power supply pins of the memory such as VDD (Voltage Drain Drain, operating voltage), VDDIO (Voltage Drain Drain Input / Output, input / output interface operating voltage), and VPP (Voltage Peak-to-Peak, peak-to-peak voltage), and transmit the power supply parameters to protection module 13.

[0052] The protection module 13 is configured to receive serial presence detection parameters and power supply parameters of the memory under test, determine the protection threshold of the memory under test based on the serial presence detection parameters, and perform corresponding protection operations based on the power supply parameters and protection threshold parameters. Specifically, the protection module 13 includes a protection threshold determination unit, an early warning unit, and a cut-off unit. The protection threshold determination unit is configured to determine a voltage protection threshold based on the product of a reference power supply voltage and a preset protection coefficient, and to determine a current protection threshold based on the product of a reference power supply current and a preset protection coefficient. The early warning unit is configured to issue a power supply protection early warning action when the actual power supply current is less than or equal to the current protection threshold, or when the actual power supply voltage is greater than or equal to the product of the voltage protection threshold and a preset percentage but less than the voltage protection threshold. The cut-off unit is configured to cut off the power supply circuit of the memory under test when the actual power supply current is greater than the current protection threshold or the actual power supply voltage is greater than or equal to the voltage protection threshold.

[0053] Display module 14 is configured to receive fault signals and drive the corresponding display unit to execute corresponding visual indication strategies based on the fault signals in order to visualize the fault type of the memory under test.

[0054] The power supply module (not shown) uses a 12V DC power input and outputs an adjustable voltage (1.0-3.3V) through a DC-DC (Direct Current to Direct Current Converter) converter (such as LM2596), which is controlled in conjunction with the protection circuit and the controller.

[0055] The assembly steps for memory testing system 1 include: Mechanical frame assembly: Fix the retractable slot assembly to the acrylic base, ensuring that the center of the slot is parallel to the edge of the base. The knob is installed on the side of the frame, which can smoothly adjust the baffle spacing when rotated. Electrical connection: Connect the spring pin array to the GPIO (General-Purpose Input / Output) pin of the STM32 controller via a ribbon cable. Connect the voltage detection circuit to the controller's ADC channel. Connect the current detection resistor in series in the power supply circuit. Connect the output to another ADC channel of the controller. Indicator light and protection circuit installation: Fix the LED (Light-Emitting Diode) light board to the front panel of the base and connect it to the controller's IO port through a current-limiting resistor; the relay output terminal of the overvoltage protection circuit is connected in series in the power supply circuit, and the control signal is connected to the controller's interrupt pin. Power supply module connection: It adopts a 12V DC power input and outputs an adjustable voltage (1.0-3.3V) through a DC-DC converter (such as LM2596), which is controlled by the protection circuit and the controller.

[0056] As a concrete example, refer to Figure 4 The memory testing method in this application embodiment may further include the following steps: S210, the memory to be tested is connected and serial presence detection parameters are identified.

[0057] After the memory to be tested is inserted into the memory test fixture, the adjustable connection module 11 triggers mechanical adjustment through the displacement detection component and synchronously reads the serial presence detection parameters.

[0058] For example, the operator adjusts the retractable slot assembly to the corresponding length using the knob according to the type of memory to be tested (e.g., DDR4), aligns the memory's gold fingers with the spring pin array, and inserts it. A "click" sound indicates that it is properly installed. Pressing the specification recognition button, the I2C card reader reads the serial presence detection parameters. If the green indicator light flashes 3 times, the recognition is successful; if the red light remains constantly on, the memory to be tested needs to be re-inserted. S220, adaptive power supply and initialization.

[0059] The power supply module of the memory test fixture determines the power supply voltage based on the serial presence detection parameters, and outputs a power supply voltage that conforms to the memory specifications (such as 1.1V for DDR5) through a digital-to-analog converter (DAC). The voltage is then slowly increased to the power supply voltage based on a preset slope (for example, the preset slope can be 0.1V / ms to avoid surges). Then, the test module 12 sends an initialization command sequence to the memory under test, monitors the memory response information, and if the initialization fails, records the failure code and provides feedback through an indicator light.

[0060] S230, memory performance to be tested.

[0061] If initialization is successful, basic tests, signal tests, and stress tests will be performed. During the tests, the actual supply voltage and current will be collected once per second. If the actual supply current is less than or equal to the current protection threshold, and the actual supply voltage is less than the product of the voltage protection threshold and a preset percentage, the power supply will be maintained, and the green light will remain on. If the actual supply current is less than or equal to the current protection threshold, and the actual supply voltage is greater than or equal to the product of the voltage protection threshold and a preset percentage but less than the voltage protection threshold, a power supply protection warning will be issued, i.e., the yellow light will flash, and if the power supply does not recover after a preset duration (5 seconds), the power supply will be cut off. If the actual supply current is greater than the current protection threshold or the actual supply voltage is greater than or equal to the voltage protection threshold, the power supply circuit to the memory under test will be cut off, the red light will remain on, and the relay will immediately cut off the power supply, requiring manual reset.

[0062] S240, Results Output and Summary.

[0063] After the test is completed, the test module 12 generates a report containing the memory model, test items, and fault signals, and uploads it to the host computer via USB (Universal Serial Bus) or Ethernet interface. The display module 14 drives the corresponding display unit to execute the corresponding visual indication strategy according to the fault signals to visualize the fault type of the memory under test.

[0064] In summary, this application achieves a significant improvement in the compatibility and economy of the testing platform by integrating an adjustable mechanical structure and a universal electrical interface. Its core innovation lies in the use of a manually adjustable slot frame and a fully compatible spring pin array, which can accommodate mainstream memory specifications. The adaptive pin design, by physically covering the contact distribution of different generations of memory, fundamentally solves the contact failure problem caused by differences in gold finger definitions, reducing the number of fixtures required and lowering equipment investment costs.

[0065] In terms of test process optimization, the integrated I2C protocol parser can automatically complete the reading of serial presence detection parameters and specification identification within a short time (e.g., 200ms), improving test preparation efficiency. Synchronous voltage and current monitoring can accurately distinguish between different abnormal states such as poor contact (warning) and hardware damage (fault), reducing the false positive rate to a minimum. By implementing an initialization command response detection mechanism, latent chip faults can be effectively identified, significantly improving fault coverage.

[0066] The protection system employs a programmable overvoltage protection module, supporting manual setting of protection thresholds based on memory specifications. This ensures accurate overvoltage protection while completely preventing false triggering. Combined with a fast-cutoff circuit, it can complete power supply isolation before the short-circuit current reaches the preset current threshold, reducing the risk of chip burnout.

[0067] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0068] Embodiments of this application also provide an electronic device, with reference to Figure 5 The system includes a memory 310, a processor 320, and a memory test program stored on the memory 310 and capable of running on the processor 320. When the processor 320 executes the memory test program, it implements the aforementioned memory test method.

[0069] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0070] The present application provides a detailed description of a memory testing method and electronic device. Specific examples have been used to illustrate the principles and implementation methods of the present application. The descriptions of these embodiments are merely illustrative of the method and its core concepts. It should be noted that those skilled in the art can make various improvements and modifications to the present application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A memory testing method, characterized in that, The method includes: Collect serial presence detection parameters of the memory under test; An initialization command is sent to the memory to be tested, and the response information of the memory to be tested is received. If the initialization of the memory to be tested is successful based on the response information, the memory to be tested is tested based on the serial presence detection parameters to obtain the test result. During the testing of the memory under test, the actual power supply parameters of the memory under test are collected at preset time intervals, and corresponding protection operations are performed based on the actual power supply parameters and the serial presence detection parameters.

2. The memory testing method according to claim 1, characterized in that, The serial presence detection parameters include the reference supply voltage and reference supply current of the memory under test, and the actual supply parameters include the actual supply voltage and actual supply current. Based on the actual supply parameters and the serial presence detection parameters, corresponding protection operations are performed, including: The voltage protection threshold is determined based on the product of the reference supply voltage and the preset protection coefficient; The current protection threshold is determined based on the product of the reference power supply current and the preset protection coefficient; Perform corresponding protection operations based on the voltage protection threshold, the current protection threshold, the actual supply voltage, and the actual supply current.

3. The memory testing method according to claim 2, characterized in that, Perform corresponding protection operations based on the voltage protection threshold, the current protection threshold, the actual supply voltage, and the actual supply current, including: If the actual power supply current is less than or equal to the current protection threshold, and the actual power supply voltage is greater than or equal to the product of the voltage protection threshold and a preset percentage but less than the voltage protection threshold, the protection operation is determined to be issuing a power supply protection warning action. If the actual power supply current is greater than the current protection threshold or the actual power supply voltage is greater than or equal to the voltage protection threshold, the protection operation is determined to be to cut off the power supply circuit of the memory under test.

4. The memory testing method according to claim 1, characterized in that, The serial presence detection parameters include reference amplitude parameters and reference timing parameters for the memory data signal, address signal, and clock signal of the memory under test. The test result includes signal integrity status. The test is performed on the memory under test based on the serial presence detection parameters to obtain the test result, including: At multiple test frequencies, a preset data test sequence is sent to the memory under test to collect the actual amplitude parameters and actual timing parameters of the memory data signal, address signal and clock signal of the corresponding memory under test. The signal integrity status of the memory under test is determined based on the reference amplitude parameters and reference timing parameters of the memory data signal, address signal, and clock signal of the memory under test, as well as the actual amplitude parameters and actual timing parameters of the memory data signal, address signal, and clock signal of the memory under test.

5. The memory testing method according to claim 4, characterized in that, The signal integrity status of the memory under test is determined based on the reference amplitude parameters and reference timing parameters of the memory data signals, address signals, and clock signals, as well as the actual amplitude parameters and actual timing parameters of the memory data signals, address signals, and clock signals of the memory under test. This includes: The amplitude deviation values ​​of the memory data signal, address signal, and clock signal of the memory under test are determined based on the differences between the actual amplitude parameters of the memory data signal, address signal, and clock signal of the memory under test and the corresponding reference amplitude parameters. The timing deviation values ​​of the memory data signal, address signal, and clock signal of the memory under test are determined based on the differences between the actual timing parameters of the memory data signal, address signal, and clock signal of the memory under test and the corresponding reference timing parameters. If at least one of the absolute values ​​of the amplitude deviation of the memory data signal, the amplitude deviation of the address signal, and the amplitude deviation of the clock signal, as well as the absolute values ​​of the timing deviation of the memory data signal, the timing deviation of the address signal, and the timing deviation of the clock signal of the memory under test, is greater than the corresponding preset tolerance threshold, the signal integrity state of the memory under test is determined to be abnormal.

6. The memory testing method according to claim 1, characterized in that, The test results include the power consumption stability status, and the method further includes: Send a continuous refresh operation instruction to the memory under test, and collect the test power consumption of the memory under test during the execution of the continuous refresh operation instruction; If the test power consumption is greater than the preset test power consumption threshold, the test power consumption stability state is determined to be an abnormal state.

7. The memory testing method according to claim 1, characterized in that, The test results include bad blocks in the memory under test, including: Write the corresponding reference data to the access address of the memory to be tested, and access the access address of the memory to be tested one by one to read the corresponding target data; The reference data is matched with the target data, and the bad blocks of the memory to be tested are determined based on the matching results.

8. The memory testing method according to claim 1, characterized in that, The response information includes the response time and return code. Determining that the memory under test was successfully initialized based on the response information includes: If the response time is less than or equal to a preset response time threshold and the return code is a preset return code, the memory to be tested is determined to be successfully initialized.

9. The memory testing method according to claim 1, characterized in that, Collect serial presence detection parameters of the memory under test, including: Obtain the physical parameters and configuration information of the gold fingers of the memory to be tested; The spacing of the retractable slot assembly is adjusted based on the physical parameters of the gold fingers to adapt to the physical size of the memory under test; The conduction logic between electrical contacts is dynamically adjusted based on the configuration information of the memory under test to adapt to the pin definition of the memory under test. After completing the mechanical and electrical adaptation of the memory under test, and in response to the acquisition enable signal, the serial presence detection parameters of the memory under test are read.

10. An electronic device, characterized in that, The method includes a memory, a processor, and a memory test program stored on the memory and executable on the processor. When the processor executes the memory test program, it implements the memory test method according to any one of claims 1-9.

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