Radio frequency oscillator with ceramic resonator and surface mount integrated circuit package

Abstract

In one aspect, an apparatus is disclosed, the apparatus comprising: a surface mount integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving a surface mount integrated circuit package, the integrated ceramic resonator comprising: a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate; a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from the conductive periphery of the ceramic cavity so as not to contact the conductive periphery of the ceramic cavity; a first conductive material extending vertically through an upper planar surface of the ceramic substrate to connect a conductive periphery of the ceramic cavity to a surface mount integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate to connect the conductive rod to a surface mount integrated circuit package.

Description

[0001] open field

[0002] This disclosure generally relates to semiconductor devices, including electronic devices incorporated into semiconductor devices, and more specifically, but not exclusively, to integrated ceramic resonators and manufacturing techniques for forming integrated ceramic resonators. Background Technology

[0003] Integrated circuit technology has made significant strides in improving computing power through the miniaturization of active components. Various packaging technologies can be found in many electronic devices, including processors, servers, and radio frequency (RF) integrated circuits. Advanced packaging and processing technologies allow the manufacture of complex devices that may include multiple functional blocks, such as multi-die devices and system-on-a-chip (SoC) devices, where each functional block is designed to perform a specific function, such as, for example, microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), clock generation functions, radio frequency (RF) generation functions, and so on.

[0004] Integrated circuit devices may include oscillators for generating fixed-frequency signals. Such oscillators may use external passive resonators, such as quartz crystals, and may be configured to generate stable low-frequency signals (e.g., clocks and / or other fixed-frequency signals in the kilohertz to megahertz region of the electromagnetic spectrum). Such oscillators may also include active integrated oscillator circuitry (e.g., complementary metal-oxide-semiconductor (CMOS) devices) coupled to a quartz crystal, wherein the quartz crystal is configured to resonate at a fixed frequency.

[0005] Overview

[0006] The following is a simplified overview relating to one or more aspects disclosed herein. Therefore, this overview should not be considered an exhaustive overview relating to all aspects of the conception, nor should it be considered to identify key or decisive elements relating to all aspects of the conception or to depict the scope associated with any particular aspect. Accordingly, the sole purpose of the following overview is to present, in a simplified form, certain concepts relating to one or more aspects of the mechanism disclosed herein before the detailed description given below.

[0007] In one aspect, an apparatus includes: a surface-mount integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having a top planar surface for receiving the surface-mount integrated circuit package, the integrated ceramic resonator including: a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate; a conductive rod extending at least partially vertically into the ceramic cavity, wherein the conductive rod is isolated from the conductive periphery of the ceramic cavity to avoid contact with the conductive periphery of the ceramic cavity; a first conductive material extending vertically through the top planar surface of the ceramic substrate to connect the conductive periphery of the ceramic cavity to the surface-mount integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the top planar surface of the ceramic substrate to connect the conductive rod to the surface-mount integrated circuit package housing the active oscillator circuit.

[0008] In one aspect, an integrated ceramic resonator includes: a ceramic substrate having an upper planar surface for receiving a surface-mount electronic device; a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate; a conductive rod extending at least partially vertically into the ceramic cavity, wherein the conductive rod is isolated from the conductive periphery of the ceramic cavity to avoid contact with the conductive periphery of the ceramic cavity; a first through-hole structure disposed perpendicularly through the upper planar surface of the ceramic substrate to connect the conductive periphery of the ceramic cavity to the surface-mount electronic device; and a second through-hole structure disposed through the upper planar surface of the ceramic substrate to connect the conductive rod to the surface-mount electronic device.

[0009] In one aspect, a method for manufacturing an integrated device includes: forming a plurality of planar ceramic layers, wherein one or more of the plurality of planar ceramic layers include corresponding patterned metal layers; aligning the plurality of planar ceramic layers and the corresponding patterned metal layers to stack them on top of each other; and thermally fusing the plurality of planar ceramic layers and the corresponding patterned metal layers to form an integrated ceramic resonator having an upper planar surface for receiving a surface-mount integrated circuit package, a plurality of conductive walls defining a conductive periphery of a ceramic cavity, a conductive rod extending at least partially vertically into the ceramic cavity, wherein the conductive rod is isolated from the conductive periphery of the ceramic cavity to avoid contact with the conductive periphery of the ceramic cavity, a first via structure extending vertically through the upper planar surface to connect the conductive periphery of the ceramic cavity to the surface-mount integrated circuit package, and a second via structure extending vertically through the upper planar surface to connect the conductive rod to the surface-mount integrated circuit package.

[0010] Other objectives and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. Brief description of the attached diagram

[0012] A more complete understanding of the various aspects of this disclosure and its many accompanying advantages will become readily available when considered in the following detailed description taken in conjunction with the accompanying drawings, which are given for illustrative purposes only and do not constitute any limitation on this disclosure.

[0013] Figure 1 This is a schematic diagram of an equivalent circuit used to implement a radio frequency (RF) oscillator according to various aspects of this disclosure.

[0014] Figure 2A This is a cross-sectional view of an example integrated ceramic resonator based on various aspects of this disclosure.

[0015] Figure 2B This is a partial perspective view of an integrated ceramic resonator according to various aspects of this disclosure.

[0016] Figures 3A to 3C The influence of the diameter of the conductive rod on the frequency response of the integrated ceramic resonator according to various aspects of this disclosure is explained.

[0017] Figure 4A and Figure 4B The effect of the gap size between the end of the conductive rod and the lower conductive wall of the ceramic cavity on the frequency response of the integrated ceramic resonator according to various aspects of this disclosure is explained.

[0018] Figures 5A to 5H The various steps of manufacturing an RF oscillator having an integrated ceramic resonator and a surface-mount integrated circuit package according to various aspects of this disclosure are explained.

[0019] Figure 6 A schematic representation of a circuit model equivalent corresponding to the components of an RF oscillator constructed according to various aspects of this disclosure is shown.

[0020] Figure 7 Example methods for manufacturing integrated devices according to various aspects of this disclosure are shown.

[0021] Figure 8 Various electronic devices that can be integrated with any of the devices described herein, according to various aspects of this disclosure, are explained.

[0022] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not show all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and accompanying drawings to indicate similar features.

[0023] Detailed description

[0024] Various aspects of this disclosure are explained in the following description and accompanying drawings with reference to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of this teaching. Additionally, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted so as not to obscure the relevant details of the teachings in this disclosure.

[0025] In some of the described example implementations, instances are identified where various parts of the component structures and operations are available from known conventional techniques and are then arranged according to one or more exemplary embodiments. In such instances, internal details of the parts of known conventional component structures and / or operations may be omitted to help avoid potential confusion with the concepts illustrated in the illustrative embodiments disclosed herein.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “having,” “including,” and / or “containing,” as used herein, indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will also be understood that when one layer is described as “above,” “over,” “below,” or “under,” another layer does not necessarily exclude the use of intermediate layers and / or materials that would otherwise be used to ensure adhesion between the layers. Similarly, it will be understood that the terms “vertical,” “horizontal,” “up,” “down,” and “side” are used only to describe the relative position and / or orientation between certain components and / or structures as shown in the coordinate system used in the accompanying drawings. It will be appreciated that such relative position and / or orientation relationships may be transformed to other coordinate systems based on the orientation of the device including such components and / or structures.

[0027] To fully explain the various aspects of the design disclosed herein, manufacturing methods are proposed. Other manufacturing methods are also possible, and the manufacturing methods discussed are presented only to aid in understanding the concepts disclosed herein.

[0028] Certain aspects of this disclosure relate to ceramic resonators formed as integrated structures that can be used in conjunction with active oscillator circuitry (e.g., complementary metal-oxide-semiconductor (CMOS) integrated circuits encapsulated in surface-mount integrated circuit packages) for the generation of radio frequency (RF) signals (e.g., RF signals in the gigahertz range of the electromagnetic spectrum). The ceramic resonators disclosed herein contrast with quartz crystals commonly used to generate such RF signals. Certain aspects of the disclosed ceramic resonators allow for the surface mounting of integrated circuit packages (e.g., surface-mount integrated circuit packages including active oscillator circuitry) onto the surface of the ceramic resonator, compared to oscillators using quartz crystals. In one aspect, surface mounting the integrated circuit package onto the disclosed ceramic resonator reduces parasitic capacitances and / or inductances typically present when the resonator is coupled to the oscillator circuitry using conventional wire bonding processes. Such parasitic capacitances and / or inductances can lead to RF instability. According to certain aspects of this disclosure, by directly surface mounting the integrated circuit package onto the ceramic resonator, such RF instability is significantly reduced and / or eliminated.

[0029] Certain aspects of this disclosure relate to an integrated ceramic resonator having a ceramic cavity defined by a plurality of conductive walls and conductive rods extending at least partially into the ceramic cavity. The conductive walls and conductive rods are arranged in the integrated ceramic resonator to facilitate connection of the conductive walls and conductive rods to a planar surface of the integrated ceramic resonator, the planar surface of which is configured to receive a surface-mount integrated circuit package containing an active oscillator.

[0030] Figure 1 This is a schematic diagram of an equivalent circuit used to implement the RF oscillator 100 according to various aspects of this disclosure. In this example, the RF oscillator 100 includes an active oscillator circuit 102 coupled to a passive resonator 104. Figure 1 In this document, reference identifiers including "_" will be interpreted as indicating that any reference mark following "_" corresponds to a subscript. For example, the reference identifier "C_m" in the accompanying drawings corresponds to "C" elsewhere in this disclosure. m ".

[0031] When the RF oscillator 100 is used to generate low-frequency signals, the passive resonator 104 can be in the form of a quartz crystal. However, some aspects of this disclosure are made with the recognition that using a quartz crystal as the passive resonator 104 increases the size of the RF oscillator 100 and limits the ability to construct the RF oscillator 100 as an integrated unit. Furthermore, some aspects of this disclosure are made with the recognition that RF oscillators using quartz crystals may be sensitive to mechanical shocks and / or have slow oscillation startup. Moreover, when the quartz crystal is wire-connected to the active oscillator circuit 102, the safety of the electronic system incorporating the quartz crystal may be compromised due to the exposure of the quartz crystal's clock pins.

[0032] For scenarios where the RF oscillator 100 operates in a higher frequency range (e.g., frequencies above 1 gigahertz (GHz), quartz crystals are unsuitable as passive resonators 104. In such scenarios, the passive resonator 104 can be in the form of a bulk acoustic wave (BAW) resonator. Such BAW resonators can be thin-film BAW (FBAW) or solid-mount reflector BAW (SMR-BAW). Some BAWs may include dual reflectors (e.g., dual-sided SMR-BAW). However, certain aspects of this disclosure are implemented with the recognition that BAW resonators can be difficult to manufacture. Additionally, certain aspects of this disclosure are implemented with the recognition that such BAW resonators must be coupled to the active oscillator circuit 102 using a wire bonding process. Using wires to couple a BAW resonator to the active oscillator circuit creates difficulties in consistently manufacturing the RF oscillator 100 to tune it to the desired resonant frequency. Furthermore, such wire coupling can reduce the frequency stability of the RF oscillator 100.

[0033] According to certain aspects of this disclosure, when the passive resonator 104 is implemented as a BAW resonator, the RF oscillator 100 can operate in four possible modes. First, if C d If the value is too small, the RF oscillator 100 can operate in latch mode. Second, if C d The value is greater than n*C L / 2, then the RF oscillator 100 can operate in a parasitic relaxation oscillation mode. Third, the RF oscillator 100 can operate at a desired oscillation frequency (e.g., in the GHz range of the electromagnetic spectrum, such as 2.5 GHz).

[0034] In the fourth operating mode, the RF oscillator 100 can have a frequency f B It operates by utilizing parasitic oscillations. On one hand, when the RF oscillator 100 is configured to operate at a resonant frequency of 2.5 GHz, the frequency f... B The range is between 5GHz and 8GHz. (Using...) Figure 1The model of the RF oscillator 100 shown has a frequency f. B It can be represented as:

[0035]

[0036] Based on this equation, the bonding leads 106 that couple the active oscillator circuit 102 and the passive resonator 104 should be spaced as closely as possible, within the limits of packaging regulations, to reduce mutual coupling and ensure that the RF oscillator 100 operates at frequency f. B There is no gain at that point. Furthermore, CMOS transistors M1–M4 can be sized and biased to ensure no loop gain at any parasitic oscillation frequency.

[0037] As will be understood from the teachings of this disclosure, when the passive resonator 104 is constructed according to various aspects of this disclosure, it is not necessary to use bonding leads 106 to couple the active oscillator circuit 102 to the passive resonator 104. For this purpose, certain aspects of this disclosure allow surface mounting of an integrated circuit package (e.g., a package including the active oscillator circuit 102) onto the surface of the integrated ceramic resonator used as the passive resonator 104.

[0038] Figure 2A This is a cross-sectional view of an example integrated ceramic resonator 200 according to various aspects of this disclosure. Figure 2A As shown, the integrated ceramic resonator 200 includes a ceramic substrate 202 having an upper surface 204 configured to receive a surface-mount integrated circuit package. In this example, the integrated ceramic resonator 200 includes a plurality of conductive walls forming a conductive periphery of a ceramic cavity 206. In one aspect, these plurality of conductive walls may be formed of a metal (such as copper, silver, aluminum, etc.).

[0039] form Figure 2A The conductive periphery of the ceramic cavity 206 shown includes an upper conductive wall 208 and a lower conductive wall 210 that are perpendicularly spaced apart from each other. In this example, the upper conductive wall 208 and the lower conductive wall 210 are formed as planar structures that are generally parallel to each other. In this example, the upper conductive wall 208 and the lower conductive wall 210 define the height H of the ceramic cavity 206.

[0040] The conductive walls forming the conductive periphery of the ceramic cavity 206 also include a vertical conductive wall 212. In this example, the vertical conductive wall 212 provides a conductive path connecting the upper conductive wall 208 to the lower conductive wall 210. In one aspect, the vertical conductive wall 212 surrounds the entire vertical periphery of the ceramic cavity 206 and defines its diameter D.

[0041] The integrated ceramic resonator 200 may further include a conductive rod 214 that extends at least partially vertically into the ceramic cavity 206. The conductive rod 214 is electrically isolated from a plurality of conductive walls disposed around the ceramic cavity 206 and does not cross the total height H of the ceramic cavity 206. In one aspect, the conductive rod 214 terminates without reaching the lower conductive wall 210, such that a gap G is formed between the end of the conductive rod 214 and the lower conductive wall 210. In another aspect, the conductive rod 214 extends along the central vertical axis 216 of the ceramic cavity 206.

[0042] The integrated ceramic resonator 200 also includes structures disposed through the upper surface 204, which are used to facilitate the integration of the integrated ceramic resonator 200 with a housing integrated circuit (e.g., an active oscillator circuit, such as...). Figure 1 The formation of conductive paths between terminals of the surface-mount integrated circuit package (not shown in FIG. 2) of the active oscillator circuit 102 shown. Figure 2A In the example shown, the through-hole structure 218 covers the conductive periphery connected to the ceramic cavity 206 (e.g., Figure 2A Terminal 220 is located on the upper conductive wall 208. Another through-hole structure 222 covers terminal 225, which is connected to the conductive rod 214. On one hand, a first terminal of the active oscillator circuit housed in the surface mount package is connected to terminal 220 via through-hole structure 218 (e.g., via solder connections formed in through-hole structure 218 during the mounting of the surface mount integrated circuit package to the integrated ceramic resonator 200), while a second terminal of the active oscillator circuit housed in the surface mount package is connected to terminal 225 via through-hole structure 222 (e.g., via solder connections formed in through-hole structure 222 during the mounting of the surface mount integrated circuit package to the integrated ceramic resonator 200).

[0043] On one hand, the integrated ceramic resonator 200 may include a power bar 224 ( Figure 2A The diagram shows only one power strip 224, which provides a conductive path between a power source (not shown) and the power terminals of a surface-mount integrated circuit package mounted to the upper surface 204 of the integrated ceramic resonator 200. In this example, through-hole structures 226 and 228 cover the power strip 224. Through-hole structure 226 facilitates the connection between the power strip 224 and the power terminals of the surface-mount integrated circuit package. Figure 2A The through-hole structure 228 facilitates the formation of a conductive path between the power strip 224 and the terminals of the power supply (e.g., by filling with solder during the surface mounting process).

[0044] Figure 2BThis is a partial perspective view of an integrated ceramic resonator 200 according to various aspects of this disclosure. Figure 2B In this configuration, a surface-mount integrated circuit package 230 housing the active oscillator circuitry is mounted on the upper surface 204 of the integrated ceramic resonator 200. A power strip 224 provides power to the active oscillator circuitry within the surface-mount integrated circuit package 230. Another pair of conductive strips 232 provides a path for the RF signal output of the RF oscillator. In one aspect, the power strip 224 and the conductive strips 232 may be orthogonally oriented relative to each other to limit coupling between the power path and the RF signal output.

[0045] exist Figure 2B In this illustration, only the vertical conductive wall 212, one of the plurality of conductive walls forming the periphery of the ceramic cavity 206, is depicted. In one aspect, the vertical conductive wall 212 may be formed as a generally cylindrical structure (e.g., a cylindrical structure or a polygonal structure with multiple sides that allow the vertical conductive wall 212 to be sufficiently columnar to operate within design constraints). Figure 2B In this configuration, the vertical conductive wall 212 is formed as an octagonal structure. On one hand, the vertical conductive wall 212 can be formed as a higher-order polygonal structure (e.g., a polygonal structure with more than eight sides). However, in some scenarios, the vertical conductive wall 212 can also be formed as a lower-order polygonal structure.

[0046] According to certain aspects of this disclosure, the integrated ceramic resonator 200 can be designed to have a resonant frequency in a frequency range close to 2.5 GHz. For this purpose, the ceramic cavity 206 can have a diameter D of approximately 10 mm and a cavity height H of approximately 1.5 mm to 2 mm. The conductive rod 214 can have a diameter between approximately 125 μm and 300 μm, and the thickness of the vertical conductive wall 212 can be in the range of approximately 50 μm to 100 μm. The resulting integrated ceramic resonator possesses a quality factor (Q) similar to or better than that of a BAW resonator. For higher resonant frequency ranges (e.g., close to 10 GHz), the aforementioned dimensions can be reduced, and for lower resonant frequency ranges (e.g., close to 1 GHz), the aforementioned dimensions can be increased.

[0047] Figures 3A to 3C (Collectively referred to as Figure 3) illustrates the effect of the diameter of the conductive rod according to various aspects of this disclosure on the frequency response of the integrated ceramic resonator. In this example, Figure 3A The conductive rod 302 shown has a first diameter W1 (e.g., approximately 175 μm), while Figure 3B The conductive rod 304 shown has a second diameter W2 (e.g., approximately 275 μm) larger than the first diameter W1. The different diameters of the conductive rod affect the resonant frequency of the integrated ceramic resonator. Figure 3CThe following curve is shown in graph 306. Here, graph 306 shows the admittance of an integrated ceramic resonator that varies with frequency. In this example, line 308 corresponds to the frequency response of an integrated ceramic resonator with a conductive rod of diameter W1, where peaks 310 and 312 occur at the resonant frequency of the integrated ceramic resonator. Similarly, line 314 corresponds to the frequency response of an integrated ceramic resonator with a conductive rod of diameter W2, where peaks 316 and 318 occur at the resonant frequency of the integrated ceramic resonator. It is clear from the frequency response shown in graph 306 that the frequency response of the integrated ceramic resonator can be shifted to a higher frequency range by decreasing the diameter of the conductive rod. Similarly, the frequency response of the integrated ceramic resonator can be shifted to a lower frequency range by increasing the diameter of the conductive rod.

[0048] Figure 4A and 4B (Collectively referred to as Figure 4) illustrates the effect of the gap size between the end of the conductive rod and the lower conductive wall of the ceramic cavity, according to various aspects of this disclosure, on the frequency response of the integrated ceramic resonator. For example... Figure 4A As shown, the conductive rod 214 extends vertically into the ceramic cavity 206 and terminates to form a gap of size G with the bottom conductive wall 210. The influence of different sizes G on the frequency response of the integrated ceramic resonator is... Figure 4B The curves are shown in graph 402. Here, graph 402 shows the admittance of an integrated ceramic resonator that varies with frequency. In this example, line 404 corresponds to the frequency response of an integrated ceramic resonator with a gap G of approximately 15 μm, where peaks 406 and 408 occur at the resonant frequency of the integrated ceramic resonator. Similarly, line 410 corresponds to the frequency response of an integrated ceramic resonator with a gap G of approximately 50 μm, where peaks 412 and 414 occur at the resonant frequency of the integrated ceramic resonator. It is clear from the frequency responses shown in graph 402 that the frequency response of the integrated ceramic resonator can be shifted to a higher frequency range by decreasing the size G of the gap. Similarly, the frequency response of the integrated ceramic resonator can be shifted to a higher frequency range by increasing the size G of the gap. However, in some scenarios, increasing the size G of the gap may result in a lower Q factor compared to that obtained in an integrated ceramic resonator with a smaller gap size G.

[0049] According to certain aspects of this disclosure, the integrated ceramic resonator can be manufactured using a low-temperature co-fired ceramic (LTCC) process. In one aspect, multiple planar ceramic layers having corresponding metallizations can be formed in separate operations. The planar ceramic layers formed in separate operations can then be aligned with each other and heated (e.g., sintered) to fuse the ceramic layers and corresponding metallizations into a single integrated structure having the characteristics of the integrated ceramic resonator 200.

[0050] Figures 5A to 5H(Collectively referred to as FIG. 5) illustrates the various steps of manufacturing an RF oscillator having an integrated ceramic resonator and a surface-mount integrated circuit package according to aspects of the present disclosure. In one aspect, a ceramic layer as shown in the operation of FIG. 5 can be cut from a ceramic tape. In another aspect, a through-hole structure as shown in FIG. 5 can be formed in the ceramic layer using, for example, drilling techniques. In yet another aspect, a metal structure as shown in FIG. 5 can be deposited on the surface of the ceramic layer and in the through-hole structure using metal printing techniques. Based on the teachings of the present disclosure, it will be understood that other processes can be used to implement the manufacturing steps shown in FIG. 5.

[0051] Figures 5A to 5F The steps shown involve forming a ceramic layer and a corresponding metallization layer prior to fusion. Figure 5A In this process, a metal layer 502 is deposited on the upper surface of the first ceramic layer 504. The metal layer 502 ultimately forms the lower conductive wall 210 of the ceramic cavity 206 (see...). Figure 2A ).

[0052] exist Figure 5B and 5C In this process, via structures 506 and 508 are formed in the second ceramic layer 510 and are filled with metal during the metallization process. The via structure 506 is formed in the shape of a vertical conductive wall 212 defining the periphery of the ceramic cavity 206, while the via structure 508 is formed in the shape of a conductive rod 214. The metal filling the via structure 506 ultimately forms the vertical conductive wall 212 at the periphery of the ceramic cavity 206. Similarly, the metal filling the via structure 508 ultimately forms the conductive rod 214. The metal deposited during the filling of the via structures 506 and 508 also extends to cover a portion of the upper surface of the second ceramic layer 510. In this example, a patterned metal layer 512 is deposited on the upper surface of the second ceramic layer 510. The patterned metal layer 512 ultimately forms an upper conductive wall 208 at the upper periphery of the ceramic cavity 206. Additionally, another patterned metal layer 514 may be deposited on the upper surface of the second ceramic layer 510 to cover the metal deposited in the through-hole structure 508.

[0053] exist Figure 5DIn the third ceramic layer 520, through-hole structures 516 and 518 are formed. Each of the through-hole structures 516 and 518 is filled with a metal layer that extends around a portion of the upper surface of the third ceramic layer 520 above each of the through-hole structures 516 and 518. The metal layers deposited in and around the through-hole structures 516 and 518 form corresponding terminals 522 and 524, where terminal 522 ultimately provides an electrical connection to the conductive outer periphery of the ceramic cavity, and terminal 524 provides an electrical connection to a conductive rod. Additionally, patterned metal can be deposited on the upper surface of the third ceramic layer 520 in the form of a conductive strip 526 (only one conductive strip is shown in Figure 5). The conductive strip 526 forms a conductive path to a power source.

[0054] Figure 5E A fourth ceramic layer 528 is shown, which ultimately forms the upper surface of the integrated ceramic resonator 200. In this example, a via structure 530 is formed through the fourth ceramic layer 528, and the via structure 530 provides an opening for establishing an electrical connection between a conductive peripheral wall at the periphery of the ceramic cavity 206 and an active oscillator circuit housed in the surface-mount integrated circuit package. Another via structure 532 is formed through the fourth ceramic layer 528, and the other via structure 532 provides an opening for establishing an electrical connection between a conductive rod 214 and an active oscillator circuit housed in the surface-mount integrated circuit package. An additional set of via structures 534 and 536 may also be formed through the fourth ceramic layer 528. Through-hole structure 534 provides an opening for establishing an electrical connection between the power input of the surface-mount integrated circuit package and the power strip 224, while through-hole structure 536 provides an opening for establishing an electrical connection between a power source and the power strip 224.

[0055] Figure 5F The alignment of the ceramic layers and corresponding metallization layers is shown before the final formation of the integrated ceramic resonator 200. As shown, the lower surface of ceramic layer 528 is aligned with the upper surface of ceramic layer 520. The bottom surface of ceramic layer 520 is aligned with the upper surface of ceramic layer 510. The bottom surface of ceramic layer 510 is aligned with the upper surface of ceramic layer 504. Once aligned, these ceramic layers and their corresponding metallization layers are fused together using a sintering process.

[0056] Figure 5G An integrated ceramic resonator 200 is shown, in which all ceramic layers and corresponding metallization layers are fused together to form a single integrated structure. Figure 5H The use of solder bumps extending through the through-hole structure 532 to mount the surface mount integrated circuit package 230 onto the upper surface of the integrated ceramic resonator 200 completes the electrical connection between the surface mount integrated circuit package 230, the integrated ceramic resonator 200 and the power supply.

[0057] Figure 6 A schematic representation of the circuit model equivalents of the components corresponding to the RF oscillator 600 constructed according to various aspects of this disclosure is shown. In one aspect, the surface-mount integrated circuit package 602 housing the active oscillator circuitry can be represented by the equivalent active circuit model shown at 604. In another aspect, the integrated ceramic resonator 606 can be represented by the equivalent passive circuit model shown at 608.

[0058] Figure 7 An example method 700 for manufacturing an integrated device according to aspects of this disclosure is shown. In operation 702, a plurality of planar ceramic layers are formed, wherein one or more of the plurality of planar ceramic layers include a corresponding patterned metal layer. In operation 704, the plurality of planar ceramic layers and the corresponding patterned metal layers are aligned and stacked on top of each other. In operation 706, the plurality of planar ceramic layers and the corresponding patterned metal layers are fused together by a thermal process to form an integrated ceramic resonator having an upper planar surface for receiving a surface-mount integrated circuit package, a plurality of conductive walls defining a conductive periphery of a ceramic cavity, a conductive rod extending at least partially vertically into the ceramic cavity, wherein the conductive rod is isolated from the conductive periphery of the ceramic cavity to avoid contact with the conductive periphery of the ceramic cavity, a first via structure extending vertically through the upper planar surface to connect the conductive periphery of the ceramic cavity to the surface-mount integrated circuit package, and a second via structure extending vertically through the upper planar surface to connect the conductive rod to the surface-mount integrated circuit package.

[0059] It should be noted that Figure 7 Method 700 may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing packages including integrated ceramic resonators. In some implementations, the order of the processes may be changed or modified.

[0060] The technical advantages of method 700 include the fabrication of an integrated ceramic resonator to which a surface-mount integrated circuit package can be mounted to avoid resonant frequency tuning and stability problems that would otherwise occur when passive resonators are wired together with active oscillator circuit leads. The fabrication steps are easy to implement, and the resulting integrated ceramic resonator can be configured to operate at high RF frequencies with a high Q factor.

[0061] Figure 8This describes various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, intermediate packages, PoP (PoP) packages, system-in-package (SiP) packages, or system-on-a-chip (SoC). For example, mobile phone device 802, laptop computer device 804, fixed-location terminal device 806, wearable device 808, or motor vehicle 810 may include device 800 as described herein. Device 800 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 8 The devices 802, 804, 806, and 808, and the vehicle 810 described herein are merely exemplary. Other electronic devices may also feature the disclosed RF oscillator, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0062] The following implementation examples are described in terms of their numbering:

[0063] The devices and functionalities disclosed above can be designed and stored in computer files (e.g., register transfer level (RTL), geometric data stream (GDS) Gerber, etc.) stored on a computer-readable medium. Some or all of these files can be provided to a manufacturing disposition that manufactures devices based on such files. The resulting products can include various components comprising semiconductor wafers, which are subsequently diced into semiconductor dies and packaged into semiconductor packages, integrated devices, stacked package devices, system-on-a-chip devices, etc., which can then be used in the various devices described herein.

[0064] It will be appreciated that the aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the equipment may include means for performing the various functions discussed above. It will be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or explanations cited as examples.

[0065] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0066] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A is physically in contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "encapsulation" means that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component situated "above" a second component can mean that the first component is located above or below the second component, depending on how "bottom" or "top" is arbitrarily defined. In another example, a first component may be situated above (e.g., above) a first surface of a second component, while a third component may be situated above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It should be further noted that the term "above," as used in this application in the context of one component being above another, can be used to mean that a component is on and / or within another component (e.g., on the surface of a component or embedded within a component). Thus, for example, "first component over second component" can mean: (1) the first component is over the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0067] In some implementations, an interconnect is a element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, solder pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0068] It should also be noted that the various disclosures contained herein can be described as processes depicted as flowcharts, flow diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0069] In the detailed description above, it can be seen that different features are grouped together in the various examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each aspect. Rather, aspects of this disclosure may include fewer features than the individual example aspects disclosed. Thus, the appended aspects should be considered as being incorporated into this description, where each aspect may be a separate aspect in itself. Although each dependent aspect may refer in one aspect to a particular combination with one of the other aspects, the aspects(s) of that dependent aspect are not limited to that particular combination. It will be appreciated that other example aspects may also include combinations of the subject matter of the dependent aspects with any other dependent or independent aspects, or combinations of any feature with other dependent and independent aspects. The aspects disclosed herein explicitly include these combinations unless explicitly stated or can be readily inferred that a particular combination is not intended (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is intended that aspects of an aspect may be included in any other independent aspect, even if that aspect is not directly subordinate to that independent aspect.

[0070] While the foregoing disclosure has illustrated illustrative aspects of this disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions in the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, pluralism is also contemplated unless explicitly stated to be limited to the singular.

Claims

1. A device comprising: a surface mount integrated circuit package that houses an active oscillator circuit; and an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface that receives the surface mount integrated circuit package, the integrated ceramic resonator comprising: a plurality of electrically conductive walls forming an electrically conductive periphery of a ceramic cavity in the ceramic substrate, an electrically conductive rod extending at least partially vertically into the ceramic cavity, wherein the electrically conductive rod is isolated from the electrically conductive periphery of the ceramic cavity to not be in contact with the electrically conductive periphery of the ceramic cavity, a first electrically conductive material extending vertically through the upper planar surface of the ceramic substrate to connect the electrically conductive periphery of the ceramic cavity to the surface mount integrated circuit package that houses the active oscillator circuit, and a second electrically conductive material extending through the upper planar surface of the ceramic substrate to connect the electrically conductive rod to the surface mount integrated circuit package that houses the active oscillator circuit.

2. The device of claim 1, wherein: the electrically conductive rod extends into the ceramic cavity along a central vertical axis of the ceramic cavity.

3. The device of claim 1, wherein the plurality of electrically conductive walls forming the electrically conductive periphery of the ceramic cavity comprises: an upper electrically conductive wall; a lower electrically conductive wall vertically spaced apart from the upper electrically conductive wall; and a vertical electrically conductive wall connecting the upper electrically conductive wall with the lower electrically conductive wall.

4. The device of claim 1, wherein: the electrically conductive rod has a diameter and terminates at a distance from a bottom electrically conductive wall of the ceramic cavity, and the diameter and the distance at least partially determine a resonant frequency of the integrated ceramic resonator.

5. The device of claim 1, wherein: the integrated ceramic resonator has a resonant frequency that is near or above 1 gigahertz (GHz).

6. The device of claim 1, wherein: the plurality of electrically conductive walls and the electrically conductive rod are arranged and dimensioned to have a resonant frequency that is near 2.5 gigahertz (GHz).

7. The device of claim 1, wherein: the plurality of electrically conductive walls and the electrically conductive rod are arranged and dimensioned to have a resonant frequency that is above 2.5 gigahertz (GHz).

8. The device of claim 1, wherein the device comprises at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in an automotive vehicle.

9. An integrated ceramic resonator comprising: a ceramic substrate having an upper planar surface for receiving a surface mount integrated circuit package; a plurality of electrically conductive walls forming an electrically conductive periphery of a ceramic cavity in the ceramic substrate; an electrically conductive rod extending at least partially vertically into the ceramic cavity, wherein the electrically conductive rod is isolated from the electrically conductive periphery of the ceramic cavity to not be in contact with the electrically conductive periphery of the ceramic cavity; ​ a first via structure disposed through the upper planar surface of the ceramic substrate to connect the electrically conductive periphery of the ceramic cavity to the surface mount integrated circuit package; and a second via structure disposed through the upper planar surface of the ceramic substrate to connect the electrically conductive post to the surface mount integrated circuit package.

10. The integrated ceramic resonator of claim 9, wherein: the electrically conductive post extends along a central vertical axis of the ceramic cavity.

11. The integrated ceramic resonator of claim 9, wherein the plurality of electrically conductive walls forming the electrically conductive periphery of the ceramic cavity comprises: an upper electrically conductive wall; a lower electrically conductive wall vertically spaced apart from the upper electrically conductive wall; and a vertical electrically conductive wall connecting the upper electrically conductive wall and the lower electrically conductive wall.

12. The integrated ceramic resonator of claim 11, wherein: the upper electrically conductive wall and the lower electrically conductive wall are planar structures parallel to each other.

13. The integrated ceramic resonator of claim 11, wherein: the vertical electrically conductive wall is formed as a cylindrical structure.

14. The integrated ceramic resonator of claim 11, wherein: the vertical electrically conductive wall is formed as an octagonal or higher order polygonal structure.

15. The integrated ceramic resonator of claim 9, wherein: the electrically conductive post has a diameter and terminates at a distance from a bottom electrically conductive wall of the ceramic cavity, and the diameter and the distance determine a resonant frequency of the integrated ceramic resonator.

16. The integrated ceramic resonator of claim 1, further comprising: a first electrically conductive metal structure formed in the first via structure and providing a first electrically conductive path directly between the electrically conductive periphery of the ceramic cavity and the surface mount integrated circuit package; and a second electrically conductive metal structure formed in the second via structure and providing a second electrically conductive path directly between the electrically conductive post and the surface mount integrated circuit package.

17. The integrated ceramic resonator of claim 9, wherein: the plurality of electrically conductive walls and the electrically conductive post are arranged and dimensioned to have a resonant frequency higher than 1 gigahertz (GHz).

18. The integrated ceramic resonator of claim 9, wherein: the plurality of electrically conductive walls and the electrically conductive post are arranged and dimensioned to have a resonant frequency close to 2.5 gigahertz (GHz).

19. The integrated ceramic resonator of claim 9, wherein: the plurality of electrically conductive walls and the electrically conductive post are arranged and dimensioned to have a resonant frequency higher than 2.5 gigahertz (GHz).

20. A method for fabricating an integrated device, comprising: forming a plurality of planar ceramic layers, wherein one or more of the plurality of planar ceramic layers includes a corresponding patterned metal layer; aligning the plurality of planar ceramic layers and corresponding patterned metal layers to overlie each other; and fusing the plurality of planar ceramic layers and the corresponding patterned metal layers to each other in a thermal process to form an integrated ceramic resonator having: an upper planar surface for receiving the surface mount integrated circuit package, a plurality of electrically conductive walls defining an electrically conductive periphery of a ceramic cavity, an electrically conductive post extending through the upper planar surface of the ceramic cavity and electrically connected to the plurality of electrically conductive walls. an electrically conductive post extending at least partially vertically into the ceramic cavity, wherein the electrically conductive post is isolated from the electrically conductive periphery of the ceramic cavity to not be in contact with the electrically conductive periphery of the ceramic cavity, a first via structure extending vertically through the upper planar surface to connect the electrically conductive periphery of the ceramic cavity to the surface mount integrated circuit package, and a second via structure extending vertically through the upper planar surface to connect the electrically conductive post to the surface mount integrated circuit package.

21. The method of claim 20, wherein forming the plurality of planar ceramic layers and the corresponding patterned metal layers comprises: forming a first planar ceramic layer; forming a post-shaped hole partially through the first planar ceramic layer; forming a third via structure through the first planar ceramic layer around the post-shaped hole; and depositing a first metal layer on an upper surface of the first planar ceramic layer, within the post-shaped hole, and in the third via structure, wherein the first metal layer forms, after the plurality of planar ceramic layers and the corresponding patterned metal layers have fused to one another: an upper electrically conductive wall of the ceramic cavity, an electrically conductive side wall of the ceramic cavity, and the electrically conductive post.

22. The method of claim 21, wherein forming the plurality of planar ceramic layers and the corresponding patterned metal layers comprises: forming a second planar ceramic layer; and depositing a second metal layer on an upper surface of the second planar ceramic layer, wherein the second metal layer forms, after the plurality of planar ceramic layers and the corresponding patterned metal layers have fused to one another, a lower electrically conductive wall of the ceramic cavity.

23. The method of claim 21, wherein forming the plurality of planar ceramic layers and the corresponding patterned metal layers comprises: forming a third planar ceramic layer; forming a fourth via structure through the third planar ceramic layer; forming a fifth via structure through the third planar ceramic layer; depositing a third metal layer on a first portion of an upper surface of the third planar ceramic layer that overlies the fourth via structure, and on a second portion of the upper surface of the third planar ceramic layer that overlies the fifth via structure, wherein the third metal layer forms, after the plurality of planar ceramic layers and the corresponding patterned metal layers have fused to one another: a first electrically conductive path between the electrically conductive periphery of the ceramic cavity and the first via structure, and a second electrically conductive path between the electrically conductive post and the second via structure.

24. The method of claim 21, wherein forming the plurality of planar ceramic layers and the corresponding patterned metal layers comprises: forming a fourth planar ceramic layer; forming a sixth via structure through the fourth planar ceramic layer; and forming a seventh via structure through the fourth planar ceramic layer, wherein, after the plurality of planar ceramic layers and the corresponding patterned metal layers have fused to one another, the sixth via structure forms the first via structure of the integrated ceramic resonator, the seventh via structure forms the second via structure of the integrated ceramic resonator, and the seventh via structure forms the second via structure of the integrated ceramic resonator. An upper surface of the fourth planar ceramic layer forms the upper planar surface for receiving the surface mount integrated circuit package.

25. The method of claim 20, further comprising: mounting the surface mount integrated circuit package on the upper planar surface of the integrated ceramic resonator, wherein mounting the surface mount integrated circuit package includes: forming a first conductive path through the first via structure to a first input of an oscillator circuit housed within the surface mount integrated circuit package, and forming a second conductive path through the second via structure to a second input of the oscillator circuit housed in the surface mount integrated circuit package.

26. The method of claim 20, wherein: after the plurality of planar ceramic layers and the corresponding patterned metal layers are fused to one another, the corresponding patterned metal layers form the electrically conductive periphery of the ceramic cavity to include: an upper electrically conductive wall, a lower electrically conductive wall vertically spaced apart from the upper electrically conductive wall, and a vertical electrically conductive wall connecting the upper electrically conductive wall with the lower electrically conductive wall.

27. The method of claim 26, wherein: after the plurality of planar ceramic layers and the corresponding patterned metal layers are fused to one another, the corresponding patterned metal layers form the upper electrically conductive wall and the lower electrically conductive wall as planar structures parallel to one another.

28. The method of claim 26, wherein: after the plurality of planar ceramic layers and the corresponding patterned metal layers are fused to one another, the corresponding patterned metal layers form the vertical electrically conductive wall as a cylindrical structure.

29. The method of claim 26, wherein: after the plurality of planar ceramic layers and the corresponding patterned metal layers are fused to one another, the corresponding patterned metal layers form the vertical electrically conductive wall as an octagonal or higher order polygonal structure.

30. The method of claim 26, wherein: after the fusing, the corresponding patterned metal layers form the electrically conductive rod as a fixed diameter electrically conductive rod that extends into the ceramic cavity and terminates at a fixed distance from a lower electrically conductive wall of the ceramic cavity, and the fixed diameter electrically conductive rod and the fixed distance are selected to determine a resonant frequency of the integrated ceramic resonator.

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