Method for controlling low power consumption mode of embedded firmware and storage device
By setting an interrupt flag in the SSD kernel to determine the task and interrupt status, the problem of the SSD controller accidentally entering low-power mode during idle time is solved, thus achieving a combination of low power consumption and fast response.
Patent Information
- Application Number
- CN202511197177.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-25
- Publication Date
- 2025-12-12
AI Technical Summary
Existing SSD controllers are prone to accidentally entering low-power mode when idle, which affects the system's command response speed.
By traversing the task loop queue of the SSD kernel, it determines whether there are tasks and interrupts to be run, sets the interrupt flag, and disables the instructions to enter low-power mode, ensuring that it only enters low-power mode when there are no tasks or interrupts.
This prevents the SSD kernel from accidentally entering low-power mode, reducing standby power consumption while ensuring that the system's command response speed is not affected.
Smart Images
Figure CN121116042A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of power consumption management, and in particular, to a method for controlling a low power mode of embedded firmware and a storage device. BACKGROUND
[0002] In terms of power consumption control, enterprise SSDs not only have the demand to reduce read and write power consumption, but also have the demand to further reduce standby power consumption. To control standby power consumption, the following two methods can be used, i.e., the SSD controller reduces the frequency in idle time, or the SSD controller enters a low power mode in idle time. Since enterprise SSDs have specific requirements in terms of response delay to read and write commands, the SSD controller reducing the frequency in idle time may cause the command response to be not timely and affect the execution of background tasks. Therefore, the most appropriate way to control standby power consumption is to make the SSD controller enter a low power mode in idle time.
[0003] Currently, mainstream SSD controllers enter a low power mode through a wait event instruction WFE (Wait For Event) or a wait interrupt instruction WFI (Wait For Interrupt). For example, ARMv7 / ARMv8 supports WFE and WFI, and RISC-V only supports WFI. WFE puts the processor into a sleep state and can still respond to events from the inside or outside to wake up, and WFI puts the processor into a sleep state but only wakes up when receiving an interrupt signal, does not affect events other than interrupts, and the current CPU core immediately enters a low power state. After the SSD controller core executes the WFE or WFI instruction, it closes most of the clocks in the core and only maintains the core power supply, retains a small part of the clock, and ensures that the core can wake up from the low power state. When the core receives an event that can wake up from the low power mode, the core will exit the low power mode and continue to execute the next instruction.
[0004] The conditions for exiting the low power mode after executing the WFE instruction include:
[0005] another core in the multi-core system executes a send event SEV instruction; or
[0006] performing a local send event SEVL (send event local) in advance before entering the WFE low power mode; or
[0007] the current core receives any type of interrupt, such as an external interrupt, a software interrupt, an exception, and a debug event.
[0008] The conditions for exiting the low power mode after executing the WFI instruction include:
[0009] The current kernel receives any type of interrupt, such as an external interrupt, a software interrupt, an exception, and a debugging event.
[0010] The mainstream SSD controller enters the low-power mode by the instruction WFE or WFI, and there is a problem of misentry into the low-power mode. SUMMARY
[0011] Therefore, it is necessary to solve the problem of misentry of the SSD kernel into the low-power mode, and the embodiments of the present disclosure provide a method for controlling a low-power mode of embedded firmware and a storage device.
[0012] In a first aspect, the embodiments of the present disclosure provide a method for controlling a low-power mode of embedded firmware, the method comprising:
[0013] In response to receiving an instruction to enter a low-power mode, traversing a task loop queue of a SSD kernel, determining whether there is a task to be run and whether an interrupt occurs;
[0014] If it is determined that there is no task to be run within a preset time period and an interrupt occurs, setting a pre-set interrupt flag and invalidating the instruction to enter the low-power mode;
[0015] After re-traversing the task loop queue, clearing the interrupt flag, and controlling the SSD kernel firmware to enter the low-power mode by executing the instruction to enter the low-power mode.
[0016] In some embodiments of the present disclosure, the instruction to enter the low-power mode is a WFE instruction.
[0017] In some embodiments of the present disclosure, the setting of the pre-set interrupt flag and the invalidation of the instruction to enter the low-power mode comprise:
[0018] Setting a wake-up event to wake up an interrupt service by executing a SEVL instruction, setting the interrupt flag, and invalidating the WFE instruction.
[0019] In some embodiments of the present disclosure, the clearing of the interrupt flag comprises:
[0020] Executing the WFE instruction to clear the interrupt flag generated by the SEVL instruction.
[0021] In some embodiments of the present disclosure, when there are multiple SSD kernels, before controlling the SSD kernel to enter the low-power mode, the method further comprises entering the low-power mode in response to any of the following conditions:
[0022] When other SSD kernels need the current SSD kernel firmware to process a task, executing a SEV instruction to wake up the current SSD kernel; or
[0023] If an interrupt occurs, the SEV instruction is executed to wake up other SSD cores before the interrupt returns, or the SEVL instruction is executed to wake up the current core in response to a preset wake-up event.
[0024] In some embodiments of the present disclosure, the instruction for entering the low-power consumption mode is a WFI instruction.
[0025] In some embodiments of the present disclosure, after determining whether there is a task to be executed and whether an interrupt occurs, the method further comprises:
[0026] If it is determined that there is no task to be executed and no interrupt occurs within a preset time period, and the sleep condition is met, the WFI instruction is executed to enter the low-power consumption state.
[0027] In some embodiments of the present disclosure, the setting of the preset interrupt flag and the invalidation of the instruction for entering the low-power consumption mode comprise:
[0028] The WFI instruction is invalidated by setting the interrupt flag.
[0029] In some embodiments of the present disclosure, the invalidation of the WFI instruction comprises: entering a critical section in response to the closing of the interrupt; determining the interrupt flag, and if the interrupt flag is not set, exiting the critical section and opening the interrupt;
[0030] If the interrupt flag is set, returning from the interrupt return address.
[0031] Determining whether the operation of the interrupt return address is located after the exiting of the critical section and before the execution of the WFI instruction, and if the determination is yes, skipping the WFI instruction and modifying the interrupt return address to a next instruction address of the WFI instruction.
[0032] In some embodiments of the present disclosure, after the control of the SSD core firmware to enter the low-power consumption mode, the method further comprises:
[0033] When exiting the low-power consumption mode, the interrupt flag of the current core is cleared.
[0034] In a second aspect, embodiments of the present disclosure also provide a storage device, comprising a memory and a processor, wherein the processor comprises a plurality of cores, and the memory stores a computer program, and when the computer program is executed by the processor, the above-mentioned method for controlling the low-power consumption mode of the embedded firmware is implemented.
[0035] The present disclosure provides a method and a storage device for controlling a low-power mode of embedded firmware, at least bringing the following beneficial effects: in the embedded firmware without an operating system, by improving the interrupt handler, the instruction WFE / WFI can still be executed to enter the low-power mode; preventing false entry into the low-power mode; reducing standby power consumption, and not affecting the system response command speed due to entry into the low-power mode.
[0036] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.
[0038] Figure 1 Flowchart of the main loop of the kernel firmware in the related art;
[0039] Figure 2 Flowchart of the method for controlling the low-power mode of the embedded firmware provided by the present disclosure;
[0040] Figure 3a And 3b Flowchart of the method for controlling the low-power mode of the embedded firmware by the WFE instruction provided by one embodiment of the present disclosure;
[0041] Figures 4a-4c Flowchart of the method for controlling the low-power mode of the embedded firmware by the WFI instruction provided by another embodiment of the present disclosure;
[0042] Figure 5a And 5b Flowchart of the method for controlling the low-power mode of the embedded firmware by the WFI instruction in the interrupt mode provided by another embodiment of the present disclosure.
[0043] Figure 6 Structural diagram of an exemplary electronic device capable of implementing the embodiments of the present disclosure. DETAILED DESCRIPTION
[0044] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure, and cannot limit the present disclosure.
[0045] Task switching of the operating system brings additional software overhead, increasing the I / O command response time. In the prior art, when the SSD firmware does not use the operating system, the tasks that need to be executed by a specific kernel are usually listed in the main loop of the kernel firmware, as shown in Figure 1
[0046] Based on the above-mentioned problems, the method provided by the embodiments of the present disclosure provides a complete method for the SSD firmware without an operating system to judge entering and exiting the low-power mode, and ensures that the latency of the SSD firmware responding to read and write commands does not fluctuate greatly due to the kernel entering the low-power mode.
[0047] Referring to Figure 2 The method 200 for controlling the low-power mode of the embedded firmware provided by the embodiments of the present disclosure includes the following steps:
[0048] In step S210, in response to receiving an instruction to enter the low-power mode, the task loop queue of the SSD kernel is traversed to determine whether there is a task to be run and whether an interrupt occurs.
[0049] In step S220, if it is determined that there is no task to be run in a preset time period and an interrupt occurs, a pre-set interrupt flag is set and the instruction to enter the low-power mode is invalidated.
[0050] In step S230, after re-traversing the task loop queue, the interrupt flag is cleared, and the SSD kernel firmware is controlled to enter the low-power mode by executing the instruction to enter the low-power mode.
[0051] The above method steps will be described in detail below in combination with some specific embodiments.
[0052] Specifically, in step S210, it is determined whether the kernel meets the preset condition for entering the low-power mode. The preset condition includes that all tasks in the main loop do not need to be run in a preset time, and no interrupt occurs at the moment of entering the low-power mode.
[0053] If an interrupt occurs, it means that some tasks may need to be executed immediately, and if they cannot be processed in time and mistakenly enter the low-power mode, a large latency will be generated for the read and write commands issued by the host.
[0054] It should be noted that in the case of multiple CPU cores in the chip, the scheme of the present disclosure is executed based on each core. The execution subject is referred to as the current kernel. Accordingly, the interrupt mentioned in the present disclosure refers to the interrupt that needs to be processed by the current kernel.
[0055] The instruction for entering the low power consumption mode is a WFE instruction or a WFI instruction, and specific embodiments are described below.
[0056] In an optional embodiment of the present disclosure, the instruction for entering the low power consumption mode is a WFE instruction, as shown in the accompanying drawings Figure 3a .
[0057] In step S301, the main loop entry is entered; in step S302, the sleep target timestamp sleepTimestamp is initialized; in step S303, the status of all tasks is summarized, the tasks being serial tasks or task state machines; in step S304, the check task idle timestamp checkTimestamp is updated; in step S305, it is determined whether all tasks are in an idle state; if not, the sleep target timestamp sleepTimestamp is updated in step S306; then step S303 is re-executed; if all tasks are in an idle state, it is determined in step S307 whether the idle time satisfies the condition for entering the low power consumption; if not, step S303 is re-executed; if yes, a WFE is executed in step S308 to enter the low power consumption, and after entering the low power consumption, the code execution is stopped and waits to be woken up by an interrupt. After the current core satisfies the condition for entering the low power consumption mode, the WFE instruction is executed to enter the low power consumption mode. In a further embodiment, when other cores need the current core to process tasks, the SEV instruction is executed to wake up the current core.
[0058] In an interrupt, in addition to the current core, the assistance of other cores can be needed, and at this time, an SEV is sent in an ISR (Interrupt Service Routine thread) to request the assistance of other cores. In the ISR, by executing an SEVL, a local event to be processed is set for the current core, and the purpose is to prevent the entering of the low power consumption state when the next WFE is executed after the execution of the SEVL. If no new task to be processed is generated, the low power consumption state will be successfully entered when the next WFE is executed.
[0059] In some embodiments, after step S307 and before step S308, an interrupt can occur in this time window. In order to solve this problem, see Figure 3bIn further embodiments (steps S311-S314), before the interrupt returns, one of SEV or SEVL can be executed as needed; SEV is used to wake up other cores, while SEVL is used to pre-set a wake-up event for the current core, preventing the interrupt from occurring in a small window before the execution of WFE and causing false entry into low power mode. In step S311, the interrupt enters; in step S312, the interrupt service program determines the interrupt return; in step S313, one of SEV or SEVL is executed as needed; SEV is used to wake up other cores, while SEVL is used to pre-set a wake-up event for the current core, preventing the interrupt from occurring in a small window before the execution of WFE and causing false entry into low power mode; in step S314, the interrupt returns.
[0060] In step S220, the ISR of the current core of the present disclosure before exiting, the end executes an SEVL instruction to ensure that when the interrupt occurs as shown in the dashed box of FIG. 1 Figure 3a , the WFE after the dashed box is invalid, that is, it will not enter the low power state. But in step S230, the execution of WFE after the dashed box will clear the interrupt flag generated by this SEVL. Thus, in the next loop of the main loop of the current core, when WFE is executed again, the low power state is entered.
[0061] In the optional embodiments of the present disclosure, the above-mentioned instruction for entering low power mode is the WFI instruction, as shown in FIG. 1 Figures 4a-4c .
[0062] According to Figure 4aIn the process, in step S210, after the current kernel meets the conditions for entering low-power mode, before executing the WFI instruction to enter low-power mode, a specific wake-up interrupt is first enabled, and an interrupt flag is added to the end of the ISR to indicate that an interrupt has occurred now or recently, and then the WFI instruction is executed; after exiting low-power mode, the interrupt flag of the current kernel is cleared (steps S411-S420). In step S411, the main loop entry point is entered; in step S412, the sleep target timestamp is initialized: sleepTimestamp; in step S413, the status of all tasks is summarized, where the task is a serial task or a task state machine; in step S414, the idle timestamp of the detection task is updated: checkTimestamp; in step S415, it is determined whether all tasks are currently in an idle state; if not, the sleep target timestamp is updated in step S417; then, the interrupt flag is cleared in step S420; if all tasks are in an idle state, it is determined in step S416 whether the idle time satisfies the requirement to enter low power mode; if not, the interrupt flag is cleared in step S420; if so, the wake-up interrupt is enabled in step S418; in step S419, low power mode is entered, and after entering low power mode, code execution stops, waiting to be woken up by an interrupt; in step S420, the interrupt flag is cleared.
[0063] Correspondingly, in Figure 4b When handling wake-up interrupts (steps S421-S424), it is necessary to disable / mask the wake-up interrupt and clear its interrupt status. For example, the data link CPU uses the interrupt of receiving an I / O command from the hardware module as the wake-up interrupt. In idle state, this interrupt is enabled. Once any I / O command is received, the interrupt is triggered, and the CPU exits WFI and quickly responds to the interrupt. The interrupt's function is only to wake up the CPU. The service routine only disables / masks the interrupt and clears its interrupt status, and sets the interrupt flag. Because the interrupt has been disabled, subsequent I / O commands received by the hardware will not trigger the interrupt, and will not affect the processing of subsequent I / O commands. In step S421, the interrupt entry point is established; in step S422, the wake-up interrupt service routine disables / masks the specific wake-up interrupt and clears the interrupt status; in step S423, the interrupt flag is set; in step S424, the interrupt returns.
[0064] for Figure 4cother non-wakeup type of interrupts (steps S431-S434), such as the resident system timer tick interrupt, which is always on in the runtime state, and does not need to be re-enabled / disabled regardless of entering the low power state, and the interrupt service routine can contain other procedures, including determining whether there is an active timer task, whether the timer task is expired, whether scheduling is needed, etc. In step S431, the interrupt entry; in step S432, the other interrupt service routine determines whether there is an active timer task, whether the timer task is expired, whether scheduling is needed, etc.; in step S433, the interrupt flag is set; and in step S434, the interrupt returns.
[0065] In step S220, the flag is determined before the WFI instruction is executed, and if it has been set, the current loop does not execute the WFI instruction and does not enter the low power state; in step S230, the interrupt flag is cleared after each loop of the main loop, so that the scope of the interrupt flag set in the ISR is limited within one loop of the main loop. In other words, when there is no interrupt in one loop of the main loop and the sleep condition is met, the WFI is executed to enter the low power state;
[0066] In order to accurately determine whether the current loop needs to enter the low power state, in the ISR, it is checked whether the interrupt return address falls within the dashed time window as shown in FIG. 2B, to determine whether the WFI instruction after the dashed box is executed after the ISR returns; if the interrupt return address does not fall within the dashed time window, it is returned normally; otherwise, the interrupt return address is modified to the next instruction address of the WFI instruction. Figure 5a
[0067] Since there is a time window between determining whether the current kernel is idle and actually executing the WFI instruction to enter the low power state, and the interrupt can occur in this time window, if no protection is performed, the interrupt will not keep the current kernel in the wake-up state, thereby causing a large delay in processing read / write commands.
[0068] Figure 5a This refers to the actions performed after the sleep condition is met in the main loop (steps S501-S507). In a specific embodiment, before executing the WFI instruction, the system enters the critical section (interrupts are disabled) and checks whether an interrupt flag exists, adding critical section protection to the read interrupt flag; after exiting the critical section, interrupts are enabled, and the WFI instruction is executed, further narrowing the window for accidental entry into low-power mode. Before returning from the interrupt, it checks whether the interrupt return address is within the window; if so, the return address skips the WFI instruction; otherwise, it returns normally. In step S501, execution begins; in step S502, the system enters the critical section; in step S503, it checks whether an interrupt flag exists; if an interrupt flag exists, step S505 is executed, exiting the critical section; in step S507, the system ends and returns. If there is no interrupt flag, it is assumed that no interrupt has occurred, and the system can enter low-power mode, execute step S504, and exit the critical section. Between step S504 and step S506 when WFI is executed, it is determined whether the interrupt return address is within the window. If it is, the return address is skipped from the WFI instruction; otherwise, it returns normally.
[0069] At the end of the main loop, there may also be an operation to determine whether to sleep and enter low-power mode. This operation takes some time to execute. Therefore, if there are I / O commands that need to be processed during the execution of this operation, it will cause the system to enter low-power mode and then immediately exit low-power mode to process the I / O command. This will cause both the juggling between entering and exiting low-power mode and the delay in processing the I / O command.
[0070] In the embodiments of this disclosure, the main loop may be interrupted at any time during normal execution. After an interrupt occurs, an interrupt handler must be executed, and after the interrupt handler completes, execution returns to the point where the main loop was interrupted. Due to the uncertainty of the timing of the interrupt, it is difficult to determine whether the main loop has entered a low-power state.
[0071] Based on the above method, for cases where low-power mode is entered via the WFE instruction, a wake-up event is preset in the current kernel interrupt to prevent accidental entry into low-power mode. (See also...) Figure 5bThe method can prevent the low-power consumption mode from being entered by mistake through the WFI instruction, the method of judging the interrupt flag, and the judgment and method of skipping the WFI before the interrupt returns. The method enables the instruction WFE / WFI to be executed to enter the low-power consumption mode in the embedded firmware without the operating system, reduces the standby power consumption, and does not affect the system response speed due to the entering of the low-power consumption mode. In step S511, an interrupt is entered; in step S512, an interrupt service program is executed; in step S513, an interrupt flag is set; in step S514, it is judged whether the interrupt return address is within a window, that is, whether the WFI is executed before the critical section is exited, if yes, in step S515, the interrupt return address is modified to skip the WFI; and then step S516 is executed to return the interrupt; if no, step S516 is directly executed to return the interrupt.
[0072] It should be understood that, although Figures 1-5b The steps in the flowcharts are sequentially displayed according to the arrows, but the steps are not necessarily sequentially executed according to the arrows. Unless otherwise specified in this article, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, Figures 1-5b At least part of the steps in the flowcharts can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.
[0073] It can be understood that the same / similar parts between the above-mentioned methods in the specification can be mutually referred to, and each embodiment focuses on the differences from other embodiments, and the related parts can be referred to the description of other method embodiments.
[0074] The disclosure embodiments also provide a storage device including a processor and a memory, wherein the processor includes a plurality of cores, and the memory stores a computer program, which, when executed by the processor, can implement the method of any of the above-mentioned embodiments, and the execution manner and beneficial effects are similar, which will not be repeated here.
[0075] Figure 6 is a structural schematic diagram of a storage device provided by the disclosure embodiments, as Figure 6 shown, the storage device can include a processor 610 and a memory 620, wherein the memory 620 stores a computer program, which, when executed by the processor 610, can implement the method provided by any of the above-mentioned embodiments, and the execution manner and beneficial effects are similar, which will not be repeated here.
[0076] Of course, for the sake of simplicity, Figure 6 Only some of the components of the storage device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, input devices, and output devices. In addition, the storage device may include any other suitable components depending on the specific application.
[0077] This disclosure provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the methods of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.
[0078] The aforementioned computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0079] The computer program described above can be written in any combination of one or more programming languages to perform the operations of the embodiments of this disclosure. The programming languages include object-oriented programming languages such as Java and C++, as well as conventional procedural programming languages such as C or similar languages. The program code can be executed entirely on the user's computer device, partially on the user's device, as a standalone software package, partially on the user's computer device and partially on a remote computer device, or entirely on a remote computer device or server.
[0080] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.
[0081] The foregoing detailed description has set forth various embodiments of the present disclosure via the use of specific terminology. However, embodiments thereof can be practiced without the specific details (e.g., quantities, values, etc.) set forth in the specification and drawings whose exact nature can be apparent or as modifications or equivalents thereof depending upon the particular desired embodiment. Furthermore, the embodiments described herein are generally described in the context of a single user. However, the embodiments described herein can be practiced in the context of multiple users.
Claims
1. A method for controlling a low-power mode in embedded firmware, characterized in that, The method includes: In response to receiving a command to enter low-power mode, the task loop queue of the SSD kernel is traversed to determine whether there are any tasks to be run and whether an interrupt has occurred. If it is determined that there are no tasks to be run within the preset time period and an interrupt occurs, the preset interrupt flag is set, and the instruction to enter low-power mode is invalidated. After re-traversing the task loop queue, the interrupt flag is cleared, and the SSD kernel firmware is controlled to enter low-power mode by executing the instruction to enter low-power mode.
2. The method according to claim 1, characterized in that, The instruction to enter low-power mode is the WFE instruction.
3. The method according to claim 2, characterized in that, Setting the pre-set interrupt flag and disabling the instruction to enter low-power mode includes: The interrupt service is woken up by executing the SEVL instruction to set a wake-up event, setting the interrupt flag and disabling the WFE instruction.
4. The method according to claim 3, characterized in that, Clearing the interrupt flag includes: Execute the WFE instruction to clear the interrupt flag generated by the SEVL instruction.
5. The method according to claim 1, characterized in that, When multiple SSD cores exist, before controlling the SSD cores to enter low-power mode, the method also includes entering low-power mode in response to any of the following conditions: When other SSD kernels need the current SSD kernel firmware to process a task, the SEV instruction is executed to wake up the current SSD kernel. or If an interrupt occurs, before returning from the interrupt, the SEV instruction is executed to wake up other SSD kernels, or in response to a preset wake-up event, the SEVL instruction is executed to wake up the current kernel.
6. The method according to claim 1, characterized in that, The instruction to enter low-power mode is the WFI instruction.
7. The method according to claim 6, characterized in that, After determining whether there are tasks to be run and whether an interruption has occurred, the process also includes: If it is determined that there are no tasks to run and no interruption occurs within the preset time period, and the sleep conditions are met, the WFI instruction is executed to enter a low-power state.
8. The method according to claim 6, characterized in that, Setting the pre-set interrupt flag and disabling the instruction to enter low-power mode includes: The WFI command is disabled by setting an interrupt flag.
9. The method according to claim 8, characterized in that, The step of disabling the WFI instruction includes: in response to disabling interrupts, entering a critical section; determining the interrupt flag; if the interrupt flag is not set, exiting the critical section and enabling interrupts. If the interrupt flag is set, return from the interrupt address; If the operation to return the interrupt address is determined to be after exiting the critical section and before executing the WFI instruction, then the WFI instruction is skipped and the interrupt return address is modified to the address of the instruction following the WFI instruction.
10. The method according to claim 8, characterized in that, After controlling the SSD kernel firmware to enter low-power mode, the method further includes: When exiting the low-power mode, clear the interrupt flag of the current core.
11. A storage device, characterized in that, include: A memory and a processor, the processor including multiple cores, wherein the memory stores a computer program that, when executed by the processor, implements a method for controlling a low-power mode of embedded firmware as described in any one of claims 1-10.