A data erasing method, device, equipment and medium of a memory

Abstract

The application provides a data erasing method, device and equipment of a memory and a medium. The data erasing method comprises the following steps: obtaining a first average wear degree and a second average wear degree; reading corresponding mapping tables according to a logical address to be erased; determining an erasing mode according to a comparison result of the first average wear degree and the second average wear degree; when the first mode is adopted, determining and emptying a mapping relationship of a largest mapping table item in the mapping tables according to the logical address to be erased; when the second mode is adopted, updating a corresponding physical address in a mapping relationship of a mapping table item in the mapping tables into a preset invalid data physical address; and erasing user data and invalid data. The application provides a data erasing method, device and equipment of a memory and a medium to solve the technical problem that the life of a mapping table block and the life of user data blocks are not synchronized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a data erasing method, device and equipment of a memory and a medium. BACKGROUND

[0002] In the existing storage architecture, the mapping table of the flash translation layer (FTL) and the user data are respectively stored in the mapping table block and the user data block. Since the FTL mapping table needs to be frequently updated in response to the host write, Trim and other operations, the write amplification of the mapping table block is much higher than that of the user data block, which makes it a life bottleneck.

[0003] The traditional scheme attempts to alleviate this problem by optimizing the garbage collection (GC) process or wear leveling, but fails to fundamentally change the frequent updating characteristics of the mapping table, resulting in the actual wear rate of the mapping table block being consistently higher than that of the user data block. Due to the inconsistent wear rates of the mapping table block and the user data block, it is difficult to achieve life synchronization. The existing method cannot ensure performance while making the life of the mapping table block and the user data block tend to an ideal state. Therefore, there is room for improvement. SUMMARY

[0004] The present application provides a data erasing method, device and equipment of a memory to solve the technical problem of asynchronous life of the mapping table block and the user data block.

[0005] The present application provides a data erasing method of a memory, comprising:

[0006] In response to an erasing command of a host, obtaining a first average wear degree of all mapping table blocks and a second average wear degree of all user data blocks;

[0007] According to the logical address to be erased in the erasing command, reading the corresponding mapping table of each level from the mapping table block;

[0008] According to the comparison result of the first average wear degree and the second average wear degree, determining the erasing mode;

[0009] When the erasing mode is the first mode, according to the logical address to be erased in the erasing command, determining and emptying the mapping relationship of the largest mapping table item in the mapping table of each level, and writing the updated mapping table of each level into the corresponding mapping table block;

[0010] When the erasing mode is the second mode, the corresponding physical address of the mapping relationship of the logical address to be erased in the mapping table item of each level is updated to the physical address of the preset invalid data; after a preset time period, the updated mapping table of each level is written into the corresponding mapping table block;

[0011] According to the mapping relationship of the mapping table entries in the updated mapping tables, the corresponding user data and invalid data are erased.

[0012] In an embodiment of the present application, the first average wear degree is an average of the erasing times of all physical blocks of the mapping table, and the second average wear degree is an average of the erasing times of all physical blocks storing user data; the determination of the erasing mode according to the comparison result of the first average wear degree and the second average wear degree comprises:

[0013] comparing the first average wear degree with the second average wear degree;

[0014] when the first average wear degree is less than the second average wear degree, determining the erasing mode as the first mode;

[0015] when the first average wear degree is greater than or equal to the second average wear degree, determining the erasing mode as the second mode.

[0016] In an embodiment of the present application, the determination and clearing of the mapping relationship of the largest mapping table entry in the mapping tables according to the logical address to be erased in the erasing command, and the writing of the updated mapping tables into the corresponding mapping table blocks comprise:

[0017] determining the largest mapping table entry according to the logical address to be erased in the erasing command; wherein the largest mapping table entry is located in at least one mapping table;

[0018] clearing the mapping relationship of all the largest mapping table entries, and writing the updated mapping tables into the corresponding mapping table blocks.

[0019] In an embodiment of the present application, the determination of the largest mapping table entry according to the logical address to be erased in the erasing command comprises:

[0020] performing a screening operation from the highest level mapping table, level by level downwards, to determine the largest mapping table entry according to the logical address to be erased;

[0021] wherein the screening operation for the mapping table of the current level comprises:

[0022] screening out the mapping table entries whose logical address range has an intersection with the logical address to be erased, and recording them as to-be-determined entries;

[0023] for each to-be-determined entry, determining it as the largest mapping table entry or using it as an entry item for performing the screening operation on the mapping table of the next level according to the comparison result of its logical address range and the logical address to be erased.

[0024] In an embodiment of the present application, the determining, for each to-be-determined entry, whether it is a maximum mapping table entry or an entry to the next-level mapping table based on a comparison result of its logical address range and the logical address to be erased, comprises:

[0025] determining, for each to-be-determined entry, whether its logical address range is completely within the logical address to be erased:

[0026] if yes, determining that the to-be-determined entry is a maximum mapping table entry;

[0027] otherwise, determining that the to-be-determined entry is an entry, and performing the screening operation based on a next-level mapping table pointed to by the entry.

[0028] In an embodiment of the present application, the updating, in the mapping relationship of the mapping table entries in each level mapping table, the physical address corresponding to the logical address to be erased, to a preset invalid data physical address, comprises:

[0029] querying, based on the logical address to be erased, the mapping relationship of the mapping table entries in each level mapping table to obtain a physical address of user data pointed to by the mapping relationship;

[0030] updating, in the mapping relationship, the mapping table entry pointing to the physical address of the user data, to the preset invalid data physical address.

[0031] In an embodiment of the present application, the updating, in the mapping relationship, the mapping table entry pointing to the physical address of the user data, to the preset invalid data physical address, comprises:

[0032] reading user data from a user data block according to the physical address of the user data, and synchronously writing corresponding invalid data to a free user data block;

[0033] obtaining the physical address of the invalid data, and updating, in the mapping relationship, the mapping table entry pointing to the physical address of the user data, to the preset invalid data physical address according to the physical address of the user data and the physical address of the corresponding invalid data.

[0034] The present application also provides a data erasing device of a memory, which applies the data erasing method of the memory, and the data erasing device comprises:

[0035] a data obtaining module, configured to obtain a first average wear degree of all mapping table blocks and a second average wear degree of all user data blocks in response to an erasing command of a host;

[0036] a data reading module, configured to read corresponding mapping tables of each level from the mapping table blocks according to a logical address to be erased in the erasing command.

[0037] a wear comparison module configured to determine an erase mode according to a comparison result of the first average wear degree and the second average wear degree;

[0038] a first erase module configured to, when the erase mode is a first mode, determine and clear a mapping relationship of a largest mapping table entry in each level mapping table according to a logical address to be erased in the erase command, and write the updated each level mapping table into a corresponding mapping table block;

[0039] a second erase module configured to, when the erase mode is a second mode, update a corresponding physical address in a mapping relationship of a mapping table entry in each level mapping table of the logical address to be erased into a preset invalid data physical address, and write the updated each level mapping table into a corresponding mapping table block after a preset time length;

[0040] a third erase module configured to erase corresponding user data and invalid data according to a mapping relationship of a mapping table entry in the updated each level mapping table.

[0041] The application further provides an electronic device comprising a storage device, a processor, and a computer program stored in the storage device and executable on the processor, wherein the processor implements the steps of the data erasing method of the memory when executing the computer program.

[0042] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program implements the steps of the data erasing method of the memory when executed by a processor.

[0043] The application has the following beneficial effects: by introducing a mechanism of selecting an erase mode according to a comparison of the average wear degrees of the mapping table block and the user data block, the problem of shortening the overall service life of the memory caused by uneven wear of the two is effectively solved. When the user data block is more seriously worn, the first mode is adopted, the high-level mapping table entry is cleared and updated, the write operation is guided to the relatively durable mapping table block, and the wear of the mapping table block is actively accelerated to achieve balance. When the mapping table block is more seriously worn, the second mode is adopted, the data is redirected to the invalid data area, and the mapping table is updated with a delay, so that the write frequency to the mapping table block is significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0044] The drawings incorporated in the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. It is clear that the drawings described below are only some embodiments of the present application, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0045] In the drawings:

[0046] Figure 1 A flow chart of a data erasing method of a memory according to an embodiment of the present application is provided.

[0047] Figure 2 A schematic diagram of a data erasing apparatus of a memory according to an embodiment of the present application is provided.

[0048] Figure 3 A schematic diagram of an electronic device according to an embodiment of the present application is provided.

[0049] Reference signs are as follows: 100, data acquisition module; 200, data reading module; 300, wear comparison module; 400, first erasing module; 500, second erasing module; 600, third erasing module; 700, electronic device; 710, storage device; 720, processor. DETAILED DESCRIPTION

[0050] The above embodiments of the present application are described with reference to the drawings, and other advantages and effects of the present application will be more clearly understood from the following examples. The present application can also be variously embodied or applied to other embodiments without departing from the spirit of the present application. Therefore, the following examples and features thereof can be combined if not mutually exclusive to provide additional embodiments of the present application.

[0051] It should be noted that the diagrams provided in the following examples are merely schematic and therefore show only those components of the application that are necessary in order to explain the principles of the present application, and are not intended to show embodiments to scale. Furthermore, the present application can also be embodied in a multitude of different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. As such, the following examples are provided with the understanding that they are not to be construed as limiting the principles of the present application.

[0052] In the following description, numerous specific details are discussed so as to provide a thorough understanding of embodiments of the present application. However, the embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and devices are not described in detail so as not to obscure the description of the embodiments of the present application with unnecessary detail.

[0053] The application discloses a data erasing method of a memory, which can be applied to the memory, selects two different data erasing modes by dynamically sensing and comparing wear states of mapping table blocks and user data blocks in the memory, and thus actively adjusts wear rates of the mapping table blocks and the user data blocks. By coordinating life consumption of the mapping table blocks and the user data blocks, the technical problem that the overall service life of the memory is limited due to premature wear of one side is overcome, and finally the durability of the memory is significantly prolonged.

[0054] Please refer to Figure 1 In some embodiments, the data erasing method can comprise the following steps: step S10, in response to an erasing command of a host, obtaining a first average wear degree of all mapping table blocks and a second average wear degree of all user data blocks; the first average wear degree is an average value of erasing times of all physical blocks storing mapping tables, and the second average wear degree is an average value of erasing times of all physical blocks storing user data.

[0055] In some embodiments, after receiving the erasing command of the host, a controller of the memory can obtain the first average wear degree of all mapping table blocks. Specifically, wear statistical information recording erasing times of each physical block is maintained in the memory. The mapping table blocks are physical blocks specially used for storing flash translation layer mapping tables. The controller adds up erasing times of all physical blocks currently marked for storing mapping tables respectively by querying the wear statistical information, and then divides the sum by the total number of the mapping table blocks, to obtain the first average wear degree. The first average wear degree represents an average health state and life consumption level of all the mapping table blocks.

[0056] In some embodiments, the controller of the memory can obtain the second average wear degree of all user data blocks in parallel or sequentially. The user data blocks are physical blocks specially used for storing user data issued by the host. The controller adds up erasing times of all physical blocks currently marked for storing user data respectively by querying the wear statistical information, and then divides the sum by the total number of the user data blocks, to obtain the second average wear degree. The second average wear degree represents an average health state and life consumption situation of all the user data blocks.

[0057] Please refer to Figure 1 In some embodiments, the data erasing method can further comprise the following step: step S20, reading corresponding mapping tables of each level from the mapping table blocks according to logical addresses to be erased in the erasing command.

[0058] In some embodiments, the controller performs the operation of reading the corresponding mapping tables from the mapping table blocks according to the logical addresses to be erased carried in the erase command. Specifically, the controller first parses the erase command to accurately extract the start address and length information of the logical address range that the host requires to be erased. Subsequently, the controller starts searching from the highest level mapping table according to the mapping table tree structure adopted by the storage system. The controller calculates the mapping table entries corresponding to the logical address range to be erased in the highest level mapping table, and accesses the next level mapping table stored in the specific mapping table block according to the physical addresses recorded in the mapping table entries.

[0059] In some embodiments, the controller repeats the above searching process to traverse the mapping table levels one by one until the last level mapping table is located. In this process, all the mapping tables whose logical address ranges intersect with the logical address range to be erased are read from the mapping table blocks where they are stored and temporarily loaded into the cache.

[0060] Please refer to Figure 1 In some embodiments, the data erasing method can further include the step of: step S30, determining the erasing mode according to the comparison result of the first average wear degree and the second average wear degree.

[0061] In some embodiments, when step S30 is performed, specifically, S30 can include:

[0062] comparing the first average wear degree and the second average wear degree:

[0063] when the first average wear degree is less than the second average wear degree, determining the erasing mode as the first mode;

[0064] when the first average wear degree is greater than or equal to the second average wear degree, determining the erasing mode as the second mode.

[0065] In some embodiments, when the first average wear degree is determined to be less than the second average wear degree, it indicates that the overall wear degree of the user data block has exceeded the mapping table block at the current time. In order to balance the life of the two, the controller determines the erasing mode as the first mode at this time. In the first mode, the user data block is worn more seriously, and by adopting a specific data management strategy, a part of the write operation load or wear pressure is transferred from the user data block to the relatively good mapping table block, thereby actively accelerating the wear rate of the mapping table block to catch up with the wear progress of the user data block.

[0066] In some embodiments, when the first average wear level is determined to be greater than or equal to the second average wear level, it indicates that at the current time, the overall wear level of the mapping table block has reached or even exceeded the user data block. The controller then determines that the erase mode is the second mode. In the second mode, the mapping table block that is already at a relatively high wear level can be protected by taking a more conservative or optimized strategy to reduce the write and erase operations on the mapping table block as much as possible, slow down the further growth of its wear speed, and thus prevent the entire memory from failing due to the premature exhaustion of the mapping table, ensuring the long-term reliable operation of the storage system.

[0067] Referring to Figure 1 In some embodiments, the data erasing method can further include the following step: step S40, when the erase mode is the first mode, determining and clearing the mapping relationship of the largest mapping table entry in each level of mapping table according to the logical address to be erased in the erase command, and writing the updated each level of mapping table into the corresponding mapping table block.

[0068] In some embodiments, when step S40 is performed, specifically, S40 can include: S41, determining the largest mapping table entry according to the logical address to be erased in the erase command; wherein the largest mapping table entry is located in at least one mapping table. The largest mapping table entry refers to the mapping table entry of the highest level mapping table in the mapping table whose logical address range is completely contained in the logical address range to be erased.

[0069] In some embodiments, when step S41 is performed, specifically, step S41 can include:

[0070] determining the largest mapping table entry by performing a screening operation from the highest level of mapping table to the lower level according to the logical address to be erased;

[0071] wherein the screening operation for the current level of mapping table includes:

[0072] screening out the mapping table entry whose logical address range intersects with the logical address to be erased, denoted as the to-be-determined entry;

[0073] for each to-be-determined entry, determining it as the largest mapping table entry or using it as the entry for performing the screening operation on the next level of mapping table according to the comparison result of its logical address range and the logical address to be erased.

[0074] In some embodiments, the process of determining the maximum mapping table entry can be a precise locating process of recursive or iterative search in the mapping table tree structure. The controller can start the search process from the highest level mapping table (e.g. the first level mapping table), and prepare to go deeper into the next level mapping table (e.g. the second level mapping table, the third level mapping table) to screen out all the maximum mapping table entries that need to be emptied of mapping relationship.

[0075] In some embodiments, by screening out the mapping table entries whose logical address range intersects with the logical address to be erased, and recording these mapping table entries as to-be-judged entries, the search range can be quickly narrowed down, and only those mapping table entries that may be related to the current erase operation in terms of logical address are focused on, while those mapping table entries whose logical address range has no overlap with the address range to be erased are ignored, thereby improving processing efficiency.

[0076] In some embodiments, for example, assuming that the logical address range to be erased is 580 to 3000, and the total logical address range managed by the first level mapping table at the highest level is 1 to 10000. Then, the three mapping table entries representing the logical address range 1 to 1000, 1001 to 2000 and 2001 to 3000 all have address ranges that intersect with the address range to be erased (580-3000), so they are all screened out and become the to-be-judged entries of the current level (the first level mapping table).

[0077] In some embodiments, for each to-be-judged entry, according to the comparison result of its logical address range and the logical address to be erased, it is determined as the maximum mapping table entry, or it is used as the entry item for performing the screening operation on the next level mapping table, which can include:

[0078] For each to-be-judged entry, it is judged whether its logical address range is completely within the logical address to be erased:

[0079] If yes, it is determined that the to-be-judged entry is the maximum mapping table entry;

[0080] Otherwise, it is determined that the to-be-judged entry is the entry item, and the screening operation is performed based on the next level mapping table pointed to by the entry item.

[0081] In some embodiments, for each to-be-judged entry that needs to be screened out, the controller will check each to-be-judged entry one by one to judge whether the complete logical address range managed by the to-be-judged entry is completely within the logical address range to be erased.

[0082] In some embodiments, if the logical address range of a certain to-be-determined entry is completely contained in the logical address range to be erased, the controller can immediately determine that the to-be-determined entry is the maximum mapping table entry to be found. That is, the entire logical address interval managed by the mapping table entry needs to be erased, and thus it can be directly processed as a whole without the need to continue searching for the lower-level mapping table it points to.

[0083] In some embodiments, for example, in the above example, the mapping table entries representing 1001-2000 and 2001-3000 in the first-level mapping table have their entire address ranges located in the 580-3000 range to be erased, and thus can be directly determined as the maximum mapping table entries.

[0084] In some embodiments, if the logical address range of a certain to-be-determined entry is not completely located within the logical address range to be erased, the controller determines that the to-be-determined entry is not the maximum mapping table entry of the current level, but an entry item.

[0085] In some embodiments, the role of the entry item is to provide an access path, and the controller will, based on the next-level mapping table pointed to by the entry item, perform the screening operation again to continue searching for the maximum mapping table entry at a finer address granularity.

[0086] In some embodiments, for example, the mapping table entry representing 1-1000 in the first-level mapping table has its address range (1-1000) only partially (580-1000) located in the to-be-erased range (580-3000), and the other part (1-579) is not in the range, and thus it cannot be determined as the maximum mapping table entry, but as an entry item. The controller then accesses the second-level mapping table pointed to by the entry item (assuming it manages addresses 1-100, 101-200, …, 901-1000). In this second-level mapping table, the mapping table entries representing 601-700, 701-800, 801-900, and 901-1000 have their address ranges completely located in the 580-3000 range to be erased, and thus they are determined as the maximum mapping table entries in the second-level mapping table. The mapping table entry representing 501-600 has its address range partially overlapping with the to-be-erased range (580-600 is in the range, and 501-579 is not), and thus it becomes a new entry item in the level, guiding the controller to continue accessing the third-level mapping table it points to, and finally determining, in finer address management units (e.g., 1-10, 11-20, …), the mapping table entries such as 581-590 that are completely located in the erasing range as the maximum mapping table entries.

[0087] In some embodiments, S40 can further include: S42, clearing the mapping relationship of all the maximum mapping table entries, and writing the updated mapping tables of each level into the corresponding mapping table blocks.

[0088] In some embodiments, clearing the mapping relationship of all the maximum mapping table entries means invalidating the physical block address information recorded in these specific mapping table entries, for example, marking these mapping table entries as free or invalid state bits, or setting the physical address values pointed by them to a specific value indicating invalid or unmapped.

[0089] In some embodiments, for example, once it is determined that the mapping table entries representing logical addresses 1001 to 2000 and 2001 to 3000 in the first level mapping table are maximum mapping table entries, the mapping relationship of these two entries will be immediately cleared. Similarly, in the second level mapping table, the mapping table entries representing 601 to 700, 701 to 800, 801 to 900 and 901 to 1000 are also cleared. In the third level mapping table, the mapping table entries representing logical addresses 581 to 590 and 582 to 600 (the specific range depends on the granularity division) are also cleared of their mapping relationship. For entries like 1 to 1000 in the first level mapping table, their mapping relationship is not cleared in this step because the logical address range they manage is not completely covered by the range to be erased; the clearing operation is strictly limited to those maximum mapping table entries whose entire logical address range needs to be erased.

[0090] In some embodiments, after completing the mapping relationship clearing of all the identified maximum mapping table entries, the operation of writing the updated mapping tables of each level into the corresponding mapping table blocks can be performed. Since the above clearing operation changes the content of the mapping table, these changes must be saved persistently to the non-volatile storage medium to ensure the consistency of the mapping information. The controller will write those mapping tables whose content has changed from the cache to the corresponding mapping table blocks.

[0091] In some embodiments, it is worth emphasizing that in storage media such as NAND flash, due to the lack of support for in-place overwrite, the above write operation needs to program the updated entire mapping table page or entire mapping table block to a new physical page in a previously erased, free mapping table block. Subsequently, the metadata is updated to reflect the latest storage location of these mapping tables. This process triggers the actual write operation to the mapping table block, actively increasing the write burden of the mapping table block when its average wear level is lower than that of the user data block, so that its wear level is gradually raised to approach the wear level of the user data block, and finally the wear level of the storage medium is balanced.

[0092] Please refer to Figure 1In some embodiments, the data erasing method can further comprise the following step: in step S50, when the erasing mode is the second mode, updating the corresponding physical address of the logical address to be erased in the mapping relationship of the mapping table entry in each level mapping table to the preset invalid data physical address; and after a preset time length, writing the updated each level mapping table into the corresponding mapping table block.

[0093] In some embodiments, when step S50 is performed, specifically, S50 can comprise the following step: in step S51, querying the mapping relationship of the mapping table entry in each level mapping table according to the logical address to be erased to obtain the physical address of the user data pointed by the mapping relationship.

[0094] In some embodiments, the controller needs to traverse all mapping levels related to the logical address to be erased. The controller starts from the highest level mapping table, and according to the logical address range to be erased, finds down level by level to locate all mapping table entries in the lowest level mapping table whose logical addresses fall within the range to be erased. The mapping table entries of these lowest level mapping tables directly contain the physical addresses of the user data.

[0095] In some embodiments, S50 can further comprise the following step: in step S52, updating the mapping table entry pointing to the physical address of the user data in the mapping relationship to the preset invalid data physical address.

[0096] In some embodiments, when step S52 is performed, specifically, S52 can comprise the following steps:

[0097] reading the user data from the user data block according to the physical address of the user data, and synchronously writing the corresponding invalid data to the free user data block;

[0098] obtaining the physical address of the invalid data, and updating the mapping table entry pointing to the physical address of the user data in the mapping relationship to the preset invalid data physical address according to the physical address of the user data and the physical address of the corresponding invalid data.

[0099] In some embodiments, the controller first reads the original user data content from the corresponding user data block into the cache according to the obtained physical address of the user data. Then, instead of simply discarding these data, the controller performs a specific write operation: writing a predefined invalid data pattern (such as all 0, all 1 or a specific identifier) representing the erased state to the new physical page in the free user data block. The essence of this operation is to replace and fix the data originally stored in the old physical location corresponding to the logical address to be erased to the new physical location, and the content stored in the new location is uniform invalid data.

[0100] In some embodiments, after successfully writing the invalid data into the idle user data block, the controller obtains the specific physical address of the newly written invalid data in the idle user data block. Then, the controller performs the update of the mapping relationship. By traversing each physical address of the user data to be processed, the corresponding mapping table entry in the mapping table is found, and the physical address recorded in the entry is modified from the original old physical address where the user data is stored to the newly obtained new physical address where the invalid data is stored. Through this operation, when the host reads the logical address later, the physical location where the invalid data is stored will be directly accessed according to the updated mapping relationship, so as to return to the erased state, realizing the logical erasing effect without immediately performing the time-consuming physical block erasing.

[0101] In some embodiments, S50 can further include the following step: step S53, after a preset time length, write the updated mapping tables of each level into the corresponding mapping table blocks.

[0102] In some embodiments, after completing the update of the mapping relationship, the updates are temporarily retained in the cache and are not immediately written into the non-volatile mapping table blocks. At this time, the controller can start a timer and wait for a preset time length. During the time length, the subsequent write operation on the same or adjacent logical address that can occur during the time period can be combined with the mapping table update generated by the present erasing operation. When the preset time length arrives, the controller writes the final mapping tables of each level, which have accumulated the results of multiple updates, into the mapping table blocks corresponding to them at one time. This delayed combined writing mechanism significantly reduces the actual writing times and frequency of the mapping table blocks, effectively slowing down the growth of the wear speed.

[0103] Please refer to Figure 1 In some embodiments, the data erasing method can further include the following step: step S60, according to the mapping relationship of the mapping table entries in the updated mapping tables of each level, erase the corresponding user data and invalid data.

[0104] In some embodiments, according to the mapping relationship of the mapping table entries in the updated mapping tables of each level, it can be accurately identified which user data blocks contain invalid data that can be erased. The controller systematically scans the mapping tables of each level, especially the lowest level mapping table, and analyzes the physical address pointed by each mapping table entry. The goal of the controller is to find out those physical blocks whose data content is no longer referenced by any valid logical address.

[0105] In some embodiments, in the first mode erasing operation, when the mapping relationship of the maximum mapping table entry is emptied, the data on the user data block where the user data is stored originally pointed by the entry becomes invalid data, because they can no longer be accessed through the mapping table.

[0106] In some embodiments, in the second mode erase operation, although the mapping relationship is updated to point to the new physical address storing invalid data, the data on the old physical address originally storing valid user data also becomes invalid data. By comparing the mapping table with the actual data of the user data block, a list containing all the invalid data physical addresses can be constructed.

[0107] In some embodiments, after all the physical addresses storing invalid data are accurately identified, an operation of erasing the corresponding user data and invalid data can be performed. Here, the erasing refers to a physical erase operation of the NAND flash physical block, i.e., a garbage collection operation. The controller will initiate an erase command for the user data block containing invalid data. If all the pages in a user data block store invalid data, the block can be erased as a whole. If a user data block contains both valid data and invalid data, the controller will usually first perform a data migration operation to read out the remaining valid data in the block and write it into a new free user data block, while updating the corresponding mapping relationship to ensure that the valid data will not be lost. After that, the user data block originally storing both valid and invalid data will have its internal data all become invalid, so that the physical erase operation can be safely performed. The physical erase operation resets the entire user data block to the initial, reprogrammable state, and the recovered free block is then added to the free block pool, waiting to be used to store new user data or mapping table data.

[0108] As can be seen, in the above scheme, by introducing a mechanism of selecting the erase mode according to the comparison of the average wear levels of the mapping table block and the user data block, the problem of shortening the overall life of the memory caused by the uneven wear of the two is effectively solved. When the user data block is more severely worn, the first mode is adopted, the high-level mapping table entries are emptied and updated, and the write operation is directed to the relatively durable mapping table block, actively accelerating its wear to achieve balance. When the mapping table block is more severely worn, the second mode is adopted, the data is redirected to the invalid data area, and the mapping table is updated with delay, significantly reducing the write frequency to the mapping table block. By starting from the internal wear state of the memory, the data management strategy is dynamically adjusted, and the wear balance between the mapping table block and the user data block is autonomously realized without relying on the intervention of the host, thereby prolonging the overall service life of the memory.

[0109] Please refer to Figure 2The application further discloses a data erasing device of a memory, and the data erasing method can be applied to the data erasing device. The data erasing device can include a data acquisition module 100, a data reading module 200, a wear comparison module 300, a first erasing module 400, a second erasing module 500 and a third erasing module 600.

[0110] In some embodiments, the data acquisition module 100 can be used to acquire the first average wear degree of all the mapping table blocks and the second average wear degree of all the user data blocks in response to an erasing command of a host;

[0111] In some embodiments, the data reading module 200 can be used to read corresponding mapping tables from the mapping table blocks according to logical addresses to be erased in the erasing command;

[0112] In some embodiments, the wear comparison module 300 can be used to determine an erasing mode according to a comparison result of the first average wear degree and the second average wear degree;

[0113] In some embodiments, the first erasing module 400 can be used to determine and clear mapping relationships of maximum mapping table items in the mapping tables according to the logical addresses to be erased in the erasing command when the erasing mode is a first mode, and write the updated mapping tables into corresponding mapping table blocks;

[0114] In some embodiments, the second erasing module 500 can be used to update physical addresses corresponding to the mapping relationships of the mapping table items in the mapping tables to physical addresses of preset invalid data when the erasing mode is a second mode, and write the updated mapping tables into corresponding mapping table blocks after a preset time length;

[0115] In some embodiments, the third erasing module 600 can be used to erase corresponding user data and invalid data according to the mapping relationships of the mapping table items in the updated mapping tables.

[0116] The specific limitations of the data erasing device can refer to the limitations of the data erasing method in the above, which will not be repeated here. The modules in the data erasing device can be realized by software, hardware and combinations thereof in whole or in part. The modules can be embedded in or independent of the storage device in the electronic device in hardware form, or stored in the storage device in the electronic device in software form, so as to be called and executed by the storage device to perform the operations corresponding to the modules.

[0117] Please refer to Figure 3In some embodiments, the electronic device 700 can include a storage device 710, a processor 720, and a bus, and can further include a computer program stored in the storage device 710 and executable on the processor 720, such as the program of the data erasing method of the memory.

[0118] In some embodiments, the storage device 710 includes at least one type of readable storage medium, including a flash memory, a mobile hard disk, a multimedia card, a card-type storage device (e.g., an SD or DX memory card, etc.), a magnetic storage device, a magnetic disk, an optical disk, etc. The storage device 710 can be an internal storage unit of the electronic device 700 in some embodiments, such as a mobile hard disk of the electronic device 700. The storage device 710 can also be an external storage device of the electronic device 700 in other embodiments, such as a plug-in mobile hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 700. Further, the storage device 710 can include both an internal storage unit and an external storage device of the electronic device 700. The storage device 710 can be used not only to store application software and various data installed on the electronic device 700, such as the code of the data erasing method of the memory, but also to temporarily store data that has been output or will be output.

[0119] In some embodiments, the processor 720 can be composed of an integrated circuit, such as a single packaged integrated circuit or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 720 is the control unit of the electronic device 700, which connects various components of the entire electronic device 700 through various interfaces and lines, executes or runs programs or modules stored in the storage device 710 (such as the program of the data erasing method of the memory, etc.), and calls data stored in the storage device 710 to perform various functions and process data of the electronic device 700.

[0120] In some embodiments, the processor 720 executes an operating system of the electronic device 700 and various installed application programs. The processor 720 executes the application programs to implement the steps in the above-described data erasing method of the memory.

[0121] In some embodiments, the computer program can be segmented into one or more modules, one or more modules are stored in the storage device 710 and executed by the processor 720 to complete the present application. One or more modules can be a series of computer program instruction segments capable of completing a specific function, which is used to describe the execution process of the computer program in the electronic device 700. For example, the computer program can be segmented into a data acquisition module 100, a data reading module 200, a wear comparison module 300, a first erasing module 400, a second erasing module 500, a third erasing module 600, etc.

[0122] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for erasing data from a memory, characterized in that, include: In response to the host's erase command, obtain the first average wear of all mapping table blocks and the second average wear of all user data blocks; The first average wear rate is the average number of erases of all physical blocks in the storage mapping table, and the second average wear rate is the average number of erases of all physical blocks storing user data. Based on the logical address to be erased in the erase command, the corresponding mapping tables at each level are read from the mapping table block; The erasure mode is determined based on the comparison between the first average wear degree and the second average wear degree; When the erasure mode is the first mode, the mapping relationship of the largest mapping table entry in each level of the mapping table is determined and cleared according to the logical address to be erased in the erasure command, and the updated mapping table at each level is written to the corresponding mapping table block. When the erasure mode is the second mode, the physical address corresponding to the logical address to be erased in the mapping relationship of the mapping table entries in each level of the mapping table is updated to the physical address of the preset invalid data. After a preset time period, the updated mapping tables at each level are written to the corresponding mapping table blocks; Based on the mapping relationships of the mapping entries in the updated mapping tables at all levels, the corresponding user data and invalid data are erased.

2. The data erasure method for a memory according to claim 1, characterized in that, The step of determining the erasure mode based on the comparison between the first average wear degree and the second average wear degree includes: Compare the first average wear rate with the second average wear rate: When the first average wear is less than the second average wear, the erasure mode is determined to be the first mode; When the first average wear degree is greater than or equal to the second average wear degree, the erasure mode is determined to be the second mode.

3. The data erasure method for a memory according to claim 1, characterized in that, The step of determining and clearing the mapping relationship of the largest mapping table entry in each level of the mapping table based on the logical address to be erased in the erase command, and writing the updated mapping tables at each level into the corresponding mapping table blocks includes: Based on the logical address to be erased in the erase command, determine the maximum mapping table entry; wherein the maximum mapping table entry is located in at least one mapping table; Clear the mapping relationships of all maximum mapping table entries and write the updated mapping tables at each level into the corresponding mapping table blocks.

4. The data erasure method for a memory according to claim 3, characterized in that, The step of determining the maximum mapping table entry based on the logical address to be erased in the erase command includes: Based on the logical address to be erased, starting from the highest-level mapping table, the filtering operation is performed level by level downwards to determine the largest mapping table entry; The filtering operation for the mapping table at the current level includes: Filter out mapping table entries whose logical address range intersects with the logical address to be erased, and denot them as entries to be determined; For each item to be determined, based on the comparison result between its logical address range and the logical address to be erased, it is determined as the largest mapping table item, or it is used as the entry item for performing the filtering operation on the next level of the mapping table.

5. The data erasure method for a memory according to claim 4, characterized in that, For each item to be determined, based on the comparison result between its logical address range and the logical address to be erased, it is determined as the largest mapping table item, or used as the entry item for performing the filtering operation on the next level of the mapping table, including: For each item to be determined, determine whether its logical address range is completely within the logical address to be erased: If so, then the item to be determined is determined to be the largest mapping table item; Otherwise, the item to be determined is identified as an entry item, and the filtering operation is performed based on the mapping table of the next level pointed to by the entry item.

6. The data erasure method for a memory according to claim 1, characterized in that, The step of updating the physical address corresponding to the logical address to be erased in the mapping relationship of the mapping table entries at each level of the mapping table to the preset physical address of invalid data includes: Based on the logical address to be erased, query the mapping relationship of the mapping entries in each level of the mapping table to obtain the physical address of the user data they point to; Update the mapping table entries that point to the physical address of the user data in the mapping relationship to the preset physical address of invalid data.

7. The data erasure method for a memory according to claim 6, characterized in that, The step of updating the mapping table entry that points to the physical address of the user data in the mapping relationship to the preset physical address of invalid data includes: User data is read from the user data block based on the physical address of the user data, and corresponding invalid data is synchronously written to the idle user data block; Obtain the physical address of the invalid data, and based on the physical address of the user data and the corresponding physical address of the invalid data, update the mapping table entry in the mapping relationship that points to the physical address of the user data to the preset physical address of the invalid data.

8. A data erasure device for a memory, characterized in that, The data erasure method for a memory as described in any one of claims 1 to 7, wherein the data erasure apparatus comprises: The data acquisition module is used to obtain the first average wear level of all mapping table blocks and the second average wear level of all user data blocks in response to the erase command from the host; the first average wear level is the average number of erases of all physical blocks storing the mapping table, and the second average wear level is the average number of erases of all physical blocks storing user data. The data reading module is used to read the corresponding mapping tables at all levels from the mapping table block according to the logical address to be erased in the erase command; The wear comparison module is used to determine the erasure mode based on the comparison result between the first average wear degree and the second average wear degree; The first erasure module is used to determine and clear the mapping relationship of the largest mapping table entry in each level of the mapping table according to the logical address to be erased in the erasure command when the erasure mode is the first mode, and write the updated mapping table at each level to the corresponding mapping table block. The second erasure module is used to update the physical address corresponding to the mapping table entry in the mapping table of the logical address to be erased in each level of the mapping table to the physical address of the preset invalid data when the erasure mode is the second mode; after a preset time, the updated mapping table at each level is written to the corresponding mapping table block. The third erasure module is used to erase the corresponding user data and invalid data based on the mapping relationship of the mapping entries in the updated mapping tables at all levels.

9. An electronic device comprising a storage device, a processor, and a computer program stored in the storage device and executable on the processor, characterized in that, When the processor executes a computer program, it implements the steps of the memory data erasure method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When a computer program is executed by a processor, it implements the steps of the memory data erasure method as described in any one of claims 1 to 7.

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