Control method, storage medium and full-bridge inverter

Abstract

The invention provides a control method, a storage medium, a full-bridge inverter and electronic equipment, and the control method is applied to the full-bridge inverter, and comprises the steps: controlling the full-bridge inverter based on a triangular wave mode of an inductive current; a compensation current value is obtained, wherein the compensation current value is a negative current increment caused by full-bridge inverter inductive current falling edge sampling calculation delay; and compensating a preset extreme value of the inductive current of the full-bridge inverter based on the compensation current value. According to the control method provided by the embodiment of the invention, the compensation current is obtained based on the negative current increment caused by the full-bridge inverter inductive current falling edge sampling calculation delay, the preset extreme value of the inductive current is compensated, the negative current influence caused by the inductive current falling edge sampling calculation delay is counteracted, and the inverter efficiency and the current quality are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of full-bridge inverter control, and particularly relates to a control method, a storage medium and a full-bridge inverter. BACKGROUND

[0002] The full-bridge inverter is commonly used in electronic power systems to realize voltage conversion. The full-bridge inverter includes four switching tubes (Q1, Q2, Q3 and Q4), an inverter inductor (Ls), a resonant inductor (Lf) and a resonant capacitor (Cf). The full-bridge inverter converts a direct-current power supply U DC into an alternating-current power supply U AC .

[0003] In the control of the full-bridge inverter, the soft switching (through the parasitic diode current of the switching tube) of the switching tube can be realized by using the triangular current mode (TCM) of the inductor Ls, so as to achieve the purpose of improving the efficiency of the inverter.

[0004] The core of the TCM control is to realize the zero-voltage turn-on of the switching tube by using the reverse current of the inductor. Therefore, the negative current control of the inductor current becomes the key to achieve the desired control effect. Since the inductor current is generally a high-frequency signal, the hardware sampling circuit, the filter circuit, the signal processing and operation of the controller will all produce a certain delay. Among them, the delay caused by the hardware circuit sampling and filtering is particularly serious. This has a serious negative impact on the negative current control of the inductor, thereby causing problems such as reduced efficiency of the inverter and poor quality of the output current. SUMMARY

[0005] The present application provides a control method, a storage medium and a full-bridge inverter, which aims to solve the problem of abnormal negative current control caused by delay and improve the efficiency and current quality of the inverter.

[0006] In a first aspect, the present application provides a control method applied to a full-bridge inverter, including: controlling the full-bridge inverter based on the triangular wave mode of the inductor current; obtaining a compensation current value, the compensation current value being the negative current increase caused by the sampling calculation delay of the falling edge of the inductor current of the full-bridge inverter; and compensating the preset maximum value of the inductor current of the full-bridge inverter based on the compensation current value.

[0007] In some embodiments, the compensation of the preset maximum value of the inductor current based on the compensation current value includes: compensating the preset peak value of the inductor current based on the compensation current value in the positive phase output stage and the negative phase output stage of the full-bridge inverter.

[0008] In some embodiments, the compensating the preset maximum value of the inductor current of the full-bridge inverter based on the compensation current value comprises: compensating a preset valley value of the inductor current based on the compensation current value in a positive phase output stage and a negative phase output stage of the full-bridge inverter.

[0009] In some embodiments, the compensating the preset maximum value of the inductor current of the full-bridge inverter based on the compensation current value comprises: compensating a preset peak value of the inductor current based on the compensation current in the positive phase output stage of the full-bridge inverter; and compensating a preset valley value of the inductor current based on the compensation current in the negative phase output stage of the full-bridge inverter.

[0010] In some embodiments, the compensating the preset maximum value of the inductor current of the full-bridge inverter based on the compensation current value comprises: compensating a preset valley value of the inductor current based on the compensation current in the positive phase output stage of the full-bridge inverter; and compensating a preset peak value of the inductor current based on the compensation current in the negative phase output stage of the full-bridge inverter.

[0011] In some embodiments, the obtaining the compensation current value comprises: obtaining a negative current increase caused by a falling edge sampling delay of the inductor current of the full-bridge inverter based on a volt-second balance principle.

[0012] In some embodiments, the obtaining the negative current change value comprises:

[0013]

[0014] wherein, ΔI is the negative current change value, V DC is an input voltage value of the full-bridge inverter, V AC is an output voltage value of the full-bridge inverter, L s is an inductance value of the full-bridge inverter, and Δt is a delay time of a falling edge sampling delay of the inductor current of the full-bridge inverter.

[0015] In a second aspect, the present application provides a storage medium, the storage medium stores a plurality of instructions, the instructions are adapted to be loaded by a processor to execute the control method provided in the first aspect.

[0016] In a third aspect, the present application provides a full-bridge inverter, comprising: a bridge arm circuit, and a control circuit connected to the bridge arm circuit; the control circuit is used to control the bridge arm circuit to execute the control method provided in the first aspect.

[0017] In some embodiments, the bridge arm circuit comprises: a direct current power supply; a first switch tube, a control end of which is connected to the control circuit, and a first end of which is connected to a positive pole of the direct current power supply; a second switch tube, a control end of which is connected to the control circuit, and a first end of which is connected to a second end of the first switch tube, and a second end of which is connected to a negative pole of the direct current power supply; a third switch tube, a control end of which is connected to the control circuit, and a first end of which is connected to the positive pole of the direct current power supply; a fourth switch tube, a control end of which is connected to the control circuit, and a first end of which is connected to a second end of the third switch tube, and a second end of which is connected to the negative pole of the direct current power supply; an inverter inductor, a first end of which is connected to the second end of the first switch tube; a resonant inductor, a first end of which is connected to a second end of the inverter inductor; a resonant capacitor, a first end of which is connected to the second end of the inverter inductor, and a second end of which is connected to the second end of the third switch tube; and the second end of the resonant inductor and the second end of the resonant capacitor serving as output ends of the bridge arm circuit.

[0018] The control method provided in the embodiment is based on a compensation current obtained by sampling and calculating a negative current increment caused by delay of a falling edge of an inductor current of a full-bridge inverter, and compensates for a preset maximum value of the inductor current, so as to offset the negative current influence caused by delay of the sampling and calculation of the falling edge of the inductor current, and improve the efficiency and current quality of the inverter. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0020] Figure 1 A structure schematic diagram of a full-bridge inverter in the embodiment of the present application is shown;

[0021] Figure 2 A principle example diagram of generating a negative current based on an inductor current in the embodiment of the present application is shown;

[0022] Figure 3 A schematic diagram of each current of an inverter in an inductor current triangular wave mode under an ideal condition in the embodiment of the present application is shown;

[0023] Figure 4 A schematic diagram of each current of an inverter in an inductor current triangular wave mode under an actual condition in the embodiment of the present application is shown;

[0024] Figure 5 A flow schematic diagram corresponding to each step of the control method in the embodiment of the present application is shown;

[0025] Figure 6This paper shows a schematic diagram of the current of each inverter after valley compensation in an embodiment of this application.

[0026] Figure 7 The corresponding embodiments of this application are shown. Figure 6 A schematic diagram of a method for compensating for grid current;

[0027] Figure 8 This paper shows a schematic diagram of the currents of the inverter after peak compensation in an embodiment of this application.

[0028] Figure 9 The corresponding embodiments of this application are shown. Figure 8 A schematic diagram of a method for compensating for grid current;

[0029] Figure 10 A schematic diagram of the structure of the full-bridge inverter in an embodiment of this application is shown. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the description of this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0032] Full-bridge inverters are commonly used in electronic power systems to achieve voltage conversion. For example... Figure 1 As shown, the full-bridge inverter includes four switching transistors (Q1, Q2, Q3, and Q4), an inverter inductor (Ls), a resonant inductor (Lf), and a resonant capacitor (Cf). The full-bridge inverter converts the DC power supply U through the switching of the four transistors. DC Convert to AC power U AC .

[0033] In full-bridge inverter control, the soft switching of the switch tube (through the corresponding parasitic diode conduction current of the switch tube) can be realized by using the triangular current mode (TCM) of the inductor Ls, so as to improve the efficiency of the inverter.

[0034] The core of the TCM control is to realize the zero-voltage turn-on of the switch tube by using the reverse current of the inductor. Therefore, the negative current control of the inductor current becomes the key to realize the desired control effect. Since the inductor current is generally a high-frequency signal, the hardware sampling circuit, the filter circuit, the signal processing and operation of the controller will all produce a certain delay; among them, the delay caused by the hardware circuit sampling and filtering is particularly serious. This has a serious negative impact on the negative current control of the inductor, thereby causing problems such as reduced efficiency of the inverter and poor output current quality.

[0035] Reference Figure 1 and Figure 2 , Figure 2 is a schematic diagram of the principle of generating negative current based on the triangular wave mode of the inductor current in the embodiment.

[0036] Among them, Ugs1 represents the gate-source voltage of the switch tube Q1, and Uds1 represents the source-drain voltage of the switch tube Q1; when Ugs1 is high, it represents that the gate of the switch tube Q1 is at a high level, and the switch tube Q1 is turned on; when Ugs1 is low, it represents that the gate of the switch tube Q1 is at a low level, and the switch tube Q1 is turned off. Similarly, Ugs2 represents the gate-source voltage of the switch tube Q2, and Uds2 represents the source-drain voltage of the switch tube Q2; Ugs3 represents the gate-source voltage of the switch tube Q3, and Uds3 represents the source-drain voltage of the switch tube Q3; Ugs4 represents the gate-source voltage of the switch tube Q4, and Uds4 represents the source-drain voltage of the switch tube Q4.

[0037] When Ugs2 and Ugs3 are high, the switch tube Q2 and the switch tube Q3 are turned on, and the direct current power supply U DC The current provided by the power supply positive electrode flows through the switch tube Q3, the resonant capacitor Cf, the inductor Ls of the inverter, and the switch tube Q2 back to the power supply negative electrode, and the current of the inductor Ls decreases (increases) in the positive direction; before Ugs1 and Ugs4 are high at time T, the switch tube Q1 and the switch tube Q4 have been turned on based on the parasitic diode based on the negative current, realizing the zero-voltage turn-on of the switch tube Q1 and the switch tube Q4.

[0038] When Ugs1 and Ugs4 are high, the switch tube Q1 and the switch tube Q4 are turned on, and the direct current power supply U DCThe provided current flows out through the positive pole of the power supply, passes through the switch tube Q1, the inverter inductor Ls, the resonance capacitor Cf, and the switch tube Q4, and flows back to the negative pole of the power supply, and the current of the inverter inductor Ls is positively increased (negatively decreased); before Ugs2 and Ugs3 are high level, the switch tube Q2 and the switch tube Q3 have been turned on based on the parasitic diode based on the positive current, and zero voltage turn-on of the switch tube Q2 and the switch tube Q3 is realized.

[0039] Based on the control of the switch tube Q1, the switch tube Q2, the switch tube Q3, and the switch tube Q4, the inductor current iLs repeatedly rises and falls to form a triangular wave. Referring to Figure 3 , Figure 3 The schematic diagram of each current of the inverter in the ideal case of the inductor current triangular wave mode.

[0040] Among them, the deep blue line ipeak represents the peak current curve of the inverter. The light blue line irest represents the valley current curve of the inverter; the black line iLs is the inductor current, which is in a triangular wave mode; and the red line igrid represents the grid current output by the inverter.

[0041] It should be noted that in the description of the embodiment, the black line is the actual current value of the inductor current iLs, the deep blue line ipeak is the envelope curve of the peak value of the inductor current iLs, and the light blue line irest is the envelope curve of the valley value of the inductor current iLs; in addition, the "peak value" described in the embodiment refers to the maximum value of the inductor current iLs in the positive output (positive half cycle) and the minimum value of the inductor current iLs in the negative output (negative half cycle). The "valley value" described in the embodiment refers to the minimum value of the inductor current iLs in the positive output (positive half cycle) and the maximum value of the inductor current iLs in the negative output (negative half cycle).

[0042] Specifically, by controlling the rising and falling of the inductor current iLs through the turn-on control of the switch tube Q1, the switch tube Q2, the switch tube Q3, and the switch tube Q4, the inductor current is reversed in the peak curve and the valley interval, and at this time the output current of the inverter is a sinusoidal current.

[0043] For ipeak, in some embodiments, ipeak=A*sin(ωt+ψ), where A is the result output by the bus voltage loop; and sin(ωt+ψ) is the phase angle of the grid side sinusoidal signal sin(ωt) combined with the adjustment angle ψ.

[0044] For irest, irest is a fixed value, and the value is a relatively appropriate value selected by using a hardware parameter and an engineering debugging result; in the positive output stage of the inverter, the valley current is given as -irest; and in the negative output stage of the inverter, the valley current is given as irest.

[0045] It should be noted that the phase angle of the grid-side sinusoidal signal can be obtained based on a phase-locked loop. The phase angle of the sinusoidal signal is also used to distinguish the forward output stage and the negative output stage of the inverter. Specifically, when the phase angle of the sinusoidal signal is 0°-180°, the inverter is in the forward output stage; and when the phase angle of the sinusoidal signal is 180°-360°, the inverter is in the negative output stage.

[0046] In one example, the ipeak is given as ipeak = 2 * A * sin (ωt + ψ) ± 2 * |irest|. Taking the bipolar modulation of the inverter as an example, the turn-on time and the turn-off time of the switching tube are calculated as follows:

[0047] Turn-on time t on :

[0048] Turn-off time t off :

[0049] where Ls is the inductance value of the inverter inductance, V DC is the voltage value of the input DC power source U DC of the inverter, and Vgrid is the voltage value of the output AC power source U AC of the inverter, i.e., the grid voltage.

[0050] Since there are a series of delay links such as sampling delay and filtering in the actual circuit, these links can be approximately equivalent to a low-pass filter. on The time t off corresponds to the time when the inductor current rises, and the time t on corresponds to the time when the inductor current falls. It can be seen from the calculation formulas of t off and t off that, in one switching period, the rising slope of the inductor current is much smaller than the falling slope. In combination with the characteristics of the low-pass filter, it can be known that the phase delay when the inductor current rises is much smaller than the phase delay when the inductor current falls, and this phenomenon is more obvious at the peak value of the grid voltage. After the triangular wave passes through the low-pass filter, the phase delay of the falling edge is more than that of the rising edge due to the low rising slope and the high falling slope.

[0051] Therefore, the sampling calculation delay of the falling edge of the inductor current near the peak value is significantly exacerbated. Since the above-mentioned strategy is a TCM mode based on peak current comparison, the switching state will be changed when the inductor current reaches the valley current given value. Since the valley current given value is constant, the phase delay means that the time when the inductor current reaches the valley current given value is prolonged, i.e., t on becomes large. According to the calculation formula of t offWith the grid voltage and bus voltage remaining constant, the change in inductor current will increase, meaning the negative current will increase. If this negative current is not compensated for, the final output sinusoidal current will be insufficient at its peak. (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the various currents in the inverter under actual conditions in the inductor current triangular wave mode.

[0052] refer to Figure 4 The negative current increases in the negative direction and reaches its maximum at the valley. This not only affects the quality of the grid current and causes current waveform distortion, but also greatly affects the efficiency of the inverter due to the increase in negative current.

[0053] This application provides a control method applied to a full-bridge inverter, comprising: controlling the full-bridge inverter based on a triangular wave mode of inductor current; obtaining a compensation current value, wherein the compensation current value is the amount of negative current increase caused by the sampling and calculation delay of the falling edge of the inductor current of the full-bridge inverter; and compensating the preset maximum or minimum value of the inductor current of the full-bridge inverter based on the compensation current value.

[0054] The control method provided in this embodiment compensates for the preset maximum value of the inductor current by obtaining the compensation current based on the negative current increment caused by the sampling and calculation delay of the inductor current falling edge of the full-bridge inverter. This offsets the negative current effect caused by the sampling and calculation delay of the inductor current falling edge, thereby improving inverter efficiency and current quality.

[0055] The control method provided in this embodiment will be described in detail below with reference to the accompanying drawings. Figure 5 , Figure 5 This is a flowchart illustrating the steps of the control method provided in this embodiment. The control method is applied to a full-bridge inverter and includes steps 101 to 103.

[0056] The structure of the full-bridge inverter can be referenced. Figure 1 A full-bridge inverter includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, an inverter inductor Ls, a resonant inductor Lf, and a resonant capacitor Cf. The full-bridge inverter is used to convert the input DC power U... DC Convert to AC power U AC Output.

[0057] It should be noted that the control object of the control method mentioned in this embodiment is the first switch Q1, the second switch Q2, the third switch Q3, or the fourth switch Q4 in the full-bridge inverter; by controlling the on and off of the first switch Q1, the second switch Q2, the third switch Q3, or the fourth switch Q4, the current waveform required by this embodiment can be achieved.

[0058] Step 101, controlling the full-bridge inverter based on the triangular wave mode of the inductance current.

[0059] It should be noted that the embodiment can control the full-bridge inverter based on the single-polarity modulation triangular wave mode or the bipolar modulation triangular wave mode.

[0060] Reference Figure 1 For the full-bridge inverter, two bridge arms (a first bridge arm and a second bridge arm) are included, the first bridge arm includes a first switch tube Q1 and a second switch tube Q2, and the second bridge arm includes a third switch tube Q3 and a fourth switch tube Q4. Wherein, the control object of the single-polarity modulation is one of the first bridge arm and the second bridge arm, and the other one is based on the power frequency operation; the control object of the bipolar modulation is the first bridge arm and the second bridge arm.

[0061] The switch tube is divided into an excitation tube and a freewheeling tube according to the function. For example, in the forward output stage, when the excitation tube is turned on, the freewheeling tube is turned off, and at this time the inductance current rises. When it is detected that the inductance current reaches the expected peak value, the controller turns off the excitation tube and turns on the freewheeling tube. After the freewheeling tube is turned on, the inductance current will decrease, and when the inductance current decreases to the expected valley value, the controller turns off the freewheeling tube and turns on the excitation tube.

[0062] Step 102, obtaining a compensation current value.

[0063] Specifically, the compensation current value is obtained, and the compensation current value is the negative current increase caused by the delay of the inductance current falling edge sampling calculation of the full-bridge inverter.

[0064] Step 103, compensating the preset maximum value of the inductance current of the full-bridge inverter based on the compensation current value.

[0065] Specifically, based on the foregoing, the phase delay when the inductance current rises is much smaller than the phase delay when the inductance current falls, especially at the peak value of the grid voltage. After the triangular wave passes through the low-pass filter, because the rising slope is low and the falling slope is high, the phase delay of the falling edge is more than that of the rising edge. Therefore, the delay of the inductance current falling edge sampling calculation of the inductance current near the peak value is significantly aggravated, resulting in insufficient sinusoidal current at the peak value of the final output.

[0066] The control method provided by the embodiment compensates the preset maximum value of the inductance current based on the compensation current obtained by the negative current increase caused by the delay of the inductance current falling edge sampling calculation of the full-bridge inverter, offsets the negative current influence caused by the delay of the inductance current falling edge sampling calculation, and improves the inverter efficiency and current quality.

[0067] For step 102, in some embodiments, the method for obtaining the compensation current value comprises: obtaining a negative current increase amount caused by a full-bridge inverter inductor current falling edge sampling delay based on the volt-second balance principle.

[0068] At this time, step 103 compensates the negative current increase amount caused by the full-bridge inverter inductor current falling edge sampling delay to the preset maximum value of the inductor current, thereby offsetting the influence of the negative current change, so that the positive limit of the alternating current output by the inverter is maintained.

[0069] In some embodiments, the method for obtaining the negative current increase amount comprises:

[0070]

[0071] Where ΔI is the negative current increase amount, V DC is the voltage value of the DC power supply U DC input to the full-bridge inverter, V AC is the voltage value of the alternating current power supply U AC output by the full-bridge inverter, L s is the inductance value of the inverter inductor in the full-bridge inverter, and Δt is the delay time of the full-bridge inverter inductor current falling edge sampling delay.

[0072] In some embodiments, V DC and V AC are instantaneous values obtained by real-time sampling of the full-bridge inverter, and the delay time is obtained by finally adding the hardware delay and the DSP software delay time. The hardware delay time includes sampling chip delay, filter delay, etc., and the software delay time includes analog-to-digital conversion delay and calculation delay.

[0073] For step 103, in some embodiments, the preset maximum value of the inductor current of the full-bridge inverter is compensated based on the compensation current, comprising: during the positive phase output stage and the negative phase output stage of the full-bridge inverter, compensating the preset valley value of the inductor current based on the compensation current.

[0074] Referring to Figure 6 and Figure 7 , Figure 6 is an i-t diagram of the inverter current after valley compensation provided by the present embodiment, Figure 7 is a compensation method diagram of the grid current corresponding to Figure 6 provided by the present embodiment.

[0075] Specifically, referring to Figure 6 , during the positive phase output stage and the negative phase output stage, the preset valley value of the inductor current is compensated based on the compensation current.

[0076] Referring to Figure 7The positive phase output stage and the negative phase output stage of the full-bridge inverter are obtained based on the grid phase angle. When the grid phase angle represents a 0°-180° phase, the full-bridge inverter is in the positive phase output stage; when the grid phase angle represents a 180°-360° phase, the full-bridge inverter is in the negative phase output stage.

[0077] In the positive phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, and the DC amplitude is the current amplitude A generated by the bus voltage loop. In an example, the preset peak value is 2*A*sin(wt)+2*|irest|; and the preset valley value is -irest, where irest is a fixed value, and the value is a relatively appropriate value selected by using a hardware parameter and an engineering debugging result. In the negative phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, and the DC amplitude is the current amplitude A generated by the bus voltage loop. In an example, the preset peak value is 2*A*sin(wt)-2*|irest|; and the preset valley value is irest.

[0078] Reference is made to Figure 6 and Figure 7 When the full-bridge inverter is in the positive phase output stage, the preset valley value is compensated based on the compensation current, and the size of the compensation current is the negative current increase ΔI. After compensation, the peak current value of the inductor current is 2*A*sin(wt)+2*|irest|, and the valley current value of the inductor current is -irest+ΔI. By compensating the preset valley value of the inductor current, the negative phase output current of the inverter is reduced, so that the output current of the inverter is increased. Reference is made to Figure 4 and Figure 6 In the positive phase output stage of the full-bridge inverter, after the output current of the inverter is increased, the output waveform of the inverter output current is a sinusoidal current.

[0079] Similarly, when the full-bridge inverter is in the negative phase output stage, the preset valley value is compensated based on the compensation current, and the size of the compensation current is the negative current increase ΔI. After compensation, the peak current value of the inductor current is 2*A*sin(wt)-2*|irest|, and the valley current value of the inductor current is irest-ΔI. By compensating the preset valley value of the inductor current, the positive phase output current of the inverter is reduced, so that the output current of the inverter is decreased. Reference is made to Figure 4 and Figure 6 In the negative phase output stage of the full-bridge inverter, after the output current of the inverter is decreased, the output waveform is approximately a sinusoidal current.

[0080] For step 103, in some embodiments, the preset maximum value of the inductor current of the full-bridge inverter is compensated based on the compensation current, including: in the positive phase output stage and the negative phase output stage of the full-bridge inverter, the preset peak value of the inductor current is compensated based on the compensation current.

[0081] Reference is made to Figure 8 and Figure 9 , Figure 8 the i-t diagram of each current of the inverter after peak compensation provided by the embodiment, Figure 9 the compensation method diagram of the grid current corresponding to Figure 8 provided by the embodiment.

[0082] Specifically, reference is made to Figure 8 , in the positive phase output stage and the negative phase output stage, the preset peak value of the inductor current is compensated based on the compensation current.

[0083] Reference is made to Figure 9 , the positive phase output stage and the negative phase output stage of the full-bridge inverter are obtained based on the grid phase angle. When the grid phase angle represents 0°-180° phase, the full-bridge inverter is in the positive phase output stage, and when the grid phase angle represents 180°-360° phase, the full-bridge inverter is in the negative phase output stage.

[0084] In the positive phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, and the DC amplitude is the current amplitude A generated by the bus voltage loop. In one example, the preset peak value is 2*A*sin(wt)+2*|irest|; the preset valley value is -irest, and irest is a fixed value, and the value is a relatively appropriate value selected by using hardware parameters and engineering debugging results. In the negative phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, and the DC amplitude is the current amplitude A generated by the bus voltage loop. In one example, the preset peak value is 2*A*sin(wt)-2*|irest|; the preset valley value is irest.

[0085] Reference is made to Figure 8 and Figure 9 , when the full-bridge inverter is in the positive phase output stage, the preset peak value is compensated based on the compensation current, and the size of the compensation current is the negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)+2*|irest|+ΔI, and the valley current value of the inductor current is -irest. By compensating the preset peak value of the inductor current, the positive phase output current of the inverter is increased, so that the output current of the inverter is increased; reference is made to Figure 4 and Figure 8 , in the positive phase output stage of the full-bridge inverter, after the output current of the inverter is increased, the output waveform of the inverter output current is a sinusoidal current.

[0086] Similarly, when the full-bridge inverter is in the negative phase output stage, the preset peak value is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)-2*|irest|-ΔI, and the valley current value of the inductor current is irest. By compensating the preset peak value of the inductor current, the output current of the inverter is increased, so that the output current of the inverter is reduced; with reference to Figure 4 and Figure 8 In the negative phase output stage of the full-bridge inverter, after the output current of the inverter is reduced, the output waveform of the output current of the inverter is a sinusoidal current.

[0087] For step 103, in some embodiments, the preset maximum value of the inductor current of the full-bridge inverter is compensated based on the compensation current value, including: in the positive phase output stage of the full-bridge inverter, the preset peak value of the inductor current is compensated based on the compensation current; in the negative phase output stage of the full-bridge inverter, the preset valley value of the inductor current is compensated based on the compensation current.

[0088] Specifically, with reference to Figure 6 and Figure 8 In the positive phase output stage and the negative phase output stage of the full-bridge inverter, the grid phase angle is obtained. When the grid phase angle represents a 0°-180° phase, the full-bridge inverter is in the positive phase output stage, and when the grid phase angle represents a 180°-360° phase, the full-bridge inverter is in the negative phase output stage.

[0089] In the positive phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, the DC amplitude is the current amplitude A generated by the bus voltage loop, and in one example, the preset peak value is 2*A*sin(wt)+2*|irest|; the preset valley value is -irest, irest is a fixed value, and the value is a relatively appropriate value selected by hardware parameters and engineering debugging results. In the negative phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, the DC amplitude is the current amplitude A generated by the bus voltage loop, and in one example, the preset peak value is 2*A*sin(wt)-2*|irest|; the preset valley value is irest.

[0090] With reference to Figure 8 and Figure 9 When the full-bridge inverter is in the positive phase output stage, the preset peak value is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)+2*|irest|+ΔI, and the valley current value of the inductor current is -irest. By compensating the preset peak value of the inductor current, the output current of the inverter is increased, so that the output current of the inverter is increased; with reference to Figure 4 and Figure 8In the positive phase output stage of the full-bridge inverter, after the output current of the inverter rises, the output waveform of the output current of the inverter is a sinusoidal current.

[0091] With reference to Figure 6 and Figure 7 When the full-bridge inverter is in the negative phase output stage, the preset valley value of the inductor current is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)-2*|irest|, and the valley current value of the inductor current is irest-ΔI; by compensating the preset valley value of the inductor current, the positive phase output current of the inverter is reduced, so that the output current of the inverter is reduced, with reference to Figure 4 and Figure 6 In the negative phase output stage of the full-bridge inverter, after the output current of the inverter drops, the output waveform is approximately a sinusoidal current.

[0092] For step 103, in some embodiments, the preset maximum value of the inductor current of the full-bridge inverter is compensated based on the compensation current value, including: in the positive phase output stage of the full-bridge inverter, compensating the preset valley value of the inductor current based on the compensation current; in the negative phase output stage of the full-bridge inverter, compensating the preset peak value of the inductor current based on the compensation current.

[0093] Specifically, with reference to Figure 6 and Figure 8 In the positive phase output stage and the negative phase output stage of the full-bridge inverter, the grid phase angle is obtained. When the grid phase angle represents a 0°-180° phase, the full-bridge inverter is in the positive phase output stage, and when the grid phase angle represents a 180°-360° phase, the full-bridge inverter is in the negative phase output stage.

[0094] In the positive phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, the DC amplitude is the current amplitude A generated by the bus voltage loop, and in one example, the preset peak value is 2*A*sin(wt)+2*|irest|; the preset valley value is -irest, irest is a fixed value, and the value is a relatively appropriate value selected by hardware parameters and engineering debugging results. In the negative phase output stage, the preset peak value is obtained based on the DC amplitude and the grid phase angle, the DC amplitude is the current amplitude A generated by the bus voltage loop, and in one example, the preset peak value is 2*A*sin(wt)-2*|irest|; the preset valley value is irest.

[0095] With reference to Figure 6 and Figure 7When the full-bridge inverter is in the positive phase output stage, the preset valley value is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)+2*|irest|, and the valley current value of the inductor current is -irest+ΔI; by compensating the preset valley value of the inductor current, the output current of the inverter is reduced, so that the output current of the inverter is increased; reference Figure 4 and Figure 6 When the full-bridge inverter is in the positive phase output stage, the preset valley value is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)+2*|irest|, and the valley current value of the inductor current is -irest+ΔI; by compensating the preset valley value of the inductor current, the output current of the inverter is reduced, so that the output current of the inverter is increased; reference

[0096] reference Figure 8 and Figure 9 When the full-bridge inverter is in the negative phase output stage, the preset peak value is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)-2*|irest|-ΔI, and the valley current value of the inductor current is irest. By compensating the preset peak value of the inductor current, the negative phase output current of the inverter is increased, so that the output current of the inverter is reduced; reference Figure 4 and Figure 8 When the full-bridge inverter is in the negative phase output stage, the preset peak value is compensated based on the compensation current, and the size of the compensation current is a negative current increase ΔI; after compensation, the peak current value of the inductor current is 2*A*sin(wt)-2*|irest|-ΔI, and the valley current value of the inductor current is irest. By compensating the preset peak value of the inductor current, the negative phase output current of the inverter is increased, so that the output current of the inverter is reduced; reference

[0097] The control method provided by the embodiment compensates the preset maximum value of the inductor current based on the compensation current obtained by sampling and calculating the negative current increase caused by the delay of the falling edge of the inductor current, offsets the negative current influence caused by the delay of the sampling and calculation of the falling edge of the inductor current, and improves the efficiency and current quality of the inverter.

[0098] The embodiment of the application also provides a storage medium, which can include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc. A plurality of instructions are stored on the storage medium, and the instructions are suitable for being loaded by a processor to execute the control method provided by the above embodiment.

[0099] The embodiment of the application also provides a full-bridge inverter, which includes a bridge arm circuit and a control circuit, and aims to solve the problem of abnormal negative current control caused by delay and improve the efficiency and current quality of the inverter.

[0100] reference Figure 10 , Figure 10A structure diagram of the full-bridge inverter is provided in the embodiment, and the full-bridge inverter 200 includes a bridge arm circuit 201 and a control circuit 202, the bridge arm circuit 201 is connected to the control circuit 202, and the control circuit 202 is used to control the bridge arm circuit 201 to perform the control method provided in the above embodiment.

[0101] In some embodiments, with reference to Figure 1 , the bridge arm circuit 201 includes: a direct current power supply U DC ; a first switch tube Q1, a control end of which is connected to the control circuit 202, and a first end of which is connected to a positive electrode of the direct current power supply U DC ; a second switch tube Q2, a control end of which is connected to the control circuit 202, a first end of which is connected to a second end of the first switch tube Q1, and a second end of which is connected to a negative electrode of the direct current power supply U DC ; a third switch tube Q3, a control end of which is connected to the control circuit 202, a first end of which is connected to a positive electrode of the direct current power supply U DC ; a fourth switch tube Q4, a control end of which is connected to the control circuit 202, a first end of which is connected to a second end of the third switch tube Q3, and a second end of which is connected to a negative electrode of the direct current power supply U DC ; an inverter inductor Ls, a first end of which is connected to a second end of the first switch tube Q1; a resonant inductor Lf, a first end of which is connected to a second end of the inverter inductor Ls; a resonant capacitor Cf, a first end of which is connected to a second end of the inverter inductor Ls, and a second end of which is connected to a second end of the third switch tube Q3; and a second end of the resonant inductor Lf and a second end of the resonant capacitor Cf are used as output ends of the bridge arm circuit 201 to output an alternating current power supply U AC .

[0102] The embodiment of the application further provides an electronic device including the storage medium provided in the above embodiment or the full-bridge inverter provided in the above embodiment.

[0103] In some embodiments, the full-bridge inverter can be used in a solar power generation system, a household and office self-provided power supply, a vehicle-mounted power supply system, an uninterruptible power supply (UPS) system or a mobile communication station.

[0104] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the detailed description of other embodiments above, which will not be described herein again.

[0105] Having now described the basic concept of the application, and having shown and described several embodiments of the same, modifications to, and variations of the described embodiments are possible without departing from the spirit of the application, and, therefore, it is intended that the application be limited only by the scope of the claims presented below.

[0106] Also, the use of "a" or "an" to describe the applications is intended to be a translation of "at least one" and thus includes the possibility of more than one unless otherwise indicated. Additionally, the use of "one or more of' is intended to be a translation of "at least one" and thus includes the possibility of more than one unless otherwise indicated. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof, are used in either the detailed description and / or the claims, such terms are intended to be broad and encompass the terms "comprising", "comprises", "containing", "contains", "including", "includes", "having", "has", "with", and variants thereof. Also, as used in the description of the application and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component" or "the component" can include a plurality of such components unless the context clearly dictates otherwise.

[0107] The above provides a kind of control method, storage medium and full-bridge inverter provided by the embodiment of the application, the principle and implementation mode of the present application are described in this paper, the above embodiment is only for helping to understand the method of the present application and its core idea;Meanwhile, for the skilled in the art, according to the idea of the present application, there will be changes in specific implementation mode and application range, as described above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A control method applied to a full-bridge inverter, characterized in that, include: Triangular wave mode control of inductor current for full-bridge inverter; Obtain the compensation current value, which is the amount of negative current increase caused by the sampling and calculation delay of the falling edge of the inductor current of the full-bridge inverter. The preset maximum value of the inductor current of the full-bridge inverter is compensated based on the compensation current value.

2. The control method according to claim 1, characterized in that, The preset maximum value of compensating the inductor current of the full-bridge inverter based on the compensation current value includes: During the positive and negative output phases of the full-bridge inverter, the preset peak value of the inductor current is compensated based on the compensation current value.

3. The control method according to claim 1, characterized in that, The preset maximum value of compensating the inductor current of the full-bridge inverter based on the compensation current value includes: During the positive and negative output phases of the full-bridge inverter, the preset valley value of the inductor current is compensated based on the compensation current value.

4. The control method according to claim 1, characterized in that, The preset maximum value of compensating the inductor current of the full-bridge inverter based on the compensation current value includes: During the positive output phase of the full-bridge inverter, the preset peak value of the inductor current is compensated based on the compensation current; During the negative phase output phase of the full-bridge inverter, the inductor current is compensated for a preset valley value based on the compensation current.

5. The control method according to claim 1, characterized in that, The preset maximum value of compensating the inductor current of the full-bridge inverter based on the compensation current value includes: During the positive output phase of the full-bridge inverter, the inductor current is compensated for a preset valley value based on the compensation current; During the negative phase output phase of the full-bridge inverter, the preset peak value of the inductor current is compensated based on the compensation current.

6. The control method according to any one of claims 1 to 5, characterized in that, The acquisition of the compensation current value includes: based on the volt-second balance principle, acquiring the amount of negative current increase caused by the sampling delay of the falling edge of the inductor current of the full-bridge inverter.

7. The control method according to claim 6, characterized in that, Obtaining the increase in negative current includes: Where ΔI is the increase in negative current, V DC V is the input voltage value of the full-bridge inverter. AC L represents the output voltage value of the full-bridge inverter. s Δt is the inductance value of the full-bridge inverter, and Δt is the sampling delay time of the falling edge of the inductor current of the full-bridge inverter.

8. A storage medium, characterized in that, The storage medium stores a plurality of instructions adapted for loading by a processor to execute the control method according to any one of claims 1 to 7.

9. A full-bridge inverter, characterized in that, include: Bridge arm circuit, and control circuit connected to the bridge arm circuit; The control circuit is used to control the bridge arm circuit to perform the control method described in any one of 1 to 7.

10. The full-bridge inverter according to claim 9, characterized in that, The bridge arm circuit includes: DC power supply; The first switching transistor has its control terminal connected to the control circuit and its first terminal connected to the positive terminal of the DC power supply. The second switching transistor has its control terminal connected to the control circuit, its first terminal connected to the second terminal of the first switching transistor, and its second terminal connected to the negative terminal of the DC power supply. The third switching transistor has its control terminal connected to the control circuit and its first terminal connected to the positive terminal of the DC power supply. The fourth switching transistor has its control terminal connected to the control circuit, its first terminal connected to the second terminal of the third switching transistor, and its second terminal connected to the negative terminal of the DC power supply. The inverter inductor has its first terminal connected to the second terminal of the first switching transistor. The first end of the output inductor is connected to the second end of the inverter inductor. The output capacitor has its first end connected to the second end of the inverter inductor, and its second end connected to the second end of the third switching transistor. The second terminal of the output inductor and the second terminal of the output capacitor serve as the output terminals of the bridge arm circuit.

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