Analog circuit implementation method and device based on unified probability graph calculation architecture, equipment and medium

Abstract

The invention discloses an analog circuit implementation method and device based on a unified probability graph computing architecture, equipment and a medium, and the method comprises the steps: building a unified signal model based on the common characteristics of a baseband signal processing task; representing the unified signal model as a unified probability graph model; obtaining an initialization probability of a variable node state value in the unified probability graph model; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device comprises an initial input array, an iterative calculation array and a result output array, and node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model; a driving vector is obtained based on the initialization probability to serve as input of the initial input array, the iterative calculation array is used for completing iterative calculation of mutual message passing of variable nodes and check nodes in the unified probability graph model, and when an iteration stop condition is met, the result output array outputs a processing result to complete a baseband signal processing task.

Description

TECHNICAL FIELD

[0001] The application relates to a simulation circuit implementation method, device and equipment based on a unified probabilistic graph calculation architecture and a medium, and relates to the technical field of signal processing. BACKGROUND

[0002] Constrained by extreme working environments, extreme equipment working conditions and other extreme conditions, the energy supply of a large number of edge communication terminals is limited, which greatly limits the terminal baseband signal processing energy consumption.

[0003] In view of the extremely low power consumption signal processing requirement, the existing signal baseband processing architecture faces challenges in processing method and hardware architecture: first, the existing signal processing unit "independent optimization, linear combination" mode is difficult to solve the huge difference between the processing algorithms of each unit, and the baseband power consumption is nonlinearly coupled with the time and space dimension elements of each processing unit, so that local unit module optimization cannot achieve global energy efficiency optimization. Second, the existing baseband signal processing algorithm usually relies on digital circuit implementation, including traditional computers, MCUs, FPGAs, CMOS special integrated circuits and the like. The signal processing process involves a large number of discrete fixed-point number operations, and the energy efficiency of the communication baseband based on the traditional digital circuit is seriously restricted by the random memory access power consumption cost and the energy consumption caused by the discrete fixed-point number operation in the digital domain. The existing digital circuit processing paradigm cannot fundamentally realize the energy efficiency breakthrough. SUMMARY

[0004] The present application aims to at least solve one of the problems in the prior art. To this end, in order to solve the above problems, the purpose of the present application is to provide an extremely low power consumption simulation circuit implementation method, device, equipment and medium based on a unified probabilistic graph calculation architecture.

[0005] In order to achieve the above application purpose, the technical scheme adopted by the present application is: In a first aspect, the present application provides a simulation circuit implementation method based on a unified probabilistic graph calculation architecture, comprising: establishing a unified signal model based on the common features of baseband signal processing tasks; characterizing the unified signal model as a unified probabilistic graph model; obtaining the initialization probability of the variable node state value in the unified probabilistic graph model; setting a storage and calculation integrated characteristic device, the storage and calculation integrated characteristic device comprising an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probabilistic graph model; The driving vector obtained based on the initialization probability is used as the input of the initial input array. The iterative calculation array is used to complete the iterative calculation of mutual message passing between variable nodes and test nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result to complete the baseband signal processing task.

[0006] In some possible implementations, based on the common characteristics of baseband signal processing tasks, a unified signal model is established as follows: ,in, For unknown variables, For observed variables, For given and The correlation mapping matrix between them This is unknown disturbance noise. Each is a certain unknown variable. For each of the observed variables, For the correlation mapping matrix The number of columns, For the correlation mapping matrix number of rows.

[0007] In some possible implementations, the unified probabilistic graphical model includes variable nodes, verification nodes, and undirected edges, wherein the undirected edges are used to connect the variable nodes and the verification nodes that have a connection relationship. The variable nodes represent unknown variables; The verification node represents the coupling relationship between the unknown variable, the observed variable, and the correlation mapping matrix, and is set with a probability configuration function based on the correlation mapping matrix to characterize the differentiated constraint rules between baseband signal processing tasks.

[0008] In some possible implementations, the message passing from the verification node to the variable node is as follows:

[0009] in, For each state contained in a variable node, For verification nodes i To variable node j Passing information about variable nodes j The state value is The news For probability configuration function Take the logarithm. for The probability configuration function, Indicates and verifies the node i Connected and variable nodes j Values all combinations of variable node states of represents the value of the element in the candidate vector corresponding to the i variable node connected to the check node j with index all combinations of variable node states of represents the value of the element in the candidate vector corresponding to the variable node connected to the check node with index represents the value of the element in the candidate vector corresponding to the variable node connected to the check node with index represents the value of the element in the candidate vector corresponding to the variable node connected to the check node with index i represents the set of variable node indices connected to the check node with index represents the message passed from the variable node to the check node with index represents the message passed from the variable node to the check node with index The message passing from the variable node to the check node is:

[0010] where represents the message passed from the variable node to the check node with index represents the message passed from the variable node to the check node with index represents the message passed from the check node to the variable node with index j represents the message passed from the check node to the variable node j with index represents the message passed from the check node to the variable node

[0011] In some possible implementations, the configuration and calculation process of the initial input array are as follows: The configuration scale of the initial input array is , is the number of variable node states, is the number of candidate vectors; The input of the initial input array is an input voltage proportional to the initialization probability of the state value of the variable node: ; Based on the input voltage, the calculation performed by the initial input array is: ; The column output current of the initial input array is:

[0012] The node state value corresponding to the column node of the initial input array is:

[0013] wherein e represents the e-th element from top to bottom, represents the value satisfying The corresponding voltage input row index specifically means selecting the value of i connected to the check node The corresponding variable node is j The value of the node is set to 1 if the value exists, otherwise it is set to 0; 1 represents that the node is in a low configuration and can be turned on, 0 represents that the node is in a high resistance state and is not turned on, the value 1 corresponds to the row voltage that can be accumulated, and the current is output at the output end.

[0014] In some possible implementation manners, the iterative calculation array includes a first iterative sub-array, a second iterative sub-array and an external input sub-array, wherein the configuration and calculation process of the iterative calculation array are as follows: The first iterative sub-array is used to complete message passing from the check node to the variable node, and the scale is set to ; the output of the initial input array is connected to the column input end of the first iterative sub-array to start iteration, and when the value of is , the calculation of the first iterative sub-array is:

[0015] When the iteration starts, the row input voltage of the first iterative sub-array is:

[0016] The element order in the column output current arrangement vector corresponding to the first iterative sub-array is:

[0017] wherein ; The node state value corresponding to the column node of the first iterative sub-array is:

[0018] wherein represents the value satisfying The corresponding voltage input row index specifically means selecting the value of i ​​​The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of The value of the previous iteration input in all test nodes of If a node exists, its value is 1; otherwise, its value is 0. A special case exists when... k When =1, the state value of this node is set to 1, where 1 indicates that it can conduct and 0 indicates that it cannot conduct; e represents the e-th element from top to bottom; The second iterative subarray and the external input subarray are used to complete the message passing from the variable node to the verification node, wherein: the size of the second iterative subarray is... The size of the external input subarray is The columns of the second iterative subarray and the external input subarray correspond to the row voltage input, and the rows correspond to the current readout, and the rows of the second iterative subarray and the external input subarray are connected in series; The column voltage values ​​of the external inputs of the external input subarray:

[0019] in, ; The second iterative subarray and the external input subarray together perform the calculation as follows:

[0020] The common output of the second iterative subarray and the external input subarray is:

[0021] The relationship between the row input of the first iterative subarray and the common output of the second iterative subarray and the external input subarray is as follows:

[0022] The node state values ​​corresponding to the output of the second iterative subarray row are configured as follows:

[0023] in, Indicates satisfaction of The corresponding column index, specifically, refers to the selection and verification of nodes. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is configured as 0, where 1 indicates that it can conduct and 0 indicates that it cannot conduct; e represents the e-th array node from left to right. The node state value corresponding to the row output of the external input subarray is configured as follows:

[0024] in, Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is configured as 0, where 1 indicates that the node can conduct and 0 indicates that it cannot conduct; e represents the e-th array node from left to right.

[0025] In some possible implementations, the iteration stopping condition is met, and the result output array is used to output the processing results, wherein the configuration and calculation of the result output array are as follows: The configuration size of the result output array is The rows of the result output array are concatenated with the rows of the first iterative subarray; The result output array completes the calculation as follows:

[0026] The column output current corresponding to the output array of the results is:

[0027] The node state values ​​corresponding to the columns of nodes in the output array are:

[0028] in, Specifically, it means selecting variable nodes. j All connected verification nodes i The value of the middle is of ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is set to 0. 1 indicates that the node is conductive, 0 indicates that it is not conductive, and e represents the e-th element from the top.

[0029] Secondly, the present invention also provides an analog circuit implementation device based on a unified probabilistic graphical computing architecture, comprising: The signal model establishing unit is configured to establish a unified signal model based on common features of baseband signal processing tasks. The probability graph constructing unit is configured to represent the unified signal model as a unified probability graph model. The probability initializing unit is configured to obtain an initialization probability of a variable node state value in the unified probability graph model. The memory-computing device configuring unit is configured to set a memory-computing integrated characteristic device, the memory-computing integrated characteristic device including an initial input array, an iterative computation array, and a result output array, wherein node state values of the initial input array, the iterative computation array, and the result output array are configured based on the unified probability graph model. The iterative computation unit is configured to obtain a driving vector as an input of the initial input array based on the initialization probability, the iterative computation array is used to complete iterative computation of mutual message passing between variable nodes and check nodes in the unified probability graph model, and the result output array outputs a processing result when an iteration stopping condition is met, thereby completing a baseband signal processing task.

[0030] In a third aspect, the present application also provides an electronic device, including at least one processor, and a memory connected with the processor in communication; wherein the memory stores instructions executable by the processor, and the instructions are executed by the processor to enable the processor to execute the method.

[0031] In a fourth aspect, the present application also provides a computer readable storage medium storing one or more programs, the one or more programs including computer instructions for causing a computer to execute the method.

[0032] The present application has the following characteristics: 1. Low power consumption: the present application makes full use of memory-computing integrated characteristic devices such as memristors to load static variables in the probability graph computation process into memory-computing integrated characteristic devices such as memristors to overcome the energy overhead caused by memory access in the iteration process, and converts traditional discrete digital operation into continuous physical variable operation such as current and voltage, thereby avoiding the energy overhead caused by digital domain discrete fixed-point number operation, and fundamentally improving energy efficiency; 2. Small area: the memory-computing integrated characteristic devices such as memristors used in the present application are very small, and occupy an area of several tenths of traditional cmos circuits. In summary, the present application can be widely applied in signal processing. BRIEF DESCRIPTION OF DRAWINGS

[0033] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the application. Throughout the drawings, like reference numerals will be used to refer to like components. In the drawings: Figure 1 A multi-tasking diagram of baseband signals for embodiments of the application; Figure 2 A unified representation of differentiated baseband signal processing tasks based on probabilistic graph theory for embodiments of the application; Figure 3 Analog circuit schematic diagram based on a unified probabilistic graph computation architecture for embodiments of the application; Figure 4 Connection relationship between check nodes and each variable node in a probabilistic graph model for embodiments of the application. DETAILED DESCRIPTION

[0034] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described unless specifically indicated as such. It is also to be understood that additional or alternative steps can be employed.

[0035] In order to solve the problem that it is difficult to adapt to the low-power application environment in the baseband signal processing method, the application provides an analog circuit implementation method, device and equipment based on a unified probabilistic graph calculation architecture and a medium, which comprises the following steps: establishing a unified signal model based on the common features of baseband signal processing tasks; representing the unified signal model as a probabilistic graph model; obtaining the initialization probability of the state value of the variable node in the probabilistic graph model; and setting a storage and calculation integrated device, wherein the storage and calculation integrated device comprises an initial input array, an iterative calculation array and a result output array, the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probabilistic graph model, the driving vector is obtained as the input of the initial input array based on the initialization probability, the iterative calculation array is used to complete the iterative calculation of the message transmission between the variable nodes and the check nodes in the probabilistic graph model, and the result output array outputs the processing result when the iteration stopping condition is met, so that the baseband signal processing task is completed. Therefore, the traditional discrete digital operation is converted into continuous physical variable operation such as current and voltage, the energy consumption caused by the digital domain discrete fixed-point number operation is avoided, and the energy efficiency is fundamentally improved.

[0036] Exemplary embodiments of the present application will be described in greater detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it is understood that the present application can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thoroughly and completely understood, and will fully convey the scope of the application to those skilled in the art.

[0037] Embodiment one: the embodiment provides a unified probabilistic graph calculation architecture, which comprises: S1, establishing a unified signal model based on the common features of baseband signal processing tasks.

[0038] In the embodiment, the baseband signal processing tasks include channel decoding, channel detection, channel estimation, multi-antenna detection and image recognition, etc. For example, but not limited to.

[0039] Specifically, as shown in Figure 1 , the baseband signal processing tasks in the embodiment include: Task1: multi-antenna detection task; Task2: channel decoding task; Task3: channel estimation task; Task4: multi-user recognition task.

[0040] As shown in Figure 2 , the unified signal model is established based on the common features of baseband signal processing tasks, which is: , wherein, is an unknown variable, is an observed variable, is a given and The correlation mapping matrix between them This is unknown disturbance noise.

[0041] It should be noted that the parameters of the unified signal model have different meanings when facing different baseband signal processing tasks. For example, in a multi-antenna detection task: This is the characteristic matrix of a multi-antenna channel. For the transmitted symbol to be estimated, For the mixed signal observed by the receiver from multiple antennas, continuous, continuous, For unknown discrete variables; in channel decoding tasks: This is the codeword verification matrix. For the transmitted bits to be estimated, The bit sequence received by the receiving end. Discrete, continuous, For unknown discrete variables; in channel estimation tasks: For pilot structure matrix, For the communication channel to be estimated, The pilot signal observed at the receiving end. continuous, For unknown continuous variables; in multi-user detection tasks, For the perception matrix, This refers to the terminal activation state of the device. The signal observed by the receiver is a superimposed signal from multiple users. continuous, continuous, It is an unknown continuous variable.

[0042] S2. Based on the unified probability graph theory, the unified signal model is represented as a unified probability graph model.

[0043] In this embodiment, as Figure 2 As shown, the unified probabilistic graphical model includes multiple variable nodes, multiple check nodes, and multiple undirected edges. Undirected edges connect variable nodes and check nodes that have a connection relationship. Each variable node corresponds to an association mapping matrix. A column vector in which each verification node uniquely corresponds to an association mapping matrix. A row vector in a matrix. For example, the incidence matrix. The Middle i Row vector representation , for No. i Line number j Column elements, representing validation nodes. i With variable nodes jThe association relationship between the variable nodes and the check nodes is represented by an association mapping matrix If an element in the association mapping matrix is 1, the variable node i has a connection relationship with the check node j If an element in the association mapping matrix is 0, the variable node has no connection relationship with the check node i j

[0044] Further, based on the foregoing form transformation, each signal processing problem in the baseband signal processing task is transformed into a problem of estimating an unknown variable based on an observation variable and an association rule. The signal state of a certain task is a value space set of the state of the variable to be estimated. Specifically, it is assumed in this embodiment that the variable to be estimated has K states, which are denoted as: , For example, in a decoding scenario, the K states respectively represent the values of a transmission bit, and in LDPC decoding, K = 2, u 1 = 1, u 2 = 0.

[0045] Specifically, in the unified probabilistic graph model of this embodiment, a variable node represents an unknown variable , where each belongs to a state set space , and the cardinality (number of elements) of the state set space is A check node represents the coupling relationship between the unknown variable, the observation variable, and the association mapping matrix.

[0046] In this embodiment, the unified probabilistic graph model further includes a probability configuration function. The probability configuration function of the i th check node i is used to represent the difference in the probability iterative message from the check node to the variable node in different baseband signal processing tasks. Based on different tasks, the probability configuration functions constructed are all different, and the number of check nodes and the number of probability configuration functions are one-to-one. Specifically, the probability configuration function essentially represents the posterior probability of the observation variable with respect to the unknown variable given the association mapping matrix , and satisfies , which is used to describe the differentiated constraint rules between tasks. The core goal of the unified probabilistic graph calculation is to maximize the posterior probability, that is, , where the variable to be estimated is obtained through , and represents the state set of the variable node.

[0047] ​​​​​Further, the embodiment can effectively solve the problem of great difference in algorithm between communication signal processing elements / units by unified description of signal processing element fusion and reasoning architecture, and lay a mathematical model foundation for cross-element power consumption joint optimization. In specific signal processing, the corresponding probability configuration function is set Flexible conversion of baseband signal processing function can be realized. According to different baseband processing tasks, the probability configuration function is also different. The following will be exemplarily described for different baseband processing tasks, and the examples are not limited thereto: The configuration of the multi-antenna detection task is The configuration of the channel estimation task is The configuration of the channel decoding task is Wherein, represents the noise variance, represents the received signal, H represents the matrix transpose, represents the first row vector in the associated mapping matrix , represents the remainder calculation, represents the remainder inversion.

[0048] S3, obtaining the initial probability of the state value of the variable node.

[0049] In the embodiment, the initial probability value of each variable node corresponding to is calculated according to the received signal , the likelihood probability ratio is saved, and is obtained, wherein, is the posterior probability of the observation variable about the unknown variable after the given associated mapping matrix , is the posterior probability of the observation variable about the unknown variable after the given associated mapping matrix .

[0050] S4, calculating the message passing from the check node to the variable node.

[0051]

[0052] Wherein, is the check node​​​​​​i To variable node j Passing information about variable nodes j The state value is The message (essentially representing the verification node) i To variable node j The message about the first j Variables about The confidence level is the posterior probability. This represents the states contained in the variable node; For probability configuration function Take the logarithm. for The probability configuration function. Indicates and verifies nodes i Connected China satisfies of j The corresponding variable node is related to the validation. i (with connections), and variable nodes j Values The combination of all variable node states. Indicates the first The candidate vector constructed from the nth undirected edge element values Indicates and verifies nodes i There are connections, except for variable nodes. j The combination of all variable node states except for It is a set The vector has M There are 1 candidate vectors, where the candidate vectors are unknown variables. One of the elements, Indicates and verifies the node i Connected and variable nodes j Values The combination of all variable node states, express From the verification node i A set of indexes of variable nodes with connections Take the value from; This represents the element value corresponding to the variable node in the candidate vector. express From the verification node i A set of indexes of variable nodes with connections Take the value from the middle.

[0053] Represents variable nodes To the verification node transmitted by the check node to the variable node. The first iteration starts with, .

[0054] S5, the calculation of the check node to variable node message transmission.

[0055]

[0056] wherein, denotes the variable node j to the check node transmitted by the message about the essence of the variable node j to the check node i transmitted by the first j variable about the confidence of the prior probability), for the check node to the variable node j transmitted by the message about the variable node j state value is .

[0057] S6, repeat S4 to S5, if the maximum number of iterations is reached, stop iteration, obtain the probability of each state value in each variable node: ; further according to the set decision condition get the received symbol, wherein, .

[0058] The simulation circuit implementation process based on the unified probability graph calculation architecture is described in detail below through specific embodiments. In this embodiment, each signal processing problem in the baseband signal processing task is converted into a problem of estimating unknown variables based on observation variables and associated rules. The mutual message transmission process between each check node i to the variable node j is completed on the storage and calculation integrated device. The storage and calculation integrated device in this embodiment is only illustrated by using a memristor as an example, and is not limited thereto.

[0059] As shown in Figure 3 , the memristor array used in this embodiment includes an initial input array, an iterative calculation array, and a result output array. The node state values of the initial input array, the iterative calculation array, and the result output array are configured based on the unified probability graph model. The specific implementation process is as follows: (1) The configuration and calculation process of the initial input matrix is as follows: The scale of the initial input array is configured as , the number of columns of the associated mapping matrix . the number of rows of the associated mapping matrix , the number of variable node states, and , denotes the set denotes the number of candidate vectors i in the set j except for the variable node .

[0060] The input of the initial input array is a voltage proportional to the initialization probability of the variable node state value, specifically as follows:

[0061] Based on the above input voltage, the calculation completed by the initial input array is: . The output current sequence of the initial input array is:

[0062] wherein .

[0063] The initial input matrix has a value corresponding to the node pair in the column where the variable node is located:

[0064] wherein denotes the voltage input row index corresponding to , and specifically means selecting the value of the element in the candidate vector belonging to all variable nodes connected to the check node as i corresponding to the variable node . j denotes whether the value of exists, and if it exists, the value corresponding to the node is set to 1, otherwise it is set to 0. e denotes the e-th element from top to bottom, 1 indicates that the memristor array node is in a low state and can be turned on, and 0 indicates that the memristor array node is in a high resistance state and cannot be turned on. The row voltage corresponding to the value 1 can be accumulated, and the output current at the output end is equivalent to the calculation in .

[0065] (2) The iterative calculation array includes a first iterative sub-array, a second iterative sub-array, and an external input sub-array, wherein the configuration and calculation process of the iterative calculation array are as follows: The first iterative sub-array is used to complete the message passing from the check node to the variable node, and the size is set to .

[0066] Specifically, the row input voltage of the first iteration sub-array in the first iteration is 0, the column output of the initial input array is connected to the column input of the first iteration sub-array to start the iteration, and when x l The value is u k The complete operation in the first iteration sub-array is:

[0067] When the iteration is performed, the row input voltage corresponding to the first iteration sub-array is:

[0068] The element order in the column output current arrangement vector corresponding to the first iteration sub-array is:

[0069] Wherein, .

[0070] The node state value corresponding to the column node (n) where the first iteration sub-array is located is: Wherein,

[0071] represents the voltage input row index corresponding to that satisfies The specific meaning is that the value of the element in the candidate vector belonging to all variable nodes connected to the check node is i The variable node corresponding to is j The value of the last iteration input of all check nodes corresponding to , if it exists, the value corresponding to the node is 1, if it does not exist, the value corresponding to the node is 0, and in a special case, when k =1, the state value of the node is set to 1; e represents the e-th element from top to bottom, 1 represents that the memristor array node is in a low state and can be turned on, and 0 represents a high resistance state and is not turned on. The value of 1 corresponds to the row voltage that can be accumulated, and the output current at the output end is equivalent to the calculation in .

[0072] The second iteration sub-array and the external input sub-array are used to complete the message passing from the variable node to the check node, and are used to calculate the row input of the first iteration sub-array, specifically: The size of the second iteration sub-array is , and the size of the external input sub-array is Unlike the first iterative subarray, the second iterative subarray and the external input subarray have columns corresponding to row voltage inputs and rows corresponding to current readouts. The output of the first iterative subarray needs to undergo a current-to-voltage conversion when it reaches the input of the second iterative subarray. Conversely, the output of the second iterative subarray needs to undergo a current-to-voltage conversion when it reaches the input of the first iterative subarray.

[0073] The input to the external input subarray is directly supplied by an external voltage. The external input voltage of the external input subarray is:

[0074] in, .

[0075] The second iteration subarray and the external input subarray together complete the calculation as follows:

[0076] The common output of the second iteration subarray and the external input subarray is:

[0077] The relationship between the input of the first iteration subarray and the common output of the second iteration subarray and the external input subarray is as follows:

[0078] Second iteration subarray row output The corresponding node value configuration is as follows:

[0079] in, Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is set to 0; 'e' represents the e-th array node from left to right. External input subarray row output The corresponding node status value is configured as follows:

[0080] Where e represents the e-th array node from left to right. Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. iConnected and variable node j The combination of all variable node states , if exists, the node value is configured as 1, if does not exist, the node value is configured as 0. (3) The result output array is an output result generation matrix, the size is , and the rows of the result output array are concatenated with the rows of the first iteration subarray.

[0081] In this embodiment, the result output array is used to complete the calculation formula , which is equivalent to:

[0082] The element order in the column output current arrangement vector corresponding to the result output array is:

[0083] For , the node state value corresponding to the column node is:

[0084] Wherein, The specific meaning is to select all check nodes j connected to the variable node i , and , if exists, the node value is configured as 1, if does not exist, the node value is configured as 0; e represents the e-th element from top to bottom.

[0085] It should be noted that the node state values in all the above subarrays are configured before iteration, and when the iteration is performed to a certain number of times, the output of the result output array is obtained according to the preset decision condition to obtain the final decision result , wherein .

[0086] Further, different candidate variables can be constructed based on different baseband signal processing tasks. In order to more clearly illustrate the content of the present application, the content of the candidate vector is illustrated based on the decoding task as an embodiment: As shown in Figure 4 , for any check node , the target variable nodes and target undirected edges connected to the check node can be determined in the probabilistic graph model. As shown in Figure 3 , when ​​When i = 3, the target variable nodes connected by the third check node are the second, third and fourth variable nodes, and the number of target undirected edges is equal to 3 When i = 3, the target variable nodes connected by the third check node are the second, third and fourth variable nodes, and the number of target undirected edges is equal to 3

[0087] The target characters include 0 and 1. When i = 3 The number of candidate vectors is equal to 8, which is 23(K=2). It can be understood that the number of elements in the candidate vector is the same as the number of target undirected edges. The first, second and third target characters in the candidate vector are associated with the target variable nodes connected by the target undirected edges with internal orders 1, 2 and 3, respectively, that is, the first, second and third target characters in the candidate vector are associated with the second, third and fourth variable nodes, respectively. The internal order of the target undirected edge is i = 1, 2 and 3. When each target undirected edge is traversed, the 8 candidate vectors are divided into first candidate vectors and second candidate vectors. For example, when the third target undirected edge is traversed, the number of candidate vectors is equal to 3 If the third element in the candidate vector is 1, it is determined as the first candidate vector, and if the third element in the candidate vector is 0, it is determined as the second candidate vector. The first candidate vector at this time includes (0, 0, 1), (0, 1, 1), (1, 0, 1) and (1, 1, 1), and the second candidate vector includes (0, 0, 0), (0, 1, 0), (1, 0, 0) and (1, 1, 0). Each of the above first candidate vector and second candidate vector is taken as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is taken as a candidate vector to be processed, a zero vector with the total number of elements equal to the total number of variable nodes 6 (0, 0, 0, 0, 0, 0) is constructed, and the first, second and third target characters in the first candidate vector are associated with the second, third and fourth variable nodes, respectively. Therefore, the second, third and fourth zero elements in the zero vector can be replaced by the first, second and third target characters in the first candidate vector, respectively, to obtain the corresponding processed first candidate vector (0, 0, 1, 1, 0, 0). At this time, when the third target undirected edge is traversed, four processed first candidate vectors and four processed second candidate vectors can be obtained according to the target undirected edge.

[0088] Embodiment two: the embodiment one above provides a simulation circuit implementation method based on a unified probabilistic graph calculation architecture. Correspondingly, the present embodiment provides a simulation circuit implementation device based on a unified probabilistic graph calculation architecture. The device provided in the present embodiment can implement the simulation circuit implementation method based on the unified probabilistic graph calculation architecture of embodiment one. The device can be implemented by software, hardware or a combination of software and hardware. For the convenience of description, the device in the present embodiment is described as various units. Of course, the functions of the units can be implemented in the same or multiple software and / or hardware. For example, the device can include integrated or separate functional modules or functional units to perform the corresponding steps in the methods of embodiment one. Since the device of the present embodiment is basically similar to the method embodiment, the description process of the present embodiment is relatively simple, and the related parts can be referred to the part of the description of embodiment one. The simulation circuit implementation device based on the unified probabilistic graph calculation architecture provided in the present embodiment is only illustrative.

[0089] Specifically, the present application also provides a simulation circuit implementation device based on a unified probabilistic graph calculation architecture, comprising: a signal model establishing unit configured to establish a unified signal model based on the common features of the baseband signal processing task; a probabilistic graph constructing unit configured to represent the unified signal model as a unified probabilistic graph model; a probability initializing unit configured to obtain the initialization probability of the variable node state value in the unified probabilistic graph model; a memory-computing device configuring unit configured to set a memory-computing characteristic device, the memory-computing characteristic device including an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probabilistic graph model; an iterative calculation unit configured to obtain a driving vector as the input of the initial input array based on the initialization probability, the iterative calculation array is used to complete the iterative calculation of the mutual message passing between the variable nodes and the check nodes in the unified probabilistic graph model, and the result output array outputs the processing result when the iteration stopping condition is met, thereby completing the baseband signal processing task.

[0090] Embodiment three: the present embodiment provides an electronic device corresponding to the simulation circuit implementation method based on the unified probabilistic graph calculation architecture provided in embodiment one. The electronic device can be an electronic device for a client, such as a mobile phone, a notebook computer, a tablet computer, a desktop computer, etc., to execute the method of embodiment one.

[0091] Embodiment Four: This embodiment provides a computer readable storage medium storing one or more programs, the one or more programs comprising computer instructions that, when executed by a computer, cause the computer to perform the method provided in Embodiment One.

[0092] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In the description of the specification, the description referring to the terms "one preferred embodiment", "further", "specifically", "in this embodiment" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the embodiments of the specification. The illustrative description of the above terms in the specification does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0093] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing analog circuits based on a unified probabilistic graphical computing architecture, characterized in that, include: Based on the common characteristics of baseband signal processing tasks, a unified signal model is established; The unified signal model is represented as a unified probabilistic graphical model; Obtain the initial probabilities of the variable node state values ​​in the unified probabilistic graphical model; A memory computing device is configured, comprising an initial input array, an iterative computation array, and a result output array, wherein the node state values ​​of the initial input array, the iterative computation array, and the result output array are configured based on the unified probabilistic graphical model. The driving vector obtained based on the initialization probability is used as the input of the initial input array. The iterative calculation array is used to complete the iterative calculation of mutual message passing between variable nodes and test nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result to complete the baseband signal processing task.

2. The analog circuit implementation method according to claim 1, characterized in that, Based on the common characteristics of baseband signal processing tasks, a unified signal model is established as follows: ,in, For unknown variables, For observed variables, For given and The correlation mapping matrix between them This is unknown disturbance noise. Each is a certain unknown variable. For each of the observed variables, For the correlation mapping matrix The number of columns, For the correlation mapping matrix number of rows.

3. The analog circuit implementation method according to claim 2, characterized in that, The unified probabilistic graphical model includes variable nodes, verification nodes, and undirected edges, wherein the undirected edges are used to connect the variable nodes and the verification nodes that have a connection relationship. The variable nodes represent unknown variables; The verification node represents the coupling relationship between the unknown variable, the observed variable, and the correlation mapping matrix, and is set with a probability configuration function based on the correlation mapping matrix to characterize the differentiated constraint rules between baseband signal processing tasks.

4. The analog circuit implementation method according to claim 3, characterized in that, The message passing from the verification node to the variable node is as follows: ； in, For each state contained in a variable node, For verification nodes i To variable node j Passing information about variable nodes j The state value is The news For probability configuration function Take the logarithm. for The probability configuration function, Indicates and verifies the node i Connected and variable nodes j Values The combination of all variable node states; Indicates and verifies the node i Connected and variable nodes j Values The combination of all variable node states, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, express From the verification node i A set of indexes of variable nodes with connections Take the value from the middle. Represents variable nodes To the verification node The message conveyed about The message; The message passing from the variable node to the verification node is as follows: ； in, Represents variable nodes To the verification node The message conveyed about The news For verification nodes To variable node j Passing information about variable nodes j The state value is The news.

5. The analog circuit implementation method according to claim 4, characterized in that, The configuration and calculation process of the initial input array is as follows: The initial input array configuration size is , The number of states of the variable node. The number of candidate vectors; The input to the initial input array is an input voltage that is proportional to the initialization probability of the state values ​​of the variable nodes: ； Based on the input voltage, the initial input array performs the following calculations: ； The column output current of the initial input array is: ； The node state values ​​corresponding to the columns of nodes in the initial input array are: ； Where e represents the e-th element from the top. Indicates satisfaction of The corresponding voltage input row index, specifically, selects the node belonging to the test node. i The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of If the value exists, the value corresponding to the node is set to 1; otherwise, it is set to 0. 1 indicates that the node is in a low-impedance state and can be turned on, while 0 indicates that the node is in a high-impedance state and cannot be turned on. The row voltage corresponding to the value of 1 can be accumulated and output current at the output terminal.

6. The analog circuit implementation method according to claim 5, characterized in that, The iterative computation array includes a first iterative subarray, a second iterative subarray, and an external input subarray. The configuration and computation process of the iterative computation array are as follows: The first iterative subarray is used to complete the message passing from the verification node to the variable node, and its size is set to... The output of the initial input array is connected to the column input of the first iterative subarray to initiate iteration. Values At that time, the calculation performed by the first iterative subarray is as follows: ； At the start of the iteration, the row input voltage of the first iterative subarray is: ； The element order in the column output current arrangement vector corresponding to the first iterative subarray is: ； in, ; The node state values ​​corresponding to the columns of nodes in the first iterative subarray are: ； in, Indicates satisfaction The corresponding voltage input row index, specifically, selects the node belonging to the test node. i The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of The value of the previous iteration input in all test nodes of If a node exists, its value is 1; otherwise, its value is 0. A special case exists when... When the node is active, its state value is set to 1, where 1 indicates that the node is active and 0 indicates that the node is not active; e represents the e-th element from the top. The second iterative subarray and the external input subarray are used to complete the message passing from the variable node to the verification node, wherein: the size of the second iterative subarray is... The size of the external input subarray is The columns of the second iterative subarray and the external input subarray correspond to the row voltage input, and the rows correspond to the current readout, and the rows of the second iterative subarray and the external input subarray are connected in series; The column voltage values ​​of the external inputs of the external input subarray: ； in, ; The second iterative subarray and the external input subarray together perform the calculation as follows: ； The common output of the second iterative subarray and the external input subarray is: ； The relationship between the row input of the first iterative subarray and the common output of the second iterative subarray and the external input subarray is as follows: ； The node state values ​​corresponding to the output of the second iterative subarray row are configured as follows: ; in, Indicates satisfaction of The corresponding column index, specifically, refers to the selection and verification of nodes. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is configured as 0, where 1 indicates that it can conduct and 0 indicates that it cannot conduct; e represents the e-th array node from left to right. The node state value corresponding to the row output of the external input subarray is configured as follows: ； in, Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is configured as 0, where 1 indicates that the node can conduct and 0 indicates that it cannot conduct; e represents the e-th array node from left to right.

7. The analog circuit implementation method according to claim 6, characterized in that, If the iteration stopping condition is met, the result output array is used to output the processing results, wherein the configuration and calculation of the result output array are as follows: The configuration size of the result output array is The rows of the result output array are concatenated with the rows of the first iterative subarray; The result output array completes the calculation as follows: ； The column output current corresponding to the output array of the results is: ； The node state values ​​corresponding to the columns of nodes in the output array are: ； in, Specifically, it means selecting variable nodes. j All connected verification nodes i The value of the middle is of ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is set to 0. 1 indicates that the node is conductive, 0 indicates that it is not conductive, and e represents the e-th element from the top.

8. An analog circuit implementation device based on a unified probabilistic graphical computing architecture, characterized in that, include: The signal model building unit is configured to establish a unified signal model based on the common characteristics of baseband signal processing tasks; A probabilistic graphical construction unit is configured to characterize the unified signal model as a unified probabilistic graphical model; The probability initialization unit is configured to obtain the initial probability of the state values ​​of the variable nodes in the unified probabilistic graphical model. The in-memory computing device configuration unit is configured to set up an in-memory computing integrated feature device, which includes an initial input array, an iterative calculation array, and a result output array, wherein the node state values ​​of the initial input array, the iterative calculation array, and the result output array are configured based on the unified probabilistic graphical model. The iterative calculation unit is configured to obtain the driving vector based on the initialization probability as the input of the initial input array. The iterative calculation array is used to complete the iterative calculation of mutual message passing between variable nodes and test nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result to complete the baseband signal processing task.

9. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the method according to any one of claims 1-7.

10. A computer-readable storage medium for storing one or more programs, characterized in that, One or more programs include computer instructions for causing a computer to perform the method according to any one of claims 1-7.

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