Self-adaptive hardware BFD (Bidirectional Forwarding Detection) link detection method and system

Abstract

The invention discloses a self-adaptive hardware BFD (Bidirectional Forwarding Detection) link detection method and a self-adaptive hardware BFD link detection system, according to the scheme, millisecond-level link state detection is realized through a special BFD processing engine integrated by a switching chip, the transceiving processing of a BFD message and the maintenance of a state machine are completely completed by hardware, and the processing delay of a CPU (Central Processing Unit) is avoided; the transmission delay of historical messages is counted in real time by adopting a sliding window in the BFD link detection process, and a fault judgment threshold value is dynamically calculated and updated based on a statistical result; when packet loss is detected but the time delay is smaller than a dynamic threshold value, the BFD message sending priority is automatically improved, and when continuous packet loss occurs and the time delay exceeds the dynamic threshold value, a standby link switching mechanism is immediately triggered, so that the problem of frequent switching of a main link and a standby link caused by network fluctuation is avoided, the accuracy and reliability of network fault detection are remarkably improved, and the service life of the main link and the standby link is prolonged. And stable operation of the key service network is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network communication, in particular to a hardware acceleration-based bidirectional forwarding detection (BFD) link state monitoring technology. BACKGROUND

[0002] As an important technology for network fault detection, the accuracy of the detection mechanism of the BFD protocol directly affects the reliability of the network system. The traditional BFD implementation scheme mainly adopts a fixed detection mechanism, and its determination standard is that no BFD detection packet sent by the opposite end is received within 3 consecutive detection intervals (i.e. the detection time interval set by the local BFD session), then it is determined that the link is faulty and the session state is set to Down, and then the protection switching mechanism is triggered.

[0003] The existing detection method with a fixed threshold has significant limitations. For example, when the network load fluctuates greatly, even if the physical layer of the link is normal, false positives may occur due to packet transmission delay or temporary loss, resulting in unnecessary protection switching.

[0004] To this end, an improved scheme is given for the above-mentioned fixed threshold detection method. However, in the existing improved scheme, although some studies attempt to reduce the loss probability of BFD packets by introducing a priority scheduling mechanism, the detection efficiency is still insufficient in complex and variable network environments due to the lack of effective coordination with the dynamic threshold adjustment mechanism. Specifically, static threshold setting cannot balance detection sensitivity and accuracy, and lower threshold setting may lead to increased false positive rate, while higher threshold setting will prolong fault detection time.

[0005] In summary, how to make the BFD detection scheme effectively adapt to network state changes to improve network reliability is a problem that needs to be solved in the field. SUMMARY

[0006] In view of the technical problems of high false positive rate and difficulty in balancing detection sensitivity and accuracy caused by the fixed threshold mechanism in the existing BFD detection scheme, the purpose of the present application is to provide a self-adaptive hardware BFD link detection scheme. The present application scheme is based on sequence number and adaptive threshold, and realizes accurate detection of network faults through dynamic adjustment of detection threshold and intelligent scheduling mechanism.

[0007] To achieve the above-mentioned purpose, the present application provides a self-adaptive hardware BFD link detection method, which comprises: integrating a BFD processing engine in a switch chip, extracting BFD packet sequence numbers and timestamp information through hardware analysis, and completing data verification and calculating packet transmission delay values; Adopting a sliding window mechanism to real-time count historical packet transmission delay values, and based on the mean μ and standard deviation σ of the packet transmission delay values to real-time calculate and dynamically adjust the fault determination threshold; the sliding window mechanism includes: real-time maintaining transmission samples of the latest M BFD packets, and real-time calculating the mean μ and standard deviation σ of the transmission delay values of the maintained M BFD packet samples, and based on this to real-time calculate and dynamically adjust the fault determination threshold μ±Kσ, wherein K is a configurable parameter; Adaptive detection of BFD link state based on the dynamic fault determination threshold and the packet loss count: When detecting link packet loss but the packet transmission delay is less than the dynamic fault determination threshold, triggering the priority scheduling mechanism to promote the BFD packet sending priority; When the number of continuous packet loss reaches a preset threshold and the packet transmission delay exceeds the dynamic fault determination threshold, immediately triggering link protection switching through a hardware interrupt.

[0008] Further, the BFD processing engine includes a sequence number generation module, a BFD packet sending and receiving module, a BFD packet analysis module, a sequence number checking module, a timestamp recording module, a time difference calculation module, and a state maintenance module; The sequence number generation module is used to generate a unique and increasing sequence number for each BFD packet; The BFD packet sending and receiving module is used to send BFD packets outward and receive BFD packets; The BFD packet analysis module is used to analyze and extract sequence numbers and timestamp information from received BFD packets; The sequence number checking module checks the analyzed sequence numbers to determine the continuity state of the received BFD packet data; The timestamp recording module is used to record the sending and receiving timestamps of each BFD packet; The time difference calculation module calculates the one-way delay value of each BFD packet; The state maintenance module is used to maintain and convert the BFD state machine based on hardware.

[0009] Further, when promoting the BFD packet sending priority, the detection method includes promoting the DSCP priority field of the BFD packet from the default value to the EF-46 level, and allocating a high-priority processing queue for the BFD packet inside the switch.

[0010] Further, when triggering link protection switching, the detection method immediately notifies the control plane through a hardware interrupt mechanism, records the fault event, and generates alarm information.

[0011] In order to achieve the above object, the application provides a self-adaptive hardware BFD link detection system, which comprises: a BFD processing engine integrated in a switching chip, which is configured to analyze and extract a BFD message sequence number and timestamp information of a received BFD message by hardware, and complete data checking and calculation of a message transmission delay value; a dynamic threshold calculation module, which is configured to interact with the BFD processing engine, can use a sliding window mechanism to real-time count historical message transmission delay values, and real-time calculate and dynamically adjust a fault determination threshold based on a mean value μ and a standard deviation σ of the message transmission delay values; when the dynamic threshold calculation module calculates the dynamic threshold based on the sliding window mechanism, it maintains transmission samples of the latest M BFD messages in real time, calculates the mean value μ and the standard deviation σ of the transmission delay values of the maintained M BFD message samples in real time, and real-time calculates and dynamically adjusts the fault determination threshold μ±Kσ according to the mean value μ and the standard deviation σ, wherein K is a configurable parameter; a fault decision module, which is configured to interact with the dynamic threshold calculation module, can determine the BFD link state based on the dynamic fault determination threshold and the packet loss count; an execution control module, which is configured to interact with the fault decision module, can trigger a priority scheduling mechanism to improve the BFD message sending priority when the fault decision module detects link packet loss but the message transmission delay is less than the dynamic fault determination threshold, and can immediately trigger link protection switching through a hardware interrupt when the fault decision module detects that the number of continuous link packet losses reaches a preset threshold and the message transmission delay exceeds the dynamic fault determination threshold.

[0012] Further, the BFD processing engine comprises a sequence number generation module, a BFD message sending and receiving module, a BFD message analysis module, a sequence number checking module, a timestamp recording module, a time difference calculation module and a state maintenance module; The sequence number generation module is used to generate a unique and incremental sequence number for each BFD message; The BFD message sending and receiving module is used to send and receive BFD messages; The BFD message analysis module is used to analyze and extract the sequence number and timestamp information of the received BFD message; The sequence number checking module checks the analyzed sequence number to determine the continuity state of the received BFD message data; The timestamp recording module is used to record the sending and receiving timestamps of each BFD message; The time difference calculation module calculates the one-way delay value of each BFD message; The state maintenance module is used for maintaining and converting the BFD state machine based on hardware.

[0013] Further, the execution control module comprises lifting the DSCP priority field of the BFD packet from a default value to an EF-46 level when lifting the BFD packet sending priority, and assigning a high-priority processing queue for the BFD packet inside the switch.

[0014] Further, the execution control module records a fault event and generates alarm information by means of a hardware interrupt mechanism to immediately inform the control plane when triggering link protection switching.

[0015] The scheme provided by the application effectively distinguishes network congestion from real faults through a dynamic threshold mechanism, combines intelligent fault processing strategies, realizes high reliability detection in a complex network environment, maintains millisecond-level detection speed, and significantly improves network service quality.

[0016] Further, the scheme provided by the application realizes millisecond-level link state detection through the corresponding BFD processing engine integrated in the switch chip, so that the sending and receiving processing of the BFD packet and the state machine maintenance are completely completed by hardware, avoiding CPU processing delay.

[0017] Further, the scheme provided by the application avoids the problem of frequent switching of the main and standby links caused by network fluctuations through dynamic adjustment of the detection threshold and intelligent scheduling mechanism, can significantly improve the accuracy and reliability of network fault detection, and guarantees stable operation of critical business networks. BRIEF DESCRIPTION OF DRAWINGS

[0018] The application will be further described below in combination with the drawings and specific embodiments.

[0019] Figure 1 It is a schematic diagram of the BFD processing engine in the application; Figure 2 It is a system block diagram of the hardware BFD link detection system in the application; Figure 3 It is a schematic diagram of the module deployment of the CTC7148 switch chip platform in the application; Figure 4 It is a flowchart of the calculation of the dynamic threshold (i.e. fault determination threshold) in the application; Figure 5 It is a timing diagram of the hardware BFD link detection of the CTC7148 switch chip platform in the application. DETAILED DESCRIPTION

[0020] In order to make the technical means, creative features, purposes and effects realized by the application easy to understand, the application will be further described below in combination with specific drawings.

[0021] The present application aims at the BFD link state monitoring requirement, and gives a hardware BFD link detection scheme based on sequence number and adaptive threshold value. The scheme first realizes millisecond-level link state detection by integrating a corresponding BFD processing engine in a switching chip, so that the sending and receiving processing of BFD packets and the maintenance of a state machine are completely completed by hardware, and CPU processing delay is avoided.

[0022] On this basis, the accurate detection and processing of link faults are further realized through a dynamic adjustment of a detection threshold mechanism, a smart fault judgment and processing mechanism.

[0023] Specifically, the implementation scheme of the hardware BFD link detection method based on sequence number and adaptive threshold value given by the present application is as follows: A BFD processing engine is integrated in a switching chip, BFD packet sequence numbers and timestamp information are extracted by hardware, data verification is completed, and a packet transmission delay value is calculated; A sliding window mechanism is adopted to statistically calculate historical packet transmission delay values, and a fault judgment threshold value is calculated and dynamically adjusted based on the mean value μ and the standard deviation σ of the packet transmission delay values; The BFD link state is intelligently judged and processed based on the dynamic fault judgment threshold value and the packet loss count: When link packet loss is detected but the packet transmission delay is less than the dynamic fault judgment threshold value, a priority scheduling mechanism is triggered to improve the BFD packet sending priority; When the number of consecutive packet losses reaches a preset threshold value and the packet transmission delay exceeds the dynamic fault judgment threshold value, the link protection switching is immediately triggered by hardware interruption.

[0024] Specifically, in the present application scheme, the BFD processing engine integrated in the switching chip is used to complete the sending and receiving processing of BFD packets and the maintenance of a state machine by hardware, effectively avoiding CPU processing delay.

[0025] Further, when the BFD processing engine integrated in the switching chip is used to complete the sending and receiving processing of BFD packets and the maintenance of a state machine by hardware, the corresponding hardware processing scheme specifically includes two parts of BFD timer processing and data packet processing: The BFD timer is divided into DefectWhile and HelloWhile, which respectively time the BFD state machine and the communication time of the timing BFD packet.

[0026] On this basis, when DefectWhile is reduced to 0, the local BFD state machine will be switched from Up / Init to Down; when HelloWhile is reduced to 0, the packet generation logic will be entered, the BFD processing engine generates a sequence number and adds it to the BFD packet header; when receiving, the sequence number in the opposite packet is automatically extracted and the local timestamp is recorded, and according to the state information in the packet, the state information of the local end is combined to maintain the state machine, and finally the delay calculation and packet loss judgment are performed.

[0027] As a further illustration, referring to Figure 1 As shown in the figure, the BFD processing engine in the scheme of the application comprises a sequence number generation module 11, a BFD packet sending and receiving module 12, a BFD packet analysis module 13, a sequence number checking module 14, a timestamp recording module 15, a time difference calculation module 16 and a state maintenance module 17.

[0028] The sequence number generation module 11 in the BFD processing engine is used to generate a unique and increasing sequence number for each BFD packet to be sent.

[0029] Specifically, the sequence number generation module 11 is implemented by a hardware counter, the counter has a bit width of 32 bits, automatically increases before sending a BFD packet each time, generates a globally monotonically increasing sequence number, and writes the sequence number into the BFD packet header field.

[0030] Further, the counter is also provided with a rollover prevention mechanism, which automatically resets when the count reaches the maximum value and notifies the state maintenance module 17 to record an abnormal event, thereby ensuring the uniqueness and continuity of the sequence number and enhancing the reliability of the protocol processing.

[0031] The BFD packet sending and receiving module 12 in the BFD processing engine interacts with the sequence number generation module 11, and is used to send BFD packets with unique sequence numbers outward, and receive BFD packets with unique sequence numbers sent by the opposite end.

[0032] Specifically, the BFD packet sending and receiving module 12 is arranged to be directly connected to the network physical port through a hardware interface, adopts a dedicated sending queue and receiving queue structure, supports a back pressure flow control mechanism and a micro burst tolerance capability.

[0033] Further, the sending and receiving processes in the BFD packet sending and receiving module 12 are interacted with the on-chip cache through DMA mode without the participation of CPU, thereby realizing high-throughput and low-delay BFD packet transmission and reception, and guaranteeing the real-time detection.

[0034] The BFD packet analysis module 13 in the BFD processing engine interacts with the BFD packet sending and receiving module 12, and is used for analyzing and extracting the sequence number and timestamp information of the received BFD packet.

[0035] Specifically, the BFD packet analysis module 13 adopts a multi-stage pipeline analysis structure realized by hardware logic, and extracts the sequence number field in the BFD header and the carried timestamp information in real time while receiving the packet. The packet legality check is completed at the same time in the analysis process, and the illegal packet is directly discarded and the statistical information is recorded.

[0036] Further, the hardware BFD packet analysis module 13 is preferably integrated in the hardware unit inside the BFD processing engine, and is composed of a special hardware state machine and a multi-stage pipeline logic circuit, which can analyze each field of the BFD packet in real time and in parallel during the packet receiving process, extract the sequence number and timestamp information, and complete the legality check and abnormal packet discarding at the hardware level. The whole process does not depend on software participation.

[0037] The sequence number checking module 14 in the BFD processing engine interacts with the BFD packet analysis module 13, and can check the sequence number analyzed by the BFD packet analysis module 13 to determine the continuity state of the received BFD packet data and whether there is a packet loss.

[0038] Specifically, the sequence number checking module 14 is preferably realized by a hardware comparator, which maintains an expected sequence number register, compares the received packet sequence number with the expected value in real time, updates the expected sequence number and marks the packet as valid if the sequence number is continuous or meets the expected range, and triggers a packet loss event if the sequence number is not continuous.

[0039] Further, the sequence number checking module 14 is set to support configurable sequence number tolerance check, which can identify duplicate packets and reverse order packets, and output the link continuity state in real time through the hardware state machine, further improving the accuracy and response speed of fault detection.

[0040] The timestamp recording module 15 in the BFD processing engine interacts with the BFD packet sending and receiving module 12 and the BFD packet analysis module 13, and can record the sending and receiving timestamps of each BFD packet.

[0041] Specifically, the timestamp recording module 15 is preferably realized by a high-precision hardware clock and a special register group. The sending timestamp is automatically labeled by hardware when the packet leaves the chip port and is recorded in the sending timestamp register. The receiving timestamp is captured by hardware and stored in the receiving timestamp register after the BFD packet header is identified by the packet analysis module.

[0042] The timestamp recording module 15 ensures the atomicity and consistency of timestamp recording through hardware logic, avoids the delay and jitter introduced by software recording, and provides a high-precision data basis for time delay calculation.

[0043] The time difference calculation module 16 in the BFD processing engine interacts with the timestamp recording module 15, and can calculate the one-way time delay value of each BFD packet based on the sending and receiving timestamps of each BFD packet recorded by the timestamp recording module 15.

[0044] Specifically, the time difference calculation module 16 is preferably implemented through a hardware subtractor logic, which obtains the receiving timestamp and the sending timestamp in real time, calculates the difference between the two and outputs the one-way time delay value.

[0045] Further, the time difference calculation module 16 is configured to support clock offset compensation and overflow processing to ensure the correctness of time delay calculation; and is integrated with a first level cache to temporarily store time delay values of multiple packets for use by a subsequent statistical module.

[0046] The state maintenance module 17 in the BFD processing engine is used to maintain and convert the BFD state machine based on hardware.

[0047] Specifically, the state maintenance module 17 is preferably implemented by a corresponding hardware state machine, which maintains the current BFD session state internally and drives the state machine according to the state of the received packet and the local state.

[0048] Further, the state transition logic in the state maintenance module 17 is completely judged and executed in parallel by hardware, and at the same time provides real-time state query to the upper layer through a register interface, greatly improving the efficiency and reliability of state maintenance.

[0049] Further, in the BFD processing engine integrated in the switching chip in the present scheme, when the sliding window mechanism is used to calculate and dynamically adjust the fault determination threshold based on the hardware processing of the BFD packet, firstly, the transmission samples of the last M BFD packets are maintained in real time based on the sliding window for the BFD packets processed by the BFD processing engine, and the packet transmission delay values of the maintained BFD packet samples are statistically calculated in real time, and the mean μ and the standard deviation σ of the transmission delay values of the maintained M BFD packet samples are calculated accordingly; then the fault determination threshold μ±Kσ is calculated and dynamically adjusted in real time, wherein K is a configurable parameter.

[0050] As an example, the preferred value range of M is 100-200, and the preferred value range of K is 2-4.

[0051] Based on the above sliding window mechanism, the statistical samples are periodically updated, so that the threshold can adapt to the network state change, while ensuring the detection sensitivity and reducing the misjudgment rate.

[0052] Further, the intelligent fault judgment and processing mechanism for the BFD link state in the present solution is specifically implemented based on the continuity state (packet loss data) of the BFD packet data processed by the BFD processing engine and the dynamic fault judgment threshold calculated: (1) When the link packet loss is detected but the packet transmission delay is less than the current fault judgment threshold, it is determined that the current network state is congestion, and the sending priority of the BFD packet is automatically promoted, including adjusting the DSCP mark, allocating a high-priority queue, etc.

[0053] As an example, when the sending priority of the BFD packet is promoted, the DSCP priority field of the BFD packet can be promoted from the default value to the EF-46 level, and a high-priority processing queue is allocated for the BFD packet inside the switch.

[0054] (2) When the link packet loss is detected, and the number of consecutive packet losses reaches a preset threshold and the packet transmission delay exceeds the current fault judgment threshold, it is determined that the link is faulty and protection switching is triggered.

[0055] As an example, when the link protection switching is triggered, the control plane is immediately notified through the hardware interrupt mechanism, and the fault event is recorded and alarm information is generated.

[0056] The hardware BFD link detection method based on sequence number and adaptive threshold formed based on the above solution effectively distinguishes between network congestion and real failure through a dynamic threshold mechanism, and in combination with an intelligent fault processing scheme, it can achieve high reliability detection in a complex network environment while maintaining a millisecond-level detection speed, significantly improving the quality of network services.

[0057] For the hardware BFD link detection scheme based on sequence number and adaptive threshold given in the present example solution, a corresponding software program can be constructed to form a corresponding hardware BFD link detection system based on sequence number and adaptive threshold. The software program, when running, will execute the hardware BFD link detection method based on sequence number and adaptive threshold described above, and is stored in a corresponding storage medium for execution by a processor.

[0058] Referring to Figure 2 The hardware BFD link detection system 100 based on sequence number and adaptive threshold thus formed is mainly composed of a BFD processing engine 110, a dynamic threshold calculation module 120, a fault decision module 130, and an execution control module 140, which cooperate with each other in function.

[0059] In a specific deployment implementation, the BFD processing engine 110 in the system is directly integrated in a switching chip, and is capable of extracting the BFD packet sequence number and timestamp information of a received BFD packet by hardware, and completing data verification and calculating the packet transmission delay value.

[0060] The dynamic threshold calculation module 120 in the system is set to interact with the BFD processing engine 110, and is capable of using a sliding window mechanism to real-time statistics of historical packet transmission delay values, and real-time calculating and dynamically adjusting the fault determination threshold based on the mean μ and standard deviation σ of the packet transmission delay values.

[0061] The fault decision module 130 in the system is set to interact with the dynamic threshold calculation module 120 and the BFD processing engine 110, and is capable of determining the BFD link state based on the dynamic fault determination threshold and the packet loss count.

[0062] The execution control module 140 in the system is set to interact with the fault decision module 130, and the intelligent fault determination and processing mechanism in the execution control module 140 is capable of triggering the priority scheduling mechanism to improve the BFD packet sending priority when the fault decision module detects link packet loss but the packet transmission delay is less than the dynamic fault determination threshold, and is capable of immediately triggering link protection switching through hardware interruption when the fault decision module detects that the number of continuous link packet loss reaches a preset threshold and the packet transmission delay exceeds the dynamic fault determination threshold.

[0063] The implementation scheme of each functional module in the hardware BFD link detection system 100 is further described below.

[0064] The BFD processing engine 110 in the system is integrated in a switching chip, and realizes the complete hardware completion of the BFD packet receiving and sending processing, state machine maintenance, delay calculation and sequence number verification, effectively avoiding CPU processing delay.

[0065] The specific implementation scheme of the BFD processing engine 110 is described in the foregoing method scheme, which is not described here.

[0066] The dynamic threshold calculation module 120 in the system is capable of calculating and dynamically adjusting the fault determination threshold based on the BFD packet processing of the BFD processing engine 110 through the sliding window mechanism. First, for the BFD packet processed by the BFD processing engine, the transmission samples of the last M BFD packets are maintained in real time based on the sliding window, and the packet transmission delay values of the maintained BFD packet samples are real-time statistics, and the mean μ and standard deviation σ of the transmission delay values of the maintained M BFD packet samples are calculated accordingly. Then, the fault determination threshold μ ± Kσ is calculated and dynamically adjusted in real time, where K is a configurable parameter.

[0067] The preferred value range of M is 100-200, and the preferred value range of K is 2-4.

[0068] The dynamic threshold calculation module 120 periodically updates the statistical sample based on a sliding window mechanism, so that the threshold can adapt to network state changes, while ensuring detection sensitivity and reducing false positive rates.

[0069] The fault decision module 130 in the system interacts with the BFD processing engine 110 and the dynamic threshold calculation module 120, performs packet loss detection on each BFD packet data according to the result checked by the sequence number checking module in the BFD processing engine 110, detects whether each BFD packet data is lost and the number of lost packets, and at the same time, synchronously compares and detects the one-way delay value of each BFD packet calculated by the time difference calculation module in the BFD processing engine 110 with the dynamic fault determination threshold calculated and determined by the dynamic threshold calculation module 120. On this basis, when the fault decision module 130 detects link packet loss but the packet transmission delay is less than the current fault determination threshold, it determines that the current link state is congested; when it detects link packet loss and the number of consecutive packet losses reaches a preset threshold and the packet transmission delay exceeds the current fault determination threshold, it determines that the link state is faulty.

[0070] As a further illustration, the dynamic threshold calculation module 120 and the fault decision module 130 in the system are independent of the BFD processing engine 110 in terms of hardware architecture when they are specifically deployed and implemented, all of which are implemented with corresponding hardware logic and cooperatively interact through a high-speed data interface within the chip to jointly realize rapid detection and adaptive fault determination of the link state.

[0071] The execution control module 140 in the system interacts with the fault decision module 130 to trigger the corresponding fault processing mechanism according to the link fault state determined by the fault decision module 130. When it is determined that the current link state is congested, the sending priority of the BFD packet is automatically raised, and the priority raising strategy includes adjusting the DSCP mark, allocating a high-priority queue, etc. As an example, when the sending priority of the BFD packet is raised, the DSCP priority field of the BFD packet can be raised from the default value to the EF-46 level, and a high-priority processing queue is allocated for the BFD packet inside the switch.

[0072] When it is determined that the current link state is faulty, link protection switching is triggered. As an example, when link protection switching is triggered, the control plane is immediately notified through a hardware interrupt mechanism, and the fault event is recorded and alarm information is generated.

[0073] The specific implementation process of the present application scheme is further illustrated by the corresponding application examples below.

[0074] In this example, it is realized based on Shengke CTC7148 switching chip platform, which has built-in hardware acceleration engine supporting millisecond-level timestamp processing capability to provide high-precision hardware basis for BFD link detection. And the BFD processing engine is used to complete the receiving and sending processing of BFD packets and state machine maintenance in a complete hardware manner.

[0075] Referring to Figure 3 On this basis, the dynamic threshold calculation module, intelligent fault decision module and execution control module are further deployed in the CTC7148 switching chip platform, and the dynamic threshold calculation module, intelligent fault decision module and execution control module are cooperated with each other to complete the hardware BFD detection.

[0076] In the CTC7148 switching chip platform, when the switching chip receives a BFD packet, the sequence number and timestamp information of each received BFD packet are extracted by the BFD packet analysis module in the BFD processing engine; then the sequence number extracted is checked by the sequence number checking module to ensure the continuity of each received BFD packet data; at the same time, the one-way delay value of each BFD packet is calculated by the timestamp recording module: Wherein is the clock synchronization deviation.

[0077] The dynamic threshold calculation module in the CTC7148 switching chip platform adopts sliding window design, and the window size is set to 100 continuous BFD packet samples by default.

[0078] Among them, the sliding window maintains the latest 100 delay samples in real time, and removes the oldest historical data every time a new sample is received, so that the window always contains the latest 100 delay values, and the current fault judgment threshold μ+3σ is calculated based on the latest 100 delay values, where K is 3, and the fault judgment threshold μ+3σ is stored in the dynamic threshold register. The threshold will be automatically adjusted with the change of network state, realizing the adaptive detection of link abnormality.

[0079] Referring to Figure 4 which shows the specific calculation process of the dynamic threshold (i.e. fault judgment threshold) in this example.

[0080] Based on the diagram, when calculating the dynamic threshold in this example, the default window capacity N is 100, and the latest N BFD packet delay samples are dynamically maintained in a first-in-first-out strategy D [i] i =1,2,..., N ​), and the mean μ and the standard deviation σ are calculated recursively based on the Welford algorithm, which is mathematically expressed as: ; ; ; wherein is the updated window delay mean, is the pre-updated window delay mean, is the newly arrived BFD packet delay value, is the old delay value removed from the window, is the updated window accumulated squared difference, is the pre-updated window accumulated squared difference, is the updated window delay standard deviation. The dynamic threshold is set as , and is updated in real time through a hardware register.

[0081] When a new delay value is sent into the sliding window buffer, the statistical unit recalculates the mean and the standard deviation, and updates the dynamic threshold, realizing adaptive tracking of network status.

[0082] The fault decision module in the CTC7148 switching chip platform implements multi-level judgment based on the calculated dynamic threshold and the packet loss count: When the link packet loss is detected but the delay is less than the dynamic threshold, it is determined as network congestion, triggering the priority scheduling mechanism, adjusting the transmission priority of the BFD detection packet through the priority mechanism (COS / DSCP), ensuring the priority transmission of the detection packet in the congested link; When the link packet loss count is greater than 3 and the delay is greater than the dynamic threshold, it is determined as physical link failure, triggering a hardware interrupt signal immediately, performing protection switching operation to quickly switch the service traffic to the standby link, to ensure the continuity of network communication and reduce the service interruption time caused by link failure.

[0083] Through the cooperative work of each module, the whole hardware BFD detection pipeline realizes real-time monitoring of link status, dynamic threshold adjustment, fault discrimination and fast response, effectively improving the reliability and stability of the network.

[0084] Referring to Figure 5 , which is a timing diagram of the hardware BFD link detection of the CTC7148 switching chip platform in the present example.

[0085] Based on the diagram, the process of the hardware BFD link detection of the CTC7148 switching chip platform is as follows: (1) The message sending module in the sending end BFD processing engine generates and sends the BFD detection message, the sequence number generation module assigns a unique increasing sequence number sq=n to the message, and the timestamp recording module synchronously records the sending timestamp.

[0086] (2) After the receiving end device receives the BFD message, the analysis module extracts the sequence number sq and the timestamp information carried by the message, and the timestamp recording module records the receiving timestamp.

[0087] (3) The receiving end time difference calculation module calculates the current one-way delay D of the message based on the timestamp. The delay value D is sent to the sliding window of the dynamic threshold calculation module, which updates the delay mean μ and the standard deviation σ in real time based on the Welford algorithm, and updates the current dynamic fault judgment threshold θ=μ+3σ.

[0088] (4) Finally, the sequence number checking module of the receiving end detects that the next expected message sq=n+1 does not arrive within the specified time, and determines that a single packet loss occurs. The fault decision module integrates the current packet loss count and the delay information, and if the current delay D does not exceed the threshold θ, it is determined that the network is congested, triggering the execution control module to raise the sending priority of the subsequent BFD message; if packet loss occurs in the last 3 detection periods and the delay continuously exceeds θ, it is determined that the physical link is faulty, immediately triggering the protection switching through the hardware interrupt mechanism, and reporting the alarm to the control plane.

[0089] The basic principles, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above examples, and the above examples and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. An adaptive hardware BFD link detection method, characterized in that, The detection method includes: A BFD processing engine is integrated into the switching chip to parse and extract the BFD message sequence number and timestamp information through hardware, and to complete data verification and calculate the message transmission delay value. A sliding window mechanism is used to statistically analyze historical message transmission delay values ​​in real time. The fault determination threshold is calculated and dynamically adjusted in real time based on the mean μ and standard deviation σ of the message transmission delay values. The sliding window mechanism includes: maintaining the transmission samples of the most recent M BFD messages in real time, calculating the mean μ and standard deviation σ of the transmission delay values ​​of the maintained M BFD message samples in real time, and calculating and dynamically adjusting the fault determination threshold μ±Kσ in real time based on this, where K is a configurable parameter. Adaptive detection of BFD link status based on dynamic fault determination thresholds and packet loss counts: When a link packet loss is detected but the message transmission delay is less than the dynamic fault judgment threshold, the priority scheduling mechanism is triggered to increase the BFD message sending priority. When the number of consecutive packet losses reaches a preset threshold and the message transmission delay exceeds the dynamic fault judgment threshold, the link protection switch is immediately triggered by hardware interruption.

2. The adaptive hardware BFD link detection method according to claim 1, characterized in that, The BFD processing engine includes a sequence number generation module, a BFD message sending and receiving module, a BFD message parsing module, a sequence number verification module, a timestamp recording module, a time difference calculation module, and a status maintenance module. The sequence number generation module is used to generate a unique, incrementing sequence number for each BFD message; The BFD message sending and receiving module is used to send BFD messages and receive BFD messages. The BFD message parsing module is used to parse the received BFD messages and extract the sequence number and timestamp information; The sequence number verification module verifies the parsed sequence number to determine the continuity status of the received BFD message data. The timestamp recording module is used to record the sending and receiving timestamps of each BFD message; The time difference calculation module calculates the one-way delay value for each BFD message; The state maintenance module is used to maintain and transition the BFD state machine based on hardware.

3. The adaptive hardware BFD link detection method according to claim 1, characterized in that, When the detection method increases the sending priority of BFD packets, it includes raising the DSCP priority field of the BFD packet from the default value to a preset level, and allocating a high-priority processing queue for the BFD packet inside the switch.

4. The adaptive hardware BFD link detection method according to claim 1, characterized in that, When the detection method triggers a link protection switchover, it immediately notifies the control plane through a hardware interrupt mechanism, records the fault event, and generates alarm information.

5. An adaptive hardware BFD link detection system, characterized in that, The detection system includes: The BFD processing engine integrated in the switching chip is configured to parse and extract the BFD message sequence number and timestamp information of the received BFD message through hardware, and to complete data verification and calculate the message transmission delay value. The dynamic threshold calculation module is configured to interact with the BFD processing engine. It can use a sliding window mechanism to statistically analyze historical message transmission delay values ​​in real time, and calculate and dynamically adjust the fault judgment threshold based on the mean μ and standard deviation σ of the message transmission delay values. When performing dynamic threshold calculation based on the sliding window mechanism, the dynamic threshold calculation module maintains the transmission samples of the most recent M BFD messages in real time, and calculates the mean μ and standard deviation σ of the transmission delay values ​​of the maintained M BFD message samples in real time. Based on this, it calculates and dynamically adjusts the fault judgment threshold μ±Kσ in real time, where K is a configurable parameter. The fault decision module is configured to interact with the dynamic threshold calculation module and can determine the BFD link status based on the dynamic fault judgment threshold and packet loss count. The execution control module is configured to interact with the fault decision module. When the fault decision module detects packet loss in the link but the message transmission delay is less than the dynamic fault judgment threshold, it can trigger a priority scheduling mechanism to increase the priority of BFD message transmission. When the fault decision module detects that the number of consecutive packet losses in the link reaches a preset threshold and the message transmission delay exceeds the dynamic fault judgment threshold, it can immediately trigger link protection switching through hardware interruption.

6. The adaptive hardware BFD link detection system according to claim 5, characterized in that, The BFD processing engine includes a sequence number generation module, a BFD message sending and receiving module, a BFD message parsing module, a sequence number verification module, a timestamp recording module, a time difference calculation module, and a status maintenance module. The sequence number generation module is used to generate a unique, incrementing sequence number for each BFD message; The BFD message sending and receiving module is used to send BFD messages and receive BFD messages. The BFD message parsing module is used to parse the received BFD messages and extract the sequence number and timestamp information; The sequence number verification module verifies the parsed sequence number to determine the continuity status of the received BFD message data. The timestamp recording module is used to record the sending and receiving timestamps of each BFD message; The time difference calculation module calculates the one-way delay value for each BFD message; The state maintenance module is used to maintain and transition the BFD state machine based on hardware.

7. The adaptive hardware BFD link detection system according to claim 5, characterized in that, When the execution control module increases the sending priority of BFD messages, it includes raising the DSCP priority field of the BFD message from the default value to the EF-46 level, and allocating a high-priority processing queue for the BFD message inside the switch.

8. The adaptive hardware BFD link detection system according to claim 5, characterized in that, When the execution control module triggers a link protection switchover, it immediately notifies the control plane through a hardware interrupt mechanism, records the fault event, and generates alarm information.

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