Communication interface conversion method, device, equipment and readable storage medium

Abstract

The application is suitable for the field of communication technology, and provides a communication interface conversion method, device, equipment and readable storage medium. The method comprises the following steps: acquiring an RGMII receiving data signal, the RGMII receiving data signal being output by a PHY layer through an RGMII interface; converting the RGMII receiving data signal into an MII receiving data signal through a first FIFO buffer; acquiring an MII sending data signal, the MII sending data signal being output by a MAC layer through an MII interface; converting the MII sending data signal under an MII clock domain into an MII sending data signal under a system clock domain through a second FIFO buffer; generating an RGMII sending clock based on a system clock through an ODDR, and converting the MII sending data signal under the system clock domain into an RGMII sending data signal based on the RGMII sending clock. Therefore, the application can avoid the occurrence of data loss, data error and the like in the interface conversion process as much as possible.

Description

Technical Field

[0001] This application belongs to the field of communication technology, and in particular relates to communication interface conversion methods, apparatus, devices and readable storage media. Background Technology

[0002] In Ethernet communication systems, the Reduced Gigabit Media Independent Interface (RGMII) is a high-speed, simplified version of the Media Independent Interface (MII), widely used to connect the Physical Layer (PHY) and the Media Access Control (PHY). At 100 Mbps, RGMII uses a 25 MHz clock and transmits the same data on both the rising and falling edges of the clock in double data rate (DDR) mode. The MII interface, as a traditional standard interface, also uses a 25 MHz clock and transmits data on the rising edge of the clock in single data rate (SDR) mode.

[0003] With the evolution of network technology, in some communication systems based on logic devices, the multi-channel MAC layer uses the MII interface, and the PHY layer provides the RGMII interface. It is necessary to connect the MAC layer that supports the MII interface to the PHY layer that supports the RGMII interface to achieve cross-standard connection.

[0004] However, to achieve cross-standard connectivity, existing solutions typically rely on complex state machines or application-specific integrated circuits (ASICs). In practical applications, these solutions have shortcomings in the conversion process, which can easily lead to data loss, packet errors, or system performance degradation, thus affecting the reliability of system communication. Summary of the Invention

[0005] This application provides a communication interface conversion method, apparatus, device, and readable storage medium, which can minimize the occurrence of data loss and data errors during the interface conversion process.

[0006] In a first aspect, embodiments of this application provide a communication interface conversion method applied to an electronic device, wherein the electronic device's Media Access Control (MAC) layer supports a Media Independent Interface (MII), and the Physical PHY layer supports a Simplified Gigabit Media Independent Interface (RGMII), including:

[0007] The process involves: acquiring the RGMII receive data signal, which is output by the PHY layer through the RGMII interface; converting the RGMII receive data signal into the MII receive data signal through a first FIFO buffer (the write clock of the first FIFO buffer is the RGMII clock, and the read clock of the first FIFO buffer is the system clock); acquiring the MII transmit data signal, which is output by the MAC layer through the MII interface; converting the MII transmit data signal under the MII clock domain into the MII transmit data signal under the system clock domain through a second FIFO buffer (the write clock of the second FIFO buffer is the MII clock, and the read clock of the second FIFO buffer is the system clock); and generating the RGMII transmit clock based on the system clock by outputting the double data rate register ODDR, and converting the MII transmit data signal under the system clock domain into the RGMII transmit data signal based on the RGMII transmit clock.

[0008] In one possible implementation of the first aspect, the RGMII received data signal is converted into an MII received data signal via a first FIFO buffer, including:

[0009] The RGMII receive data signal and the RGMII receive enable signal are bit-concatenated to obtain the first packet signal. The RGMII receive enable signal is used to indicate whether the RGMII receive data signal is valid. The RGMII receive enable signal is output by the PHY layer through the RGMII interface. In the RGMII clock domain, the first packet signal is written into the first FIFO buffer. In the system clock domain, based on the first packet signal, the second packet signal is read from the first FIFO buffer and split into the MII receive enable signal and the MII receive data signal.

[0010] In one possible implementation of the first aspect, the MII transmit data signal under the MII clock domain is converted into the MII transmit data signal under the system clock domain through a second FIFO buffer, including:

[0011] The MII transmit data signal and the MII transmit enable signal are bit-concatenated to obtain the third packet signal. The MII transmit enable signal is used to indicate whether the MII transmit data signal is valid. The MII transmit enable signal is output by the MAC layer through the MII interface. In the MII clock domain, the third packet signal under the MII clock domain is written into the second FIFO buffer. In the system clock domain, based on the third packet signal, the fourth packet signal is read from the second FIFO buffer and split into the fourth packet signal to obtain the MII transmit enable signal and the MII transmit data signal under the system clock domain.

[0012] In one possible implementation of the first aspect, after bit-concatenating the RGMII received data signal and the RGMII receive enable signal to obtain the first packet signal, the method further includes:

[0013] When the RGMII receive enable signal output by the PHY layer is detected to change from an effective signal to an invalid signal, a first frame end indication signal is generated; in response to the first frame end indication signal, N first additional packet signals are generated, where N is a positive integer greater than or equal to 2, and each of the N first additional packet signals includes at least two all-zero data; after writing the first packet signals into the first FIFO buffer in the RGMII clock domain, the method further includes: writing the N additional packet signals into the first FIFO buffer sequentially in the RGMII clock domain.

[0014] In one possible implementation of the first aspect, after bit-concatenating the MII transmit data signal and the MII transmit enable signal to obtain the third packet signal, the method further includes:

[0015] When the MII transmit enable signal output by the MAC layer is detected to change from an effective signal to an invalid signal, a second frame end indication signal is generated; in response to the second frame end indication signal, M second additional packet signals are generated, where M is a positive integer greater than or equal to 2, and each of the M second additional packet signals includes at least two all-zero data; after writing the third packet signal in the MII clock domain into the second FIFO buffer in the MII clock domain, the method further includes: writing the M second additional packet signals into the second FIFO buffer sequentially in the MII clock domain.

[0016] In one possible implementation of the first aspect, reading the second packet signal from the first FIFO buffer includes:

[0017] When the amount of data in the first FIFO buffer is greater than or equal to the first start-read threshold, the second packet signal is read from the first FIFO buffer; when the amount of data in the first FIFO buffer is less than or equal to the first stop-read threshold, the reading of the second packet signal from the first FIFO buffer ends, and the first start-read threshold is greater than the first stop-read threshold.

[0018] In one possible implementation of the first aspect, reading the fourth packet signal from the second FIFO buffer includes:

[0019] When the amount of data in the second FIFO buffer is greater than or equal to the second start-read threshold, the fourth packet signal is read from the second FIFO buffer; when the amount of data in the second FIFO buffer is less than or equal to the second stop-read threshold, the reading of the second packet signal from the second FIFO buffer ends, and the second start-read threshold is greater than the second stop-read threshold.

[0020] Secondly, embodiments of this application provide a communication interface conversion device, comprising:

[0021] The receive conversion module is used to acquire the RGMII receive data signal, which is output by the PHY layer through the RGMII interface. The RGMII receive data signal is converted into the MII receive data signal through the first FIFO buffer. The write clock of the first FIFO buffer is the RGMII clock, and the read clock of the first FIFO buffer is the system clock.

[0022] The transmission conversion module is used to acquire the MII transmission data signal, which is output by the MAC layer through the MII interface. Through the second FIFO buffer, it converts the MII transmission data signal under the MII clock domain into the MII transmission data signal under the system clock domain. The write clock of the second FIFO buffer is the MII clock, and the read clock of the second FIFO buffer is the system clock. Through the output double data rate register ODDR, it generates the RGMII transmission clock based on the system clock, and converts the MII transmission data signal under the system clock domain into the RGMII transmission data signal based on the RGMII transmission clock.

[0023] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in any one of the first aspects above.

[0024] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in any one of the first aspects above.

[0025] Fifthly, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to perform the method described in any one of the first aspects above.

[0026] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0027] The beneficial effects of the embodiments of this application compared with the prior art are:

[0028] Since the write clock of the first FIFO buffer's write port is the RGMII clock and the read clock of the read port is the system clock, data is written to the first FIFO buffer at a dual data rate in the RGMII clock domain and read from the first FIFO buffer at a single data rate in the system clock domain. In this way, the dual data rate data stream can be converted into a single data rate data stream, realizing the conversion of the RGMII receive data signal into the MII receive data signal. This enables the conversion of RGMII interface data to MII interface data, allowing the MAC layer to successfully receive data from the PHY layer. Furthermore, during the data transmission process from the PHY layer to the MAC layer, data loss and data errors can be avoided, ensuring the reliability of system communication.

[0029] Furthermore, since the write clock of the write port of the second FIFO buffer is the MII clock and the read clock of the read port is the system clock, MII data is written to the second FIFO buffer in the MII clock domain and read from the second FIFO buffer in the system clock domain. In this way, MII data in the system clock domain can be obtained. Then, ODDR can be used to generate the RGMII transmit clock based on the system clock, and the MII data in the system clock domain can be converted into RGMII data based on the RGMII transmit clock. The aforementioned process can convert single data rate data into dual data rate data stream, realize the conversion of MII transmit data signal into RGMII transmit data signal, thereby realizing the conversion of MII interface data to RGMII interface data, enabling the PHY layer to receive data smoothly from the MAC layer, and avoiding data loss, data errors and other situations during the data transmission process from the MAC layer to the PHY layer, thus ensuring the reliability of system communication. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a scenario for a communication interface conversion method provided in an embodiment of this application;

[0032] Figure 2 This is a flowchart illustrating a communication interface conversion method provided in an embodiment of this application;

[0033] Figure 3This is a flowchart illustrating a communication interface conversion method provided in an embodiment of this application;

[0034] Figure 4 This is a flowchart illustrating a communication interface conversion method provided in an embodiment of this application;

[0035] Figure 5 This is a flowchart illustrating a communication interface conversion method provided in an embodiment of this application;

[0036] Figure 6 This is a flowchart illustrating a communication interface conversion method provided in an embodiment of this application;

[0037] Figure 7 This is a schematic diagram of the communication interface conversion device provided in the embodiments of this application;

[0038] Figure 8 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0039] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0040] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0041] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0042] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0043] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0045] For ease of understanding, the examples provided are for reference only and are related to the concepts in the embodiments of this application.

[0046] 1. Media Independent Interface (MII): MII is a standard interface defined by the IEEE 802.3 standard between the Ethernet MAC layer and PHY layer. Data width: 4 bits (10 / 100Mbps). Clock frequency: 25MHz (100M mode). Features: Independent transmit and receive paths, using separate clocks and control signals.

[0047] 2. Reduced Gigabit Media Independent Interface (RGMII): RGMII is a high-speed, simplified version of MII, supporting 10 / 100 / 1000 Mbps rates. It achieves higher integration by reducing the number of pins (from approximately 16 in MII to 12). In 100Mbps mode: it uses a 25MHz clock and employs dual data rates (DDR mode—i.e., sampling on both the rising and falling edges of the clock, but transmitting the same data). Control signals (such as TX_CTL / RX_CTL) multiplex enable and error indication functions.

[0048] 3. First-In, First-Out (FIFO): A data buffer where the data stored first is read out first. It is commonly used for processing data streams or cross-clock domain synchronization. The write side uses one clock domain (such as the RGMII clock), and the read side uses another clock domain (such as the system clock). FIFO acts as a shared buffer, safely isolating these two clock domains.

[0049] This application provides a communication interface conversion method, apparatus, device, and readable storage medium. The method is applied to a scenario where MII interface data of the MAC layer and RGMII interface data of the PHY layer are converted bidirectionally. Specifically, it includes: converting RGMII data signals received from the RGMII interface of the PHY layer into MII data signals for transmission to the MAC layer, and converting MII data signals received from the MII interface of the MAC layer into RGMII data signals for transmission to the PHY layer.

[0050] This method can be applied to embedded systems of field-programmable gate arrays (FPGAs) that require Ethernet interface conversion, such as industrial automation, network communication equipment, intelligent transportation, power systems, and security monitoring, to solve the interconnection problem between the MII interface of the MAC layer and the RGMII interface of the PHY layer.

[0051] This method can be implemented using electronic devices, such as FPGAs, application-specific integrated circuits (SICs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), etc. This application does not limit the type of electronic device.

[0052] It should be noted that in some possible implementations, the electronic device may also be referred to as a terminal device (station), user equipment (UE), etc., and the embodiments of this application do not limit this.

[0053] Based on the above scenario description, the communication interface conversion method provided in the embodiments of this application will be described in detail below, taking electronic devices as the executing entity.

[0054] It should be understood that electronic devices include a MAC layer and a PHY layer. The MAC layer supports the MII interface, and the PHY layer supports the RGMII interface. The MAC layer can send data to the PHY layer, and the PHY layer can receive data sent by the MAC layer. Similarly, the PHY layer can send data to the MAC layer, and the MAC layer can receive data sent by the PHY layer.

[0055] Please see Figure 1 , Figure 1 A flowchart illustrating a communication interface conversion method according to an embodiment of this application is shown. Figure 1 As shown, the communication interface conversion method provided in this application may include:

[0056] S101. Obtain the RGMII received data signal. The RGMII received data signal is output by the PHY layer through the RGMII interface.

[0057] In RGMII, the received data signal is typically data that the PHY layer obtains from the physical link (such as the network) and needs to send to the MAC layer. In other words, the RGMII received data signal is data that the MAC layer needs to receive from the PHY layer. The "receive" in RGMII is relative to the MAC layer, not the PHY layer.

[0058] Since the PHY layer supports the RGMII interface, the data sent from the PHY layer to the MAC layer is in RGMII format. In other words, the RGMII received data signal is in RGMII format.

[0059] S102. The RGMII received data signal is converted into the MII received data signal through the first FIFO buffer. The write clock of the first FIFO buffer is the RGMII clock, and the read clock of the first FIFO buffer is the system clock.

[0060] It should be understood that RGMII data signals typically use dual data rate timing, while MII data signals use single data rate timing. For example, at 100 Mbps, the RGMII receive data signal uses a 25 MHz clock, transmitting the same 4 bits of data on both the rising and falling edges of the clock; at 100 Mbps, the MII signal also uses a 25 MHz clock, but transmits 4 bits of data only once on the rising edge of the clock.

[0061] Therefore, for the MII interface, it may not be possible to directly receive RGMII data signals, and for the RGMII interface, it may not be possible to directly receive MII data signals, requiring corresponding cross-clock conversion.

[0062] The RGMII clock is typically 25MHz. The system clock, a global clock signal generated by the internal clock management circuitry of the electronic device (such as a phase-locked loop (PLL)), is used to provide a synchronization timing reference and is usually 50MHz or 100MHz. Since the RGMII clock is provided by an external PHY layer and is asynchronous with the internal system clock of the electronic device, directly using the system clock to sample the RGMII received data signal may lead to metastability due to cross-clock domain issues, resulting in data errors.

[0063] The first FIFO buffer is a data buffer and clock domain isolation area, which can serve as a cross-clock data channel to temporarily store data and is often used for cross-clock domain transmission. The first FIFO buffer has a write port and a read port. The clock of the write port is the write clock, and the clock of the read port is the read clock. The system clock corresponding to the read clock is the global clock used by the internal logic of the electronic device.

[0064] For the write port, the electronic device can write the RGMII received data signal to the first FIFO buffer at a double data rate under the drive of the RGMII clock, thus enabling secure sampling of the RGMII received data signal. For the read port, the electronic device can read the RGMII received data signal from the first FIFO buffer at a single data rate under the drive of the system clock, thus generating a stable MII received data signal.

[0065] Through the above process, the first FIFO buffer separates data read by the write clock and data read by the read clock. Data can be written according to the rhythm of the RGMII clock through the write port, and data can be read according to the rhythm of the system clock through the read port. In this way, the electronic device can realize cross-clock conversion of RGMII format data to obtain MII format data, that is, convert the RGMII received data signal into the MII received data signal.

[0066] For example, this process can be understood as follows: writing based on the RGMII clock and reading based on the system clock, converting a dual data rate stream that transmits 4 bits of data twice in one clock cycle into a 4-bit data stream that transmits once in one clock cycle, thereby converting a dual data rate data signal into a single data rate data signal.

[0067] It should be noted that the PHY layer can send data to the MAC layer. The above describes the process of converting the RGMII receive data signal output by the PHY layer through the RGMII interface into the MII receive data signal. Converting the RGMII receive data signal output by the PHY layer into the MII receive data signal makes it easier for the MAC layer of the MII interface to receive the data.

[0068] S103. Obtain the MII transmit data signal. The MII transmit data signal is output by the MAC layer through the MII interface.

[0069] In this context, the MII data transmission signal typically represents data that the MAC layer receives from an upper layer (such as the application layer) and needs to send to the PHY layer. In other words, the MII data transmission signal represents data that the MAC layer needs to send to the PHY layer. The transmission in the MII data transmission signal is relative to the MAC layer, not the PHY layer.

[0070] Because the MAC layer supports the MII interface, the data sent from the MAC layer to the PHY layer is in MII format. In other words, the MII sends data signals in MII format.

[0071] S104. Through the second FIFO buffer, the MII transmit data signal under the MII clock domain is converted into the MII transmit data signal under the system clock domain. The write clock of the second FIFO buffer is the MII clock, and the read clock of the second FIFO buffer is the system clock.

[0072] Based on the above description, MII data signals typically use single-data-rate timing. RGMII transmit data signals use dual-data-rate timing. Therefore, for the MII interface, it may not be possible to directly receive RGMII data signals, and for the RGMII interface, it may not be possible to directly receive MII data signals, requiring corresponding cross-clock conversion.

[0073] Since the MII clock is provided by the MAC layer and is asynchronous with the system clock inside the electronic device, if the system clock is used directly to sample the MII data signal, metastability may occur due to cross-clock domain, resulting in data errors.

[0074] Similar to the first FIFO buffer, the second FIFO buffer is a data buffer and clock domain isolation area. It can serve as a cross-clock data channel to temporarily store data and is often used for cross-clock domain transmission. The second FIFO buffer has a write port and a read port. The clock of the write port is the write clock, and the clock of the read port is the read clock. The system clock corresponding to the read clock is the global clock used by the internal logic of the electronic device.

[0075] For the write port, the electronic device can write the MII transmit data signal to the second FIFO buffer at a single data rate under the drive of the MII clock, thus enabling secure sampling of the MII transmit data signal. For the read port, the electronic device can read the MII transmit data signal from the second FIFO buffer at a single data rate under the drive of the system clock, thus generating a stable MII transmit data signal under the system clock domain.

[0076] Through the above process, the second FIFO buffer separates data read by the write clock and data read by the read clock. Data can be written according to the rhythm of the MII clock through the write port, and data can be read according to the rhythm of the system clock through the read port. In this way, electronic devices can realize cross-clock conversion of MII format data.

[0077] S105. By using the output double data rate register (ODDR), an RGMII transmit clock is generated based on the system clock, and the MII transmit data signal under the system clock domain is converted into an RGMII transmit data signal based on the RGMII transmit clock.

[0078] Based on S104, the electronic device can obtain the MII transmit data signal under the system clock domain. The electronic device inputs the MII transmit data signal under the system clock domain into ODDR. ODDR can output the RGMII transmit data signal with dual data rate through the RGMII transmit clock.

[0079] It should be noted that the MAC layer can send data to the PHY layer. The above describes the process of converting the MII data signal output by the MAC layer through the MII interface into an RGMII data signal. Converting the MII data signal output by the MAC layer into an RGMII data signal makes it easier for the PHY layer of the RGMII interface to receive the data.

[0080] It should be noted that, as Figure 2 As shown, the MAC layer of an electronic device has multiple channels or multiple interfaces. The electronic device may include a top-level module, at least one receive conversion module, and at least one transmit conversion module. The top-level module has a configurable MAC interface quantity parameter, which is set by the designer before compilation to indicate the number of supported MAC channels or interfaces. By adjusting the number of channels or interfaces, that number of receive conversion modules and transmit conversion modules can be generated. The top-level module is used to manage at least one receive conversion module and at least one transmit conversion module.

[0081] Continue to combine Figure 2 For any one of the receiving conversion modules, the receiving conversion module includes a data writing control unit (which can be called the first data writing control unit for easy distinction), a FIFO buffer (first FIFO buffer), and a read FIFO control unit (which can be called the first read FIFO control unit). The data writing control unit is used to acquire the RGMII received data signal and write the RGMII received data signal into the first FIFO buffer. The read FIFO control unit is used to read the MII received data signal from the first FIFO buffer.

[0082] For any one of the transmission conversion modules, the transmission conversion module also includes a data write control unit (which can be called the second data write control unit for easy distinction), a FIFO buffer (second FIFO buffer), and a read FIFO control unit (which can be called the second read FIFO control unit). The data write control unit is used to acquire the MII transmission data signal and write the MII reception data signal into the second FIFO buffer. The read FIFO control unit is used to read the RGMII reception data signal from the second FIFO buffer.

[0083] In this embodiment, since the write clock of the write port of the first FIFO buffer is the RGMII clock and the read clock of the read port is the system clock, data is written to the first FIFO buffer at a dual data rate in the RGMII clock domain and read from the first FIFO buffer at a single data rate in the system clock domain. Thus, this process can convert the dual data rate data stream into a single data rate data stream, thereby converting the RGMII received data signal into the MII received data signal. This enables the conversion of RGMII interface data to MII interface data, allowing the MAC layer to successfully receive data from the PHY layer. Furthermore, during the data transmission process from the PHY layer to the MAC layer, data loss and data errors can be avoided, ensuring the reliability of system communication.

[0084] Furthermore, since the write clock of the write port of the second FIFO buffer is the MII clock and the read clock of the read port is the system clock, MII data is written to the second FIFO buffer in the MII clock domain and read from the second FIFO buffer in the system clock domain. In this way, MII data in the system clock domain can be obtained. Then, ODDR can be used to generate the RGMII transmit clock based on the system clock, and the MII data in the system clock domain can be converted into RGMII data based on the RGMII transmit clock. The aforementioned process can convert single data rate data into dual data rate data stream, realize the conversion of MII transmit data signal into RGMII transmit data signal, thereby realizing the conversion of MII interface data to RGMII interface data, enabling the PHY layer to receive data smoothly from the MAC layer, and avoiding data loss, data errors and other situations during the data transmission process from the MAC layer to the PHY layer, thus ensuring the reliability of system communication.

[0085] Furthermore, when the MAC layer has multiple channels or multiple interfaces, the above solution can be used for any one of the interfaces, making it suitable for multi-channel or variable-rate scenarios.

[0086] based on Figure 1 and Figure 2According to the description of the embodiment shown, the electronic device can realize writing and reading in the first FIFO buffer by splicing the RGMII receive data signal and the RGMII receive enable signal.

[0087] Below, in conjunction with Figure 3 This paper details the specific implementation process of the communication interface conversion method described in this application.

[0088] Please see Figure 3 , Figure 3 A flowchart illustrating a communication interface conversion method according to an embodiment of this application is shown. Figure 3 As shown, the communication interface conversion method provided in this application includes:

[0089] S201. The RGMII received data signal and the RGMII received enable signal are bit-concatenated to obtain the first packet signal. The RGMII received enable signal is used to indicate whether the RGMII received data signal is a valid signal. The RGMII received enable signal is output by the PHY layer through the RGMII interface.

[0090] It should be understood that when writing data to the first FIFO buffer, if only data is written, the first FIFO buffer cannot determine whether the current data is a valid byte within the frame or invalid padding between frames. Therefore, it is necessary to package the data and the validity signal into a whole and write them together into the first FIFO buffer to ensure that the two do not become disconnected when crossing clock domains.

[0091] Bit splicing is an operation in a hardware description language used to connect multiple signals of different widths in sequence to form a new, wider signal.

[0092] The data width of the RGMII received data signal is typically 4 bits, which can be represented as rxd[3:0]. In 100Mbps operating mode, for the RGMII received data signal, the same 4 bits of data are output on both the rising and falling edges of the 25MHz clock.

[0093] The RGMII receive enable signal is usually a 1-bit signal, which can be represented as rx_ctl. When rx_ctl=1, it means that the corresponding rxd[3:0] is a valid signal. When rx_ctl=0, it means that the corresponding rxd[3:0] is an invalid signal (such as inter-frame interval, idle).

[0094] Based on this, by bit-concatenating the RGMII receive data signal and the RGMII receive enable signal, a 5-bit data signal can be obtained, which is the first packet signal.

[0095] In the first packet signal, the highest bit (4th bit) is the RGMII receive enable signal, and the lower 4 bits (3rd to 0th bits) are the RGMII receive data signals.

[0096] For example, if the RGMII receive data signal is 1101 and the RGMII receive enable signal is 1 (indicating that 1101 is a valid signal), then the first packet signal is 1_1101.

[0097] For example, if the RGMII receives data signal xxxx and the RGMII receive enable signal is 0 (indicating that xxxx is an invalid signal), then the first packet signal is 0_xxxx.

[0098] Based on the above description, bit-concatenating the RGMII receive data signal and the RGMII receive enable signal ensures that the RGMII receive data signal and the RGMII receive enable signal can be written into the first FIFO buffer as an atomic unit, and the corresponding relationship is maintained during reading to avoid data misinterpretation. S202, In the RGMII clock domain, the first packet signal is written into the first FIFO buffer.

[0099] As described above, the first FIFO buffer has a write port and a read port. The clock of the write port is the write clock, which is the RGMII clock. Therefore, the electronic device can write the first packet signal to the first FIFO buffer through the write port under the drive of the RGMII clock.

[0100] S203. In the system clock domain, based on the first packet signal, the second packet signal is read from the first FIFO buffer, and the second packet signal is split to obtain the MII receive enable signal and the MII receive data signal.

[0101] As described above, the first FIFO buffer has a write port and a read port. The clock of the read port is the read clock, which is the system clock. Therefore, the electronic device can read the second packet signal from the first FIFO buffer based on the first packet signal under the drive of the system clock.

[0102] The second package signal is usually split bit by bit, separating the most significant bit from the other bits.

[0103] Based on the above description, it can be seen that the data bit width of the RGMII receive data signal is usually 4 bits, and the RGMII receive enable signal is usually 1 bit. The RGMII receive data signal is 4 bits. When concatenating bits, the highest bit (the 4th bit) is the RGMII receive enable signal, and the lower 4 bits (bits 3-0) are the RGMII receive data signal. Therefore, when splitting, the highest bit and the lower 4 bits can be separated to obtain a 4-bit wide MII receive data signal and a 1-bit MII receive enable signal.

[0104] For example, the second packet signal is 1_1101, which, after being split, includes the MII receive data signal 1101 and the MII receive enable signal 1.

[0105] For example, the second packet signal is 0_xxxx, which, after being split, includes the MII receive data signal xxxx and the MII receive enable signal 0.

[0106] In some embodiments, reading the second packet signal from the first FIFO buffer includes: reading the second packet signal from the first FIFO buffer when the amount of data in the first FIFO buffer is greater than or equal to a first start-read threshold; and stopping reading the second packet signal from the first FIFO buffer when the amount of data in the first FIFO buffer is less than or equal to a first stop-read threshold, wherein the first start-read threshold is greater than the first stop-read threshold.

[0107] The start-read threshold is used to prevent insufficient data in the first FIFO buffer. By using the start-read threshold, it can be ensured that there is enough data in the first FIFO buffer when reading begins, guaranteeing that data can be continuously read from the first FIFO buffer when reading is started, so that the read second packet signal is a stable and uninterrupted Ethernet frame.

[0108] The stop-read threshold is used to prevent situations where the amount of data in the first FIFO buffer is too small. By using the stop-read threshold, sufficient time is allowed to re-store data in the first FIFO buffer, preventing the first FIFO buffer from becoming empty.

[0109] Based on this, when the amount of data in the first FIFO buffer is greater than or equal to the start-read threshold, the second packet signal is read from the first FIFO buffer; when the amount of data in the first FIFO buffer is less than or equal to the stop-read threshold, the reading of the second packet signal from the first FIFO buffer ends. This balances the read and write rates, prevents the first FIFO buffer from being too empty or too full, and ensures the stability of the data flow across clock domains. In some embodiments, after bit-concatenating the RGMII receive data signal and the RGMII receive enable signal to obtain the first packet signal, the method further includes: generating a first frame end indication signal when the RGMII receive enable signal output by the PHY layer changes from an effective signal to an invalid signal; and generating N first additional packet signals in response to the first frame end indication signal, where N is a positive integer greater than or equal to 2, and each of the N first additional packet signals includes at least two all-zero data.

[0110] In some embodiments, after writing the first packet signal into the first FIFO buffer in the RGMII clock domain, the method further includes: sequentially writing N additional packet signals into the first FIFO buffer in the RGMII clock domain.

[0111] For example, in the i-th clock cycle, the RGMII receive enable signal indicates that the RGMII receive data signal is valid, and in the (i+1)-th clock cycle, the RGMII receive enable signal indicates that the RGMII receive data signal is invalid. In this way, the electronic device can detect that the RGMII receive enable signal changes from valid to invalid, and can determine that the RGMII receive data signal in the i-th clock cycle is the end-of-frame data.

[0112] The first frame end indication signal is usually a 1-bit signal, but it can be a signal of any number of bits. This application does not limit this.

[0113] The N first additional packet signals typically refer to the first additional packet signals over N clock cycles.

[0114] It should be noted that at the read end of the first FIFO buffer, the validity of the data is usually determined based on the most significant bit (i.e., the enable signal) of the first signal packet read. If the first FIFO buffer happens to be empty at the end of the frame, the enable signal at the read end may abnormally remain at a high level (valid state), which will be mistakenly interpreted as the next data being valid as well, thus reading incorrect data and causing a short read error.

[0115] Thus, by appending N all-zero packets (N first append packet signals), it is ensured that even after the last valid signal is read, there are still N all-zero packets in the first FIFO buffer. The read logic continues to read these packets and detects that their highest bit is 0 (invalid), thereby preventing abnormal data reading at the read end.

[0116] In addition, combined again Figure 2 The description states that the first data writing control unit is used to acquire the RGMII receive data signal and the RGMII receive enable signal, and the first read FIFO control unit is also used to determine whether the amount of data in the first FIFO buffer is greater than or equal to the start read level threshold, and whether the amount of data in the first FIFO buffer is less than or equal to the stop read level threshold.

[0117] The receive conversion module also includes a frame tail detection unit (which can be called the first frame tail detection unit) and an MII timing generation unit (which can be called the first MII timing generation unit). The frame tail detection unit is used to monitor whether the RGMII receive enable signal output by the PHY layer changes from a valid signal to an invalid signal. The MII timing generation unit is used to split the second packet signal.

[0118] In this embodiment, the electronic device can perform bit-concatenation of the RGMII received data signal and the RGMII receive enable signal. This bit-concatenation operation packages the data signal and its validity indication signal into atomic units, ensuring strict synchronization between the two during subsequent cross-clock domain transmission and fundamentally avoiding data misjudgment caused by signal misalignment. Furthermore, employing a first FIFO buffer as the core of cross-clock domain processing effectively isolates asynchronous clock domains, prevents the propagation of metastability, and improves the system's reliability and stability.

[0119] based on Figure 3 According to the description of the embodiment shown, the electronic device can realize writing and reading in the second FIFO buffer by splicing the MII transmit data signal and the MII transmit enable signal.

[0120] Below, in conjunction with Figure 4 This paper details the specific implementation process of the communication interface conversion method described in this application.

[0121] Please see Figure 4 , Figure 4 A flowchart illustrating a communication interface conversion method according to an embodiment of this application is shown. Figure 4 As shown, the communication interface conversion method provided in this application includes:

[0122] S301. The MII transmit data signal and the MII transmit enable signal are bit-concatenated to obtain a third packet signal. The MII transmit enable signal is used to indicate whether the MII transmit data signal is a valid signal. The MII transmit enable signal is output by the MAC layer through the MII interface.

[0123] It should be understood that when writing data to the second FIFO buffer, if only data is written, the second FIFO buffer cannot determine whether the current data is a valid byte within the frame or invalid padding between frames. Therefore, it is necessary to package the data and the validity signal into a whole and write them together into the second FIFO buffer to ensure that the two do not become disconnected when crossing clock domains.

[0124] The data width of the MII data transmission signal is typically 4 bits, which can be represented as rxd[3:0]. In 100Mbps operating mode, for the MII data transmission signal, data is transmitted once on the rising edge of the 25MHz clock.

[0125] The MII transmit enable signal is usually a 1-bit signal, which can be represented as rx_ctl. When rx_ctl=1, it means that the corresponding rxd[3:0] is a valid signal. When rx_ctl=0, it means that the corresponding rxd[3:0] is an invalid signal (such as inter-frame interval, idle).

[0126] Based on this, by bit-concatenating the MII transmit data signal and the MII transmit enable signal, a 5-bit data signal can be obtained, which is the third packet signal.

[0127] In the third packet signal, the highest bit (the 4th bit) is the MII transmit enable signal, and the lower 4 bits (bits 3-0) are the MII transmit data signals.

[0128] For example, if the MII transmit data signal is 1101 and the MII transmit enable signal is 1 (indicating that 1101 is a valid signal), then the third packet signal is 1_1101.

[0129] For example, if the MII transmits data signal xxxx and the MII transmits enable signal 0 (indicating that xxxx is an invalid signal), then the third packet signal is 0_xxxx.

[0130] Based on the above description, by bit-concatenating the MII transmit data signal and the MII transmit enable signal, it can be ensured that the MII transmit data signal and the MII transmit enable signal can be written into the second FIFO buffer as an atomic unit, and the corresponding relationship is maintained when reading out, so as to avoid data misjudgment.

[0131] S302. In the RGMII clock domain, write the third packet signal under the MII clock domain into the second FIFO buffer.

[0132] Based on the above description, the second FIFO buffer has a write port and a read port. The clock of the write port is the write clock, which is the RGMII clock. Therefore, the electronic device can write the third packet signal to the second FIFO buffer through the write port under the drive of the RGMII clock.

[0133] S303. In the system clock domain, based on the third packet signal, the fourth packet signal is read from the second FIFO buffer, and the fourth packet signal is split to obtain the MII transmit enable signal and the MII transmit data signal in the system clock domain.

[0134] Based on the above description, the second FIFO buffer has a write port and a read port. The clock of the read port is the read clock, which is the system clock. Therefore, the electronic device can read the fourth packet signal from the second FIFO buffer based on the third packet signal under the drive of the system clock.

[0135] The fourth packet signal is usually split bit by bit, separating the most significant bit from the other bits.

[0136] Based on the above description, the data width of the MII transmit data signal is usually 4 bits, and the MII transmit enable signal is usually 1 bit. The MII transmit data signal is 4 bits. When concatenating bits, the highest bit (the 4th bit) is the MII transmit enable signal, and the lower 4 bits (bits 3-0) are the MII transmit data signal. Therefore, when splitting, the highest bit and the lower 4 bits can be separated to obtain the 4-bit wide MII transmit data signal and the 1-bit MII transmit enable signal.

[0137] For example, the fourth packet signal is 1_1101, which, after being split, includes the MII transmit data signal 1101 and the MII transmit enable signal 1.

[0138] For example, the fourth packet signal is 0_xxxx, which, after being split, includes the MII transmit data signal xxxx and the MII transmit enable signal 0.

[0139] In some embodiments, reading the fourth packet signal from the second FIFO buffer includes: reading the fourth packet signal from the second FIFO buffer when the amount of data in the second FIFO buffer is greater than or equal to a second start-read level threshold; and stopping reading the fourth packet signal from the second FIFO buffer when the amount of data in the second FIFO buffer is less than or equal to a stop-read level threshold, wherein the second start-read level threshold is greater than the second stop-read level threshold.

[0140] The details regarding reading the fourth packet signal from the second FIFO buffer can be found in the description of reading the second packet signal from the first FIFO buffer, and will not be repeated here.

[0141] In some embodiments, after bit-concatenating the MII transmit data signal and the MII transmit enable signal to obtain a third packet signal, the method further includes: generating a second frame end indication signal when the MII transmit enable signal output by the MAC layer changes from an effective signal to an invalid signal; and generating M second additional packet signals in response to the second frame end indication signal, where M is a positive integer greater than or equal to 2, and each of the M second additional packet signals includes at least two all-zero data.

[0142] In some embodiments, after writing the first packet signal into the first FIFO buffer in the RGMII clock domain, the method further includes: sequentially writing M second additional packet signals into the second FIFO buffer in the RGMII clock domain.

[0143] The foregoing content can be found in the description of the process of bit-concatenating the RGMII receive data signal and the RGMII receive enable signal to obtain the first packet signal, and the process of writing the first packet signal into the first FIFO buffer in the RGMII clock domain. These details will not be repeated here.

[0144] In addition, combined again Figure 2 The description states that the second data write control unit is used to acquire the MII transmit data signal and the MII transmit enable signal, and the second read FIFO control unit is also used to determine whether the amount of data in the second FIFO buffer is greater than or equal to the second start read level threshold, and whether the amount of data in the second FIFO buffer is less than or equal to the second stop read level threshold.

[0145] The transmission conversion module also includes a frame tail detection unit (which can be called the second frame tail detection unit) and an RGMII timing generation unit (which can be called the second MII timing generation unit). The frame tail detection unit is used to monitor whether the MII transmission enable signal output by the MAC layer changes from a valid signal to an invalid signal. The RGMII timing generation unit is used to split the fourth packet signal.

[0146] In this embodiment, the electronic device can perform bit-concatenation of the MII transmit data signal and the MII transmit enable signal. This bit-concatenation operation packages the data signal and its validity indication signal into atomic units, ensuring strict synchronization between the two during subsequent cross-clock domain transmission and fundamentally avoiding data misjudgment caused by signal misalignment. Furthermore, employing a second FIFO buffer as the core of cross-clock domain processing effectively isolates asynchronous clock domains, prevents the propagation of metastability, and improves the system's reliability and stability.

[0147] Based on the above description, in a specific embodiment, the above solution is illustrated in conjunction with specific modules.

[0148] For the receive conversion module, such as Figure 5 As shown, it can include two parts: the write FIFO processing flow (RGMII_RXC clock domain, also known as the RGMII clock domain mentioned above), and the read FIFO processing flow (local 25M clock domain). Writing to the FIFO can be understood as writing signals into the first FIFO buffer, and reading from the FIFO can be understood as reading signals from the first FIFO buffer.

[0149] The FIFO writing process includes: waiting for the RGMII receive data signal input; checking if the RGMII receive enable signal (which can be represented as RGMII_RXCTL) is 1; if it is 0, it is a low voltage level, indicating that the signal is invalid, and continuing to wait for the RGMII signal input; if it is 1, it is a high level, indicating that the signal is valid, and generating the FIFO signal (which can be understood as the first packet signal mentioned above); checking if it is the end of the RGMII receive data signal (by checking if the RGMII receive enable signal changes from a valid signal to an invalid signal); if so, performing frame end zero data padding (for example, writing all zero data to the FIFO twice); thus, the write operation ends.

[0150] in, Figure 5 In the write FIFO processing flow, Wr_fifo=1 is an enable signal, indicating that a write operation is performed to the first FIFO buffer in the current clock cycle. Wr_fifo_data represents the signal written to the first FIFO buffer, which includes 5 bits of the first packet signal. Wr_fifo_data={RGMII_RXCTL,RGMII_RXD} indicates that the signal written to the first FIFO buffer includes the first packet signal obtained by concatenating the RGMII receive data signal and the RGMII receive enable signal. RGMII_RXCTL represents the RGMII receive enable signal, and RGMII_RXD represents the RGMII receive data signal. The FIFO read process includes: checking whether the FIFO level in the first FIFO buffer is greater than or equal to the first read start threshold (e.g., 3); if it is greater than or equal to, then start the FIFO read operation and obtain the MII receive data signal; it also needs to determine whether the level is less than or equal to the first stop read threshold (e.g., 1); if the level is less than or equal to the stop read threshold, then stop the FIFO read operation; thus the read operation ends.

[0151] in, Figure 5 In the FIFO read processing flow, MII_rd_fifo_q[4] represents the signal read from the first FIFO buffer, including 5 bits, from bit 4 to bit 0. Bit 4 is the MII receive enable signal. MII_RXD=rd_fifo_q[3:0] indicates that the 4-bit MII receive data signal is taken from the lower 4 bits of the 5-bit signal, including bit 3 to bit 0. For the transmit conversion module, such as Figure 6 As shown, it can include two parts: the write FIFO processing flow (MII clock domain) and the read FIFO processing flow (local 25M clock domain). Writing to the FIFO can be understood as writing signals into the first FIFO buffer, and reading from the FIFO can be understood as reading signals from the first FIFO buffer.

[0152] The FIFO writing process includes: waiting for the MII receive data signal input; checking if the MII receive enable signal (which can be represented as MII_RXCTL) is 1; if it is 0, it is a low frequency, indicating that the signal is invalid, and continuing to wait for the MII signal input; if it is 1, it is a high level, indicating that the signal is valid, and generating the FIFO signal (which can be understood as the third packet signal mentioned above); checking if it is the end of the MII receive data signal (by checking if the RGMII receive enable signal changes from a valid signal to an invalid signal); if so, performing frame end zero data padding (for example, writing all zero data to the FIFO twice); thus, the write operation ends.

[0153] in, Figure 6 In the write FIFO processing flow, the descriptions of Wr_fifo=1 and Wr_fifo_data={MII_RXCTL,MII_RXD} are... Figure 5 The description is similar to that in the text, so I will not go into details here.

[0154] The FIFO read process includes: checking whether the FIFO level in the second FIFO buffer is greater than or equal to the first read start threshold (e.g., 3); if it is greater than or equal to, then start the FIFO read operation and obtain the RGMII receive data signal; it also needs to determine whether the level is less than or equal to the second read stop threshold (e.g., 1); if the level is less than or equal to the read stop threshold, then stop the FIFO read operation; thus the read operation ends.

[0155] in, Figure 6 In the FIFO read processing flow, the descriptions of RGMII_rd_fifo_q[4] and RGMII_RXD=rd_fifo_q[3:0] are consistent with... Figure 5 The description is similar to that in the text, so I will not go into details here.

[0156] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0157] Corresponding to the communication interface conversion method described in the above embodiments, Figure 7 A structural block diagram of the communication interface conversion device provided in the embodiments of this application is shown. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0158] Reference Figure 7 The device includes:

[0159] The receiving conversion module 401 is used to acquire the RGMII received data signal, which is output by the PHY layer through the RGMII interface; through the first first-in-first-out FIFO buffer, the RGMII received data signal is converted into the MII received data signal. The write clock of the first FIFO buffer is the RGMII clock, and the read clock of the first FIFO buffer is the system clock.

[0160] The transmission conversion module 402 is used to acquire the MII transmission data signal, which is output by the MAC layer through the MII interface; through the second FIFO buffer, it converts the MII transmission data signal under the MII clock domain into the MII transmission data signal under the system clock domain. The write clock of the second FIFO buffer is the MII clock, and the read clock of the second FIFO buffer is the system clock; by outputting the double data rate register ODDR, it generates the RGMII transmission clock based on the system clock, and based on the RGMII transmission clock, it converts the MII transmission data signal under the system clock domain into the RGMII transmission data signal.

[0161] In some embodiments, the receiving conversion module 401 is specifically used for:

[0162] The RGMII receive data signal and the RGMII receive enable signal are bit-concatenated to obtain the first packet signal. The RGMII receive enable signal is used to indicate whether the RGMII receive data signal is valid. The RGMII receive enable signal is output by the PHY layer through the RGMII interface. In the RGMII clock domain, the first packet signal is written into the first FIFO buffer. In the system clock domain, based on the first packet signal, the second packet signal is read from the first FIFO buffer and split into the MII receive enable signal and the MII receive data signal.

[0163] In some embodiments, the transmission conversion module 402 is specifically used for:

[0164] The MII transmit data signal and the MII transmit enable signal are bit-concatenated to obtain the third packet signal. The MII transmit enable signal is used to indicate whether the MII transmit data signal is valid. The MII transmit enable signal is output by the MAC layer through the MII interface. In the MII clock domain, the third packet signal under the MII clock domain is written into the second FIFO buffer. In the system clock domain, based on the third packet signal, the fourth packet signal is read from the second FIFO buffer and split into the fourth packet signal to obtain the MII transmit enable signal and the MII transmit data signal under the system clock domain.

[0165] In some embodiments, the receiving conversion module 401 is specifically used for:

[0166] When the RGMII receive enable signal output by the PHY layer is detected to change from an effective signal to an invalid signal, a first frame end indication signal is generated; in response to the first frame end indication signal, N first additional packet signals are generated, where N is a positive integer greater than or equal to 2, and each of the N first additional packet signals includes at least two all-zero data; in the RGMII clock domain, the N additional packet signals are sequentially written into the first FIFO buffer.

[0167] In some embodiments, the transmission conversion module 402 is specifically used for:

[0168] When the MII transmit enable signal output by the MAC layer is detected to change from an effective signal to an invalid signal, a second frame end indication signal is generated; in response to the second frame end indication signal, M second additional packet signals are generated, where M is a positive integer greater than or equal to 2, and each of the M second additional packet signals includes at least two all-zero data; in the RGMII clock domain, the M second additional packet signals are sequentially written into the second FIFO buffer.

[0169] In some embodiments, the receiving conversion module 401 is specifically used for:

[0170] When the amount of data in the first FIFO buffer is greater than or equal to the first start-read threshold, the second packet signal is read from the first FIFO buffer; when the amount of data in the first FIFO buffer is less than or equal to the first stop-read threshold, the reading of the second packet signal from the first FIFO buffer ends, and the first start-read threshold is greater than the first stop-read threshold.

[0171] In some embodiments, the transmission conversion module 402 is specifically used for:

[0172] When the amount of data in the second FIFO buffer is greater than or equal to the second start-read threshold, the fourth packet signal is read from the second FIFO buffer; when the amount of data in the second FIFO buffer is less than or equal to the second stop-read threshold, the reading of the second packet signal from the second FIFO buffer ends, and the second start-read threshold is greater than the second stop-read threshold.

[0173] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0174] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0175] This application also provides an electronic device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above method embodiments.

[0176] For example, this application also provides a schematic diagram of the structure of an electronic device. Figure 8 As shown, the electronic device 500 includes a processor 501, a memory 502, a communication interface 503, and a bus 504. The processor 501, memory 502, and communication interface 503 communicate via the bus 504, or via other means such as wireless transmission. The memory 502 stores instructions, and the processor 501 executes the instructions stored in the memory 502. The memory 502 stores program code 5021, and the processor 501 can call the program code 5021 stored in the memory 502 to execute the methods described in the above embodiments.

[0177] It should be understood that in this application, processor 501 can be a CPU, or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor, etc.

[0178] The memory 502 may include read-only memory and random access memory, and provides instructions and data to the processor 501. The memory 502 may also include non-volatile random access memory. The memory 502 may be volatile memory or non-volatile memory, or may include both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0179] In addition to the data bus, the 504 bus may also include a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 8 The general designated all buses as Bus 504.

[0180] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0181] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the above-described method embodiments.

[0182] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0183] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0184] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0185] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0186] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0187] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A communication interface conversion method, characterized in that, Applied to electronic devices, wherein the Media Access Control (MAC) layer of the electronic device supports a Media Independent Interface (MII) and the Physical PHY layer supports a Simplified Gigabit Media Independent Interface (RGMII), the method includes: Acquire the RGMII received data signal, which is output by the PHY layer through the RGMII interface; The RGMII received data signal is converted into an MII received data signal through a first FIFO buffer. The write clock of the first FIFO buffer is the RGMII clock, and the read clock of the first FIFO buffer is the system clock; and, Acquire the MII transmit data signal, which is output by the MAC layer through the MII interface; The MII transmit data signal and the MII transmit enable signal are bit-concatenated to obtain a third packet signal. The third packet signal is written into the second FIFO buffer in the MII clock domain. When the signal frame of the MII transmit data signal is detected to end, M second additional packet signals are generated and written into the second FIFO buffer in the MII clock domain. The write clock of the second FIFO buffer is the MII clock, and the read clock of the second FIFO buffer is the system clock. M is a positive integer greater than or equal to 2. In the system clock domain, based on the third packet signal, the fourth packet signal is read from the second FIFO buffer, and the fourth packet signal is split to obtain the MII transmit enable signal and the MII transmit data signal in the system clock domain; By outputting the double data rate register ODDR, an RGMII transmit clock is generated based on the system clock, and the MII transmit data signal under the system clock domain is converted into an RGMII transmit data signal based on the RGMII transmit clock.

2. The method as described in claim 1, characterized in that, The step of converting the RGMII received data signal into an MII received data signal through the first FIFO buffer includes: The RGMII received data signal and the RGMII received enable signal are bit-concatenated to obtain the first packet signal. The RGMII received enable signal is used to indicate whether the RGMII received data signal is a valid signal. The RGMII received enable signal is output by the PHY layer through the RGMII interface. In the RGMII clock domain, the first packet signal is written into the first FIFO buffer; In the system clock domain, based on the first packet signal, the second packet signal is read from the first FIFO buffer, and the second packet signal is split to obtain the MII receive enable signal and the MII receive data signal.

3. The method as described in claim 1, characterized in that, The MII transmit enable signal is used to indicate whether the MII transmit data signal is a valid signal. The MII transmit enable signal is output by the MAC layer through the MII interface.

4. The method as described in claim 2, characterized in that, After bit-concatenating the RGMII received data signal with the RGMII receive enable signal to obtain the first packet signal, the method further includes: When the RGMII receive enable signal output by the PHY layer changes from an effective signal to an invalid signal, a first frame end indication signal is generated. In response to the first frame end indication signal, N first additional packet signals are generated, where N is a positive integer greater than or equal to 2, and each of the N first additional packet signals includes at least two all-zero data. After writing the first packed signal into the first FIFO buffer in the RGMII clock domain, the method further includes: In the RGMII clock domain, the N first additional packet signals are sequentially written into the first FIFO buffer.

5. The method as described in claim 4, characterized in that, The step of generating M second additional packet signals upon detecting the end of the signal frame of the MII transmitted data signal, and writing the M second additional packet signals into the second FIFO buffer in the MII clock domain, includes: When the MII transmission enable signal output by the MAC layer is detected to change from an effective signal to an invalid signal, a second frame end indication signal is generated. In response to the end of the second frame indication signal, M second additional packet signals are generated, where M is a positive integer greater than or equal to 2, and each of the M second additional packet signals includes at least two all-zero data. In the MII clock domain, the M second additional packet signals are sequentially written into the second FIFO buffer.

6. The method according to any one of claims 2 to 5, characterized in that, Reading the second packet signal from the first FIFO buffer includes: When the amount of data in the first FIFO buffer is greater than or equal to the first start-read threshold, the second packet signal is read from the first FIFO buffer; When the amount of data in the first FIFO buffer is less than or equal to the first stop reading threshold, the reading of the second packet signal from the first FIFO buffer ends, and the first start reading threshold is greater than the first stop reading threshold.

7. The method as described in claim 6, characterized in that, Reading the fourth packet signal from the second FIFO buffer includes: When the amount of data in the second FIFO buffer is greater than or equal to the second start-read threshold, the fourth packet signal is read from the second FIFO buffer; When the amount of data in the second FIFO buffer is less than or equal to the second stop reading threshold, the reading of the second packet signal from the second FIFO buffer ends, and the second start reading threshold is greater than the second stop reading threshold.

8. A communication interface conversion device, characterized in that, include: A receiving and conversion module is used to acquire the RGMII received data signal, which is output by the PHY layer through the RGMII interface; The RGMII received data signal is converted into the MII received data signal through the first FIFO buffer. The write clock of the first FIFO buffer is the RGMII clock, and the read clock of the first FIFO buffer is the system clock. A transmission conversion module is used to acquire the MII transmission data signal, which is output by the MAC layer through the MII interface; to perform bit concatenation of the MII transmission data signal and the MII transmission enable signal to obtain a third packet signal; to write the third packet signal into the second FIFO buffer in the MII clock domain; and to generate M second additional packet signals when the signal frame detecting the MII transmission data signal ends, to write the M second additional packet signals into the second FIFO buffer in the MII clock domain, wherein the write clock of the second FIFO buffer is the MII clock, and the read clock of the second FIFO buffer is the system clock; M is a positive integer greater than or equal to 2; In the system clock domain, based on the third packet signal, the fourth packet signal is read from the second FIFO buffer and split into the fourth packet signal to obtain the MII transmit enable signal and the MII transmit data signal under the system clock domain; by outputting the double data rate register ODDR, the RGMII transmit clock is generated based on the system clock, and based on the RGMII transmit clock, the MII transmit data signal under the system clock domain is converted into the RGMII transmit data signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

Images