Manufacturing method of asymmetric PCB and asymmetric PCB

Abstract

The invention relates to the technical field of printed circuit boards, and discloses an asymmetric PCB manufacturing method and an asymmetric PCB, and the asymmetric PCB manufacturing method comprises the steps: providing a substrate, the substrate comprises an embedded layer, a first dielectric layer and a first conductive layer, the embedded layer is internally provided with a power module, and the substrate is also provided with a first connecting hole; the substrate is electroplated to obtain a first conductive part, a first electroplated layer and a second electroplated layer, the first conductive part fills the first connecting hole, the electronic element and the first conductive layer are both connected with the first conductive part, the first electroplated layer covers the first conductive part and the first conductive layer, the first electroplated layer and the first conductive layer form a first circuit layer, and the second electroplated layer covers the second conductive layer; the second electroplated layer covers one surface, deviating from the first dielectric layer, of the embedded layer. The manufacturing method of the asymmetric PCB and the asymmetric PCB provided by the invention are used for solving the problem that a circuit board embedded with a power module is easy to warp in the manufacturing process in the related technology.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, and in particular to a method for manufacturing an asymmetric PCB and the asymmetric PCB itself. Background Technology

[0002] As electronic products become lighter, thinner, shorter, and smaller, and the required functions increase, the number of electronic components on printed circuit boards (PCBs) is also increasing. However, the usable area outside the PCB is becoming smaller, which has led to the development of PCB products with embedded electronic components. For applications such as automotive electronics, the circuits on the PCB need to be densely arranged and also meet the requirements of high-current operation. Therefore, a heat sink for high-power electronic components (such as chips) needs to be placed at the bottom of the embedded electronic components. The heat sink and the electronic components together form a power module.

[0003] Currently, the mainstream embedded power module circuit boards are generally semi-embedded structures. This means that after the power module is embedded in a through groove on the core board of the circuit board, a prepreg and copper foil are applied to the side of the power module where the electronic components are located. After lamination, holes are drilled to conduct the electronic components and the circuit is fabricated. However, the circuit board is prone to warping during this process. The electronic components in the power module are fragile. At the same time, if the heat sink in the power module needs to achieve internal insulation (i.e., insulation of the electronic component base), the heat sink usually uses an AMB (Active Metal Brazing) ceramic substrate. Once the circuit board warps after the power module is pressed into the circuit board, it will not only cause damage to the electronic components and the heat sink, but also lead to difficulties in circuit board processing (poor exposure, horizontal line jamming, poor laser drilling, and other quality problems), as well as voids in the subsequent soldering between the circuit board and the heat sink, which will eventually lead to the failure and scrapping of the circuit board. Therefore, the circuit boards of the current mainstream embedded power modules need to be improved. Summary of the Invention

[0004] This application provides a method for manufacturing an asymmetric PCB and an asymmetric PCB, which improves the problem of board warping that easily occurs during the manufacturing process of circuit boards with embedded power modules in related technologies.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing an asymmetric PCB, comprising:

[0006] A substrate is provided, the substrate comprising a buried layer, a first dielectric layer and a first conductive layer arranged sequentially and stacked, a power module being disposed inside the buried layer, the power module comprising a heat sink base and electronic components, the electronic components being disposed on the side of the heat sink base facing the first conductive layer, the substrate further comprising a first connection hole, the first connection hole penetrating the first conductive layer and the first dielectric layer, the electronic components defining the bottom surface of the first connection hole;

[0007] The substrate is electroplated to obtain a first conductive portion, a first electroplated layer, and a second electroplated layer. The first conductive portion fills the first connection hole. The electronic component and the first conductive layer are both connected to the first conductive portion. The first electroplated layer covers the first conductive portion and the first conductive layer. The first electroplated layer and the first conductive layer form a first circuit layer. The second electroplated layer covers the side of the embedded layer that faces away from the first dielectric layer.

[0008] In some embodiments, after electroplating the substrate to obtain the first conductive portion, the first electroplated layer, and the second electroplated layer, the method for manufacturing the asymmetric PCB further includes:

[0009] A portion of the first circuit layer is removed to divide the remaining first circuit layer into a first network portion and a second network portion. The first network portion and the second network portion are spaced apart, and the first network portion is connected to the first conductive portion and is electrically conductive.

[0010] In some embodiments, the substrate further includes a second connection hole that penetrates a portion of the embedded layer, and the heat sink defines the bottom surface of the second connection hole; when the substrate is electroplated, a second conductive portion is obtained, the second conductive portion fills the second connection hole, the heat sink and the first conductive layer are both connected to the second conductive portion, and the first electroplated layer covers the second conductive portion; when a portion of the first circuit layer is removed to divide the remaining first circuit layer into a first network portion and a second network portion, the second network portion is connected to the second conductive portion and is electrically conductive.

[0011] In some embodiments, after removing a portion of the first circuit layer to divide the remaining first circuit layer into a first network portion and a second network portion, the method for manufacturing the asymmetric PCB further includes:

[0012] A second dielectric layer and a second conductive layer are laminated onto the first circuit layer to obtain a multilayer board, wherein the second dielectric layer is located between the second conductive layer and the first circuit layer.

[0013] A third connection hole and a fourth connection hole are processed to penetrate the second dielectric layer and the second conductive layer. The first network portion defines the bottom surface of the third connection hole, and the second network portion defines the bottom surface of the fourth connection hole.

[0014] The multilayer board is electroplated to obtain a third conductive portion, a fourth conductive portion, a third electroplated layer, and a fourth electroplated layer. The third conductive portion fills the third connecting hole. The first network portion and the second conductive layer are both connected to the third conductive portion. The fourth conductive portion fills the fourth connecting hole. The second network portion and the second conductive layer are both connected to the fourth conductive portion. The third electroplated layer covers the third conductive portion, the fourth conductive portion, and the second conductive layer. The third electroplated layer and the second conductive layer form a second circuit layer. The fourth electroplated layer covers the side of the second electroplated layer that faces away from the embedded layer.

[0015] In some embodiments, after electroplating the multilayer board to obtain the third conductive portion, the fourth conductive portion, the third electroplating layer, and the fourth electroplating layer, the method for manufacturing the asymmetric PCB further includes:

[0016] A portion of the second circuit layer is removed to divide the remaining second circuit layer into a third network portion and a fourth network portion, the third network portion and the fourth network portion being spaced apart, the third network portion being connected to and electrically conductive with the third conductive portion, and the fourth network portion being connected to and electrically conductive with the fourth conductive portion.

[0017] In some embodiments, after removing a portion of the first circuit layer to divide the remaining first circuit layer into a first network portion and a second network portion, the method for manufacturing the asymmetric PCB further includes:

[0018] A second dielectric layer and a second conductive layer are laminated onto the first circuit layer to obtain a multilayer board, wherein the second dielectric layer is located between the second conductive layer and the first circuit layer.

[0019] A third connection hole is formed that penetrates the second dielectric layer and the second conductive layer, and the first network portion defines the bottom surface of the third connection hole;

[0020] The multilayer board is electroplated to obtain a third conductive part, a third electroplated layer, and a fourth electroplated layer. The third conductive part fills the third connecting hole. The first network part and the second conductive layer are both connected to the third conductive part. The third electroplated layer covers the third conductive part and the second conductive layer. The third electroplated layer and the second conductive layer form a second circuit layer. The fourth electroplated layer covers the side of the second electroplated layer that is away from the embedded layer.

[0021] In some embodiments, after electroplating the multilayer board to obtain the third conductive portion, the third electroplated layer, and the fourth electroplated layer, the method for manufacturing the asymmetric PCB further includes:

[0022] A portion of the second circuit layer is removed to divide the remaining second circuit layer into a third network portion and a fourth network portion, the third network portion and the fourth network portion being spaced apart, the third network portion being connected to the third conductive portion and electrically conductive.

[0023] In some embodiments, the heat dissipation base penetrates the embedded layer in a direction away from the first dielectric layer; when the substrate is electroplated to obtain the first conductive part, the first electroplated layer and the second electroplated layer, the thickness of the second electroplated layer is greater than the thickness of the first electroplated layer.

[0024] Secondly, embodiments of this application provide an asymmetric PCB, including a substrate. The substrate includes a buried layer, a first dielectric layer, and a first conductive layer stacked sequentially. A power module is disposed inside the buried layer. The power module includes a heat sink and electronic components. The electronic components are disposed on the side of the heat sink facing the first conductive layer. The substrate also has a first connection hole that penetrates the first conductive layer and the first dielectric layer. The electronic components define the bottom surface of the first connection hole. The asymmetric PCB further includes a first conductive portion, a first electroplated layer, and a second electroplated layer. The first conductive portion fills the first connection hole. The electronic components and the first conductive layer are both connected to the first conductive portion. The first electroplated layer covers the first conductive portion and the first conductive layer. The first electroplated layer and the first conductive layer form a first circuit layer. The second electroplated layer covers the side of the buried layer facing away from the first dielectric layer.

[0025] Thirdly, embodiments of this application provide an asymmetric PCB, which is manufactured by the asymmetric PCB manufacturing method described in the first aspect.

[0026] The asymmetric PCB manufacturing method provided in this application has the following advantages: Since the substrate includes a buried layer, a first dielectric layer, and a first conductive layer arranged sequentially and in layers, and the substrate is electroplated to obtain a first conductive part, a first electroplated layer, and a second electroplated layer, when the first conductive part fills the first connection hole, the electronic components and the first conductive layer are connected to the first conductive part. The first electroplated layer covers the first conductive part and the first conductive layer, and the first electroplated layer and the first conductive layer form a first circuit layer. The second electroplated layer covers the side of the buried layer that is away from the first dielectric layer. Therefore, the stress difference caused by the first dielectric layer, the first conductive layer, the first conductive part, and the first electroplated layer can be balanced by the second electroplated layer, and the rigidity of the second electroplated layer can be used to effectively suppress board warping.

[0027] The advantages of the asymmetric PCB provided in this application compared to the prior art can be found in the description of the advantages of the asymmetric PCB manufacturing method provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart of a method for manufacturing an asymmetric PCB in one embodiment of this application;

[0030] Figure 2 This is a schematic diagram of the substrate structure in one embodiment of this application;

[0031] Figure 3 Yes Figure 2 A schematic diagram showing the electroplating process applied to the substrate.

[0032] Figure 4 It is to remove Figure 3 A schematic diagram of a portion of the first circuit layer of the substrate shown;

[0033] Figure 5 This is a schematic diagram of the structure of a multilayer board in one embodiment of this application;

[0034] Figure 6 Yes Figure 5 The diagram shows a multilayer board undergoing electroplating.

[0035] Figure 7 It is to remove Figure 6 The diagram shows a partial second circuit layer of a multilayer board.

[0036] The markings in the diagram mean:

[0037] 100. Substrate; 110. Multilayer board;

[0038] 10. Embedded layer; 11. Heat sink base; 12. Electronic components;

[0039] 20. First dielectric layer;

[0040] 30. First conductive layer;

[0041] 40. First connecting hole; 41. Second connecting hole;

[0042] 501. First Network Department; 502. Second Network Department;

[0043] 50. First conductive part; 51. First electroplated layer; 52. Second electroplated layer; 53. Second conductive part;

[0044] 60. Second dielectric layer;

[0045] 70. Second conductive layer;

[0046] 80. Third connecting hole; 81. Fourth connecting hole;

[0047] 901. Third Network Department; 902. Fourth Network Department;

[0048] 90. Third conductive part; 91. Third electroplating layer; 92. Fourth electroplating layer; 93. Fourth conductive part. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0052] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0053] As electronic products become lighter, thinner, shorter, and smaller, and the required functions increase, the number of electronic components on circuit boards also increases. However, the usable area outside the circuit board is becoming smaller, which has led to the development of circuit board products with embedded electronic components. For applications such as automotive electronics, the circuit boards not only need to be densely arranged, but also need to meet the high-current operating environment. Therefore, it is necessary to place a heat sink for high-power electronic components (such as chips) at the bottom of the embedded electronic components. The heat sink and the electronic components together form a power module.

[0054] Currently, the mainstream embedded power module circuit boards are generally semi-embedded structures. This means that after the power module is embedded in a through groove on the core board of the circuit board, a prepreg and copper foil are applied to the side where the electronic components of the power module are located. After lamination, holes are drilled to conduct the electronic components and to fabricate the circuit. However, due to the asymmetry of the circuit board structure caused by lamination on one side, the circuit board is prone to warping. The electronic components in the power module are fragile. In addition, if the heat sink in the power module needs to achieve internal insulation (i.e., insulation of the electronic component base), the heat sink usually uses an AMB ceramic substrate. Once the circuit board warps after the power module is laminated into the circuit board, it will not only cause damage to the electronic components and the heat sink, but also lead to difficulties in circuit board processing (poor exposure, horizontal line jamming, poor laser drilling, and other quality problems), as well as voids in the subsequent soldering between the circuit board and the heat sink, which will eventually lead to the failure and scrapping of the circuit board. Therefore, the circuit boards of the current mainstream embedded power modules need to be improved.

[0055] In view of this, this application provides a method for manufacturing an asymmetric PCB and an asymmetric PCB. Since the substrate includes a buried layer, a first dielectric layer and a first conductive layer arranged sequentially and stacked, and the substrate is electroplated to obtain a first conductive part, a first electroplated layer and a second electroplated layer, when the first conductive part fills the first connection hole, the electronic components and the first conductive layer are connected to the first conductive part. The first electroplated layer covers the first conductive part and the first conductive layer, and the first electroplated layer and the first conductive layer form a first circuit layer. The second electroplated layer covers the side of the buried layer away from the first dielectric layer. Therefore, the stress difference caused by the first dielectric layer, the first conductive part, the first conductive layer and the first electroplated layer can be balanced by the second electroplated layer, and the rigidity of the second electroplated layer can be used to effectively suppress board warping.

[0056] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0057] Please refer to Figures 1 to 3 In a first aspect, embodiments of this application provide a method for manufacturing an asymmetric PCB, comprising:

[0058] S100: A substrate 100 is provided. The substrate 100 includes a buried layer 10, a first dielectric layer 20 and a first conductive layer 30 arranged sequentially and stacked. A power module is disposed inside the buried layer 10. The power module includes a heat sink 11 and an electronic component 12. The electronic component 12 is disposed on the side of the heat sink 11 facing the first conductive layer 30. The substrate 100 is also provided with a first connection hole 40. The first connection hole 40 penetrates the first conductive layer 30 and the first dielectric layer 20. The electronic component defines the bottom surface of the first connection hole 40.

[0059] The embedded layer 10 may include a core board and a dielectric layer. Multiple core boards and dielectric layers may be provided. That is, the embedded layer 10 may be composed of one or N core boards and a prepreg, where N is a positive integer greater than or equal to 2.

[0060] The substrate 100 can be manufactured through processes such as the fabrication of the inner layer circuit of the embedded layer 10, opening windows in the embedded layer 10, stacking, lamination, and drilling.

[0061] Fabrication of inner layer circuitry for embedded layer 10: The inner layer circuitry of each core board of embedded layer 10 is fabricated according to conventional production methods.

[0062] Embedded layer 10 window opening: The area where the power module needs to be embedded is opened. The window size needs to be larger than the overall heat dissipation base 11 of the power module so that the power module can be completely embedded in the window.

[0063] Stacking: The core board, dielectric layer, power module, first dielectric layer 20 and first conductive layer 30 of the embedded layer 10 are stacked sequentially, and the power module is embedded in the opening of the embedded layer 10. Before stacking, a high-temperature resistant protective film is attached to the side of the power module away from the chip to fix the power module.

[0064] Pressing: The embedded layer 10, power module, first dielectric layer 20 and first conductive layer 30 after stacking are pressed together as a whole. Before the first pressing, the process also includes riveting and positioning, in which the embedded layer 10, first dielectric layer 20 and first conductive layer 30 after stacking are fixed by rivets to prevent misalignment during pressing.

[0065] Drilling: The first connecting hole 40 is formed by laser drilling from the first conductive layer 30.

[0066] The heat sink 11 can be made of metal or ceramic, etc., and the electronic component 12 can be a chip, etc. The first dielectric layer 20 can be formed by laminating a prepreg, and the first conductive layer 30 can be made of copper, silver, or aluminum, etc.

[0067] Since the first dielectric layer 20 and the first conductive layer 30 are only laminated on one side of the embedded layer 10, and no dielectric layer and conductive layer are provided on the other side of the embedded layer 10, the structure of the substrate 100 is asymmetrical, resulting in different stresses on both sides, which makes it easy for the board to warp.

[0068] S200: Electroplating is performed on the substrate 100 to obtain a first conductive part 50, a first electroplated layer 51 and a second electroplated layer 52. The first conductive part 50 fills the first connection hole 40. The electronic component 12 and the first conductive layer 30 are both connected to the first conductive part 50. The first electroplated layer 51 covers the first conductive part 50 and the first conductive layer 30. The first electroplated layer 51 and the first conductive layer 30 form a first circuit layer. The second electroplated layer 52 covers the side of the embedded layer 10 that faces away from the first dielectric layer 20.

[0069] The materials of the first conductive part 50, the first electroplated layer 51, and the second electroplated layer 52 can be copper, silver, or aluminum, and can be the same as the material of the first conductive layer 30. For example, the materials of the first conductive part 50, the first electroplated layer 51, and the second electroplated layer 52 can all be copper, and can be the same as the material of the first conductive layer 30. Chemical copper deposition can be performed first inside the first connecting hole 40, on the surface of the first conductive layer 30, and on the side of the second electroplated layer 52 covering the embedded layer 10 away from the first dielectric layer 20, followed by electroplating, so as to obtain the first conductive part 50, the first electroplated layer 51, and the second electroplated layer 52.

[0070] Since both the electronic component 12 and the first conductive layer 30 are connected to the first conductive part 50, and the first electroplated layer 51 covers the first conductive part 50 and the first conductive layer 30, electrical conduction between the electronic component 12 and the first circuit layer can be achieved.

[0071] Since the second electroplating layer 52 covers the side of the embedded layer 10 facing away from the first dielectric layer 20, the first dielectric layer 20, the first conductive layer 30, the first conductive part 50 and the first electroplating layer 51 are provided on one side of the second electroplating layer 52 of the embedded layer 10, while the second electroplating layer 52 is provided on the other side of the embedded layer 10. Thus, the stress difference caused by the first dielectric layer 20, the first conductive layer 30, the first conductive part 50 and the first electroplating layer 51 on both sides of the embedded layer 10 can be balanced by the second electroplating layer 52, and the rigidity of the second electroplating layer 52 can effectively suppress board warping.

[0072] As can be seen from the above, the asymmetric PCB manufacturing method provided in this application embodiment, since the substrate 100 includes a buried layer 10, a first dielectric layer 20 and a first conductive layer 30 arranged sequentially and in layers, and the substrate 100 is electroplated to obtain a first conductive part 50, a first electroplated layer 51 and a second electroplated layer 52, when the first conductive part 50 fills the first connection hole 40, the electronic component 12 and the first conductive layer 30 are both connected to the first conductive part 50, the first electroplated layer 51 covers the first conductive part 50 and the first conductive layer 30, the first electroplated layer 51 and the first conductive layer 30 form a first circuit layer, and the second electroplated layer 52 covers the side of the buried layer 10 away from the first dielectric layer 20, so the stress difference caused by the first dielectric layer 20, the first conductive layer 30, the first conductive part 50 and the first electroplated layer 51 can be balanced by the second electroplated layer 52, and the rigidity of the second electroplated layer 52 can be used to effectively suppress board warping, and solve the board warping problem caused by the asymmetric lamination of the embedded power module circuit board.

[0073] Optionally, the heat sink 11 penetrates the embedded layer 10 in a direction away from the first dielectric layer 20; when the substrate 100 is electroplated to obtain the first conductive part 50, the first electroplated layer 51 and the second electroplated layer 52, the thickness of the second electroplated layer 52 is greater than the thickness of the first electroplated layer 51.

[0074] With this configuration, the stress differences caused by the first dielectric layer 20, the first conductive layer 30 and the first electroplating layer 51 can be better balanced by the second electroplating layer 52, and the rigidity of the second electroplating layer 52 can be used to effectively suppress board warping.

[0075] Understandably, the first conductive layer 30 can be made of ultra-thin copper foil (e.g., with a thickness of 10μm-35μm) to reduce initial stress and decrease the thickness difference between the first circuit layer and the second electroplated layer 52. The specific thickness of the ultra-thin copper foil is matched to the final required total copper thickness of the circuit board. For example, if the target total copper thickness of the first circuit layer is 150μm, a 35μm thick ultra-thin copper foil is selected. The initial pressing of this ultra-thin copper foil can effectively reduce the thickness difference between the first circuit layer and the second electroplated layer 52 on both sides after subsequent electroplating, thereby reducing the risk of board warping caused by thickness difference.

[0076] It should be noted that when electroplating the substrate 100, the current density and spray pressure on one side of the second electroplating layer 52 can be increased to increase the thickness of the second electroplating layer 52, so that the thickness of the second electroplating layer 52 is greater than the thickness of the first electroplating layer 51, effectively compensating for the initial thickness difference on both sides, reducing the overall thickness difference, balancing stress, and suppressing board warping.

[0077] For example, the first circuit layer, the first electroplated layer 51, and the second electroplated layer 52 are all made of copper. When the target copper thickness of the first circuit layer is 150 μm (the first conductive layer 30 with a thickness of 35 μm plus the first electroplated layer 51 with a thickness of 115 μm), before adjustment, the thickness of the second electroplated layer 52 is equal to the thickness of the first electroplated layer 51 and is approximately 115 μm. At this time, the copper thickness difference between the first circuit layer and the second electroplated layer 52 is approximately 35 μm. After adjusting the balance layer current density and spray pressure, the thickness of the first electroplated layer 51 is approximately 115 μm, and the copper thickness of the second electroplated layer 52 increases to 145 μm. At this time, the copper thickness difference between the first circuit layer and the second electroplated layer 52 is reduced to 5 μm, reducing the copper thickness difference on both sides of the embedded layer 10 and effectively suppressing board warping.

[0078] Please refer to Figures 2 to 4 In some embodiments, after electroplating the substrate 100 to obtain the first conductive portion 50, the first electroplated layer 51, and the second electroplated layer 52, the method for manufacturing an asymmetric PCB further includes:

[0079] A portion of the first circuit layer is removed to divide the remaining first circuit layer into a first network section 501 and a second network section 502. The first network section 501 and the second network section 502 are spaced apart. The first network section 501 is connected to the first conductive section 50 and is electrically conductive.

[0080] By adopting the above scheme, the first circuit layer can be separated to disperse its own stress, reduce the residual rate of the first circuit layer, and make the residual rates of the first circuit layer and the second electroplated layer 52 closer. This can effectively reduce the stress difference between the first dielectric layer 20, the first conductive layer 30 and the first electroplated layer 51 and the intact second electroplated layer 52, and further suppress board warping.

[0081] It is understandable that when removing part of the first circuit layer, the second electroplated layer 52 is not processed and is completely retained. Removing part of the first circuit layer can be the process of creating circuits on the first circuit layer. The first network section 501 and the second network section 502 are different circuits. The first network section 501 can be used as the control circuit of the electronic component 12.

[0082] It should be noted that when the first circuit layer is made of copper, removing part of the first circuit layer can disperse its own stress and reduce the residual copper content. Part of the first circuit layer can be removed through methods such as chemical etching or mechanical processing.

[0083] Optionally, a portion of the first line layer is removed to divide the remaining first line layer into a first network section 501 and a second network section 502, including:

[0084] First, a first protective film is attached to the surface of the first electroplated layer 51 facing away from the embedded layer 10, and a second protective film is attached to the surface of the second electroplated layer 52 facing away from the embedded layer 10.

[0085] Then, the second protective film is completely cured by exposure and development, while the first protective film is partially cured.

[0086] Next, a portion of the first circuit layer is removed by chemical etching to divide the remaining first circuit layer into a first network section 501 and a second network section 502.

[0087] This configuration allows the second electroplated layer 52 to be completely preserved when part of the first circuit layer is removed.

[0088] It should be noted that both the first and second protective films can be dry or wet films. After the film is applied, the second protective film is exposed and cured on the entire surface, completely protecting the second electroplated layer 52. After etching, the second electroplated layer 52 can be 100% preserved.

[0089] Optionally, the substrate 100 is further provided with a second connection hole 41, the second connection hole 41 penetrates a portion of the embedded layer 10, and the heat sink 11 defines the bottom surface of the second connection hole 41; when the substrate 100 is electroplated, a second conductive portion 53 is obtained, the second conductive portion 53 fills the second connection hole 41, the heat sink 11 and the first conductive layer 30 are both connected to the second conductive portion 53, and the first electroplated layer 51 covers the second conductive portion 53; when a portion of the first circuit layer is removed to divide the remaining first circuit layer into a first network portion 501 and a second network portion 502, the second network portion 502 is connected to the second conductive portion 53 and is electrically conductive.

[0090] With this configuration, the heat from the heat sink 11 can be dissipated through the second conductive part 53 and the second network part 502.

[0091] Please refer to Figures 2 to 7 In some embodiments, after removing a portion of the first circuit layer to divide the remaining first circuit layer into a first network portion 501 and a second network portion 502, the method for manufacturing an asymmetric PCB further includes:

[0092] First, a second dielectric layer 60 and a second conductive layer 70 are laminated onto the first circuit layer to obtain a multilayer board 110, wherein the second dielectric layer 60 is located between the second conductive layer 70 and the first circuit layer.

[0093] The second dielectric layer 60 can be formed by laminating a prepreg, and the second conductive layer 70 can be made of copper, silver, or aluminum, etc.

[0094] Next, a third connection hole 80 and a fourth connection hole 81 are processed to penetrate the second dielectric layer 60 and the second conductive layer 70. The first network portion 501 defines the bottom surface of the third connection hole 80, and the second network portion 502 defines the bottom surface of the fourth connection hole 81.

[0095] The third connecting hole 80 and the fourth connecting hole 81, which penetrate the second dielectric layer 60 and the second conductive layer 70, can be processed by mechanical processing or laser ablation.

[0096] Then, the multilayer board 110 is electroplated to obtain a third conductive part 90, a fourth conductive part 93, a third electroplated layer 91, and a fourth electroplated layer 92. The third conductive part 90 fills the third connecting hole 80. The first network part 501 and the second conductive layer 70 are both connected to the third conductive part 90. The fourth conductive part 93 fills the fourth connecting hole 81. The second network part 502 and the second conductive layer 70 are both connected to the fourth conductive part 93. The third electroplated layer 91 covers the third conductive part 90, the fourth conductive part 93, and the second conductive layer 70. The third electroplated layer 91 and the second conductive layer 70 form a second circuit layer. The fourth electroplated layer 92 covers the side of the second electroplated layer 52 that faces away from the embedded layer 10.

[0097] The third conductive part 90, the fourth conductive part 93, the third electroplating layer 91 and the fourth electroplating layer 92 can be made of copper, silver or aluminum, etc., and can be made of the same material as the second conductive layer 70.

[0098] Since the third conductive part 90 fills the third connecting hole 80, the first network part 501 and the second conductive layer 70 are both connected to the third conductive part 90, the fourth conductive part 93 fills the fourth connecting hole 81, and the second network part 502 and the second conductive layer 70 are both connected to the fourth conductive part 93, the electronic component 12 and the second circuit layer can be electrically connected, and the heat of the heat sink 11 can be dissipated through the fourth conductive part 93 and the second circuit layer.

[0099] Since the fourth electroplating layer 92 covers the side of the second electroplating layer 52 that faces away from the embedded layer 10, the first dielectric layer 20, the first conductive layer 30, the first conductive part 50, the first electroplating layer 51, the second dielectric layer 60, the second conductive layer 70, the third conductive part 90, the fourth conductive part 93, and the third electroplating layer 91 are provided on one side of the second electroplating layer 52 of the embedded layer 10, while the second electroplating layer 52 and the fourth electroplating layer 92 are provided on the other side of the embedded layer 10. Thus, the stress difference caused by the first dielectric layer 20, the first conductive layer 30, the first conductive part 50, the first electroplating layer 51, the second dielectric layer 60, the second conductive layer 70, the third conductive part 90, the fourth conductive part 93, and the third electroplating layer 91 on both sides of the embedded layer 10 can be balanced by the second electroplating layer 52 and the fourth electroplating layer 92, and the rigidity of the second electroplating layer 52 and the fourth electroplating layer 92 can be used to effectively suppress board warping.

[0100] By adopting the above scheme, the rigidity of the second electroplating layer 52 and the fourth electroplating layer 92 can be used to effectively suppress board warping.

[0101] Understandably, the second conductive layer 70 can be made of ultra-thin copper foil (e.g., with a thickness of 10μm-35μm) to reduce initial stress and reduce the thickness difference between the second circuit layer and the fourth electroplated layer 92.

[0102] Optionally, the thickness of the fourth electroplated layer 92 is greater than the thickness of the third electroplated layer 91.

[0103] This configuration effectively suppresses board warping by utilizing the rigidity of the second electroplating layer 52 and the fourth electroplating layer 92.

[0104] It should be noted that when electroplating the substrate 100, the current density and spray pressure on one side of the fourth electroplating layer 92 can be increased to increase the thickness of the fourth electroplating layer 92 in order to balance the stress.

[0105] For example, the second circuit layer, the third electroplating layer 91, and the fourth electroplating layer 92 are all made of copper. Taking the thickness of the second conductive layer 70 as 35 μm and the thickness of the third electroplating layer 91 as 115 μm, the thickness of the second circuit layer after electroplating is 35 μm + 115 μm = 150 μm. The copper thickness of the fourth electroplating layer 92 is 115 μm without adjusting the current and spraying pressure. The copper thickness difference between the second circuit layer and the fourth electroplating layer 92 is 35 μm. By increasing the current density and spraying pressure on the fourth electroplating layer 92 side, the copper thickness of the fourth electroplating layer 92 after electroplating is greater than that of the third electroplating layer 91. For example, if the thickness of the second circuit layer is 150 μm and the thickness of the fourth electroplating layer 92 is 155 μm, the copper thickness difference between the two can be reduced from 35 μm to 5 μm, reducing the copper thickness difference on both sides and effectively suppressing board warping.

[0106] Optionally, after electroplating the multilayer board 110 to obtain the third conductive portion 90, the fourth conductive portion 93, the third electroplated layer 91, and the fourth electroplated layer 92, the method for manufacturing an asymmetric PCB further includes:

[0107] A portion of the second circuit layer is removed to divide the remaining second circuit layer into a third network section 901 and a fourth network section 902. The third network section 901 and the fourth network section 902 are spaced apart. The third network section 901 is connected to the third conductive section 90 and is electrically conductive. The fourth network section 902 is connected to the fourth conductive section 93 and is electrically conductive.

[0108] By adopting the above scheme, the second circuit layer can be separated to disperse its own stress and reduce the residual rate of the second circuit layer. This can effectively reduce the stress difference between the first dielectric layer 20, the first conductive layer 30, the first conductive part 50, the first electroplated layer 51, the second dielectric layer 60, the second conductive layer 70, the third conductive part 90, the fourth conductive part 93, and the third electroplated layer 91 and the intact fourth electroplated layer 92, and further suppress board warping.

[0109] It is understandable that when removing part of the second circuit layer, the fourth electroplated layer 92 is not processed and is completely retained. Removing part of the second circuit layer can be the process of creating circuits on the second circuit layer. The third network section 901 and the fourth network section 902 are different circuits. The third network section 901 can be used as the control circuit of the electronic component 12.

[0110] It should be noted that when the second circuit layer is made of copper, removing part of the second circuit layer can disperse its own stress and reduce the residual copper content. Part of the second circuit layer can be removed through methods such as chemical etching or mechanical processing. The specific method for removing part of the second circuit layer is similar to the method for removing part of the first circuit layer.

[0111] It should also be noted that after removing part of the second circuit layer to divide the remaining second circuit layer into the third network section 901 and the fourth network section 902, the second dielectric layer 60 and the second conductive layer 70 can continue to be laminated on the second circuit layer.

[0112] In another embodiment, after removing a portion of the first circuit layer to divide the remaining first circuit layer into a first network portion 501 and a second network portion 502, the method for manufacturing an asymmetric PCB further includes:

[0113] First, a second dielectric layer 60 and a second conductive layer 70 are laminated onto the first circuit layer to obtain a multilayer board 110, wherein the second dielectric layer 60 is located between the second conductive layer 70 and the first circuit layer.

[0114] Next, a third connection hole 80 is formed that penetrates the second dielectric layer 60 and the second conductive layer 70, and the bottom surface of the third connection hole 80 is defined by the first network portion 501.

[0115] Then, the multilayer board 110 is electroplated to obtain a third conductive part 90, a third electroplated layer 91 and a fourth electroplated layer 92. The third conductive part 90 fills the third connecting hole 80. The first network part 501 and the second conductive layer 70 are both connected to the third conductive part 90. The third electroplated layer 91 covers the third conductive part 90 and the second conductive layer 70. The third electroplated layer 91 and the second conductive layer 70 form a second circuit layer. The fourth electroplated layer 92 covers the side of the second electroplated layer 52 that is away from the embedded layer 10.

[0116] By adopting the above scheme, the rigidity of the second electroplating layer 52 and the fourth electroplating layer 92 can be used to effectively suppress board warping.

[0117] It is understood that in another embodiment, the fourth connection hole 81 and the fourth conductive part 93 may not be provided.

[0118] Optionally, after electroplating the multilayer board 110 to obtain the third conductive part 90, the third electroplated layer 91, and the fourth electroplated layer 92, the method for manufacturing an asymmetric PCB further includes:

[0119] A portion of the second circuit layer is removed to divide the remaining second circuit layer into a third network section 901 and a fourth network section 902. The third network section 901 and the fourth network section 902 are spaced apart. The third network section 901 is connected to the third conductive section 90 and is electrically conductive.

[0120] By adopting the above scheme, the second circuit layer can be separated to disperse its own stress and reduce the residual rate of the second circuit layer. This can effectively reduce the stress difference between the first dielectric layer 20, the first conductive layer 30, the first conductive part 50, the first electroplated layer 51, the second dielectric layer 60, the second conductive layer 70, the third conductive part 90, and the third electroplated layer 91 and the intact fourth electroplated layer 92, and further suppress board warping.

[0121] Secondly, embodiments of this application provide an asymmetric PCB, including a substrate 100. The substrate 100 includes a buried layer 10, a first dielectric layer 20, and a first conductive layer 30, which are sequentially and stacked. A power module is disposed inside the buried layer 10. The power module includes a heat sink 11 and an electronic component 12. The electronic component 12 is disposed on the side of the heat sink 11 facing the first conductive layer 30. The substrate 100 also has a first connection hole 40, which penetrates the first conductive layer 30 and the first dielectric layer 20. The electronic components define the bottom surface of the first connection hole 40; the asymmetric PCB also includes a first conductive part 50, a first electroplated layer 51 and a second electroplated layer 52. The first conductive part 50 fills the first connection hole 40. The electronic components 12 and the first conductive layer 30 are both connected to the first conductive part 50. The first electroplated layer 51 covers the first conductive part 50 and the first conductive layer 30. The first electroplated layer 51 and the first conductive layer 30 form the first circuit layer. The second electroplated layer 52 covers the side of the embedded layer 10 that faces away from the first dielectric layer 20.

[0122] The asymmetric PCB provided in this application embodiment includes a substrate 100 comprising a buried layer 10, a first dielectric layer 20, and a first conductive layer 30 arranged sequentially and in layers. The electronic components 12 and the first conductive layer 30 are both connected to the first conductive portion 50. The first electroplating layer 51 covers the first conductive portion 50 and the first conductive layer 30, and the first electroplating layer 51 and the first conductive layer 30 form a first circuit layer. The second electroplating layer 52 covers the side of the buried layer 10 facing away from the first dielectric layer 20. Therefore, the stress difference caused by the first dielectric layer 20, the first conductive layer 30, the first conductive portion 50, and the first electroplating layer 51 can be balanced by the second electroplating layer 52, and the rigidity of the second electroplating layer 52 can effectively suppress board warping.

[0123] Thirdly, embodiments of this application provide an asymmetric PCB, which is manufactured using the asymmetric PCB manufacturing method as described in the first aspect.

[0124] The asymmetric PCB provided in this application embodiment includes a substrate 100 comprising a buried layer 10, a first dielectric layer 20, and a first conductive layer 30 arranged sequentially and in layers. When the substrate 100 is electroplated to obtain a first conductive portion 50, a first electroplated layer 51, and a second electroplated layer 52, the electronic component 12 and the first conductive layer 30 are connected to the first conductive portion 50 when the first conductive portion 50 fills the first connection hole 40. The first electroplated layer 51 covers the first conductive portion 50 and the first conductive layer 30, and the first electroplated layer 51 and the first conductive layer 30 form a first circuit layer. The second electroplated layer 52 covers the side of the buried layer 10 facing away from the first dielectric layer 20. Therefore, the stress difference caused by the first dielectric layer 20, the first conductive layer 30, the first conductive portion 50, and the first electroplated layer 51 can be balanced by the second electroplated layer 52, and the rigidity of the second electroplated layer 52 can effectively suppress board warping.

[0125] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of manufacturing an asymmetric PCB, characterized by, The application relates to an asymmetric PCB manufacturing method. A substrate is provided, the substrate comprises a buried embedding layer, a first dielectric layer and a first conductive layer arranged in sequence and in a stacked mode, the interior of the buried embedding layer is provided with a power module, the power module comprises a heat dissipation base and an electronic element, the electronic element is arranged on the side of the heat dissipation base facing the first conductive layer, the substrate is further provided with a first connecting hole, the first connecting hole penetrates the first conductive layer and the first dielectric layer, and the electronic element defines the bottom surface of the first connecting hole; The substrate is subjected to electroplating treatment to obtain a first conductive part, a first electroplating layer and a second electroplating layer, the first conductive part fills the first connecting hole, the electronic element and the first conductive layer are connected with the first conductive part, the first electroplating layer covers the first conductive part and the first conductive layer, the first electroplating layer and the first conductive layer constitute a first circuit layer, and the second electroplating layer covers the side of the buried embedding layer away from the first dielectric layer.

2. The method of claim 1, wherein the asymmetric PCB is manufactured by: After the substrate is subjected to the electroplating treatment to obtain the first conductive part, the first electroplating layer and the second electroplating layer, the asymmetric PCB manufacturing method further comprises the following steps: Part of the first circuit layer is removed to divide the remaining first circuit layer into a first network part and a second network part, the first network part and the second network part are arranged at intervals, and the first network part is connected with the first conductive part and electrically connected.

3. The method of claim 2, wherein the asymmetric PCB is manufactured by: The substrate is further provided with a second connecting hole, the second connecting hole penetrates part of the buried embedding layer, the heat dissipation base defines the bottom surface of the second connecting hole; when the substrate is subjected to the electroplating treatment, a second conductive part is obtained, the second conductive part fills the second connecting hole, the heat dissipation base and the first conductive layer are connected with the second conductive part, and the first electroplating layer covers the second conductive part; when part of the first circuit layer is removed to divide the remaining first circuit layer into a first network part and a second network part, the second network part is connected with the second conductive part and electrically connected.

4. The method of claim 3, wherein the asymmetric PCB is manufactured by: After the part of the first circuit layer is removed to divide the remaining first circuit layer into a first network part and a second network part, the asymmetric PCB manufacturing method further comprises the following steps: A second dielectric layer and a second conductive layer are laminated on the first circuit layer to obtain a multilayer board, the second dielectric layer is arranged between the second conductive layer and the first circuit layer; Third connecting holes and fourth connecting holes penetrating the second dielectric layer and the second conductive layer are processed, the first network part defines the bottom surface of the third connecting hole, and the second network part defines the bottom surface of the fourth connecting hole; The multi-layer board is subjected to electroplating treatment to obtain a third conductive part, a fourth conductive part, a third electroplated layer and a fourth electroplated layer, the third conductive part fills the third connecting hole, the first network part and the second conductive layer are connected with the third conductive part, the fourth conductive part fills the fourth connecting hole, the second network part and the second conductive layer are connected with the fourth conductive part, the third electroplated layer covers the third conductive part, the fourth conductive part and the second conductive layer, the third electroplated layer and the second conductive layer constitute a second circuit layer, and the fourth electroplated layer covers one side of the second electroplated layer away from the embedded layer.

5. The method of claim 4, wherein the asymmetric PCB is manufactured by: After the multi-layer board is subjected to the electroplating treatment to obtain the third conductive part, the fourth conductive part, the third electroplated layer and the fourth electroplated layer, the method for manufacturing the asymmetric PCB further comprises: part of the second circuit layer is removed to divide the remaining second circuit layer into a third network part and a fourth network part, the third network part and the fourth network part are arranged at intervals, the third network part is connected with the third conductive part and electrically connected, and the fourth network part is connected with the fourth conductive part and electrically connected.

6. The method of claim 2, wherein the asymmetric PCB is manufactured by: After the part of the first circuit layer is removed to divide the remaining first circuit layer into the first network part and the second network part, the method for manufacturing the asymmetric PCB further comprises: The second dielectric layer and the second conductive layer are laminated on the first circuit layer to obtain a multi-layer board, the second dielectric layer is arranged between the second conductive layer and the first circuit layer; A third connecting hole penetrating through the second dielectric layer and the second conductive layer is formed, and the first network part defines a bottom surface of the third connecting hole; The multi-layer board is subjected to electroplating treatment to obtain a third conductive part, a third electroplated layer and a fourth electroplated layer, the third conductive part fills the third connecting hole, the first network part and the second conductive layer are connected with the third conductive part, the third electroplated layer covers the third conductive part and the second conductive layer, the third electroplated layer and the second conductive layer constitute a second circuit layer, and the fourth electroplated layer covers one side of the second electroplated layer away from the embedded layer.

7. The method of claim 6, wherein the asymmetric PCB is manufactured by: After the multi-layer board is subjected to the electroplating treatment to obtain the third conductive part, the fourth conductive part, the third electroplated layer and the fourth electroplated layer, the method for manufacturing the asymmetric PCB further comprises: part of the second circuit layer is removed to divide the remaining second circuit layer into a third network part and a fourth network part, the third network part and the fourth network part are arranged at intervals, the third network part is connected with the third conductive part and electrically connected, and the fourth network part is connected with the fourth conductive part and electrically connected.

8. The method of claim 1 to 7, wherein The heat dissipation base penetrates through the embedded layer in a direction away from the first dielectric layer; when the substrate is subjected to electroplating treatment to obtain a first conductive part, a first electroplated layer and a second electroplated layer, the thickness of the second electroplated layer is greater than the thickness of the first electroplated layer.

9. An asymmetric PCB characterized by, The asymmetric PCB comprises a substrate, the substrate comprises a buried layer, a first dielectric layer and a first conductive layer arranged in sequence and in a stacked manner, an inner portion of the buried layer is provided with a power module, the power module comprises a heat dissipation base and an electronic element, the electronic element is arranged on a side of the heat dissipation base facing the first conductive layer, the substrate is further provided with a first connecting hole, the first connecting hole penetrates through the first conductive layer and the first dielectric layer, and the electronic device defines a bottom surface of the first connecting hole; the asymmetric PCB further comprises a first conductive part, a first electroplated layer and a second electroplated layer, the first conductive part fills the first connecting hole, the electronic element and the first conductive layer are connected with the first conductive part, the first electroplated layer covers the first conductive part and the first conductive layer, the first electroplated layer and the first conductive layer constitute a first circuit layer, and the second electroplated layer covers a side of the buried layer away from the first dielectric layer.

10. An asymmetric PCB characterized by, The asymmetric PCB is processed by the manufacturing method of the asymmetric PCB according to any one of claims 1 to 8.

Images