High-voltage-withstanding over-temperature protection circuit for power amplifier

Abstract

The invention relates to a high-voltage-withstanding over-temperature protection circuit for a power amplifier, and belongs to the field of integrated circuits. The over-temperature protection circuit comprises low-voltage NMOS (N-channel metal oxide semiconductor) tubes NM0-NM2, low-voltage PMOS (P-channel metal oxide semiconductor) tubes PM0-PM10, high-voltage NLDMOS (N-channel laterally diffused metal oxide semiconductor) tubes NM3-NM4, a high-voltage NLPMOS (N-channel P-channel metal oxide semiconductor) tube PM11, NPN triodes Q0-Q2, a Schmitt trigger schmitt, inverters inv1-inv2 and resistors R0-R2. The MOS tubes NM1-NM2, the MOS tubes PM0-PM1 and the resistor R0 form a self-bias current source; the MOS transistors PM2-PM3 are P-type current mirrors and copy the current of the self-bias current source; a low-voltage logic level with temperature information is provided by the MOS tube NM0, the triode Q0 and the resistors R1-R2; the flip of a logic level is realized by the Schmitt trigger schmitt and the phase inverters inv1-inv2; the MOS tubes PM4-PM9 realize conversion from low voltage to high voltage; the MOS tubes NM3-NM4 are high-voltage-resistant devices and play a role in voltage resistance; the MOS transistors PM10-PM11 and the triodes Q1-Q2 play a bias role, so that correct logic high level is output under high voltage. The over-temperature protection circuit solves the problem that the logic level is difficult to confirm under high voltage, and is simple in structure, low in power consumption and resistant to high voltage, so that the over-temperature protection circuit has very high use value and popularization value.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power management integrated circuits, in particular to a high-voltage over-temperature protection circuit for power amplifier. BACKGROUND

[0002] The power amplifier is one of the core modules of analog integrated circuits, and its core function is to raise the power of the input signal to the level required to drive the load. Especially in wireless communication, radar systems and various radio frequency applications, power amplifiers play a vital role, and their performance directly affects the efficiency, power consumption and reliability of the system. For high-voltage and high-current power amplifiers in the automotive industry, special attention should be paid to the design of the over-temperature protection circuit to prevent over-temperature problems caused by abnormal operation of the chip in harsh external environments, which may even cause the circuit board to burn. Therefore, the present application proposes a high-voltage over-temperature protection circuit for power amplifier. SUMMARY

[0003] The purpose of the present application is to provide a high-voltage over-temperature protection circuit for power amplifier, which uses devices that are easy to integrate and suitable for various mainstream BCD processes, making it easy to integrate. It solves the problem of abnormal operation of the power amplifier at high temperature in the prior art.

[0004] In view of the above problems, the technical solution proposed by the present application is:

[0005] The present application provides a high-voltage over-temperature protection circuit for power amplifier, which includes low-voltage NMOS tubes NM0~NM2, low-voltage PMOS tubes PM0~PM10, high-voltage NLDMOS tubes NM3~NM4, high-voltage NLPMOS tube PM11, NPN triodes Q0~Q2, Schmitt trigger schmitt, inverters inv1~inv2, resistors R0~R2; Four external interfaces: low-voltage power input port vdd, high-voltage input port vcc, output port OVP, and ground port GND.

[0006] In order to better implement the technical solution of the present application, the connection relationship of the devices is as follows:

[0007] The low-voltage power input port vdd is connected to the source S of PMOS transistors PM0, PM1, PM2, and PM3; the gate G of PMOS transistor PM0 is connected to the gate G of PMOS transistors PM1, PM2, and PM3; the drain D of PMOS transistor PM0 is connected to the gate G of PMOS transistor PM0 and the drain D of NMOS transistor NM1; the drain D of PMOS transistor PM1 is connected to the gate G of NMOS transistor NM2 and the drain D of NMOS transistor NM2; the gate G of NMOS transistor NM1 is connected to the gate G of NMOS transistor NM2; the source S of NMOS transistor NM1 is connected to the upper end of resistor R0; the drain of PMOS transistor PM2... D is connected to the upper end of resistor R1 and the base B of transistor Q0; the drain D of PMOS transistor PM3 is connected to the collector C of transistor Q0, the gate G of NMOS transistor NM0, and the input of Schmitt trigger; the drain D of NMOS transistor NM0 is connected to the lower end of resistor R1 and the upper end of resistor R2; the output of Schmitt trigger is connected to the input of inverter inv1; the output of inverter inv1 is connected to the gate G of NLDMOS transistor NM3 and the input of inverter inv2; the output of inverter inv2 is connected to the gate G of NLDMOS transistor NM4; the high-voltage power supply input port Vcc is connected to the source S of PMOS transistor PM4, the source S of PMOS transistor PM5, the source S of PMOS transistor PM8, the source S of PMOS transistor PM9, and PMO... The source (S) of transistor PM10 is connected to the source (S); the gate (G) of PMOS transistor PM4 is connected to the gate (G), drain (D), and source (S) of PMOS transistor PM5; the gate (G) of PMOS transistor PM8 is connected to the drain (D), source (S), and gate (G) of PMOS transistor PM7; the gate (G) of PMOS transistor PM9 is connected to the gate (G) of PMOS transistor PM10; the output port OVP is connected to the drain (D), drain (D), and gate (G) of PMOS transistor PM7, gate (G) of PMOS transistor PM7, gate (G) of PLDMOS transistor PM11, and drain (D) of NLDMOS transistor NM4; the gate (G) of PMOS transistor PM6 is connected to the drain (D) of PMOS transistor PM6, drain (D) of PMOS transistor PM9, and NLDMOS transistor NM4. The drain D of M3 is connected; the drain D of PMOS transistor PM10 is connected to the source S of PLDMOS transistor PM11 and the substrate B of PLDMOS transistor PM11; the source S of NLDMOS transistor NM3 is connected to the substrate B of NLDMOS transistor NM3, the substrate B of NLDMOS transistor NM4, and the source S of NLDMOS transistor NM4; the drain D of PLDMOS transistor PM11 is connected to the base B of transistor Q1 and the collector C of transistor Q1; the emitter E of transistor Q1 is connected to the base B of transistor Q2 and the collector C of transistor Q2; the power input port GND is connected to the lower end of resistor R0, the source S of NMOS transistor NM2, the lower end of resistor R2, the emitter E of transistor Q0, the source S of NMOS transistor NM0, and the emitter E of transistor Q2.

[0008] The beneficial effects of the high-voltage over-temperature protection circuit for power amplifiers provided by this invention are as follows: when the power amplifier is working, the over-temperature protection circuit will detect the current temperature value in real time. When the temperature exceeds the temperature threshold set by the over-temperature protection circuit, the over-temperature protection circuit will output a shutdown signal, and the circuit will stop working to prevent the circuit from working at high temperature for a long time. When the temperature drops back to the normal temperature range, the over-temperature protection circuit will output an activation signal, and the circuit will start working again. Attached Figure Description

[0009] Figure 1 The present invention discloses a high-voltage over-temperature protection circuit for a power amplifier.

[0010] Figure 2 This invention provides a high-voltage over-temperature protection circuit for a power amplifier.

[0011] Figure 3 : Figure 2 Simulation results of the circuit shown. Detailed Implementation

[0012] The high-voltage over-temperature protection circuit for a power amplifier proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description.

[0013] The present invention provides a high-voltage over-temperature protection circuit operation for a power amplifier, as follows: Figure 1 As shown, the high-voltage input is converted to low voltage by the pre-regulator circuit, which then provides a low-voltage logic level with temperature information to the over-temperature circuit. This low-voltage logic level is then converted to a high-voltage logic level with temperature information by the level shifter circuit, enabling the switch to confirm the opening and closing of the circuit. This invention provides a high-voltage over-temperature protection circuit for a power amplifier, the principle of which is as follows: Figure 2As shown, the circuit includes the following components: low-voltage NMOS transistors NM0~NM2, low-voltage PMOS transistors PM0~PM10, high-voltage NLDMOS transistors NM3~NM4, high-voltage NLPMOS transistor PM11, NPN transistors Q0~Q2, Schmitt trigger, inverters inv1~inv2, and resistors R0~R2; four external interfaces: low-voltage power input port vdd, high-voltage voltage input port vcc, output port OVP, and ground port GND.Specifically, the low-voltage power input port vdd is connected to the source S of PMOS transistors PM0, PM1, PM2, and PM3; the gate G of PMOS transistor PM0 is connected to the gate G of PMOS transistors PM1, PM2, and PM3; the drain D of PMOS transistor PM0 is connected to the gate G of PMOS transistor PM0 and the drain D of NMOS transistor NM1; the drain D of PMOS transistor PM1 is connected to the gate G and drain D of NMOS transistor NM2; the gate G of NMOS transistor NM1 is connected to the gate G of NMOS transistor NM2; the source S of NMOS transistor NM1 is connected to the upper end of resistor R0; and the PMOS transistor PM2... The drain D of PMOS transistor PM3 is connected to the upper end of resistor R1 and the base B of transistor Q0; the drain D of PMOS transistor PM3 is connected to the collector C of transistor Q0, the gate G of NMOS transistor NM0, and the input of Schmitt trigger; the drain D of NMOS transistor NM0 is connected to the lower end of resistor R1 and the upper end of resistor R2; the output of Schmitt trigger is connected to the input of inverter inv1; the output of inverter inv1 is connected to the gate G of NLDMOS transistor NM3 and the input of inverter inv2; the output of inverter inv2 is connected to the gate G of NLDMOS transistor NM4; the high-voltage power supply input port Vcc is connected to the source S of PMOS transistor PM4, the source S of PMOS transistor PM5, the source S of PMOS transistor PM8, the source S of PMOS transistor PM9, and PM... The source (S) of transistor PM10 is connected to the source (S); the gate (G) of PMOS transistor PM4 is connected to the gate (G), drain (D), and source (S) of PMOS transistor PM5; the gate (G) of PMOS transistor PM8 is connected to the drain (D), source (S), and gate (G) of PMOS transistor PM7; the gate (G) of PMOS transistor PM9 is connected to the gate (G) of PMOS transistor PM10; the output port OVP is connected to the drain (D), drain (D), and gate (G) of PMOS transistor PM7, gate (G) of PMOS transistor PM7, gate (G) of PLDMOS transistor PM11, and drain (D) of NLDMOS transistor NM4; the gate (G) of PMOS transistor PM6 is connected to the drain (D) of PMOS transistor PM6, drain (D) of PMOS transistor PM9, and NLDMOS transistor NM4. The drain D of M3 is connected; the drain D of PMOS transistor PM10 is connected to the source S of PLDMOS transistor PM11 and the substrate B of PLDMOS transistor PM11; the source S of NLDMOS transistor NM3 is connected to the substrate B of NLDMOS transistor NM3, the substrate B of NLDMOS transistor NM4, and the source S of NLDMOS transistor NM4; the drain D of PLDMOS transistor PM11 is connected to the base B of transistor Q1 and the collector C of transistor Q1; the emitter E of transistor Q1 is connected to the base B of transistor Q2 and the collector C of transistor Q2; the power input port GND is connected to the lower end of resistor R0, the source S of NMOS transistor NM2, the lower end of resistor R2, the emitter E of transistor Q0, the source S of NMOS transistor NM0, and the emitter E of transistor Q2.

[0014] When operating within the normal temperature range, transistor Q0 is not conducting, and its collector C is at a high level. This output is a low-voltage logic high level after passing through a Schmitt trigger and an inverter. Then, through MOSFETs PM4-PM9, the low-voltage logic high level is converted to a high-voltage logic high level (Vcc). The external PMOS switch is turned off, and the chip operates normally. When the chip temperature rises for some reason and exceeds the preset temperature value, the turn-on voltage Von of transistor Q0 decreases with increasing temperature. In this case, Q0 is forced to turn on, pulling its collector potential low. This low-level signal is adjusted by a Schmitt trigger and an inverter to output a logic low level. Then, through MOSFETs PM4-PM9, the low-voltage logic high level is converted to a high-voltage logic low level (Vcc-2.5V). The external PMOS switch is turned on, and the chip stops operating. When the chip temperature drops to the set system recovery temperature value, Q0 turns off again, its collector potential returns to a high potential, and through MOSFETs PM4-PM9, the low-voltage logic high level is converted back to a high-voltage logic high level (Vcc). The external PMOS switch is turned off, and the chip resumes normal operation. In this circuit, R1, R2, and MN0 form a hysteresis circuit. Their presence allows the circuit to achieve different upper and lower threshold temperature values ​​for the voltage. Adjusting the resistance of R1 adjusts the upper threshold temperature (decreasing R1 increases the upper threshold temperature); adjusting the resistance of R2 adjusts the lower threshold temperature (increasing R2 decreases the lower threshold temperature). Simulations of the high-voltage over-temperature protection circuit for power amplifiers based on this application were performed using the Cadence Virtuoso platform. Figure 3 This is the final output result of the over-temperature protection circuit under transient simulation.

[0015] In summary, the over-temperature protection circuit proposed in this paper was built using a 60V BCD process and verified through Cadence Virtuoso simulation. Under a high-voltage 60V input, the over-temperature protection circuit proposed in this invention can correctly output a hysteresis voltage. When the ambient temperature exceeds 130℃, it outputs a logic low level vcc-2.5V under high voltage, enabling the PMOS switch to turn on and shutting down the circuit. When the ambient temperature drops to 115℃, it outputs a logic high level vcc under high voltage, the PMOS switch turns off, and the circuit restarts.

[0016] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. All technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A high-voltage over-temperature protection circuit for a power amplifier, characterized in that, include: Low-voltage NMOS transistors NM0~NM2, low-voltage PMOS transistors PM0~PM10, high-voltage NLDMOS transistors NM3~NM4, high-voltage NLPMOS transistor PM11, NPN transistors Q0~Q2, Schmitt triggers, inverters inv1~inv2, resistors R0~R2; four external interfaces: low-voltage power input port Vdd, high-voltage voltage input port Vcc, output port OVP, and ground port GND.

2. The high-voltage over-temperature protection circuit for a power amplifier according to claim 1, characterized in that: The NMOS transistors NM0~NM2 are low-voltage NMOS transistors, the PMOS transistors PM0~PM10 are low-voltage PMOS transistors, the NLDMOS transistors NM3~NM4 are high-voltage NMOS transistors, and the PLDMOS transistor PM11 is a high-voltage PMOS transistor.

3. The high-voltage over-temperature protection circuit for a power amplifier according to claim 1, characterized in that: The low-voltage power input port vdd is connected to the source S of PMOS transistors PM0, PM1, PM2, and PM3; the gate G of PMOS transistor PM0 is connected to the gate G of PMOS transistors PM1, PM2, and PM3; the drain D of PMOS transistor PM0 is connected to the gate G of PMOS transistor PM0 and the drain D of NMOS transistor NM1; the drain D of PMOS transistor PM1 is connected to the gate G of NMOS transistor NM2 and the drain D of NMOS transistor NM2; the gate G of NMOS transistor NM1 is connected to the gate of NMOS transistor NM2. The source S of the NMOS transistor NM1 is connected to the upper end of the resistor R0; the drain D of the PMOS transistor PM2 is connected to the upper end of the resistor R1 and the base B of the transistor Q0; the drain D of the PMOS transistor PM3 is connected to the collector C of the transistor Q0, the gate G of the NMOS transistor NM0, and the input terminal of the Schmitt trigger; the drain D of the NMOS transistor NM0 is connected to the lower end of the resistor R1 and the upper end of the resistor R2; the output terminal of the Schmitt trigger is connected to the input terminal of the inverter inv1; the output terminal of the inverter inv1 is connected to the gate G of the NLDMOS transistor NM3 and the input terminal of the inverter inv2; the output terminal of the inverter inv2 is connected to the NLDMOS transistor N... The gate G of PMOS transistor PM4 is connected to the PMOS transistor PM5; the high-voltage power input port Vcc is connected to the source S of PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM8, PMOS transistor PM9, and PMOS transistor PM10; the gate G of PMOS transistor PM4 is connected to the gate G of PMOS transistor PM5, the drain D of PMOS transistor PM5, and the source S of PMOS transistor PM6; the gate G of PMOS transistor PM8 is connected to the drain D of PMOS transistor PM8, the source S of PMOS transistor PM7, the gate G of PMOS transistor PM9, and the gate G of PMOS transistor PM10; the output port OVP is connected to the PMOS transistor... The drain D of PM4, the drain D of PMOS transistor PM7, the gate G of PMOS transistor PM7, the gate G of PLDMOS transistor PM11, and the drain D of NLDMOS transistor NM4 are connected; the gate G of PMOS transistor PM6 is connected to the drain D of PMOS transistor PM6, the drain D of PMOS transistor PM9, and the drain D of NLDMOS transistor NM3; the drain D of PMOS transistor PM10 is connected to the source S of PLDMOS transistor PM11 and the substrate B of PLDMOS transistor PM11; the source S of NLDMOS transistor NM3 is connected to the substrate B of NLDMOS transistor NM3 and the substrate B of NLDMOS transistor NM4 and the source S of NLDMOS transistor NM4.The drain (D) of PLDMOS transistor PM11 is connected to the base (B) and collector (C) of transistor Q1; the emitter (E) of transistor Q1 is connected to the base (B) and collector (C) of transistor Q2; the power input port GND is connected to the lower end of resistor R0, the source (S) of NMOS transistor NM2, the lower end of resistor R2, the emitter (E) of transistor Q0, the source (S) of NMOS transistor NM0, and the emitter (E) of transistor Q2.

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