Accelerating tube full-process automatic reliability test system and device

Abstract

The invention discloses an acceleration tube full-process automatic reliability test system and device, and relates to the technical field of high-power microwave device testing, and the system specifically comprises the following modules: a control test module, a hardware control module, an acquisition processing module, a business logic module, a data persistence module, and a user performance module. Writing and executing an automatic reliability test script of the acceleration tube; receiving and executing a hardware control instruction, and uploading an original analog / digital signal of the equipment; the communication module communicates with equipment in the hardware control module, converts an original analog / digital signal into a digital signal which can be processed by a C # program, and carries out filtering, unit conversion and validity verification on the digital signal; an over-limit alarm function is provided, and the structured test data is sent to the data persistence layer; storing all test related data through a relational database; test parameter configuration, real-time monitoring, alarm states, data records and dose rate curves are provided based on a graphical user interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-power microwave device testing, in particular to an accelerator tube full-process automatic reliability testing system and device. BACKGROUND

[0002] As the core component of medical linear accelerators, industrial non-destructive testing equipment, irradiation devices and other equipment, the reliability, service life and performance stability of the electronic linear accelerator tube are crucial. The traditional accelerator tube testing platform usually relies on manual operation, local files or handwritten records of data.

[0003] The prior art has the following disadvantages: (1) Data islands and poor consistency: test data is scattered in different files, formats are not uniform, and it is difficult to effectively compare horizontally and analyze long-term trends.

[0004] (2) Low degree of automation: the testing process relies heavily on manual intervention, the testing efficiency is low, and human operation errors are easily introduced.

[0005] (3) Weak reliability analysis capability: lacking deep mining capability for massive historical test data, unable to effectively establish a fault prediction model and a service life evaluation model.

[0006] (4) Difficulty in tracing and reproducing: when a problem occurs, it is difficult to quickly and accurately trace all original data, environmental parameters and equipment status of a specific test, and accurately reproduce the test conditions.

[0007] (5) Poor collaboration: data is difficult to share and collaboratively analyze within a project team or between different departments.

[0008] The above information disclosed in the background section is only used to strengthen the understanding of the background of the present disclosure, and therefore it can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0009] The purpose of the present application is to provide an accelerator tube full-process automatic reliability testing system and device to solve the problems in the background.

[0010] In order to achieve the above purpose, the present application provides the following technical solution: an accelerator tube full-process automatic reliability testing system, specifically comprising the following modules: a control testing module, a hardware control module, a collection processing module, a business logic module, a data persistence module, and a user performance module. Control testing module: writing and executing reliability automatic testing scripts for the accelerator tube, controlling the step order, conditions and loop times of the testing script; Hardware control module: receiving and executing hardware control instructions, uploading the original analog / digital signals of the equipment; The acquisition processing module communicates with the device in the hardware control module, converts the test script instruction into a protocol recognizable by the device, and converts the original analog / digital signal into a digital signal processable by the C# program, and filters, unit converts, and validity checks the digital signal. The business logic module provides an out-of-limit alarm function, provides a unified data access interface for the upper layer application, and sends the structured test data to the data persistence layer. The data persistence module stores all test-related data through a relational database. The user performance module provides test parameter configuration, real-time monitoring, alarm status, data recording, and dose rate curve based on a graphical user interface.

[0011] As a preferred scheme of the full-process automatic reliability test system of the accelerating tube, the test system comprises: The reliability automatic test script of the accelerating tube is written and executed by using the C# language. The test flow of the script is established according to the structured description, including a plurality of test step nodes and control relationships between the nodes, and the control relationships include sequential flow, parallel flow, conditional branching, loop control and timeout constraint. The test flow is saved to the flow configuration unit in the form of structured data. The flow definition in the flow configuration unit is read, and syntax analysis and semantic verification are performed on the flow nodes, connection relationships and conditional expressions. If the syntax analysis and semantic verification find inconsistencies or potential dangers, an analysis error report is generated, and the flow is prevented from being scheduled and executed until the upper logic is corrected. The test flow is driven and executed according to the analyzed node sequence, and the node life cycle is managed through event driving. The nodes are activated in sequence according to the sequential flow between the nodes, and the test script instructions for corresponding device control are sent in sequence; after the node returns successfully, the next sequential node is allowed to be entered. When there are parallel branches in the test flow, a plurality of sub-nodes are scheduled and executed at the same time, and when all the parallel branches meet the merging conditions, the subsequent flow is continued. When there is a conditional branch in the test flow, the value of the conditional expression is calculated, and the corresponding subsequent branch is selected according to the result. When there is a loop control in the test flow, specifically including: For a number of times of loop, the loop counter is initialized to a preset number of times before execution, the counter is decremented after each loop is completed, the counter is returned to the loop entrance for continuous execution when the counter is not zero, and the loop is exited when the counter is zero.

[0012] For conditional loops, the loop condition expression is re-evaluated at the end of each loop according to the flow, and if the condition is true, the loop continues, otherwise it is broken out; If each execution node is not completed within the specified time, it is configured to enter the failure processing path; Define multi-level exception strategy: immediate interruption (emergency stop), branch rollback (back to the previous step or safe node), retry, skip this step and record the risk; Exception triggering conditions include node execution failure, timeout, device alarm signal or safety constraint violation; The flow exception handling strategy is specified in the flow definition stage and can be checked by the flow parsing unit.

[0013] For exceptions that trigger a safety interruption, the engine should first execute the preset safety recovery sub-process, preserve the scene data and alarm.

[0014] As a preferred scheme of the full-process automatic reliability test system of the accelerating tube described in the application, wherein: Receive and execute hardware control instructions, and the instruction message structure includes but is not limited to operation type, target hardware identification, execution time sequence, priority, data acquisition indication; Syntax analysis and semantic verification are performed on the received instructions, and the verification content includes instruction integrity, parameter range, target hardware accessibility, required resources available and safety constraints; For batch delivery of multiple instructions, the instructions are queued and sorted according to priority and time sequence requirements, an execution plan is generated and written into a local execution queue; Establish a hardware abstraction layer, map the logical hardware identification in the instruction to a specific physical interface and channel, and record the type, electrical parameters and connection state of each physical interface and channel through the abstraction layer; In the mapping process, the current state and mutual exclusion relationship of the physical interface and channel are verified; The parsed instructions are converted into specific drive operation sequences; According to the physical interface and channel specified in the instruction, the sampling rate, sampling accuracy and trigger condition, the analog / digital signal of the device under test is sampled; For analog signals, high-resolution analog-to-digital converters are used in conjunction with front-end filters and anti-aliasing circuits; For digital signals, high-speed logic samplers or counter modules are used for capture.

[0015] As a preferred scheme of the full-process automatic reliability test system of the accelerating tube described in the application, wherein: Define the semantics of hardware control instructions and the mapping table of underlying device protocols, and the mapping table contains the protocol format, field meaning, verification method, timeout and retransmission strategy, and priority information of each type of control command and device recognizable; The system receives hardware control commands and automated test scripts, performs semantic parsing on the commands, and generates command messages for the underlying devices according to the mapping table. The messages include a frame header, command code, parameter fields, timestamp, checksum, and frame trailer. The raw analog / digital signals are received through the communication channel with the hardware control module; After decoding, the corresponding original code value is written to the local buffer according to the channel identifier and timestamp; The digitized analog signal is filtered, and the filtering algorithm can be selected according to the test requirements, such as finite impulse response filter, infinite impulse response filter, median filter, moving average, bandpass filter or adaptive filter, and the filter parameters can be switched or configured at runtime. The decoded raw code value is converted according to the channel calibration coefficient. The conversion process includes zero-point correction, gain amplification correction, linear / nonlinear correction and temperature compensation, etc., to obtain the true value of the physical quantity. The converted physical quantities are subjected to range verification, continuity verification, abrupt change detection, noise spectrum analysis and consistency verification to determine whether the data is valid; The physical relationship between channels is verified. If an inconsistency is detected, it is marked as a suspected anomaly and the original data is recorded for subsequent review.

[0016] For data that is deemed abnormal or invalid, it will be automatically repaired and the records will be directly isolated according to the configuration, and all processing paths must leave unalterable audit traces.

[0017] As a preferred embodiment of the fully automated reliability testing system for accelerator tubes described in this invention, wherein: The real-time display unit subscribes to data from a specified channel in the processed data stream and displays it on the interface in various forms, including waveforms, numerical values, statistical curves, alarm signs, and status panels. The display should show the original signal, the filtered signal, and the converted physical quantities, and indicate the filtering delay, unit, sampling rate, and calibration version; It provides trend predictions and historical comparisons, and highlights abnormal areas and trigger times on the interface.

[0018] As a preferred embodiment of the fully automated reliability testing device for the accelerator tube described in this invention, wherein: The water chiller unit cools the acceleration pipe window, pipe body, target, magnetron, pulse transformer and four-terminal circulator; The control modulation group specifically includes: a regulating motor, a hardware control module, a pulsed high voltage, and a three-phase power supply; the control modulation group is connected to the pulse transformer in the test group for voltage boosting; The test group specifically includes: pulse transformer, magnetic filament power supply, magnetron, motor, four-terminal loop current, SF6 gas tank, titanium pump power supply, electron gun power supply, and accelerating tube; The titanium pump power supply and the electron gun power supply are connected to the accelerating tube, wherein the titanium pump power supply is used to monitor the vacuum state, and the electron gun power supply provides the voltage and current of the gun filament and the gun high voltage for the accelerating tube; The magnetic filament power supply provides the voltage and current of the magnetic filament for the magnetron, and the magnetron provides microwaves for the accelerating tube, and the frequency of the magnetron is controlled by the motor; The SF6 gas tank uses SF6 as an inert medium in the test process to reduce the probability of sparking during the output of microwaves; The test group is controlled by the module of the accelerating tube full-process automatic reliability test system of the control modulation group, and the state is fed back to the control modulation group, and all data are transmitted to a relational database for storage.

[0019] In another aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the computer program is executed by the processor to implement the module of the accelerating tube full-process automatic reliability test system as described above.

[0020] In another aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the module of the accelerating tube full-process automatic reliability test system as described above.

[0021] In the above technical solution, the present application provides the following technical effects and advantages: (1) The test script writing, process analysis, hardware delivery, data acquisition, signal processing, alarm processing, data storage and visualization are integrated in the same system, avoiding information loss, time sequence dislocation and manual errors caused by manual connection of multiple systems, and improving test efficiency and consistency; (2) Through structured process configuration and syntax and semantic verification before scheduling, inconsistencies or potential dangers can be found before execution and scheduling is prevented, reducing equipment damage and safety accidents caused by script errors or dangerous configurations; (3) Support sequential flow, parallel flow, conditional branching, number / condition loop and timeout constraint, which can express complex test scenarios and test logic, and adapt to various reliability test requirements; (4) Through the hardware abstraction layer and the mapping table of control instructions to the bottom layer protocol, the differences between the bottom layer devices are shielded, and the mutual exclusion and interface state are checked in the mapping process to avoid hardware conflicts; (5) Syntax and semantic checking of the issued instruction, resource availability and target hardware accessibility checking, and generation of an execution plan according to priority and time sequence to ensure orderly and safe execution in a complex batch issuance scenario; (6) Conversion of the original code value according to the channel calibration coefficient for zero point / gain / nonlinearity / temperature compensation, followed by range checking, continuity checking, mutation detection, noise spectrum and channel consistency checking, which can effectively identify abnormal or invalid data and improve the reliability of test conclusions; (7) All test process definitions, execution instances, node logs, issued instructions, original samples, processed data, alarms and audit records are stored in a relational database, and the reference correctness and consistency between data can be ensured through transactions, foreign key constraints and integrity checking to avoid data out of sync or loss caused by decentralized storage. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0023] Figure 1 The method flowchart of the full-process automatic reliability test system for the accelerator tube of the present application.

[0024] Figure 2 The module schematic diagram of the full-process automatic reliability test system for the accelerator tube of the present application.

[0025] Figure 3 The structure schematic diagram of the full-process automatic reliability test device for the accelerator tube of the present application. DETAILED DESCRIPTION

[0026] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the gist of each example to those skilled in the art. Like reference numerals refer to like elements throughout.

[0027] Embodiment 1, with reference to Figure 1 and Figure 2 , the first embodiment of the present application provides a full-process automatic reliability test system for the accelerator tube, which specifically includes the following modules: a control test module, a hardware control module, a collection and processing module, a business logic module, a data persistence module, and a user performance module. Control test module: write and execute reliability automation test scripts of the accelerator tube, control the step sequence, conditions and loop times of the test script; Write and execute reliability automation test scripts of the accelerator tube through C# language; According to the structured description, the test flow of the script is established, including a plurality of test step nodes and control relationships between the nodes, the control relationships including sequential flow, parallel flow, conditional branching, loop control and timeout constraint; Each test step node description includes at least: step identification, step type (device control, waiting, measurement, verification, recording, delay, sub-flow calling), input and output parameters, execution timeout threshold, failure retry strategy and step priority; More importantly, for conditional branching and loop control, a condition expression model is provided to express Boolean conditions and numerical comparisons, and the condition expression can refer to real-time collected sensor data, device state, historical test data snapshot or internal flow variables; The above test flow is saved to the flow configuration unit in structured data (tree-based or graph-based intermediate representation); Read the flow definition in the flow configuration unit, and perform syntax analysis and semantic verification on the flow nodes, connection relationships and condition expressions; More importantly, static checking is performed on the test script and the flow, including but not limited to: legality of the entry and exit nodes, whether the loop has a termination condition, coverage of the conditional branching, existence of the referenced parameters, and rationality of the timeout and retry strategy configuration; If the syntax analysis and semantic verification find inconsistencies or potential dangers (infinite loop, undefined variable, no exit branch), generate an analysis error report and prevent the flow from being scheduled and executed until the upper logic is corrected; The test flow is driven and executed according to the analyzed node sequence, and the node life cycle (preparation, execution, completion, failure, rollback) is managed through event-driven; According to the sequential flow between nodes, the nodes are activated in sequence, and the test script instructions corresponding to the device control are sent in sequence; after the node returns successfully, the next sequential node is allowed to enter; When there are parallel branches in the test flow, multiple sub-nodes are scheduled and executed simultaneously, and when all parallel branches meet the merging conditions, the subsequent flow continues; When there are conditional branches in the test flow, the value of the condition expression is calculated, and the corresponding subsequent branch is selected according to the result; When there is loop control in the test flow, it specifically includes: For the number of times loop, the loop counter is initialized to the preset number of times before execution, the counter is decremented after each loop is completed, the counter is returned to the loop entrance for continuous execution when the counter is not zero, and the loop is exited when the counter is zero.

[0028] For conditional loops, the loop condition expression is re-evaluated at the end of each loop according to the flow, and if the condition is true, the loop continues, otherwise it jumps out; If each execution node is not completed within the specified time, it enters the failure processing path according to the node configuration; Define multi-level exception strategy: immediate interruption (emergency stop), branch rollback (back to the previous step or safe node), retry, skip this step and record the risk; Exception triggering conditions include node execution failure, timeout, device alarm signal or safety constraint violation, etc. The flow exception handling strategy is specified in the flow definition stage and can be checked by the flow parsing unit.

[0029] For exceptions that trigger a safety interruption, the engine should first execute the preset safety recovery sub-process (such as power off, trigger off, high voltage off, etc.), preserve the scene data and alarm.

[0030] Hardware control module: receive and execute hardware control instructions, upload the original analog / digital signals of the device; Receive and execute hardware control instructions, the instruction message structure includes but is not limited to operation type, target hardware identification, execution timing, priority, data acquisition indication; Syntax analysis and semantic verification of received instructions, verification content includes instruction integrity, parameter range, target hardware accessibility, required resources available and safety constraints; For batch delivery of multiple instructions, queue and sort the instructions according to priority and timing requirements, generate an execution plan and write it to the local execution queue; Establish a hardware abstraction layer, map the logical hardware identifier in the instruction to a specific physical interface and channel, and record the type (analog output, analog input, digital output, digital input, high voltage output, low voltage trigger, relay control, servo drive, etc.), electrical parameters and connection state of each physical interface and channel through the abstraction layer; Check the current state and mutual exclusion relationship of the physical interface and channel during mapping to avoid executing instructions that may cause hardware conflicts (driving the same voltage output to different values at the same time); Convert the parsed instructions into specific drive operation sequences, including setting analog output voltage or current, switching digital signal level, triggering relay, starting or stopping external power supply, setting signal generator parameters, controlling switch quantity acquisition module, etc. According to the physical interface and channel specified in the instruction, the sampling rate, sampling accuracy and trigger condition, the analog / digital signals of the device under test are sampled, and the sampling methods include periodic sampling, event-triggered sampling and synchronous sampling; For analog signals, a high-resolution analog-to-digital converter is used in conjunction with a front-end filter and anti-aliasing circuitry. For digital signals, they are captured using a high-speed logic sampler or counter module.

[0031] Acquisition and processing module: Communicates with the devices in the hardware control module, converts test script instructions into protocols that the devices can recognize, converts raw analog / digital signals into digital signals that can be processed by C# programs, and performs filtering, unit conversion, and validity verification on the digital signals; Define a mapping table between hardware control command semantics and underlying device protocols. The mapping table contains the protocol format, field meaning, verification method, timeout and retransmission strategy, and priority information that each type of control command can recognize and the device. The system receives hardware control commands and automated test scripts, performs semantic parsing on the commands, and generates command messages for the underlying devices according to the mapping table. The messages include a frame header, command code, parameter fields, timestamp, checksum, and frame trailer. The raw analog / digital signals are received through the communication channel with the hardware control module; After decoding, the corresponding original code value is written to the local buffer according to the channel identifier and timestamp; The digitized analog signal is filtered, and the filtering algorithm can be selected according to the test requirements, such as finite impulse response filter, infinite impulse response filter, median filter, moving average, bandpass filter or adaptive filter, and the filter parameters can be switched or configured at runtime. The decoded raw code value is converted according to the channel calibration coefficient. The conversion process includes zero-point correction, gain amplification correction, linear / nonlinear correction and temperature compensation, etc., to obtain the true value of physical quantities (voltage, current, pressure, temperature). Unit conversion supports the exchange between the International System of Units (SI) and other engineering units, and clearly records the unit type and conversion formula in the data element information to ensure that it can be used directly in the backend analysis. For channels requiring high-precision conversion, interpolation or lookup table methods are supported for non-linear conversion, and the lookup table version and interpolation method are recorded for traceability. The converted physical quantities are subjected to range verification, continuity verification, abrupt change detection, noise spectrum analysis and consistency verification to determine whether the data is valid; Verify the physical relationship between channels (the correspondence between current and voltage). If an inconsistency is detected, mark it as a suspected anomaly and record the original data for subsequent review.

[0032] For data that is deemed abnormal or invalid, it will be automatically repaired and the records will be directly isolated according to the configuration, and all processing paths must leave unalterable audit traces.

[0033] Business logic module: provide out-of-limit alarm function, provide unified data access interface for upper layer application, send structured test data to data persistence layer; Data persistence module: store all test related data through relational database; User performance module: provide test parameter configuration, real-time monitoring, alarm status, data recording and dose rate curve based on graphical user interface; Real-time display unit subscribes data of specified channel from processed data stream and displays in the form of waveform, numerical value, statistical curve, alarm sign and state panel on the interface; The display should show the original signal, the filtered signal and the converted physical quantity, and mark the filter delay, unit, sampling rate and calibration version, so as to facilitate the operator to quickly determine the data source and reliability; Provide trend prediction and historical comparison and highlight the abnormal area and trigger time on the interface. Embodiment

[0034] Below, another embodiment of the present application provides an accelerator tube full-process automatic reliability test system. In order to verify the beneficial effects of the present application, scientific demonstration is carried out through simulation experiment.

[0035] Define 10 template processes (including sequence, parallel, conditional branch, number of cycles, conditional cycle and timeout), each process contains 8-30 nodes; Prepare 5 types of equipment, each containing 4 channels (analog channel + digital channel), a total of 20 analog channels and 20 digital channels; The sampling mode is divided into: normal mode (10Hz / channel), high frequency mode (1kHz / channel) and transient capture (10kHz, short period); Each test process runs for 60-600s, and the overall simulation lasts for 24 hours to simulate long-term stability; Inject 3 types of anomalies (sudden noise, device response timeout, device alarm firing event), each type of event is distributed in the simulation period at an average of 2 times per hour during the test process.

[0036] Define five experimental scenarios, including: Normal load scenario (low concurrency): single process concurrency is 1, sampling rate is 10Hz / channel, and lasts for 24h; Concurrent scenario (medium concurrency): 10 processes are executed concurrently, the sampling rate is 100Hz / channel, and lasts for 6h; Pressure scenario (high concurrency + high frequency sampling): 50 processes are executed concurrently, the sampling rate is 1kHz / channel, and lasts for 2h; Long-term archiving scenario: mass collection events generated within 24 hours, performance evaluation of archiving and partitioning operation; Playback / reproduction scenario: historical playback and reproduction verification of 50 injected abnormal events.

[0037] Control A: raw_sample is only written to the file system CSV / binary file, and the process / alarm is written to the relational database. Playback needs to merge file and database data; Control B: all data is written to the database using a non-transactional batch insertion method, and no audit hash chain is established; Control C: raw_sample is written to a special time-series database, and process / alarm / audit is written to a relational database. The influence of mixed storage on query and playback is compared; After starting the test process, the data integrity of control A is 99.80%±0.15%, the data integrity of control group B is 98.60%±0.5%, the data integrity of control group C is 99.90%±0.05%, and the data integrity of the present application is 99.995%±0.002%; The number of consistency errors of control A is 25, the number of consistency errors of control group B is 11, the number of consistency errors of control group C is 3, and the data integrity of the present application is 1; The average single-channel time window query delay of control A is 850ms±120ms, the average single-channel time window query delay of control group B is 140ms±40ms, the average single-channel time window query delay of control group C is 95ms±25ms, and the average single-channel time window query delay of the present application is 120ms±30ms.

[0038] The test script writing, process analysis, hardware delivery, data acquisition, signal processing, alarm processing, data storage and visualization are integrated in the same system, avoiding information loss, time sequence dislocation and manual misoperation caused by manual connection of multiple systems, improving test efficiency and consistency; Through structured process configuration and syntax and semantic verification before scheduling, inconsistencies or potential dangers can be found before execution and scheduling is prevented, reducing device damage and safety accidents caused by script errors or dangerous configurations; Supporting sequential flow, parallel flow, conditional branching, number / conditional loop and timeout constraint, it can express complex test scenarios and test logic, and adapt to various reliability test requirements; Through the hardware abstraction layer and the mapping table of control instructions to the bottom layer protocol, the differences between the bottom layer devices are shielded, and the mutual exclusion and interface state are checked in the mapping process to avoid hardware conflicts; The syntax and semantics of the issued instruction are checked, resource availability and target hardware accessibility are checked, and an execution plan is generated according to priority and time sequence, so that orderly and safe execution can be ensured even in a complex batch issuance scene. The original code value is converted by a channel calibration coefficient for zero point / gain / nonlinearity / temperature compensation, and then range check, continuity check, mutation detection, noise spectrum and channel consistency check are performed, so that abnormal or invalid data can be effectively identified, and the reliability of test conclusion can be improved. All test process definitions, execution instances, node logs, issued instructions, original samples, processed data, alarms and audit records are stored in a relational database, and the reference correctness and consistency between data can be ensured through transactions, foreign key constraints and integrity checks, so that data asynchronization or loss caused by dispersed storage can be avoided.

[0039] The above only describes some exemplary embodiments of the present application in a descriptive manner, and it is needless to say that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present application. Therefore, the above drawings and descriptions are illustrative in nature and should not be understood as limiting the scope of protection of the claims of the present application.

Claims

1. An accelerated tube full flow automated reliability test system, characterized by, Specifically includes the following modules: control test module, hardware control module, acquisition processing module, business logic module, data persistence module, user performance module; Control test module: write and execute the reliability of the accelerator tube automation test script, control the step sequence, condition and loop times of the test script; Hardware control module: receive and execute hardware control instructions, upload the original analog / digital signals of the device; Acquisition processing module: communicate with the device in the hardware control module, convert the test script instructions into a protocol that the device can recognize, and convert the original analog / digital signals into digital signals that the C# program can process, filter, unit conversion, and validity check the digital signals; Business logic module: provides an alarm function for exceeding the limit, provides a unified data access interface for the upper application, and sends the structured test data to the data persistence layer; Data persistence module: stores all test-related data through a relational database; User performance module: provides test parameter configuration, real-time monitoring, alarm status, data recording, and dose rate curve based on a graphical user interface.

2. The accelerator tube full-process automated reliability test system of claim 1, wherein: The control test module writes and executes the reliability of the accelerator tube automation test script through C# language; The test flow of the script is established according to the structured description; The test flow is saved as structured data to the flow configuration unit; The flow definition in the flow configuration unit is read, and the syntax analysis and semantic verification of the flow nodes, connection relationships and condition expressions are performed; The test flow is driven and executed according to the analyzed node sequence, and the node life cycle is managed through event driving; The nodes are activated in sequence according to the order between the nodes, and the test script instructions for controlling the corresponding devices are sent in sequence; After the node returns successfully, the next sequential node is allowed to enter; When there are parallel branches in the test flow, multiple sub-nodes are scheduled for execution, and when all parallel branches meet the merging conditions, the subsequent test flow continues; When there are conditional branches in the test flow, the value of the condition expression is calculated, and the corresponding subsequent branch is selected according to the result; When there is a loop control in the test flow, it specifically includes: For the number of times of loop, the loop counter is initialized to the preset number of times before execution, the counter is decremented after each loop is completed, the counter is not zero then return to the loop entrance for continuous execution, and the counter is zero then jump out of the loop; For conditional loop, the loop condition expression is re-evaluated at the end of each loop according to the flow, and if the condition is true, the loop continues, otherwise it jumps out; If each execution node is not completed within the specified time, the node configuration enters the failure processing path; Define multi-level exception strategies: immediate interruption, branch backtracking, retry, skip the step and record the risk; For exceptions that trigger a safety interruption, execute the preset safety recovery sub-flow, preserve the on-site data and alarm.

3. The accelerator tube full-process automated reliability test system of claim 1, wherein: The hardware control module receives and executes hardware control instructions; Syntax analysis and semantic verification are performed on the received instructions; For batch delivery of multiple instructions, the instructions are queued and sorted according to priority and timing requirements, an execution plan is generated and written to the local execution queue; A hardware abstraction layer is established to map logical hardware identifiers in the instructions to specific physical interfaces and channels, and the type, electrical parameters and connection state of each physical interface and channel are recorded through the abstraction layer; The current state and mutual exclusion relationship of the physical interface and channel are checked during the mapping process; The parsed instructions are converted into specific driver operation sequences; The analog / digital signals of the device under test are sampled according to the physical interface and channel, sampling rate, sampling accuracy and trigger conditions specified in the instructions.

4. The full-process automatic reliability test system of the accelerating tube according to claim 1, characterized in that: The acquisition and processing module defines the hardware control instruction semantics and the bottom-layer device protocol mapping table; Receives hardware control instructions and automatic test scripts, performs semantic analysis on the instructions, and generates instruction messages for the bottom-layer device according to the mapping table; Receives the processed original analog / digital signals through the communication channel with the hardware control module, and performs frame checking, field decoding and error detection; Writes the corresponding original code values into the local buffer area according to the channel identifier and time stamp after decoding; Checks the physical relationship between channels, and if an inconsistency is detected, marks it as a suspected anomaly and records the corresponding original analog / digital signals, automatically repairs and directly isolates the record according to the configuration, and all processing paths are marked with non-tamperable audit traces.

5. The full-process automatic reliability test system of the accelerating tube according to claim 1, characterized in that: The user performance module displays the data subscribed by the unit from the processed data stream in the specified channel on the interface in the form of waveform, numerical value, statistical curve, alarm sign and state panel; Displays the original signal, filtered signal and converted physical quantity, and labels the filtering delay, unit, sampling rate and calibration version; Provides trend prediction and historical comparison and highlights the abnormal area and trigger time on the interface.

6. A full-process automatic reliability test device for accelerating tubes, comprising a water unit, a control modulation group and a test group, characterized in that: The water unit cools the accelerating tube window, tube body, target, magnetron, pulse transformer and four-terminal loop current device; The control modulation group specifically includes: regulating motor, hardware control module, pulse high voltage and three-phase power supply; the control modulation group is connected to the pulse transformer in the test group for voltage boosting; The test group specifically includes: pulse transformer, magnet filament power supply, magnetron, motor, four-terminal loop current device, SF6 gas tank, titanium pump power supply, electron gun power supply and accelerating tube; The titanium pump power supply and the electron gun power supply are connected to the accelerating tube, wherein the titanium pump power supply is used to monitor the vacuum state, and the electron gun power supply provides the voltage and current of the gun filament and the gun high voltage for the accelerating tube; The magnet filament power supply provides the voltage and current of the magnet filament for the magnetron, which in turn provides microwaves for the accelerating tube through the magnetron, and the motor controls the frequency of the magnetron; The SF6 gas tank uses SF6 as an inert medium in the test process to reduce the probability of sparking during the output of microwaves; The control modulation group controls the test group based on the module of the accelerator tube whole-process automatic reliability test system, feeds back the state to the control modulation group, and transmits all data to a relational database for storage. 7.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is characterized in that: The processor implements the module of the accelerator tube whole-process automatic reliability test system in any one of claims 1 to 6 when executing the computer program.

8. A computer readable storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to implement the module of the accelerator tube whole-process automatic reliability test system in any one of claims 1 to 6.

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