Circuit board electrical performance test and diagnosis method

Abstract

The invention provides a circuit board electrical performance test and diagnosis method, which comprises the following steps of: constructing a structured process-electrical data set by collecting process parameters such as etching time, pressing temperature, drilling precision, copper foil thickness and the like and electrical test indexes such as impedance deviation, leakage current, signal attenuation and the like; screening key process variables by adopting mutual information analysis and a maximum correlation-minimum redundancy criterion; through modeling of a three-layer causal diagram and a structural equation, quantitative influence evaluation of process parameters on electrical performance and fault types is realized; when a fault is detected, the system can automatically perform reverse reasoning, identify a main manufacturing deviation item and generate attribution diagnosis and process optimization suggestions, so that the accuracy of fault diagnosis and the pertinence of process adjustment are improved, and the fault occurrence rate is reduced and the product quality is improved.

Description

Technical Field

[0001] This invention relates to the field of causal attribution analysis of electrical performance failures in circuit boards, and in particular to a method for testing and diagnosing electrical performance failures in circuit boards. Background Technology

[0002] Currently, printed circuit boards (PCBs) are a core component of electronic products, and the stability and reliability of their electrical performance are crucial to the overall quality of the product. In the PCB manufacturing and testing stages, electrical performance faults such as short circuits and open circuits are among the main defects affecting product yield. To address these faults, mainstream industry technologies typically employ automated testing equipment (such as flying probe testing and in-circuit testers, ICT) to perform high-precision electrical performance testing on finished PCBs, automatically identifying short circuits, open circuits, or impedance anomalies using the electrical performance test data. Furthermore, in recent years, with the development of data analysis technology, more and more manufacturing companies have begun to introduce methods based on machine learning and statistical modeling to perform pattern mining on large-scale test data to improve fault detection rates and location efficiency. However, the existing technology still has the following limitations: (1) Most existing circuit board electrical performance fault analysis systems only use data analysis and modeling based on the final inspection test data itself. Although they can quickly identify short circuits, open circuits and other types of faults, they cannot analyze their causes layer by layer, especially the specific contribution of manufacturing process parameters to the occurrence of electrical performance faults. Therefore, the use of existing test data is limited to the level of phenomenon interpretation and fault presentation, and lacks the ability to trace the causes in depth. (2) Due to the lack of direct coupling between manufacturing process parameters and test data, the attribution paths obtained by traditional correlation analysis or machine learning classification models can only reflect the statistical relationship between test indicators, and are difficult to provide quantitative and reliable causal evidence for the precise optimization of manufacturing process links. Existing methods rely more on empirical rules or qualitative analysis in the output of process adjustment suggestions, and are difficult to form an automated, precise parameter control closed loop based on quantitative causal inference; (3) Some experimental strategies use manual annotation or process traceability tables to superficially match limited process history information with test results. These methods are limited by the shallow characteristics of data association and subjective interference, and cannot be promoted on modern automated production lines with complex processes and numerous variables. Although some universities and enterprises have proposed the idea of ​​process-electrical multidimensional data fusion, most of them stop at the stage of feature correlation analysis and have not yet formed a structured causal model framework that can automatically reverse reasoning, and lack effective expression of the quantitative transmission chain of the influence of process parameters. Summary of the Invention

[0003] In order to solve the above-mentioned technical problems, the present invention provides a method for testing and diagnosing the electrical performance of circuit boards.

[0004] The technical solution of this invention is implemented as follows: A method for testing and diagnosing the electrical performance of a circuit board, comprising: S1: Collect manufacturing process parameter data of the circuit board test sample. The manufacturing process parameters include etching time, pressing temperature, drilling accuracy, and copper foil thickness. Record the data synchronously with the corresponding electrical performance test response signal to form a process-electrical dual-dimensional dataset. S2: Standardize the process-electrical dual-dimensional dataset to eliminate data offsets and dimensional differences between different batches of samples and generate a structured input matrix in a unified format; S3: Based on the structured input matrix, the mutual information analysis method is used to calculate the correlation between each manufacturing process parameter and electrical test index, and key process variables that have a significant impact on electrical performance fluctuations are screened out. S4: Construct a three-layer cause-effect graph topology, where the top-level nodes are the selected key manufacturing process parameters, the middle-level nodes are electrical test indicators, and the bottom-level nodes are fault type labels, forming a cause-effect reasoning path of 'process → electrical response → fault'. S5: The structural equation modeling (SEM) framework is used to estimate the parameters of the causal graph topology. The causal connection weights between each node are learned by the joint maximum likelihood estimation method, and a joint process-electrical causal model is constructed. S6: After detecting a short circuit or open circuit fault on the circuit board, input the current electrical test data into the process-electrical joint causal model, perform backpropagation inference, and calculate the posterior contribution score of each key manufacturing process parameter to the fault. S7: Based on the posterior contribution score, identify the most likely manufacturing deviation item that caused the current failure, and output the corresponding process parameter anomaly type and its confidence level to generate an interpretable attribution diagnosis report. S8: Based on the attribution diagnosis report, output process optimization suggestions that match the abnormality type of the process parameters to guide parameter adjustment and quality improvement in the manufacturing process.

[0005] The circuit board electrical performance testing and diagnostic method provided in this application has the following beneficial effects: (1) This invention significantly expands the input dimension of the causal reasoning model by directly embedding manufacturing process parameters as top-level causal variables into the model, forming a three-layer causal topology covering the entire process of "process → electrical response → fault". By screening key process variables through mutual information analysis and the maximum correlation-minimum redundancy (mRMR) method, redundant information is effectively eliminated, improving the diagnostic specificity and traceability accuracy of the model. Traditional technologies often focus on the test data itself and cannot establish an intuitive causal link between the manufacturing process and electrical anomalies. However, this invention substantially solves the problem of structured coupling between process parameters and test data, enhancing the data representation ability and the physical interpretability of the model. (2) This invention, through structural equation modeling (SEM) and joint maximum likelihood estimation, can quantify the specific impact of each manufacturing process parameter on electrical performance fluctuations and fault occurrence, achieving full-link quantitative modeling from process variables to fault output. This causal parameter learning method far surpasses traditional correlation modeling, not only identifying the main causes of faults but also objectively assessing the contribution of each process link, significantly improving the accuracy and reliability of the cause diagnosis results; (3) In the fault detection and diagnosis stage, the proposed backpropagation attribution mechanism can automatically locate the manufacturing deviations most likely to cause short circuit / open circuit faults based on real-time test data and output a confidence assessment. Compared with the existing technology, which can only provide macro-risk warnings, this invention can generate a highly interpretable attribution diagnosis report, clearly indicating the specific process parameters that need to be optimized (such as etching solution concentration, pressing process window, etc.), providing a quantitative basis for process improvement and effectively shortening the decision-making cycle for anomaly investigation and production adjustment. Attached Figure Description

[0006] Figure 1 This is a flowchart of a circuit board electrical performance testing and diagnostic method according to the present invention; Figure 2 This is a sub-flowchart of a circuit board electrical performance testing and diagnostic method according to the present invention; Figure 3 This is another sub-flowchart of a circuit board electrical performance testing and diagnostic method according to the present invention. Detailed Implementation

[0007] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0008] The following disclosure provides many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0009] like Figure 1 As shown, the present invention provides a method for testing and diagnosing the electrical performance of a circuit board, specifically including: S1: Collect manufacturing process parameter data of the circuit board test sample. The manufacturing process parameters include etching time, pressing temperature, drilling accuracy, and copper foil thickness. Record the data synchronously with the corresponding electrical performance test response signal to form a process-electrical dual-dimensional dataset. S2: Standardize the process-electrical dual-dimensional dataset to eliminate data offsets and dimensional differences between different batches of samples and generate a structured input matrix in a unified format; S3: Based on the structured input matrix, the mutual information analysis method is used to calculate the correlation between each manufacturing process parameter and electrical test index, and key process variables that have a significant impact on electrical performance fluctuations are screened out. S4: Construct a three-layer cause-effect graph topology, where the top-level nodes are the selected key manufacturing process parameters, the middle-level nodes are electrical test indicators, and the bottom-level nodes are fault type labels, forming a cause-effect reasoning path of 'process → electrical response → fault'. S5: The structural equation modeling (SEM) framework is used to estimate the parameters of the causal graph topology. The causal connection weights between each node are learned by the joint maximum likelihood estimation method, and a joint process-electrical causal model is constructed. S6: After detecting a short circuit or open circuit fault on the circuit board, input the current electrical test data into the process-electrical joint causal model, perform backpropagation inference, and calculate the posterior contribution score of each key manufacturing process parameter to the fault. S7: Based on the posterior contribution score, identify the most likely manufacturing deviation item that caused the current failure, and output the corresponding process parameter anomaly type and its confidence level to generate an interpretable attribution diagnosis report. S8: Based on the attribution diagnosis report, output process optimization suggestions that match the abnormality type of the process parameters to guide parameter adjustment and quality improvement in the manufacturing process.

[0010] Step S1: Collect manufacturing process parameter data of the circuit board test samples. These parameters include etching time, lamination temperature, drilling accuracy, and copper foil thickness, and are recorded synchronously with the corresponding electrical performance test response signals to form a process-electrical dual-dimensional dataset. Specifically, this includes: S1.1: Obtain the raw data of the manufacturing process parameters of the circuit board test sample, including etching time, lamination temperature, drilling accuracy, and copper foil thickness, in order to construct the process parameter input feature space; The sensor interface initialization operation is performed on the manufacturing process parameter acquisition object. A high-precision process parameter acquisition module (configuration: etching time measurement resolution 0.1s, pressing temperature acquisition accuracy ±0.5℃, drilling accuracy acquisition accuracy ±1μm, copper foil thickness measurement accuracy ±0.2μm) is used to realize the real-time reading of the physical signals of each parameter. Furthermore, through the process data acquisition algorithm (parameter sampling frequency: 10Hz), each physical quantity is converted into a digital signal and the data is encoded to obtain the original process measurement sequence including etching time, pressing temperature, drilling accuracy and copper foil thickness. Furthermore, by utilizing the data identification and batch binding mechanism (binding parameters: sample number, production batch number, and collection timestamp), the collected process parameter digital signals are associated one by one with the current test sample to form a set of process parameters with metadata tags. Furthermore, a physical quantity unit conversion algorithm (parameter benchmark: national metrology standard) is used to uniformly convert each parameter of the original signal sequence into a standard metrology system, such as seconds, degrees Celsius, micrometers, etc., to generate an original process parameter matrix with unified units; By using a multi-channel data caching mechanism, the original process parameter matrix of standardized units is stored in a temporary data buffer, enabling real-time data supply for the downstream feature space construction process. For example, during the acquisition of process data for a batch of circuit board samples, the etching time acquisition module is set to a sampling frequency of 10Hz, and records the etching time series values ​​as follows: Seconds; the pressing temperature acquisition module records the temperature sequence values. Celsius; the mean value of the offset matrix acquired for borehole accuracy is Micrometers; Copper foil thickness sensor records thickness sequence values Micrometers. The raw signals from each channel are uniformly converted to seconds, degrees Celsius, and micrometers, and then bound to a sample number such as "LB20240305001" and batch number "BX107" to form the process parameter feature space input matrix for that sample. This matrix is ​​used for subsequent synchronous acquisition and joint modeling with the electrical performance test response signals, significantly improving the accuracy and usability of process information at the top-level nodes of the causal graph model. S1.2: The signal acquisition module based on the test platform acquires electrical performance test response signals corresponding to the manufacturing process parameters, including electrical indicators such as impedance deviation, leakage current, and signal attenuation, in order to generate an electrical response feature space. Based on the signal acquisition module of the test platform, a multi-channel synchronous sampling method is adopted (parameters: sampling frequency ≥1MS / s, number of channels ≥3) to realize the parallel acquisition function of electrical indicators such as impedance deviation, leakage current, and signal attenuation. Furthermore, by using lock-in amplification technology (parameters: the reference frequency matches the test signal frequency, bandwidth <10Hz), high-sensitivity detection of impedance deviation signals is achieved, and the impedance deviation vector data of each test point at a specific frequency is obtained; Furthermore, through a constant voltage source-ammeter closed-loop measurement method (parameters: constant voltage source stability <0.01%, ammeter resolution ≤10nA), precise acquisition of leakage current data is achieved, and two types of data results, static leakage current and dynamic leakage current, are generated. Furthermore, the amplitude-frequency characteristics of signal attenuation in the circuit board channel are calculated using a frequency domain analysis algorithm (parameters: FFT points ≥ 1024, window function type is Hanning window), generating signal amplitude attenuation curve data at different frequencies. By using the above chain-based acquisition method, the process parameter data from the previous step is mapped to the corresponding impedance deviation, leakage current, and signal attenuation data, thereby realizing the synchronous construction of the feature space corresponding to process variables and electrical responses. For example, on a circuit board testing production line, the signal acquisition module is configured with a sampling frequency of 2MS / s, and the three channels correspond to impedance testing, leakage current testing, and signal attenuation testing, respectively. Impedance deviation detection uses a lock-in amplifier with a reference frequency of 1kHz and a bandwidth of 5Hz to obtain the impedance deviation vector of a test sample at 10 measurement points. Ω. The leakage current test was performed under a constant voltage of 5V, with an ammeter resolution of 10nA, to measure the static leakage current. nA and dynamic leakage current nA. In signal attenuation analysis, with 1024 FFT points, a Hanning window, and a test frequency range of 100Hz to 10kHz, the amplitude attenuation rate at a certain frequency point of 1kHz is obtained. Amplitude attenuation rate at dB and 10kHz dB. The impedance deviation, leakage current and signal attenuation data collected through the above configuration correspond one-to-one with the previously collected process parameters such as etching time, pressing temperature, drilling accuracy and copper foil thickness, forming an electrical response feature space that can be directly used for training causal inference models, which significantly improves the accuracy of subsequent modeling and the correlation between process variables; S1.3: Perform timestamp alignment on the collected manufacturing process parameters and electrical performance test response signals. Based on the time synchronization mechanism, sample-level matching between process parameters and electrical responses is achieved to ensure the consistency and modelability of data pairs. S1.4: The process parameters and electrical response data are processed by anomaly detection and removal using a data cleaning algorithm to eliminate data noise caused by sensor failure or human error, thereby improving the reliability of subsequent modeling. S1.5: The manufacturing process parameters after cleaning are structurally integrated with the corresponding electrical performance test response signals to generate a process-electrical dual-dimensional dataset, which serves as the input matrix for constructing the causal reasoning model.

[0011] Step S2: Standardize the process-electrical dual-dimensional dataset to eliminate data offsets and dimensional differences between different batches of samples, generating a structured input matrix in a unified format. Specifically, this includes: S2.1: Perform missing value detection and filling processing on the collected process parameter data and electrical performance test response signals to eliminate data loss caused by equipment acquisition abnormalities or communication interruptions, and obtain a complete data sample set; S2.2: Based on the complete data sample set, the Z-score normalization method is used to standardize the data of each dimension to eliminate the dimensional differences between different sample batches caused by equipment calibration deviation or environmental fluctuations, and obtain a standardized dataset with zero mean and unit variance. S2.3: Perform outlier detection on the manufacturing process parameters and electrical test indicators in the standardized dataset, and use the IQR criterion based on box plots to identify and remove data points that exceed the reasonable range, so as to avoid outlier samples causing deviations in the subsequent modeling process and obtain a clean dataset; S2.4: Based on the clean dataset, feature encoding and format unification processing are performed on the manufacturing process parameters and electrical test indicators respectively to convert heterogeneous data into structured numerical matrices and obtain feature matrices and label vectors in a unified format. For the manufacturing process parameters and electrical test indicators in the clean data set, a label encoding method (parameters: process parameter type enumeration table, electrical indicator enumeration table) is adopted to realize the numerical conversion of categorical or enumerated process variables and obtain the encoding sequence that can be used for matrix processing. Furthermore, by using the one-hot encoding method (parameters: number of categories n, encoding dimension n), a sparse vector representation of discrete category data is achieved, and the order dependency between categories is eliminated, generating a high-dimensional sparse feature vector that is suitable for machine learning modeling. Furthermore, for continuous process parameters and electrical test indicators, a numerical formatting processing algorithm (parameters: floating-point precision, unified unit system) is adopted to convert numerical values ​​with different dimensions and units into the same international standard unit and maintain a uniform decimal precision to ensure the comparability of matrix elements. Furthermore, based on field mapping rules (parameters: feature field index table, label field index table), the encoded process parameters are concatenated into a feature matrix by column, and the fault types or electrical performance evaluation indicators are organized into a label vector by column, ensuring the standard consistency of the data structure; The matrix dimension verification algorithm (parameter: row and column tolerance λ) is used to match and verify the number of rows of the feature matrix with the number of rows of the label vector, thereby eliminating data sample alignment errors and achieving strict sample synchronization of the input matrix. By using feature encoding and format unification processing, the clean data obtained in the previous step is transformed into numerical matrices and label vectors that can be directly input into the modeling algorithm, thereby achieving efficient connection and feature consistency in the subsequent causal modeling stage. For example, a batch of cleanroom datasets includes four process parameters: etching time (in seconds), bonding temperature (in degrees Celsius), drilling accuracy (in micrometers), and copper foil thickness (in micrometers), as well as three electrical test indicators: impedance deviation (in ohms), leakage current (in amperes), and signal attenuation (in decibels). Categorical process parameters, such as bonding temperature levels, are mapped to values ​​0, 1, and 2 via label encoding; one-hot encoding is performed on the three bonding temperatures to obtain a sparse vector of length 3. Continuous parameters, such as etching time, are uniformly converted from the original millisecond units to seconds, retaining three decimal places of precision. Using field mapping rules, the [etching time encoding, bonding temperature encoding vector, drilling accuracy value, copper foil thickness value, impedance deviation value, leakage current value, and signal attenuation value] are sequentially concatenated into columns of a feature matrix of size 1000×7, and the label vector is a 1000×1 matrix composed of the corresponding short-circuit / open-circuit identifiers (0 or 1). The matrix dimension verification results show that the number of rows matches and there are no missing samples. After being processed in this unified format, the model can significantly improve the stability of parameter correlation calculation in the subsequent mutual information analysis step and reduce modeling bias caused by inconsistent data formats. S2.5: Perform a dataset partitioning operation on the feature matrix and label vector, dividing the data into a training set and a validation set according to a preset ratio to support cross-validation in the subsequent causal graph construction and model parameter estimation process, and generate a standardized structured input matrix.

[0012] Step S3: Based on the structured input matrix, the correlation between each manufacturing process parameter and electrical test index is calculated using mutual information analysis, and key process variables that have a significant impact on electrical performance fluctuations are screened out. For example... Figure 2As shown, it specifically includes: S3.1: Discretize the manufacturing process parameters and electrical test indicators in the structured input matrix to adapt to the input requirements of the mutual information analysis algorithm and obtain the discretized process-electrical joint feature matrix; For the structured input matrix with unified format obtained after S2 standardization, the interval discretization method is used (parameter: the number of intervals is determined according to the Sturgess formula of variable distribution) to realize the equal-width segmentation mapping of continuous manufacturing process parameters into integer interval labels. Furthermore, by using an equal-frequency discretization method based on frequency distribution (parameter: the number of bins is set according to the sample capacity and the stability of mutual information calculation), the quantile segmentation of electrical test indicators is realized, and the equal-frequency segmented coding results are obtained; Furthermore, a hybrid discretization strategy is adopted (parameter: chi-square splitting threshold is set based on a 95% confidence level) to perform supervised splitting of the joint distribution of manufacturing process parameters and electrical test indicators, mapping the original continuous variables to the optimal discrete interval encoding matrix; Furthermore, the category coding algorithm is called (parameter: the coding method is set to one-hot coding) to realize the sparse binary coding of the discretized interval label vector in the matrix column space, and to generate the process-electrical joint feature matrix adapted for mutual information calculation; Through the above discretization algorithm and encoding processing method, the standardized continuous data in the previous step is transformed into a discretized joint feature matrix that meets the input requirements of mutual information analysis, thereby realizing the stability and feasibility of variable mutual information calculation. For example, a certain batch of structured input matrices includes three types of continuous variables: etching time (minutes), bonding temperature (degrees Celsius), and impedance deviation (ohms), with the etching time distribution range set as follows: to minutes, according to the Sturgess formula Calculate when the sample size When, number of intervals Etching times were mapped to intervals of 1 to 8 using an equal-width method. Impedance deviations were segmented using equal-frequency methods, with segment boundaries set by quartiles and encoded as tags of 1 to 4. After one-hot encoding of all discrete tag matrices, the etching time interval tag "3" was transformed into [0,0,1,0,0,0,0,0], and the impedance deviation interval tag "2" was transformed into [0,1,0,0]. The final output process-electrical joint feature matrix exhibited numerical stability in subsequent mutual information calculations, and the fluctuation of mutual information values ​​was significantly reduced in the validation set, improving the accuracy and robustness of screening key process variables. S3.2: Based on the discretized process-electrical joint feature matrix, the kernel density estimation method is used to calculate the probability distribution function of each manufacturing process parameter and electrical test index, and to obtain the marginal distribution and joint distribution parameters of each variable; Based on the discretized process-electrical joint feature matrix, a kernel density estimation method (parameters: Gaussian kernel function type, bandwidth selection strategy is Silverman's rule) is used to nonparametrically model the probability distribution of each manufacturing process parameter in order to characterize its univariate marginal distribution characteristics. Furthermore, by using the kernel density estimation method (parameters: the same kernel function type and bandwidth as the marginal distribution), the probability distribution function of each electrical test index is modeled, and marginal distribution data reflecting the global value characteristics of each index is obtained; Furthermore, a two-dimensional kernel density estimation method is adopted (parameters: bivariate Gaussian kernel function, covariance matrix estimated from samples) to realize the joint probability distribution model of manufacturing process parameters and corresponding electrical test indicators, and generate a joint distribution parameter matrix containing probability density values ​​under different combinations of values; Furthermore, by solving the marginal distribution function and joint distribution function at the sample points of the feature matrix, the distribution function data of each pair of manufacturing process parameters-electrical index variables are obtained, providing the necessary probabilistic basis for subsequent mutual information calculation; By using the probability distribution function estimated by kernel density, the discretized feature matrix is ​​transformed into marginal and joint distribution technical indicators that can be used for information-theoretic correlation measurement, thus achieving the input preparation effect for parametric correlation analysis. For example, in a discretized feature matrix containing etch time and impedance deviation, the kernel density estimation uses a Gaussian kernel function with bandwidth... Calculated using Silverman's rule: in, The standard deviation of the sample is 1. This represents the number of samples. For the etching time samples, the calculation is as follows: , ,bandwidth This bandwidth is applied to Gaussian kernel density estimation to estimate the marginal distribution function of etching time for all samples. The same method is applied to impedance deviation; after calculating its marginal distribution function, a joint distribution function of etching time and impedance deviation is constructed in two-dimensional space. The joint probability density matrix shows that the joint probability density values ​​for etching time in the 5.0-6.0 minute range and impedance deviation in the 0.15-0.25 ohm range are significantly higher than in other regions. This result will serve as input for mutual information calculation in S3.3, significantly enhancing the correlation of this process variable in the subsequent information contribution matrix and improving the accuracy of overall process parameter selection. S3.3: Based on the marginal distribution and joint distribution parameters, calculate the mutual information value between the manufacturing process parameters and the electrical test indicators to quantify the degree of nonlinear correlation between the two and obtain the information contribution matrix of each parameter to the electrical performance fluctuation. Based on the marginal and joint distribution parameters of the manufacturing process parameters and electrical test indicators obtained by step S3.2, the mutual information calculation method is adopted (parameter setting: mutual information calculation is based on the Shannon information definition, and the marginal distribution P(X), P(Y) and joint distribution P(X,Y) are input) to realize the quantification of the nonlinear dependency relationship between the manufacturing process parameters and electrical test indicators; Furthermore, the discretized process parameter variables are calculated using the mutual information formula. Electrical indicator variables The probability distribution is input into the following structure: in For process parameter variables Electrical indicator variables mutual trust value, This represents the joint probability of process parameter x and electrical index y. and These represent the corresponding marginal probabilities, enabling the summation of information for each combination of values; Furthermore, by numerically calculating the above mutual information formula, the mutual information value between each manufacturing process parameter and each electrical performance index is obtained, and the calculation results are organized into a two-dimensional matrix structure to form an information contribution matrix, so as to reflect the relative contribution of different process variables to the fluctuation of electrical performance. Furthermore, numerical stability optimization techniques are employed to smooth the logarithmic operation in the mutual information summation process (parameter: a small constant ε=1e-10 is added to the log(x) calculation to prevent numerical overflow when the probability is zero), thereby achieving stable calculation of mutual information values ​​and preventing invalid or outlier values ​​from appearing in the information contribution matrix; By using mutual information calculation methods and numerical stability optimization, the marginal distribution and joint distribution parameters are transformed into quantifiable nonlinear correlation indicators, thereby generating the information contribution matrix and providing accurate correlation basis for the feature selection algorithm in the subsequent S3.4 step. For example, when processing a batch of circuit board samples, the etching time variable X1 and the impedance deviation variable Y1 are selected as the objects for mutual information calculation. The marginal probability distributions P(X1) = {0.25, 0.35, 0.40} and P(Y1) = {0.30, 0.45, 0.25} are obtained from the kernel density estimation in step S3.2, and the joint probability distribution P(X1, Y1) is [[0.10, 0.08, 0.07], [0.12, 0.15, 0.08], [0.08, 0.10, 0.22]]. Inputting the above probability parameters into the mutual information formula, the calculation result is... In the calculation of other process parameters and electrical indicators in the same batch, a 3×3 information contribution matrix is ​​formed, where each element represents the nonlinear dependence strength between the corresponding process parameter and electrical indicator. The numerical results of this matrix show that the mutual information value of X1 to Y1 is significantly higher in all combinations and is preferentially retained in the subsequent feature selection step, thereby enhancing the causal graph model's ability to accurately characterize the causes of short circuits / open circuits. S3.4: Based on the information contribution matrix, a feature selection algorithm based on information threshold is used to screen out manufacturing process parameters with mutual information values ​​higher than a preset threshold, and a preliminary candidate set of key process variables is obtained. Based on the information contribution matrix, a feature selection algorithm based on an information threshold is adopted (parameter: preset information threshold). This allows for the selection of highly correlated manufacturing process parameters from the calculated set of mutual information values. Furthermore, by comparing the mutual information value corresponding to each manufacturing process parameter in the matrix with the threshold... The size relationship is used to mark parameters that meet the filtering conditions and generate a parameter index list containing the marked status. Furthermore, an index list is used to retrieve the feature space of the original process parameters, extract the feature subset whose mutual information value exceeds the threshold, and organize the feature subset into a preliminary candidate set data structure for key process variables to ensure that the input dimensions of the subsequent redundancy analysis are concentrated in the range of high contribution parameters. Furthermore, to improve the robustness of the screening, a cross-screening method based on ranking weight is implemented by combining the ranking of parameters in the information contribution matrix. Process parameters that simultaneously meet the threshold conditions under different electrical test indicators are given higher priority scores, and the priority label field of the candidate set is updated synchronously. Furthermore, the duplicate process parameter records under different index conditions are processed by set deduplication algorithm. The duplicate items are merged and their maximum mutual information value is retained as the final score, forming a preliminary candidate set of key process variables without redundancy. By using a feature selection algorithm based on information thresholds, the mutual information value matrix from the previous step is transformed into a preliminary candidate set of key process variables, thereby achieving the expected technical effect of eliminating low-correlation variables from the full set of process parameters. For example, in a batch of circuit board test data, an information threshold is set. The mutual information value of etching time and impedance deviation in the mutual information value matrix is The mutual information value between pressing temperature and leakage current is The mutual information value between drilling accuracy and signal attenuation is The mutual information value between copper foil thickness and impedance deviation is During the calculation, a mutual information determination formula is used based on a threshold value. Etching time, bonding temperature, and copper foil thickness must satisfy a mutual information value ≥ The conditions are met, and the sample is included in the candidate set. Drilling accuracy is rejected because it is below the threshold. In the cross-screening of different electrical indicators, the bonding temperature meets the conditions in both leakage current and impedance deviation analysis, and its priority score is improved. The final output candidate set is {etching time, bonding temperature, copper foil thickness}, and each item is given a maximum mutual information score. This output provides concentrated and high-value feature input for subsequent mRMR redundancy analysis. S3.5: Perform redundancy analysis on the candidate set of key process variables, and use a variable optimization method based on the maximum correlation-minimum redundancy (mRMR) criterion to remove the collinearity effect between variables, and finally output the set of key process variables that have a significant and independent impact on electrical performance fluctuations.

[0013] Step S4: Construct a three-layer cause-effect graph topology, where the top-level nodes are the selected key manufacturing process parameters, the middle-level nodes are electrical test indicators, and the bottom-level nodes are fault type labels, forming a causal reasoning path of 'process → electrical response → fault'. Figure 3 As shown, it specifically includes: S4.1: Based on the selected key manufacturing process parameters, electrical test indicators, and fault type labels, the node types of the three types of variables are defined, with key manufacturing process parameters as top-level causal nodes, electrical test indicators as intermediate effect nodes, and fault type labels as bottom-level result nodes, to form a hierarchical division of the causal reasoning path. S4.2: Perform causal sorting on the key manufacturing process parameters in the top-level causal nodes, and determine the initial causal direction of each node in the causal graph based on their occurrence sequence in the manufacturing process and their potential impact mechanism on electrical performance, so as to construct the prior causal dependency relationship between process parameters. S4.3: Perform causal sorting on the electrical test indicators in the intermediate effect nodes, identify the dynamic causal order between each electrical indicator based on its transmission path in the abnormal evolution of electrical performance, and perform causal connection mapping with the top-level process node to establish the causal transmission path of 'process → electrical response'. The electrical test indices in the intermediate effect nodes are subjected to causal sorting processing. The input conditions are the set of electrical test indices retained after S3 filtering and the top-level causal node dataset. A Granger causality test-based method (parameters: lag order p, significance level α) is used to determine the time-series causal relationship between electrical test indicators and obtain the sequential transmission order matrix of each indicator in the evolution of electrical performance anomalies. Furthermore, by using a dynamic Bayesian network inference method (parameters: state transition probability matrix, observation probability matrix), the conditional dependency relationship of each electrical indicator between different time slices is modeled, and a dynamic causal sequence linked list between electrical indicators is generated to characterize the propagation path of electrical anomalies. Furthermore, a path weight estimation algorithm (parameters: covariance matrix based on historical samples, regularization coefficient λ) is used to quantitatively assess the causal connection strength among various electrical indicators and generate a causal strength scoring table among the indicators. Furthermore, by using a connection mapping algorithm (parameters: top-level process node set, intermediate-level causal order matrix), a one-to-one causal path connection is realized between key manufacturing process parameters and intermediate-level electrical test indicators, forming a causal transmission path mapping data structure of 'process → electrical response'. By using causal sorting and connection mapping, the causal relationship results of the electrical test indicators in the previous step are transformed into a complete process-to-electrical response transmission path, thereby achieving the traceability of electrical abnormal states and the directional correlation of process parameters. For example, in cases involving impedance deviation Leakage current Signal attenuation In the set of electrical test indicators, the lag order p of the Granger causality test is set as... The significance level α is The test revealed that impedance deviation changes before leakage current changes in the time series, and leakage current changes before signal attenuation. In dynamic Bayesian network modeling, the state transition probability matrix is ​​used... With the observation probability matrix It is inferred that there is a conditional dependence between impedance deviation and leakage current, and that leakage current has a conduction relationship with signal attenuation. In path weight estimation, the covariance matrix and regularization coefficients of historical samples are used. The connection weight from impedance deviation to leakage current is obtained as follows The connection weight from leakage current to signal attenuation is The etching time in the top-level process node. Establish a causal path connection with impedance deviation, pressing temperature By establishing a path connection with the leakage current, the generated process → electrical response conduction path can completely explain the abnormal propagation process of short-circuit faults in the verification set, significantly improving the interpretability and location accuracy of causal reasoning; S4.4: Perform causal convergence processing on the fault type labels in the bottom result nodes, establish a causal output mapping relationship between them and the intermediate layer electrical test indicators, identify the direct causal contribution path of each electrical indicator to short circuit / open circuit faults, and construct the causal output path of 'electrical response → fault'. For the fault type labels in the bottom result nodes, a convergence processing method based on causal path analysis is adopted (parameters: electrical test index set, intermediate layer node causal directed edge set) to realize the direct mapping relationship between fault type labels and intermediate layer electrical test indexes. Furthermore, by using a correlation screening algorithm based on path coefficient thresholds (parameters: path coefficient matrix, significance level α=0.05), the significant causal path identification of each electrical test index for short circuit faults is realized, and the set of direct contribution indicators corresponding to the fault type label "short circuit" is obtained. Furthermore, using the same method, we can identify the significant causal path of each electrical test index to the open circuit fault, and obtain the set of direct contribution indicators corresponding to the fault type label "open circuit". Furthermore, a causal weight normalization processing algorithm (parameter: maximum value normalization method) is adopted to unify the dimensions of the weights of each contribution path and generate an electrical index contribution score matrix that can be compared across fault types. Furthermore, based on the contribution scoring matrix, a fault convergence mapping construction function is used to generate a set of bidirectional output paths from 'electrical response → fault', enabling the causal effects of different electrical indicators to be aggregated and expressed in the fault label dimension. By using causal convergence processing and output path construction, the causal transmission results of the intermediate layer nodes in the previous step are transformed into a direct mapping relationship of the underlying interpretable fault types, thereby realizing the construction and quantification of the causal output path from electrical test indicators to short circuit / open circuit. For example, path coefficient significance analysis is performed on the electrical test indicators in the structured input matrix, and a significance level is set. Impedance deviation, leakage current, and signal attenuation were selected as the direct contributing factors. Under short-circuit fault conditions, the path factor of impedance deviation is... The path coefficient of leakage current is The path coefficient for signal attenuation is In the case of an open-circuit fault, the path factor of the impedance deviation is... The path coefficient of leakage current is The path coefficient for signal attenuation is After performing maximum value normalization on the above path coefficients, the normalized contribution of impedance deviation in short-circuit faults is: = The leakage current is = The signal attenuates to = The normalized contribution of impedance deviation in an open-circuit fault is... = The leakage current is = The signal attenuates to = By aggregating the convergence mapping function, the set of direct output paths for short-circuit faults is obtained as {impedance deviation (1), leakage current (0.9268), signal attenuation (0.5976)}, and the set of direct output paths for open-circuit faults is obtained as {signal attenuation (1), impedance deviation (0.8767), leakage current (0.7534)}. This effectively realizes the quantitative construction and interpretable expression of the causal output path of 'electrical response → fault'. S4.5: Based on the above causal hierarchy division and causal path mapping, a complete three-layer causal graph topology is generated, in which the top layer is the causal network of key manufacturing process parameters, the middle layer is the electrical test index transmission network, and the bottom layer is the fault type output node. The whole forms an interpretable 'process → electrical response → fault' causal reasoning graph, which is used for subsequent structural equation modeling and attribution reasoning. The input conditions are the top-level key manufacturing process parameter node set, the middle-level electrical test index node set, and the bottom-level fault type node set obtained by hierarchical division and path mapping through steps S4.1 to S4.4, and include the initial causal connection relationship and path direction information between nodes of each layer. A causal graph structure generation algorithm (parameters: node set, connection weight threshold, path direction set) is used to construct a causal network in the form of a directed acyclic graph for the top-level key manufacturing process parameter nodes, thereby realizing the expression of causal dependencies between the top-level process parameters. Furthermore, by using a node connection mapping method (parameters: process node set, electrical index node set, mapping matrix), the top-level process parameter network and the intermediate-level electrical test index network are structurally connected to realize the generation of a causal transmission path across layers of "process → electrical response"; Furthermore, through a causal output mapping algorithm (parameters: electrical indicator node set, fault type node set, contribution matrix), the intermediate layer electrical test indicator network and the bottom layer fault type node are connected in a directed manner to realize the generation of the causal output path of "electrical response → fault" and ensure that the connection weight meets the set interpretability threshold. Furthermore, a graph topology optimization method (parameters: node degree constraint, path redundancy threshold, topology connectivity index) is adopted to remove low-weight redundant edges and adjust node positions, thereby improving the readability and logical consistency of the graph. By using the causal graph structure serialization processing method, the top-level, middle-level and bottom-level causal networks are merged into a unified three-layer causal graph topology, realizing full-link visualization and modelable expression between process parameters, electrical indicators and fault types. The results of the previous step are transformed into a highly interpretable causal reasoning graph by using a causal graph structure generation algorithm, thereby realizing the construction of the topological foundation for subsequent structural equation modeling and attribution reasoning. For example, in a batch of circuit board test samples, the top-layer key manufacturing process parameter node set includes four nodes: etching time (EtchTime), lamination temperature (LamTemp), drilling accuracy (DrillAcc), and copper foil thickness (CuThick); the middle layer electrical test indicators include three nodes: impedance deviation (ImpDev), leakage current (LeakCur), and signal attenuation (SigAtt); the bottom layer fault type nodes include short circuit (Short) and open circuit (Open). In the causal ordering result, EtchTime and LamTemp are in the preceding process sequence, while DrillAcc and CuThick are subsequent process variables. When using the causal graph structure generation algorithm, the connection weight threshold is set to 0.2, the node degree limit is 4, and the path redundancy threshold is 0.05. In the "Process → Electrical Response" mapping, EtchTime and LamTemp are connected to ImpDev with weights of 0.45 and 0.38, respectively; DrillAcc and CuThick are connected to LeakCur and SigAtt with weights ranging from 0.25 to 0.41. In the "Electrical Response → Fault" mapping, the connection weight between ImpDev and Short is 0.52, the connection weight between LeakCur and Open is 0.47, and the connection weight between SigAtt and Short is 0.33. Redundant edges with weights less than 0.2 are removed using graph topology optimization methods; for example, the CuThick → ImpDev connection is deleted. The resulting three-layer causal graph topology is visualized in the modeling software as four process nodes at the top layer, three electrical indicator nodes in the middle layer, and two fault type nodes at the bottom layer. All valid connections are directed edges, ensuring traceability from the fault node back to the specific process deviation. This topology significantly improves the explanatory power of process parameters for fault attribution in subsequent structural equation modeling, achieving a stable mapping of the attribution path.

[0014] Step S5: The structural equation modeling (SEM) framework is used to estimate the parameters of the causal graph topology. The causal connection weights between nodes are learned using a joint maximum likelihood estimation method, and a process-electrical joint causal model is constructed. Specifically, this includes: S5.1: Based on the constructed three-layer causal graph topology, initialize the structural equation modeling parameters between each node. The structural equation modeling parameters include the path coefficients between the top-level manufacturing process parameter node and the intermediate electrical test index node, the path coefficients between the intermediate node and the output fault type node, and the error terms corresponding to each node, so as to form an initial causal model parameter set. Based on the already constructed three-layer cause-effect graph topology, the connection relationship between the top-level manufacturing process parameter node, the intermediate electrical test index node, and the bottom-level fault type node is imported as the initial input condition of the model. The structural equation model parameter initialization method (parameters: node type definition, path direction matrix, initial value of node error term) is adopted to assign the initial path coefficients between the top-level manufacturing process parameter nodes and the intermediate electrical test index nodes; Furthermore, by using a path coefficient setting algorithm (parameters: causal direction constraint, initial weight range), the initial path coefficients between the intermediate layer electrical test index nodes and the bottom layer fault type nodes are determined, and a multi-layer path coefficient set is obtained. Furthermore, by using the error term initialization method (parameters: zero mean setting, variance range constraint), the initial sampling of the error term vector of each node is realized, and the node noise control parameter set is generated; The node parameter set merging method is used to integrate the path coefficients from the top layer to the middle layer, the path coefficients from the middle layer to the bottom layer, and the node error terms into a complete initial parameter matrix of the structural equation model, which is used to support the subsequent maximum likelihood estimation and parameter optimization process. Through the above initialization algorithm or processing method, the causal graph topology structure of the previous step is transformed into a computable initial model parameter set, realizing the mathematical expression and solution feasibility of the process-electrical joint causal model. For example, in a batch of circuit board manufacturing datasets, the four key manufacturing process parameters—top layer etching time, lamination temperature, drilling accuracy, and copper foil thickness—are denoted as P1, P2, P3, and P4, respectively. The intermediate layer electrical parameters—impedance deviation, leakage current, and signal attenuation—are denoted as E1, E2, and E3, respectively. The bottom layer fault types—short circuit and open circuit—are denoted as F1 and F2, respectively. The initial path coefficients for P1→E1 are set to 0.35, P2→E2 to 0.28, P3→E3 to 0.41, E1→F1 to 0.52, E2→F2 to 0.46, and E3→F1 to 0.33. Each node error term is initialized using a Gaussian distribution with zero mean and a variance of 0.05. For example, the etching time node error term... It follows a normal distribution with a variance of 0.05, and the impedance deviation node error term... They also follow a normal distribution with the same variance, ensuring statistical consistency in subsequent estimation processes. Under this configuration, the initial parameter matrix of the structural equation model is formed as follows: the path coefficient matrix from the top layer to the intermediate layer is... The path coefficient matrix from the intermediate layer to the bottom layer is The error term vector is the set of Gaussian sampling results. In the subsequent maximum likelihood optimization process, this initialization matrix significantly improves the convergence speed and ensures the identifiability and interpretability of the causal relationship between process parameters and electrical indicators; S5.2: Standardize and constrain the parameter set for the structural equation modeling. Based on the path direction and connection relationship in the causal graph topology, set the identifiability constraint for the path coefficients and apply the distribution assumption of zero mean and constant variance to the error term to ensure the estimability of the model parameters. S5.3: Based on the process-electrical dual-dimensional data in the structured input matrix, perform covariance matrix fitting calculation for structural equation modeling, and use the maximum likelihood function to model the joint probability distribution of the observed variables to generate a measure of the difference between the theoretical covariance matrix and the sample covariance matrix. S5.4: Perform joint maximum likelihood optimization on the difference measure between the theoretical covariance matrix and the sample covariance matrix, and use an iterative nonlinear optimization algorithm to update the path coefficients to minimize the model fitting error and obtain the optimal causal connection weight matrix. S5.5: Based on the optimized causal connection weight matrix, an interpretable process-electrical joint causal model is generated. The causal model includes the influence strength of the top-level process parameters on intermediate electrical indicators, the influence path of intermediate electrical indicators on the bottom-level fault types, and the statistical significance test results of each path, so as to support subsequent reverse attribution reasoning.

[0015] Step S6: After detecting a short circuit or open circuit fault on the circuit board, the current electrical test data is input into the process-electrical joint causal model, backpropagation inference is performed, and the posterior contribution score of each key manufacturing process parameter to the fault is calculated. Specifically, this includes: S6.1: Perform electrical test data extraction operation on the detected circuit board short circuit or open circuit fault samples, and obtain the target electrical test index from the original response signal based on the preset feature extraction rules to form a standardized input feature vector for subsequent causal model inference; S6.2: Input the standardized input feature vector into the trained process-electrical joint causal model, and start the backpropagation inference mechanism based on the causal graph topology under the structural equation modeling (SEM) framework to locate the potential top-level process parameter node that caused the fault. S6.3: In the causal graph topology, based on the causal connection weights between nodes and the joint maximum likelihood estimation parameters, calculate the posterior probability distribution of each key manufacturing process parameter on the current failure, and form a process parameter contribution score matrix to reflect the influence intensity of each process deviation on the occurrence of the failure. Based on the set of structural equation parameters of the input process-electrical joint causal model, the current standardized input feature vector is mapped to the corresponding electrical test index node in the causal graph topology, ensuring that the observed values ​​of each node maintain a one-to-one correspondence with the model variables; The Bayesian posterior inference method (parameters: causal connection weight matrix, variance of error terms of each node) is adopted to calculate the conditional probability on the path of 'process parameters → electrical test indicators → fault type' in the model, and update the posterior probability distribution of the top-level manufacturing process parameters according to the current fault observation conditions. Furthermore, by using the joint maximum likelihood estimation method (parameters: sample covariance matrix, theoretical covariance matrix), the likelihood function is optimized under the causal path constraint to maximize the goodness of fit between the posterior probability estimate and the observed data, and to generate the probability value vector of each manufacturing process parameter node. Furthermore, the contribution score of each process parameter is calculated using the following formula. : in, This represents the posterior probability of process parameter C under the observed fault F. This represents the prior probability of process parameter C; Furthermore, a matrix processing approach is adopted to assemble the contribution scores of all process parameters according to node indices. A score matrix in the form of a normalization matrix ensures the feasibility of subsequent normalization and sorting operations; By calculating and assembling the matrix using the above formulas, the impact of each key manufacturing process parameter on the current failure is quantified into a directly comparable contribution score matrix, thereby enabling interpretable causal reasoning data output. For example, in the short-circuit diagnosis process of a batch of circuit boards, the input feature vector includes an impedance deviation of 0.8Ω, a leakage current of 2.1mA, and a signal attenuation of 0.15dB. The process parameters are an etching time of 45s, a bonding temperature of 180℃, a drilling accuracy of ±5μm, and a copper foil thickness of 35μm. After maximum likelihood optimization, the path coefficient matrix in the model has a coefficient of 0.62 from the etching time node to the impedance deviation node, and a coefficient of 0.85 from the impedance deviation to the short-circuit fault. After inputting the observed data, the posterior probability of the etching time node is calculated. The prior probability is 0.74. The value is 0.50, corresponding to a contribution score of [missing value]. =0.48. Perform similar calculations on all parameters to form a score matrix. Among them, the etching time score was the highest, indicating that the deviation of this parameter significantly increased the impact of short-circuit faults. The inference results were used to generate subsequent process optimization suggestions. S6.4: Perform normalization processing on the process parameter contribution score matrix to eliminate the influence of different parameter dimensions on the contribution calculation, and generate a posterior contribution score vector with unified dimensions for subsequent attribution analysis and process optimization suggestion generation; S6.5: Based on the posterior contribution score vector, identify the key manufacturing process parameter with the highest score as the main cause of failure, and combine it with the path weight information of the cause-effect graph to generate structured reasoning path data to support the interpretability output of subsequent diagnostic reports. Based on the normalized posterior contribution score vector, a maximum value search algorithm (parameters: score vector dimension, search direction, comparison precision) is used to locate the maximum element of the score value, thereby realizing the identification of the main fault cause nodes; Furthermore, the main fault cause node is indexed and bound to the upper-level manufacturing process parameter node in the causal graph through a path weight mapping algorithm (parameters: causal connection weight matrix, node index mapping table), and all valid causal path sets between the node and the fault type node are extracted to realize the collection of path dependency data. Furthermore, by performing sequential product operations on the connection coefficients of each causal path through path traversal and weight accumulation calculation methods (parameters: path set, weight matrix, accumulation mode), the total transmission strength of the path to the fault type is obtained, resulting in a structured inference path strength matrix. Furthermore, a structured coding method (parameters: path node sequence, node type label, connection weight value) is used to convert the above inference path strength matrix into a data structure in the format of node-connection-weight triples, so as to realize the standardized recording and visualization support of causal inference paths; Through the above multi-level chain processing, the key manufacturing process parameters with the highest posterior contribution and their causal path information are transformed into highly interpretable structured reasoning path data, achieving a clear mapping effect between the cause of failure and process deviation. For example, in a short-circuit fault detection scenario for a batch of circuit boards, the posterior contribution score vector has a length of 4, and each element corresponds to etching time, lamination temperature, drilling accuracy, and copper foil thickness, with normalized scores of 0.25, 0.18, 0.46, and 0.11, respectively. When using the maximum value search algorithm, the comparison precision is set to... The highest scoring element was identified as drilling accuracy (score 0.46). This parameter node was indexed and bound to the process node set in the cause-effect graph, extracting three valid paths to the fault type node: drilling accuracy → impedance deviation → short circuit, drilling accuracy → leakage current → short circuit, and drilling accuracy → signal attenuation → short circuit. When calculating path strength, the weight of drilling accuracy to impedance deviation was assumed to be... The weight of impedance deviation to short circuit is The total transmission strength along the path is calculated using the formula... Calculated Similarly, the total transmission strength of the other two paths can be calculated, generating the following triplet data: {node sequence: [drilling accuracy, impedance deviation, short circuit], weight value: 0.4588}, {node sequence: [drilling accuracy, leakage current, short circuit], weight value: 0.4032}, {node sequence: [drilling accuracy, signal attenuation, short circuit], weight value: 0.3765}. This structured result can be directly called in the diagnostic report generation module and can present the complete causal chain in the MES system visualization interface, significantly improving the efficiency of engineers in interpreting the causes of faults and the targeting of process optimization.

[0016] Step S7: Based on the posterior contribution score, identify the most likely manufacturing deviation causing the current fault, output the corresponding process parameter anomaly type and its confidence level, and generate an interpretable attribution diagnosis report. Specifically, this includes: S7.1: Normalize the posterior contribution scores of each key manufacturing process parameter obtained by backpropagation inference to eliminate the differences in dimensions and weights among different parameters and obtain a standardized process parameter contribution distribution vector. S7.2: Based on the standardized process parameter contribution distribution vector, the maximum a posteriori probability criterion is used to identify the manufacturing deviation item most likely to cause the current failure and determine the corresponding process parameter anomaly type, such as insufficient etching, abnormal pressing temperature, drilling offset or uneven copper foil thickness. S7.3: For the most likely manufacturing deviation item identified, combine the corresponding path coefficients and error terms in the structural equation model to calculate its causal confidence level for the current failure type, and form a statistically significant attribution confidence index. For the highest contribution parameter in the standardized process parameter contribution distribution vector, the path coefficient mapping analysis method (parameters: cause-effect graph topology, path coefficient matrix between nodes) is used to quantify and locate the direct and indirect causal paths of this parameter in the structural equation model. Furthermore, by using the error term variance decomposition method (parameter: residual variance of each node in the structural equation model), the proportion of noise influence of this process parameter on the transmission path is calculated, and it is weighted and combined with the path coefficient to obtain the noise-corrected path effect matrix. Furthermore, a posterior probability transformation algorithm (parameters: weighted path action value matrix, Bayes' theorem) is adopted to map the path action value to the posterior probability distribution of the current fault type caused by the process parameter, and generate probability vectors under different fault labels; Furthermore, based on the significance test method (parameters: path coefficient statistic, degrees of freedom, significance level), the statistical reliability of each probability value in the posterior probability distribution is evaluated to eliminate probability components with high volatility and insignificance. By using the causal confidence calculation formula, the effective posterior probability vector of the previous step is transformed into an attribution confidence index, thereby realizing the statistical quantification of the causal contribution of the process parameter in the current failure. in, As a causal confidence index, This represents the posterior probability value of the process parameter. For path coefficients, The variance of the error term along this path; For example, in a batch of circuit board samples with abnormal lamination temperatures, the highest normalized value of the process parameter contribution corresponds to the lamination temperature variable. The direct path coefficient for lamination temperature → impedance deviation in the path coefficient matrix is... The path coefficient for impedance deviation → short circuit fault is The variance of the error term was measured as follows: The combined effect of pressing temperature on short circuits was obtained through path coefficient mapping analysis. After correcting for the noise effect using variance decomposition, the effect value is... The posterior probability is calculated based on Bayes' theorem. And after significance testing, it is at a significance level. The following test was passed. Substituting into the causal confidence score calculation formula: The causal confidence index is approximately This result was marked as a high-confidence attribution in the diagnostic output, supporting the identification of abnormal pressing temperature as the main cause of failure and providing quantitative basis for subsequent process optimization; S7.4: Based on the abnormal types of the process parameters and the corresponding causal confidence index, construct a structured attribution diagnosis report template to transform the causal reasoning results into a highly readable and operable diagnostic output; The input conditions are the process parameter anomaly type data output from step S7.3 and their corresponding causal confidence index. The data exists in the form of a structured array, which includes parameter identifiers, anomaly type labels and confidence values. The template mapping method (parameters: exception type label set, template library index rules) is used to match each exception type with predefined report structure paragraphs at the field level and generate corresponding text placeholder frames. Furthermore, by using a data filling algorithm (parameters: report structure paragraphs, causal confidence values), quantitative confidence information is injected into the placeholder areas of each field, and a set of diagnostic cause descriptions with clear numerical explanations is obtained. Furthermore, through an interpretability enhancement algorithm (parameters: causal path weight matrix, anomaly type label), a cause-effect link description is generated, and the transmission mechanism from each process deviation item to the fault type is presented in a structured table format, generating causal link visualization data; Furthermore, through a format standardization process (parameters: diagnostic cause description set, causal link visualization data), the font, indentation, and numbering rules of each paragraph are unified, and a structured diagnostic report object that meets the interface requirements of the patent specification and the quality management system is generated. By combining structured template generation with data filling, the anomaly type and confidence index results from the previous step are transformed into a highly readable attribution diagnosis report that includes causal link explanations, enabling actionable output of manufacturing deviations. For example, in the attribution analysis of short-circuit faults on a batch of circuit boards, the input anomaly type label is "insufficient etching," with a corresponding causal confidence index of 0.87. The template mapping method is used to match "insufficient etching" to the "Etching Process Deviation Description" paragraph of the process anomaly report template, generating a field framework containing a title, cause description, and causal link location. A data filling algorithm is used to fill the confidence value of 0.87 into the "Confidence" field and convert it into the text description "This conclusion has 87% statistical significance." In the interpretability enhancement algorithm, based on the path coefficient matrix obtained in the SEM model, the path coefficient 0.65 from the "Etching Time" node to the "Impedance Deviation" node is mapped to the causal link table, generating a link description of "Reduced Etching Time → Decreased Impedance → Short-Circuit Fault." In the format standardization process, the chapter numbers are standardized from Arabic numerals to two-level heading numbers, and the link table is set to a three-column format: cause node, conduction mechanism, and intermediate electrical indicators. The final structured diagnostic report includes a textual explanation of the cause of the etching deficiency, a corresponding causal confidence score of 0.87, a clear process-electrical-fault link, and a standardized data structure for use in the quality management system interface. S7.5: Output the attribution diagnosis report to the Manufacturing Execution System (MES) or Quality Management System (QMS) through a visual interface or standard data interface to provide a direct basis for subsequent process parameter adjustments and quality improvements.

[0017] Step S8: Based on the attribution diagnosis report, output process optimization suggestions that match the abnormality type of the process parameters, to guide parameter adjustment and quality improvement in the manufacturing process. Specifically, this includes: S8.1: Analyze the abnormal types and confidence levels of process parameters output in the attribution diagnosis report to identify the main manufacturing deviations that cause the current circuit board short circuit or open circuit faults and obtain the set of key process abnormal parameters. S8.2: Based on the set of key process abnormal parameters, call the preset process knowledge graph, retrieve the process optimization strategy template that matches the abnormal parameters, and generate a preliminary process adjustment suggestion list; S8.3: Perform a feasibility assessment on each suggestion in the preliminary process adjustment suggestion list, and select feasible optimization schemes that meet the actual production conditions by combining the current production line equipment capacity, process window limitations and historical stable operating parameter ranges. S8.4: Based on the feasible optimization scheme, the process simulation engine is used to predict and simulate the electrical performance after the proposed parameter adjustment, calculate the impedance deviation, leakage current and signal attenuation trend of the circuit board after adjustment, and obtain the performance prediction results after process adjustment. S8.5: Based on the performance prediction results after the process adjustment, rank the effectiveness of each optimization scheme, output hierarchical process optimization suggestions, and attach the expected improvement effect and recommended implementation priority to generate a structured process optimization report.

[0018] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

[0019] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and rules of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing and diagnosing the electrical performance of a circuit board, characterized in that, Includes the following steps: S1: Collect manufacturing process parameter data of circuit board test samples and record them synchronously with the corresponding electrical performance test response signals to form a process-electrical dual-dimensional dataset; S2: Standardize the process-electrical dual-dimensional dataset to generate a structured input matrix in a unified format; S3: Based on the structured input matrix, calculate the correlation between each manufacturing process parameter and electrical test index, and screen out key process variables that have a significant impact on electrical performance fluctuations; S4: Construct a three-layer cause-effect graph topology, where the top-level nodes are the selected key manufacturing process parameters, the middle-level nodes are electrical test indicators, and the bottom-level nodes are fault type labels. S5: The structural equation modeling framework is used to estimate the parameters of the causal graph topology, learn the causal connection weights between each node, and construct a process-electrical joint causal model. S6: After detecting a short circuit or open circuit fault on the circuit board, input the current electrical test data into the process-electrical joint causal model, perform backpropagation inference, and calculate the posterior contribution score of each key manufacturing process parameter to the fault. S7: Based on the posterior contribution score, identify the most likely manufacturing deviation item that caused the current failure, and output the corresponding process parameter anomaly type and its confidence level to generate an interpretable attribution diagnosis report. S8: Based on the attribution diagnosis report, output process optimization suggestions that match the abnormality type of the process parameters.

2. The method for testing and diagnosing the electrical performance of a circuit board according to claim 1, characterized in that, Step S1 specifically includes: Obtain the raw data of manufacturing process parameters for circuit board test samples and construct the process parameter input feature space; Based on the signal acquisition module of the test platform, electrical performance test response signals corresponding to the manufacturing process parameters are acquired, and an electrical response feature space is generated. The manufacturing process parameters and the electrical performance test response signal are timestamp aligned, and sample-level matching between the process parameters and the electrical response is performed based on a time synchronization mechanism. Data cleaning algorithms are used to detect and remove outliers from the manufacturing process parameters and electrical response data; The manufacturing process parameters after cleaning are structurally integrated with the corresponding electrical performance test response signals to generate a process-electrical dual-dimensional dataset.

3. The method for testing and diagnosing the electrical performance of a circuit board according to claim 2, characterized in that, The manufacturing process parameters include etching time, pressing temperature, drilling accuracy, and copper foil thickness.

4. The method for testing and diagnosing the electrical performance of a circuit board according to claim 1, characterized in that, Step S2 specifically includes: Missing value detection and imputation are performed on the collected process parameter data and electrical performance test response signals to obtain a complete data sample set; Based on the complete data sample set, a normalization method is used to standardize the data in each dimension to obtain a standardized dataset with zero mean and unit variance. Outlier detection is performed on the manufacturing process parameters and electrical test indicators in the standardized dataset. The IQR criterion based on box plots is used to identify and remove data points that exceed the reasonable range to obtain a clean dataset. Based on the clean dataset, the manufacturing process parameters and electrical test indicators are respectively subjected to feature encoding and format unification processing, and the heterogeneous data is converted into a structured numerical matrix to obtain a feature matrix and label vector in a unified format. Perform a dataset partitioning operation on the feature matrix and label vector, dividing the data into a training set and a validation set according to a preset ratio, and generating a standardized structured input matrix.

5. The method for testing and diagnosing the electrical performance of a circuit board according to claim 1, characterized in that, Step S3 specifically includes: The manufacturing process parameters and electrical test indicators in the standardized structured input matrix are discretized to obtain the discretized process-electrical joint feature matrix; Based on the discretized process-electrical joint feature matrix, the kernel density estimation method is used to calculate the probability distribution function of each manufacturing process parameter and electrical test index, and to obtain the marginal distribution and joint distribution parameters of each variable. Based on the marginal distribution and joint distribution parameters, the mutual information value between the manufacturing process parameters and electrical test indicators is calculated to obtain the information contribution matrix of each parameter to the electrical performance fluctuation. Based on the information contribution matrix, a feature selection algorithm based on information threshold is used to screen out manufacturing process parameters with mutual information values ​​higher than a preset threshold, thereby obtaining a preliminary candidate set of key process variables. Redundancy analysis is performed on the candidate set of key process variables, and a variable optimization method based on the maximum correlation-minimum redundancy criterion is adopted to output the set of key process variables.

6. The method for testing and diagnosing the electrical performance of a circuit board according to claim 5, characterized in that, Step S3 further includes discretizing process parameters and electrical test indicators through mutual information analysis, constructing a probability distribution using Gaussian kernel density estimation, outputting an information contribution matrix, and screening key variables.

7. The method for testing and diagnosing the electrical performance of a circuit board according to claim 1, characterized in that, Step S4 specifically includes: Based on the selected key manufacturing process parameters, electrical test indicators, and fault type labels, node types are defined for the three types of variables. Key manufacturing process parameters serve as top-level causal nodes, electrical test indicators serve as intermediate effect nodes, and fault type labels serve as bottom-level result nodes, forming a hierarchical division of the causal reasoning path. The key manufacturing process parameters in the top-level causal nodes are causally ordered, and the initial causal direction of each node in the causal graph is determined based on their occurrence sequence in the manufacturing process and their potential impact mechanism on electrical performance, thus constructing the prior causal dependency relationship between the process parameters. The electrical test indicators in the intermediate effect nodes are causally ordered. Based on their transmission paths in the evolution of abnormal electrical performance, the dynamic causal order between each electrical indicator is identified, and they are causally connected and mapped to the top-level process nodes to establish a causal transmission path of 'process → electrical response'. The fault type labels in the bottom result nodes are subjected to causal convergence processing, and a causal output mapping relationship is established between them and the intermediate layer electrical test indicators. The direct causal contribution path of each electrical indicator to short circuit / open circuit fault is identified, and the causal output path of 'electrical response → fault' is constructed. Based on the causal hierarchy division and causal path mapping results, a complete three-layer causal graph topology is generated, where the top layer is the causal network of key manufacturing process parameters, the middle layer is the transmission network of electrical test indicators, and the bottom layer is the fault type output node, forming an interpretable 'process → electrical response → fault' causal reasoning graph.

8. The method for testing and diagnosing the electrical performance of a circuit board according to claim 7, characterized in that, In step S4, the causal modeling process constructs a three-layer causal graph structure, with the top layer being key process parameter nodes, the middle layer being electrical test index nodes, and the bottom layer being fault type nodes. The direct and indirect causal paths of process parameters to fault types are inferred through causal directions and Bayesian networks.

9. The method for testing and diagnosing the electrical performance of a circuit board according to claim 1, characterized in that, Step S5 specifically includes: Based on the constructed three-layer causal graph topology, the structural equation modeling parameters between each node are initialized to form an initial causal model parameter set; The parameter set for structural equation modeling is standardized and constrained. Based on the path direction and connection relationship in the causal graph topology, the identifiability constraint condition of the path coefficient is set, and the distribution assumptions of zero mean and constant variance are applied to the error term. Based on the process-electrical dual-dimensional data in the structured input matrix, the covariance matrix fitting calculation of structural equation modeling is performed, and the joint probability distribution of the observed variables is modeled using the maximum likelihood function to generate a measure of the difference between the theoretical covariance matrix and the sample covariance matrix. Joint maximum likelihood optimization is performed on the difference measure between the theoretical covariance matrix and the sample covariance matrix. An iterative nonlinear optimization algorithm is used to update the path coefficients, minimize the model fitting error, and obtain the optimal causal connection weight matrix. Based on the optimized causal connection weight matrix, a process-electrical joint causal model is generated.

10. A method for testing and diagnosing the electrical performance of a circuit board according to claim 9, characterized in that, The process-electrical joint causal model includes the influence strength of top-level process parameters on intermediate electrical indicators, the influence path of intermediate electrical indicators on bottom-level fault types, and the statistical significance test results of each path.

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