Implementation method and apparatus for RISC-V-based write mask vector instructions
By generating and adapting mask calculation identifiers, the problem of reduced execution efficiency caused by register renaming in the RISC-V vector extension standard is solved, and instruction execution efficiency is improved and resource consumption is reduced without increasing the number of uops and VRF ports.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU QUNXIN MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2025-09-26
- Publication Date
- 2026-05-26
AI Technical Summary
In the RISC-V vector extension standard, existing technologies involve multiple micro-operations written to different physical registers due to register renaming, resulting in reduced execution efficiency and increased resource consumption, especially in high-performance CPUs where additional read ports and execution cycles are added.
By generating a mask to calculate the identifier, the original mask of the current micro-operation uop is processed and the vector length is adapted. The execution result of the previous uop is used to keep the number of uops and the VRF ports unchanged, and the instruction calculation is completed.
This improves command execution efficiency, reduces resource consumption, and avoids the need to increase the number of uops or VRF ports.
Smart Images
Figure CN121326406B_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of computer technology, and in particular to a method and apparatus for implementing write mask vector instructions based on RISC-V. Background Technology
[0002] In some instructions of the RISC-V Vector Extensions (RVV) standard, such as vector comparison instructions, the source operands vs2 and vs1 are vector registers, and the destination operands vd and mask v0 are mask registers. When the Vector register group multiplier (LMUL) is greater than 1, multiple micro-operations (uops) need to write to the same destination register. However, due to the existence of register renaming in the processor, without additional processing, these uops will write to different physical registers, and thus cannot obtain the correct result.
[0003] In existing technologies, since multiple uops write to different physical registers, additional uops are added to read the calculation results from different physical registers into the new uops for combination, which can complete the entire calculation. However, because additional uops are added, the number of uops that can be split within one clock cycle is exceeded, requiring two clock cycles to complete the calculation. Furthermore, this increases the number of times an instruction needs to be executed, significantly reducing execution efficiency.
[0004] If no additional UOP is added, meaning the calculation result of the previous UOP needs to be read when the next UOP is executed, and since a single UOP originally needs to read a maximum of four sets of data, the VRF needs to provide four read windows. If an additional set of data needs to be read, then an additional read window is required. However, adding an extra read window inevitably increases the area, and in high-performance CPUs, there are often multiple execution pipelines, requiring multiple additional VRF read ports, which consumes significant resources. Summary of the Invention
[0005] To address the problems existing in the prior art, this specification provides a method and apparatus for implementing write mask vector instructions based on RISC-V, which achieves the functionality while keeping the number of uops and the Vector Register File (VRF) port unchanged.
[0006] The specific technical solutions of the embodiments in this specification are as follows:
[0007] On the one hand, embodiments of this specification provide a method for implementing write mask vector instructions based on RISC-V, the method comprising:
[0008] The original mask for the current micro-operation uop is generated based on the mask in the instruction opcode;
[0009] The original mask of the current uop is adapted to the vector length vlen to obtain the final mask of the current uop;
[0010] Obtain the execution result of the previous uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop; execute the current uop to obtain the execution result of the current uop.
[0011] Furthermore, the process of generating the original mask for the current micro-operation uop based on the mask calculation identifier in the instruction opcode further includes:
[0012] If the mask calculation identifier in the instruction opcode indicates mask calculation, then the original mask of the current uop is extracted from the mask register v0 according to the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype.
[0013] If the mask calculation identifier in the instruction opcode indicates non-mask calculation, then the original mask of the current uop is generated based on the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype.
[0014] Furthermore, extracting the original mask of the current UOP from v0 based on the position of the valid processing segment body of the vector register group of the current UOP operation, the index of the current UOP, and the number of UOP processing elements determined according to the configuration of the vector configuration register vtype further includes:
[0015] Set all bits between the bit corresponding to the vector start index vstart position and the bit corresponding to the effective vector length vl position in the first binary number with the same length as vlen, and set the remaining bits of the first binary number to 0.
[0016] Perform a bitwise AND operation between the first binary number and v0 to obtain the mask result;
[0017] Based on the index of the current uop and the number of elements processed by the uop, the mask corresponding to the current uop is extracted from the mask result to obtain the original mask of the current uop.
[0018] Furthermore, generating the original mask of the current UOP based on the position of the valid processing segment body in the vector register group of the current UOP operation, the index of the current UOP, and the number of UOP processing elements determined according to the configuration of the vector configuration register vtype further includes:
[0019] Set all bits between the starting index vstart and the effective vector length vl of the vector register group in the first binary number with the same length vlen to 1, and set the remaining bits of the first binary number to 0 to obtain the mask result;
[0020] Based on the index of the current uop and the number of elements processed by the uop, the mask corresponding to the current uop is extracted from the mask result to obtain the original mask of the current uop.
[0021] Furthermore, extracting the mask corresponding to the current UOP from the mask result based on the index of the current UOP and the number of elements processed by the UOP, to obtain the original mask of the current UOP, further includes:
[0022] The starting truncation position is calculated based on the index of the current uop and the number of elements processed by the uop;
[0023] Starting from the initial truncation position in the mask result, a total of several bits of the mask for the number of elements processed by the uop are extracted to obtain the original mask of the current uop.
[0024] Furthermore, the original mask of the current uop is adapted to the vector length vlen to obtain the final mask of the current uop, which further includes:
[0025] The placement position of the original mask of the current uop in a second binary number with the same length as vlen is determined based on the index of the current uop and the length of the original mask;
[0026] Set the values of each bit corresponding to the placement position in the second binary number to the values of the corresponding bits of the original mask of the current uop;
[0027] Set the values of all bits in the second binary number except for the placement position to 0 to obtain the final mask.
[0028] Furthermore, determining the placement of the original mask of the current uop in a second binary number of the same length as vlen, based on the index of the current uop and the length of the original mask, further includes:
[0029] The starting position for placement is calculated based on the index of the current uop and the length of the original mask;
[0030] The placement end position is calculated based on the starting position and the length of the original mask.
[0031] Furthermore, setting the values of the bits corresponding to the placement positions in the second binary number to the values of the corresponding bits of the original mask of the current UOP further includes:
[0032] The values of the placement start bit to the placement end bit in the second binary number are sequentially set to the values of the least significant bit to the most significant bit of the original mask of the current uop.
[0033] Further, if the current UOP is the first UOP, then obtaining the execution result of the previous UOP, the first source operand and the second source operand corresponding to the current UOP, and the final mask of the current UOP, and executing the current UOP, the execution result of the current UOP further includes:
[0034] Obtain the target operand, the first source operand and the second source operand corresponding to the first uop, and the final mask of the first uop. Execute the first uop to obtain the execution result of the first uop.
[0035] Furthermore, all positions 1 in the vector register group of the first binary number with the same length as vlen, from the bit corresponding to the vector start index vstart position to the bit corresponding to the effective vector length vl position, further include:
[0036] The number of bits corresponding to each element in the first binary number is determined based on the element bit width;
[0037] Calculate the total number of bits for the multiple elements based on the multiple elements between the vstart position and the vl position and the number of bits;
[0038] Set the value of each bit in the first binary number, starting from the bit corresponding to the vstart position, to 1.
[0039] On the other hand, embodiments of this specification also provide an implementation apparatus for a RISC-V-based write mask vector instruction, the apparatus comprising:
[0040] The vector mask generation unit is used to generate the original mask of the current micro-operation uop based on the mask calculation identifier in the instruction opcode;
[0041] A vector masking unit is used to adapt the original mask of the current uop to the vector length vlen to obtain the final mask of the current uop.
[0042] The vector result selection unit is used to obtain the execution result of the previous uop of the current uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop, execute the current uop, and obtain the execution result of the current uop.
[0043] On the other hand, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.
[0044] By processing the mask of the uop using the method in the embodiments of this specification, when the current uop is executed, the execution result of the previous uop, the first source operand, the second source operand corresponding to the current uop, and the final mask of the current uop are obtained. Utilizing the characteristics of the mask, the calculation result of the previous uop remains unchanged during the execution of the current uop. Thus, the calculation result of the current uop, the calculation result of the previous uop, and the target operand are saved, thereby keeping the number of uops and the VRF ports unchanged, completing the instruction calculation. Compared to existing methods that additionally increase the number of uops or increase the number of VRF ports, the method in the embodiments of this specification improves instruction execution efficiency and reduces resource consumption. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 The diagram shown is a schematic diagram of the vector instruction execution microstructure in the embodiments of this specification;
[0047] Figure 2 The diagram shown is a flowchart illustrating the implementation method of the RISC-V-based write mask vector instruction in the embodiments of this specification.
[0048] Figure 3 The diagram shown is a schematic representation of the update result of uop in an embodiment of this specification.
[0049] Figure 4 The diagram shown is a flowchart illustrating the process of generating the original mask of the current uop in the case of mask calculation in the embodiments of this specification.
[0050] Figure 5The diagram shown is a flowchart illustrating the process of generating the original mask of the current uop in the case of non-mask calculation in the embodiments of this specification.
[0051] Figure 6 The diagram shown is a schematic diagram of generating the original mask of the current uop in an embodiment of this specification;
[0052] Figure 7 The diagram shown is a flowchart illustrating the process of extracting the mask corresponding to the current UOP from the mask result based on the index of the current UOP and the number of elements processed by the UOP in an embodiment of this specification, thereby obtaining the original mask of the current UOP.
[0053] Figure 8 The diagram shown is a flowchart illustrating how the original mask of the current uop is adapted to the vector length vlen in an embodiment of this specification to obtain the final mask of the current uop.
[0054] Figure 9 The diagram shown is a schematic of the process of adapting the original mask of the current uop to the vector length vlen in an embodiment of this specification.
[0055] Figure 10 The diagram shown is a schematic diagram of vector result selection in an embodiment of this specification;
[0056] Figure 11 The diagram shown is a schematic representation of a RISC-V-based write mask vector instruction implementation device in an embodiment of this specification.
[0057] Figure 12 The diagram shown is a structural schematic of the computer device in an embodiment of this specification.
[0058] [Explanation of Figure Markers]:
[0059] 1101, Vector mask generation unit;
[0060] 1102, Vector mask unit;
[0061] 1103. Vector Result Selection Unit;
[0062] 1202. Computer equipment;
[0063] 1204. Processing equipment;
[0064] 1206. Storage resources;
[0065] 1208. Drive system;
[0066] 1210. Input / output module;
[0067] 1212. Input devices;
[0068] 1214. Output devices;
[0069] 1216. Presentation equipment;
[0070] 1218. Graphical User Interface;
[0071] 1220. Network interface;
[0072] 1222. Communication link;
[0073] 1224. Communication bus. Detailed Implementation
[0074] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this specification, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this specification.
[0075] It should be noted that the terms "first," "second," etc., in the description, claims, and accompanying drawings of the embodiments herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0076] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of the embodiments of this specification all comply with the relevant provisions of national laws and regulations.
[0077] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.
[0078] The vector instruction execution microstructures in the embodiments of this specification are as follows: Figure 1As shown, the vector mask generation, vector mask unit, and vector result selection are improvements made in the embodiments of this specification. Vector mask generation is used to generate the original mask of the current micro-operation uop based on the mask calculation identifier in the instruction opcode. The vector mask unit is used to adapt the original mask of the current uop to the vector length vlen to obtain the final mask of the current uop. Vector result selection is used to obtain the execution result of the previous uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop. The current uop is then executed to obtain its execution result. Finally, the instruction is written back to the VRF normally to complete the instruction execution.
[0079] To address the problems existing in the prior art, this specification proposes an implementation method for write mask vector instructions based on RISC-V, which achieves the functionality while keeping the number of uops and the Vector Register File (VRF) ports unchanged. Figure 2 The diagram shows a flowchart illustrating an implementation method of a RISC-V-based write mask vector instruction according to an embodiment of this specification. The improved uop execution process is depicted in this diagram. The order of steps listed in the embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the method shown in the embodiment or the accompanying drawings can be executed sequentially or in parallel. Specifically, as shown... Figure 2 As shown, the method may include:
[0080] Step 201: Calculate the identifier based on the mask in the instruction opcode to generate the original mask of the current micro-operation uop;
[0081] Step 202: The original mask of the current uop is adapted to the vector length vlen to obtain the final mask of the current uop;
[0082] Step 203: Obtain the execution result of the previous uop of the current uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop, execute the current uop, and obtain the execution result of the current uop.
[0083] By processing the mask of the uop using the method in the embodiments of this specification, when the current uop is executed, the execution result of the previous uop, the first source operand, the second source operand corresponding to the current uop, and the final mask of the current uop are obtained. Utilizing the characteristics of the mask, the calculation result of the previous uop remains unchanged during the execution of the current uop. Thus, the calculation result of the current uop, the calculation result of the previous uop, and the target operand are saved, thereby keeping the number of uops and the VRF ports unchanged, completing the instruction calculation. Compared to existing methods that additionally increase the number of uops or increase the number of VRF ports, the method in the embodiments of this specification improves instruction execution efficiency and reduces resource consumption.
[0084] In the embodiments of this specification, the mask calculation flag in the instruction opcode indicates mask calculation. Specifically, if vm = 0, it means that the mask register v0 is used as the execution mask. The operation of this element will only be executed when the corresponding bit of v0 is 1, and the result will be written to the destination register vd; for elements with the corresponding bit being 0, the bit in vd remains unchanged or is set to 1 according to the reduction strategy (depending on the vtype setting). If vm = 1, it means that no mask is executed, and all active elements will be compared.
[0085] Therefore, if it is a mask calculation, the original mask of the current uop is extracted from the mask register v0 according to the position of the effective processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype.
[0086] If it is a non-mask calculation, the original mask of the current uop is generated based on the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype.
[0087] This can be understood as follows: In the mask calculation of this embodiment, the original mask of the current uop is split from the mask register v0, and then the original mask of the current uop is adapted to vlen. The length of the final mask of the current uop is vlen. When the uop is executed, one bit of the current uop mask in the final mask corresponds to one element processed by the current uop, while other bits in the final mask other than the current uop mask are 0, indicating that the corresponding bits in vd remain unchanged. Because this embodiment uses the execution result of the previous uop as the vd of the current uop, when the current uop is executed, all bits in the execution result of the previous uop remain unchanged except for the bit corresponding to the current uop mask. The bit corresponding to the current uop mask is written into the mask calculation result corresponding to that bit. Therefore, the execution result of the current uop includes the execution result of the previous uop and the execution result of the current uop. This mechanism is achieved by the final mask obtained after mask segmentation and adaptation to vlen.
[0088] Therefore, taking the vector comparison instruction (vmseq.vv vd, vs2, vs1, v0) as an example, the uop decomposition in this embodiment is shown in Table 1:
[0089] Table 1
[0090]
[0091]
[0092] Therefore, in the embodiments of this specification, when LMUL is greater than 1, the first uop (uop0) reads the second source operand (vs2), the first source operand (vs1), the target operand (vd(src)) and the mask register (v0), executes uop0, and stores the execution result of uop0 in vtemp0; uop1 reads vs2+1, vs1+1, vtemp0 and v0, executes uop1, and stores the execution result of uop1 in vtemp1, and so on.
[0093] A diagram illustrating the update results of Uop is shown below. Figure 3 As shown, in Figure 3In the above, the original value of vd is the target operand read by uop0. The new mask of uop0 refers to the final mask of uop0 obtained in step 202. It can be seen that in the final mask of uop0, only the bit corresponding to uop0 is the uop0 mask, and the other bits are 0, indicating that the corresponding bits in vd remain unchanged. Therefore, the execution result obtained by executing uop0 includes the original value of vd and the result of uop0, which is stored in vtemp0. When executing uop1, vtemp0 is read. The new mask of uop1 refers to the final mask of uop1 obtained in step 202. It can be seen that in the final mask of uop1, only the bit corresponding to uop1 is the uop1 mask, and the other bits are 0, indicating that the corresponding bits in vtemp0 remain unchanged. Therefore, the execution result obtained by executing uop1 includes the original value of vd, the result of uop0, and the result of uop1.
[0094] In the embodiments described in this specification, such as Figure 4 As shown, if it is a mask calculation, the process of extracting the original mask of the current UOP from v0 based on the position of the effective processing segment body of the vector register group of the current UOP operation in the vector register group, the index of the current UOP, and the number of UOP processing elements determined according to the configuration of the vector configuration register vtype further includes:
[0095] Step 401: Set all bits between the bit corresponding to the vector start index vstart position of the vector register group in the first binary number with the same length as vlen to the bit corresponding to the effective vector length vl position, and set the remaining bits of the first binary number to 0;
[0096] Step 402: Perform a bitwise AND operation between the first binary number and v0 to obtain the mask result;
[0097] Step 403: Extract the mask corresponding to the current uop from the mask result according to the index of the current uop and the number of uop processing elements to obtain the original mask of the current uop.
[0098] like Figure 5 As shown, if it is a non-mask calculation, generating the original mask of the current UOP based on the position of the valid processing segment body of the vector register group of the current UOP operation in the vector register group, the index of the current UOP, and the number of UOP processing elements determined according to the configuration of the vector configuration register vtype further includes:
[0099] Step 501: Set all bits between the bit corresponding to the vector start index vstart position of the vector register group in the first binary number with the same length as vlen to the bit corresponding to the effective vector length vl position, and set the remaining bits of the first binary number to 0 to obtain the mask result;
[0100] Step 502: Extract the mask corresponding to the current UOP from the mask result based on the index of the current UOP and the number of elements processed by the UOP, and obtain the original mask of the current UOP.
[0101] Specifically, a diagram illustrating the generation of the original mask for the current uop is shown below. Figure 6 As shown. Figure 6 Taking a vector with length vlen = 128 as an example... Figure 4 and Figure 5 The method shown will be explained.
[0102] In the embodiments of this specification, the mask conversion is byte_index or byte_index_body with byte as the granularity. byte_index represents the original mask of the current uop split from v0 when the mask is calculated, and byte_index_body represents the original mask of the current uop generated when the mask is not calculated. Figure 6 Both byte_index and byte_index_body in the vector register are byte-level, with element widths (sew) of 8, 16, 32, and 64 bits. The number of elements in the vector register is vlen / sew, so when converted to byte-level granularity, both byte_index and byte_index_body contain 16 bits, with one bit corresponding to one byte.
[0103] Taking sew=8 as an example, since the vstart and tail parts of the vector register group are 0 (i.e., 0 before the vstart position and after the effective vector length vl position), they do not contain information about the actual mask v0. Therefore, in this embodiment, a first binary number with the same length as vlen is configured. The i part of sew8 cycles from 0 to 127 128 times, with each bit representing an element. After comparing with vstart and vl, all bits between the bits corresponding to the vstart position and the bits corresponding to the vl position in the first binary number are set to 1, and the remaining bits are set to 0. If it is a non-mask calculation, the mask corresponding to the current uop is extracted from the first binary number according to the index of the current uop and the number of elements processed by the uop, to obtain the original mask byte_index_body of the current uop. If it is a mask calculation, the mask of the current uop needs to be extracted from v0 using the first binary number. That is, the first binary number is bitwise ANDed with v0 to obtain the mask result. Then, the mask corresponding to the current uop is extracted from the mask result according to the index of the current uop and the number of elements processed by the uop, so as to obtain the original mask byte_index of the current uop.
[0104] If sew is 16, 32, or 64, then with vlen = 128, sew16 contains 8 elements, sew32 contains 4 elements, and sew64 contains 2 elements. When both byte_index and byte_index_body contain 16 bits, sew16 should have two bits corresponding to one element in byte_index or byte_index_body; sew32 should have four bits corresponding to one element; and sew64 should have eight bits corresponding to one element. Therefore, this embodiment further determines the number of bits corresponding to each element in the first binary number based on the element bit width; calculates the total number of bits of the multiple elements based on the multiple elements between vstart and vl positions and the number of bits; and sets the value of each bit of the total number of bits in the first binary number, starting from the bit corresponding to vstart position, to 1.
[0105] Feasibly, the `sew16` part `i` cycles from 0 to 63 64 times, with each two bits representing an element. It is compared with `vstart` and `vl`, and each cycle sets two bits in the first binary number to 1. The `sew32` part `i` cycles from 0 to 32 32 times, with each four bits representing an element. It is compared with `vstart` and `vl`, and each cycle sets four bits in the first binary number to 1. The `sew64` part `i` cycles from 0 to 16 16 times, with each eight bits representing an element. It is compared with `vstart` and `vl`, and each cycle sets eight bits in the first binary number to 1. If it is a non-mask calculation, then based on the current uop index and the number of elements processed by the uop, the mask corresponding to the current uop is extracted from the first binary number to obtain the original mask `byte_index_body` of the current uop. If it is a mask calculation, the mask of the current uop needs to be extracted from v0 using the first binary number. That is, the first binary number is bitwise ANDed with v0 to obtain the mask result. Then, the mask corresponding to the current uop is extracted from the mask result according to the index of the current uop and the number of elements processed by the uop, so as to obtain the original mask byte_index of the current uop.
[0106] In the embodiments described in this specification, such as Figure 7 As shown, extracting the mask corresponding to the current UOP from the mask result based on the index of the current UOP and the number of elements processed by the UOP, to obtain the original mask of the current UOP, further includes:
[0107] Step 701: Calculate the starting truncation bit based on the index of the current uop and the number of elements processed by the uop;
[0108] Step 702: Starting from the initial truncation position in the mask result, truncate a total of bits of the mask for the number of elements processed by the uop to obtain the original mask of the current uop.
[0109] For example, if the number of elements processed by uop is vlen / sew = 128 / 8 = 16, then the 16 bits in the mask result are the original mask of one uop. The starting truncation bit of the current uop can be obtained by multiplying the index of the current uop by the number of elements processed by the uop. For example, if the current uop is uop0, then 16 bits (i.e., bit0-bit15) are truncated from bit0 in the mask result as the original mask of uop0. If the current uop is uop1, then 16 bits (i.e., bit16-bit31) are truncated from bit16 in the mask result as the original mask of uop1.
[0110] In the embodiments of this specification, since the source operand element width is sew and the calculation result element width is 1 bit, a 128-bit input data can only produce a 128 / sew-bit calculation result. The final data bus written to the VRF is 128 bits, therefore, the uop index needs to be used to move and arrange the position of the calculation result, the principle of which is the same as masking. Specifically, as... Figure 8 As shown, the process of adapting the original mask of the current uop to the vector length vlen to obtain the final mask of the current uop further includes:
[0111] Step 801: Determine the placement position of the original mask of the current uop in a second binary number with the same length as vlen, based on the index of the current uop and the length of the original mask;
[0112] Step 802: Set the values of each bit corresponding to the placement position in the second binary number to the values of the corresponding bits of the original mask of the current UOP;
[0113] Step 803: Set the values of all bits in the second binary number except for the placement position to 0 to obtain the final mask.
[0114] In the embodiments described in this specification, the purpose of adapting the original mask to vlen is to place the original mask of uop in the correct position within the second binary number of length vlen, thus obtaining... Figure 3 The new mask shown in the specification means that, according to the index of the current uop and the length of the original mask (the length of the original mask of each uop is the same), the placement position of the original mask of the current uop in the second binary number is determined. Then, the values of the bits corresponding to the placement position in the second binary number are set to the values of the corresponding bits of the original mask of the current uop, and the values of the other bits in the second binary number except for the placement position are set to 0 to obtain the final mask.
[0115] Specifically, determining the placement of the original mask of the current uop in a second binary number of the same length as vlen, based on the index of the current uop and the length of the original mask, further includes:
[0116] The starting position for placement is calculated based on the index of the current uop and the length of the original mask;
[0117] The placement end position is calculated based on the starting position and the length of the original mask.
[0118] In the embodiments described in this specification, the product of the current UOP index and the original mask length can be calculated to obtain the placement start position, such as... Figure 9As shown, `uop_index` represents the index of `uop`. When the `uop` index is 0, bit 0 of the second binary number is the starting bit for placing `uop0`. Then, the sum of the starting bit and the length of the original mask is calculated, and then 1 is subtracted (because the bits of the second binary number start from 0) to obtain the ending bit. For example, when the `uop` index is 0, bit 15 of the second binary number is the ending bit for placing `uop0`. Then, the values from the starting bit to the ending bit in the second binary number are sequentially set to the least significant bit to the most significant bit of the original mask of the current `uop`. For example... Figure 9 As shown, `index` represents the original mask. The original mask of `uop0` is placed at position `j0`, corresponding to bits 0-15. The original mask of `uop1` is placed at position `j1`, corresponding to bits 16-31, and so on. After placement, all bits in the second binary number except for the placement position are set to 0, resulting in the final mask (i.e., ...). Figure 3 (New mask in the middle).
[0119] The number of elements contained in different sews is different. The original mask of the current uop is filled into the corresponding position of the second binary number according to the element bit width according to the index of the current uop. At this time, the effective position of the mask is aligned with the position of the calculation result of the uop.
[0120] In some other embodiments of this specification, such as Figure 10 As shown, for Figure 1 The vector operation shown executes calculations in all units of the pipeline except the vector mask unit. It needs to determine whether the result to be written back is the calculated result or the original value of vd, based on the mask. Other units can use... Figure 6 The obtained byte_index is used as a mask, with a granularity of 1 bit representing one byte. The byte_index needs to be expanded to the same length as the final mask. After selection, the merge vd operation can be completed and written back to VRF.
[0121] Based on the same inventive concept, embodiments of this specification also provide an implementation apparatus for RISC-V-based write mask vector instructions, such as... Figure 11 As shown, it includes:
[0122] The vector mask generation unit 1101 is used to generate the original mask of the current micro-operation uop based on the mask calculation identifier in the instruction opcode;
[0123] Vector masking unit 1102 is used to adapt the original mask of the current uop to the vector length vlen to obtain the final mask of the current uop.
[0124] The vector result selection unit 1103 is used to obtain the execution result of the previous uop of the current uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop, execute the current uop, and obtain the execution result of the current uop.
[0125] The beneficial effects obtained by the above-described device are the same as those obtained by the above-described method, and will not be described in detail in the embodiments of this specification.
[0126] like Figure 12 The diagram shown is a structural schematic of a computer device according to an embodiment of this specification. The methods described in this specification can be applied to the computer device of this embodiment.
[0127] Specifically, such as Figure 12 As shown, computer device 1202 may include one or more processing devices 1204, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. Computer device 1202 may also include any storage resource 1206 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, storage resource 1206 may include any one or more combinations of: any type of RAM, any type of ROM, flash memory devices, hard disks, optical disks, etc. More generally, any storage resource can use any technology to store information.
[0128] Furthermore, any storage resource can provide volatile or non-volatile retention of information.
[0129] Furthermore, any storage resource can represent a fixed or removable component of the computer device 1202. In one case, when the processing device 1204 executes associated instructions stored in any storage resource or combination of storage resources, the computer device 1202 can perform any operation of the associated instructions. The computer device 1202 also includes one or more drive systems 1208 for interacting with any storage resource, such as a hard disk drive system, an optical disk drive system, etc.
[0130] Computer device 1202 may also include an input / output module 1210 (I / O) for receiving various inputs (via input device 1212) and providing various outputs (via output device 1214). A specific output mechanism may include a presentation device 1216 and an associated graphical user interface (GUI) 1218. In other embodiments, the input / output module 1210 (I / O), input device 1212, and output device 1214 may be omitted, and the device may function solely as a computer device within a network. Computer device 1202 may also include one or more network interfaces 1220 for exchanging data with other devices via one or more communication links 1222. One or more communication buses 1224 couple the components described above together.
[0131] Communication link 1222 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 1222 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.
[0132] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.
[0133] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the above-described method.
[0134] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.
[0135] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0136] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments in this specification.
[0137] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0138] In the embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.
[0139] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.
[0140] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0141] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this specification, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0142] This specification describes the principles and implementation methods of the embodiments using specific examples. The above descriptions of the embodiments are only for the purpose of helping to understand the methods and core ideas of the embodiments in this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments in this specification. Therefore, the content of this specification should not be construed as a limitation on the embodiments in this specification.
Claims
1. A method of implementing a RISC-V based write mask vector instruction, the method comprising: The method includes: The original mask for the current micro-operation uop is generated based on the mask in the instruction opcode; The original mask of the current uop is adapted to the vector length vlen to obtain the final mask of the current uop; Obtain the execution result of the previous uop of the current uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop; execute the current uop and obtain the execution result of the current uop. The original mask for generating the current micro-operation uop based on the mask calculation identifier in the instruction opcode further includes: If the mask calculation identifier in the instruction opcode indicates mask calculation, then the original mask of the current uop is extracted from the mask register v0 according to the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype. If the mask calculation identifier in the instruction opcode indicates non-mask calculation, then the original mask of the current uop is generated based on the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype. The original mask of the current uop is adapted to the vector length vlen to obtain the final mask of the current uop, which further includes: The placement position of the original mask of the current uop in a second binary number with the same length as vlen is determined based on the index of the current uop and the length of the original mask; Set the values of each bit corresponding to the placement position in the second binary number to the values of the corresponding bits of the original mask of the current uop; Set the values of all bits in the second binary number except for the placement position to 0 to obtain the final mask; If the current uop is the first uop, then obtain the execution result of the previous uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop, execute the current uop, and obtain the execution result of the current uop, which further includes: Obtain the target operand, the first source operand and the second source operand corresponding to the first uop, and the final mask of the first uop. Execute the first uop to obtain the execution result of the first uop.
2. The method according to claim 1, characterized in that, Extracting the original mask of the current UOP from v0 based on the position of the valid processing segment body in the vector register group of the current UOP operation, the index of the current UOP, and the number of UOP processing elements determined according to the configuration of the vector configuration register vtype further includes: Set all bits between the bit corresponding to the vector start index vstart position and the bit corresponding to the effective vector length vl position in the first binary number with the same length as vlen, and set the remaining bits of the first binary number to 0. Perform a bitwise AND operation between the first binary number and v0 to obtain the mask result; Based on the index of the current uop and the number of elements processed by the uop, the mask corresponding to the current uop is extracted from the mask result to obtain the original mask of the current uop.
3. The method according to claim 1, characterized in that, Generating the original mask of the current UOP based on the position of the valid processing segment body in the vector register group of the current UOP operation, the index of the current UOP, and the number of UOP processing elements determined according to the configuration of the vector configuration register vtype further includes: Set all bits between the starting index vstart and the effective vector length vl of the vector register group in the first binary number with the same length vlen to 1, and set the remaining bits of the first binary number to 0 to obtain the mask result; Based on the index of the current uop and the number of elements processed by the uop, the mask corresponding to the current uop is extracted from the mask result to obtain the original mask of the current uop.
4. The method according to claim 2 or 3, characterized in that, Extracting the mask corresponding to the current UOP from the mask result based on the index of the current UOP and the number of elements processed by the UOP, to obtain the original mask of the current UOP, further includes: The starting truncation position is calculated based on the index of the current uop and the number of elements processed by the uop; Starting from the initial truncation position in the mask result, a total of several bits of the mask for the number of elements processed by the uop are extracted to obtain the original mask of the current uop.
5. The method according to claim 1, characterized in that, Determining the placement of the original mask of the current uop in a second binary number of the same length as vlen, based on the index of the current uop and the length of the original mask, further includes: The starting position for placement is calculated based on the index of the current uop and the length of the original mask; The placement end position is calculated based on the starting position and the length of the original mask.
6. The method according to claim 5, characterized in that, Setting the values of the bits corresponding to the placement positions in the second binary number to the values of the corresponding bits of the original mask of the current uop further includes: The values of the placement start bit to the placement end bit in the second binary number are sequentially set to the values of the least significant bit to the most significant bit of the original mask of the current uop.
7. The method according to claim 2 or 3, characterized in that, The bits between the starting index vstart position and the bit position vl position of the vector register group in the first binary number of the same length as vlen, further include: The number of bits corresponding to each element in the first binary number is determined based on the element bit width; Calculate the total number of bits for the multiple elements based on the multiple elements between the vstart position and the vl position and the number of bits; Set the value of each bit in the first binary number, starting from the bit corresponding to the vstart position, to 1.
8. An implementation apparatus for write mask vector instructions based on RISC-V, characterized in that, The device includes: The vector mask generation unit is used to generate the original mask of the current micro-operation uop based on the mask calculation identifier in the instruction opcode; A vector masking unit is used to adapt the original mask of the current uop to the vector length vlen to obtain the final mask of the current uop. The vector result selection unit is used to obtain the execution result of the previous uop of the current uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop, execute the current uop, and obtain the execution result of the current uop; The original mask for generating the current micro-operation uop based on the mask calculation identifier in the instruction opcode further includes: If the mask calculation identifier in the instruction opcode indicates mask calculation, then the original mask of the current uop is extracted from the mask register v0 according to the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype. If the mask calculation identifier in the instruction opcode indicates non-mask calculation, then the original mask of the current uop is generated based on the position of the valid processing segment body of the vector register group of the current uop operation in the vector register group, the index of the current uop, and the number of uop processing elements determined according to the configuration of the vector configuration register vtype. The original mask of the current uop is adapted to the vector length vlen to obtain the final mask of the current uop, which further includes: The placement position of the original mask of the current uop in a second binary number with the same length as vlen is determined based on the index of the current uop and the length of the original mask; Set the values of each bit corresponding to the placement position in the second binary number to the values of the corresponding bits of the original mask of the current uop; Set the values of all bits in the second binary number except for the placement position to 0 to obtain the final mask; If the current uop is the first uop, then obtain the execution result of the previous uop, the first source operand and the second source operand corresponding to the current uop, and the final mask of the current uop, execute the current uop, and obtain the execution result of the current uop, which further includes: Obtain the target operand, the first source operand and the second source operand corresponding to the first uop, and the final mask of the first uop. Execute the first uop to obtain the execution result of the first uop.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 7.
Citation Information
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