Method and device for calculating metal wiring overhead of silicon substrate interposer

Abstract

The invention relates to a silicon substrate interposer metal wiring overhead calculation method and device. The method comprises the following steps: determining the number of first metal layers required for wiring of a power ground network according to the number of first convex points corresponding to the power ground network of a silicon interposer and the convex point bearing capacity value of a single metal layer; determining the number of second metal layers required by signal network wiring according to the size parameter of the chip to which the silicon interposer belongs and the wiring mode of the signal network of the silicon interposer; and according to the first metal layer number and the second metal layer number, obtaining the total metal layer number required by wiring of the silicon interposer. By adopting the method, the metal layer overhead of the silicon interposer wiring can be accurately calculated.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method and apparatus for calculating metal wiring overhead. Background Technology

[0002] Silicon substrate packaging is a crucial aspect of chip design. The silicon interposer, as the core carrier for 2.5D and 3D packaging, utilizes the high-precision photolithography capabilities of the silicon substrate to achieve sub-micron level wiring. Consequently, silicon substrate packaging technology places extremely stringent requirements on wiring, with different wiring types and schemes imposing varying demands on the overall metal layer wiring overhead.

[0003] Therefore, in order to improve packaging efficiency and reduce costs, it is urgent to solve the problem of how to accurately calculate the metal layer overhead of silicon interposer wiring. Summary of the Invention

[0004] Therefore, it is necessary to provide a method and apparatus for calculating metal wiring overhead that can accurately calculate the metal layer overhead of silicon interposer wiring, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a method for calculating the overhead of metallic wiring. The method includes:

[0006] The number of first metal layers required for power ground network cabling is determined based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0007] Based on the size parameters of the chip to which the silicon interposer belongs and the wiring pattern of the signal network of the silicon interposer, determine the number of second metal layers required for the signal network wiring;

[0008] The total number of metal layers required for silicon interposer wiring is obtained based on the number of the first metal layer and the number of the second metal layer.

[0009] In one embodiment, the number of first metal layers required for power ground network cabling is determined based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer, including:

[0010] The number of candidate metal layers is determined based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0011] The first metal layer number is obtained by multiplying the candidate metal layer number by the layer multiple; wherein the layer multiple is determined based on the number of sub-wiring layers corresponding to the power ground network.

[0012] In one embodiment, the number of candidate metal layers is determined based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer, including:

[0013] The intermediate calculation parameters are obtained based on the ratio of the first bump number to the reference bump number; where the first bump number is the number of micro-bumps used for voltage transmission at the top layer, and the reference bump number is the number of C4 bumps used for voltage transmission at the bottom layer.

[0014] The number of candidate metal layers is obtained by calculating the ratio of the logarithm of the intermediate calculation parameter (base 10) to the logarithm of the convex load-bearing capacity value (base 10).

[0015] In one embodiment, the number of second metal layers required for the signal network routing is determined based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer, including:

[0016] Determine the required width of the single-layer metal fan-out signal line based on the wiring pattern;

[0017] The number of second metal layers is determined based on the ratio of the width to the dimension parameter; where the dimension parameter is the width or height of the chip.

[0018] In one embodiment, determining the required width of the single-layer metal fan-out signal line based on the wiring pattern includes:

[0019] Based on the wiring pattern, determine the width calculation formula corresponding to the wiring pattern;

[0020] Based on the signal line parameters and width calculation formula, the required width of the single-layer metal fan-out signal line is calculated.

[0021] In one embodiment, if the wiring mode is a full-signal parallel mode, the signal line parameters include the number of interconnect signal lines, the signal line width, and the signal line spacing. The number of interconnect signal lines is the number of interconnect signal lines fanned out from the convex points of the signal network to opposite sides.

[0022] Based on the signal line parameters and width calculation formula, the required width of the single-layer metal fan-out signal line is calculated, including:

[0023] The first reference width is determined based on the number of interconnect signal lines and the signal line width;

[0024] The second reference width is determined based on the number of interconnect signal lines and the spacing between the signal lines;

[0025] The required width of the single-layer metal fan-out signal line is obtained by summing the first reference width and the second reference width.

[0026] In one embodiment, determining a first reference width based on the number of interconnect signal lines and the signal line width includes: taking half of the interconnect signal lines, the product of the number of interconnect signal lines and the signal line width as the first reference width; determining a second reference width based on the number of interconnect signal lines and the signal line spacing includes: obtaining a first candidate parameter based on the sum of half of the number of interconnect signal lines and 1; and taking the product of the first candidate parameter and the signal line spacing as the second reference width.

[0027] In one embodiment, if the wiring pattern is a signal-to-ground-signal pattern or a ground-to-signal-ground pattern, the signal line parameters include the number of interconnect signal lines, signal line width, ground line width, ground line spacing, and group spacing, where the group spacing is the spacing between two GSG groups. Based on the signal line parameters and the width calculation formula, the required width of the fan-out signal line for a single metal layer is calculated, including: determining a third reference width based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing; determining a fourth reference width based on the number of interconnect signal lines and the group spacing; and obtaining the required width of the fan-out signal line for a single metal layer based on the sum of the third and fourth reference widths.

[0028] In one embodiment, if the wiring pattern is a signal-ground-signal pattern, a third reference width is determined based on the number of interconnect signal lines, the signal line width, the ground line width, and the ground line spacing. This includes: obtaining a second candidate parameter based on twice the signal line width, twice the ground line spacing, and the sum of the ground line widths; and using the product of one-quarter of the number of interconnect signal lines and the second candidate parameter as the third reference width. A fourth reference width is then determined based on the number of interconnect signal lines and the group spacing. This includes: obtaining a third candidate parameter based on one-quarter of the number of interconnect signal lines and 1; and using the product of the third candidate parameter and the group spacing as the fourth reference width.

[0029] If the wiring pattern is ground-signal-ground, then the third reference width is determined based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing, including: obtaining a fourth candidate parameter based on the sum of the signal line width, twice the ground line spacing, and twice the ground line width; and using the product of half the number of interconnect signal lines and the fourth candidate parameter as the third reference width; and the fourth reference width is determined based on the number of interconnect signal lines and the group spacing, including: obtaining a fifth candidate parameter based on the sum of half the number of interconnect signal lines and 1; and using the product of the fifth candidate parameter and the group spacing as the fourth reference width.

[0030] Secondly, this application also provides a metal wiring overhead calculation device. The device includes:

[0031] The power ground calculation module is used to determine the number of first metal layers required for power ground network cabling based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0032] The signal calculation module is used to determine the number of second metal layers required for signal network routing based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer.

[0033] The total number of layers calculation module is used to obtain the total number of metal layers required for silicon interposer wiring based on the first metal layer number and the second metal layer number.

[0034] Thirdly, this application also provides a computer device, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described in any of the first aspects above.

[0035] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0036] Fifthly, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0037] The aforementioned method and apparatus for calculating metal wiring overhead determine the first number of metal layers required for power and ground network wiring based on the first bump count corresponding to the power and ground network of the silicon interposer and the bump carrying capacity of a single metal layer; determine the second number of metal layers required for signal network wiring based on the size parameters of the chip to which the silicon interposer belongs and the wiring pattern of the signal network of the silicon interposer; and obtain the total number of metal layers required for silicon interposer wiring based on the first and second metal layers. In this way, by decoupling the physical requirements of the power and ground network and the signal network, and performing accurate prediction calculations of the number of metal layers separately, the total number of metal layers required for the silicon interposer can be obtained efficiently and accurately. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1This is a flowchart illustrating a method for calculating metal wiring overhead in one embodiment;

[0040] Figure 2 This is a flowchart illustrating the process of determining the number of first metal layers in one embodiment;

[0041] Figure 3 This is a flowchart illustrating the process of determining the number of second metal layers in one embodiment;

[0042] Figure 4 This is a flowchart illustrating the process of determining the required width of a single-layer metal fan-out signal line in one embodiment.

[0043] Figure 5 This is a flowchart illustrating a method for calculating the wiring overhead of a silicon substrate interposer layer in one embodiment.

[0044] Figure 6 This is a structural block diagram of a metal wiring overhead calculation device in one embodiment;

[0045] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0046] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0049] It is understandable that "at least one" refers to one or more, while "multiple" refers to two or more.

[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0051] Silicon-based packaging, a key technology in the post-Moore's Law era, is centered on utilizing high-density integration and ultra-high bandwidth interconnects through silicon interposers to form large-scale computing clusters with ultra-high bandwidth. Compared to traditional single-chip packaging, it achieves high-density interconnects through redistribution layers (RDLs) and copper pillars (Cu Pillars), reducing I / O bump spacing from 150μm to below 40μm. While this technology significantly improves integration, it introduces many design challenges for routing. First, its routing requirements are extremely stringent, with only five metal layers available for routing, and the trace length must be less than 50mm; otherwise, it will introduce a significant bit error rate problem, leading to a sharp increase in communication latency. Second, how to perform layout and routing under limited routing resources poses a significant challenge to physical back-end simulation and verification. Efficient MIPI routing simulation requires a long time and significant manpower costs, slowing down the overall design and iteration time. Currently, there is a lack of relevant rapid analysis and computational model design, and there is no systematic analysis and modeling of the routing requirements, routing modes, and routing overhead calculations for metal routing layers.

[0052] Silicon interposers, as the core carriers of 2.5D and 3D packaging, utilize the high-precision photolithography capabilities of silicon substrates to achieve submicron-level wiring. Passive silicon interposers are widely used due to their low yield, stress, cost, and design complexity. They support interconnect network architectures between multiple chips, enabling various types of information exchange and data communication. Different wiring types and schemes impose varying requirements on the overall metal layer wiring overhead. Therefore, it is crucial to address the issue of how to systematically analyze and model various wiring types and schemes to determine the metal layer wiring overhead.

[0053] In view of this, embodiments of this application provide a method for calculating metal wiring overhead, which can efficiently and accurately calculate the metal layer wiring overhead, that is, accurately determine the number of metal layers required for the silicon interposer, and provide a reference for chip design.

[0054] It should be noted that the metal wiring overhead calculation method provided in this application can be executed by a metal wiring overhead calculation device, which can be implemented as part or all of a computer device through software, hardware, or a combination of software and hardware. The computer device can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and servers, etc. The server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. This application does not limit the type of computer device. In the following method embodiments, the execution subject is described as a computer device.

[0055] In one embodiment, such as Figure 1 As shown, a method for calculating metal wiring overhead is provided, including the following steps:

[0056] Step 101: Determine the number of first metal layers required for power ground network cabling based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0057] A silicon interposer is a passive interposer, referring to a silicon layer located between the substrate and the die that facilitates information exchange without voltage regulators or power networks. Routing cost refers to the quantified cost of metal layer routing resources, i.e., the number of metal layers required to deploy different types of traces on the silicon interposer.

[0058] Silicon interposer wiring includes three types: PDN (Power Delivery Network) wiring, GND (Ground) wiring, and SIG (Signal) wiring. Since PDN and GND are often designed together, the Power and Ground Network (PG) is a network that integrates PDN and GND wiring, involving the distribution and management of power and ground. The design of the Power and Ground Network is crucial for ensuring stable circuit operation and reducing noise and electromagnetic interference.

[0059] In this embodiment, the power and ground networks and signal networks are decoupled, that is, the number of metal layers required for PG layer routing and the number of metal layers required for SIG layer routing are calculated separately. In this way, accurate calculations can be performed for various types of routing, avoiding mutual interference, thereby achieving accurate prediction of the number of metal layers.

[0060] The first bump count corresponding to the power ground network can be the number of micro-bumps on the top layer of the power ground network used for voltage transmission. The bump conversion ratio between the top and bottom metal layers can be calculated based on this first bump count and the number of C4 bumps used for voltage transmission. Furthermore, the bump conversion ratio can also be obtained based on the bump conversion ratio of a single metal layer and the number of metal layers required for the power ground network; this single-layer bump conversion ratio represents the bump carrying capacity value of a single metal layer. Therefore, by linking the two calculation methods, it can be seen that the number of metal layers required for the power ground network, i.e., the first metal layer count, can be determined based on the first bump count, combined with the number of C4 bumps and the bump conversion ratio of a single metal layer.

[0061] Based on this, in the embodiments of this application, the number of first metal layers required for power ground network cabling is determined according to the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0062] Step 102: Determine the number of second metal layers required for signal network routing based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer.

[0063] Silicon interposer routing includes three routing modes: SSS (All Signal Parallel), SGS (Signal-Ground-Signal), and GSG (Ground-Signal-Ground).

[0064] SSS mode routing arranges all signal lines in parallel without shielding. It maximizes routing density within a single metal layer, allowing for extremely high density design based on process limits for line width / spacing. However, it introduces significant impedance mismatch, near-end crosstalk, and electromagnetic compatibility issues. SGS mode routing inserts a ground wire between every two signal lines, directly connected to the chip's GND pad. This achieves crosstalk suppression and impedance stability at the cost of some routing density, but introduces power integrity adjustments and increases design complexity. GSG mode routing wraps each signal line with a ground wire, optimizing signal integrity and providing strong anti-interference capabilities, supporting high-speed protocols such as PCIe and CXL. However, it significantly reduces signal line routing density due to the introduction of more GND routing resources, leading to a surge in manufacturing costs. Furthermore, different routing modes occupy different routing space, thus routing overhead is related to the size of the chip.

[0065] Therefore, in this embodiment, the number of second metal layers required for signal network routing is calculated specifically by combining the set wiring pattern and chip size parameters.

[0066] Among them, the silicon interposer belongs to the silicon substrate chip (Wafer-scale chips), which refers to a chip that is assembled into a wafer-scale chip using advanced integration schemes.

[0067] Step 103: Based on the number of the first metal layer and the number of the second metal layer, obtain the total number of metal layers required for silicon interposer wiring.

[0068] In this embodiment of the application, the number of the first metal layer and the number of the second metal layer are added together to obtain the total number of metal layers.

[0069] The aforementioned method for calculating metal routing overhead determines the number of first metal layers required for power and ground network routing based on the number of first bumps corresponding to the power and ground network of the silicon interposer and the bump carrying capacity of a single metal layer. It then determines the number of second metal layers required for signal network routing based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer. Finally, based on the number of first and second metal layers, the total number of metal layers required for silicon interposer routing is obtained. In this way, by decoupling the physical requirements of the power and ground network and the signal network, and performing accurate prediction calculations of the number of metal layers separately, the total number of metal layers required for the silicon interposer can be obtained efficiently and accurately.

[0070] In one related technology, the number of metal layers is estimated by minimizing the total interconnect path length using a Steiner tree. Its core formula is the ratio of total wiring length to single-layer wiring capacity. It employs a partitioned multi-instantiation strategy to determine the global number of metal layers based on the peak demand of sub-regions, while also introducing wiring path correction. However, this approach comprehensively calculates the number of metal layers required for various types of wiring in the silicon interposer, failing to decouple the power / ground network from the signal network. This leads to the conflation of electromagnetic shielding requirements for continuous planar layers needed for power supplies and those for signal lines. Furthermore, it only optimizes geometric paths, ignoring differences in wiring patterns, and cannot dynamically adapt to the GSG shielding pattern for high-speed signals or the SSS density pattern for low-frequency signals. The actual number of layers needs manual correction, resulting in low accuracy and efficiency. Another implementation fixes the number of routable metal layers and designs the chip layout based on this. Its core assumption is that wiring resources are uniformly distributed, ignoring signal type differences and optimizing only geometric area and manufacturing cost. This method completely ignores the impact of the number of wiring metal layers on the design and manufacturing of the actual interposer layer, directly fixing it and leading to rigid resource allocation. This makes it difficult to support multi-dimensional interposer layer designs, thus limiting the overall chip performance. Furthermore, it struggles to accommodate various application scenarios. For example, high-speed signals require GSG routing patterns, which occupy additional shielding space, but this method only supports a single design, failing to adapt to diverse scenarios and lacking generalization. It also fails to consider that changes in corresponding process design parameters may further lead to design failure.

[0071] The method provided in this application decouples the power and ground network from the signal network and performs calculations separately, that is, it considers the physical requirements of the power and ground network and the signal network separately, improves the accuracy of calculating metal wiring overhead, and integrates various wiring patterns, has generalization, and is applicable to various design methods.

[0072] The process of calculating the number of the first metal layers is illustrated below.

[0073] In one embodiment, such as Figure 2 A flowchart illustrating the process of determining the number of first metal layers is shown. Based on the number of first bumps corresponding to the power / ground network of the silicon interposer and the bump carrying capacity value of a single metal layer, the number of first metal layers required for power / ground network cabling is determined, including:

[0074] Step 201: Determine the number of candidate metal layers based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0075] Based on the design methods of micro-bumps and C4 bumps, the following formula can be obtained:

[0076] (1)

[0077] The number of microbumps in the topmost metal layer of each metal layer corresponding to the power ground network cabling, used for voltage (VDD), that is, the number of microbumps in the topmost layer used for voltage transmission. The number of C4 bumps on the topmost metal layer used for voltage (VDD) transmission in the power ground network cabling is the same as the number of C4 bumps on the bottommost metal layer used for voltage transmission. According to the above formula, This represents the conversion ratio between the top and bottom layers.

[0078] Furthermore, it is assumed that the merging factor of each metal layer is the same, which is 1. ,but:

[0079] (2)

[0080] Merging factor The conversion ratio of each metal layer, specifically the bump conversion ratio of a single metal layer as mentioned above, characterizes the bump load-bearing capacity of a single metal layer. Typically, The extreme value is determined by the process.

[0081] For example, the bottom layer is generally coarser, so it has fewer bumps, while the top layer is finer, so it has more bumps. For instance, if the bottom layer can have 10 bumps, then the top layer can have 40 bumps, so the conversion ratio for each metal layer is 40 / 10=4. The number of metal layers dedicated to the PG layer, i.e., the number of candidate metal layers.

[0082] Therefore, we can calculate the result by combining formulas 1 and 2. .

[0083] Step 202: Obtain the first metal layer number by multiplying the candidate metal layer number by the layer multiplier. The layer multiplier is determined based on the number of sub-wiring layers corresponding to the power / ground network.

[0084] in, The number of metal layers is dedicated to the PG layer. However, as described above, one PG layer corresponds to one PDN layer and one GND layer. Therefore, the metal layers corresponding to one PG layer should be the metal layers required for the PDN layer and the metal layers required for the GND layer. The number of sub-routing layers corresponding to the power ground network is 2. Therefore, the total number of first metal layers required for the power ground network should be twice the number of candidate metal layers. That is, the layer multiple is 2, and the number of first metal layers... for:

[0085] (3)

[0086] In one embodiment, determining the number of candidate metal layers based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer includes:

[0087] Intermediate calculation parameters are obtained based on the ratio of the first bump number to the reference bump number. The number of candidate metal layers is obtained by calculating the ratio of the logarithm of the intermediate calculation parameters (base 10) to the logarithm of the bump carrying capacity value (base 10). Here, the first bump number represents the number of microbumps used for voltage transmission in the top layer, and the reference bump number represents the number of C4 bumps used for voltage transmission in the bottom layer.

[0088] That is, according to Formula 1 and Formula 2, we can obtain:

[0089] (4)

[0090] Therefore, based on the number of the first convex points and reference convex number The ratio can be used to obtain intermediate calculation parameters, and then the relationship between the intermediate calculation parameters and the bearing capacity value of the convex point can be calculated. The number of candidate metal layers is obtained by taking the logarithm of the ratio.

[0091] It is understood that, in this embodiment of the application, a metal layer prediction model can be pre-deployed in the computer device. This model includes the formulas mentioned above. The calculation data required for the formula calculation (such as the number of first bumps, the number of reference bumps, the bump load-bearing capacity value, etc.) is input into the metal layer prediction model, and the metal layer prediction model calculates according to the formula to obtain the number of first metal layers. This embodiment of the application does not impose specific limitations on the order of input of each calculation data.

[0092] In summary, based on the method provided in the embodiments of this application, the number of first metal layers required for power and ground network routing can be determined conveniently and efficiently.

[0093] The process of calculating the number of second metal layers is illustrated below.

[0094] In one embodiment, such as Figure 3 A flowchart illustrating the determination of the number of second metal layers is shown. Based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network in the silicon interposer, the number of second metal layers required for the signal network routing is determined, including:

[0095] Step 301: Determine the required width of the single-layer metal fan-out signal line according to the wiring pattern.

[0096] The signal line parameters required for calculating the width of the fan-out signal line of a single metal layer are different under different wiring patterns, and the calculation methods are also different. Therefore, in this embodiment, a targeted calculation is performed according to the wiring pattern.

[0097] Step 302: Determine the number of second metal layers based on the ratio of the width and size parameters required for the signal line fan-out from the single metal layer.

[0098] The size parameter refers to the width or height of the chip.

[0099] In other words, the number of second metal layers required for signal network routing can be determined by the ratio of the width required for a signal line fanned out from a single metal layer to the width of the chip. Similarly, the number of second metal layers required for signal network routing can also be determined by the ratio of the width required for a signal line fanned out from a single metal layer to the height of the chip.

[0100] This calculation represents the minimum number of metal layers required for signal network cabling.

[0101] In one embodiment, such as Figure 4 A flowchart illustrating the process of determining the required width of a single-layer metal fan-out signal line is provided. Determining the required width of the single-layer metal fan-out signal line based on the routing pattern includes:

[0102] Step 401: Determine the width calculation formula corresponding to the wiring pattern.

[0103] The width calculation formulas differ for different wiring patterns.

[0104] Step 402: Calculate the required width of the single-layer metal fan-out signal line based on the signal line parameters and width calculation formula.

[0105] Different wiring patterns may require different signal line parameters.

[0106] In the first possible implementation, the routing mode is a full-signal parallel mode, and the signal line parameters include the number of interconnected signal lines. Signal line width and signal line spacing .

[0107] The number of interconnect signal lines refers to the number of interconnect signal lines fanned out from the convex points of the signal network to opposite sides. For example, the number of interconnect lines fanned out from the convex points of the signal network to the left and right sides. This fanning out is mainly for connecting computing chips and memory chips. Therefore, the number of interconnect signal lines can be obtained from the number of signal lines D2D that need to be fanned out laterally between computing chips and the number of signal lines D2M that need to be fanned out laterally between computing chips and memory chips. For example:

[0108] D2D+D2M (5)

[0109] Furthermore, since the traces of the signal network are signal lines, the signal line width and signal line spacing are closely related to the required number of metal layers. The signal line spacing is the distance between two signal lines.

[0110] Correspondingly, in the case of a full-signal parallel routing mode, the required width of the fan-out signal line for a single metal layer is calculated based on the signal line parameters and width calculation formula, including:

[0111] A first reference width is determined based on the number of interconnect signal lines and the signal line width. A second reference width is determined based on the number of interconnect signal lines and the signal line spacing.

[0112] For example, determining a first reference width based on the number of interconnect signal lines and the signal line width includes: taking half of the product of the number of interconnect signal lines and the signal line width as the first reference width.

[0113] That is: First reference width =

[0114] For example, determining the second reference width based on the number of interconnect signal lines and the signal line spacing includes:

[0115] The first candidate parameter is obtained by summing half the number of interconnect signal lines and 1; the product of the first candidate parameter and the signal line spacing is used as the second reference width.

[0116] That is, the first candidate parameter =

[0117] Second reference width = .

[0118] Then, based on the sum of the first reference width and the second reference width, the required width of the single-layer metal fan-out signal line is obtained.

[0119] In other words, in full-signal parallel mode, the width required for a single metal layer to fan out a signal line. for:

[0120] (6)

[0121] In the second possible implementation, the wiring pattern is a signal-to-ground-to-signal pattern, and the signal line parameters include the number of interconnecting signal lines. Signal line width Ground wire width Ground wire spacing and group spacing .

[0122] The group spacing is the distance between two GSG groups. It can be understood that a GSG group includes ground-signal-ground wires.

[0123] Correspondingly, in the case of a signal-ground-signal routing pattern, the required width of the single-layer metal fan-out signal line is calculated based on the signal line parameters and width calculation formula, including:

[0124] The third reference width is determined based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing. The fourth reference width is determined based on the number of interconnect signal lines and group spacing.

[0125] For example, when the wiring pattern is signal-to-ground-to-signal, the third reference width is determined based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing, including:

[0126] The second candidate parameter is obtained by combining twice the signal line width, twice the ground line spacing, and the sum of the ground line widths; the product of one-quarter of the interconnect signal line count and the second candidate parameter is used as the third reference width.

[0127] That is, the second candidate parameter = .

[0128] Third reference width = .

[0129] In addition, the fourth reference width is determined based on the number of interconnect signal lines and the group spacing, including: obtaining a third candidate parameter based on the sum of one-quarter of the number of interconnect signal lines and 1; and using the product of the third candidate parameter and the group spacing as the fourth reference width.

[0130] That is: the third candidate parameter = .

[0131] Fourth reference width = .

[0132] Then, based on the sum of the third reference width and the fourth reference width, the required width of the single-layer metal fan-out signal line is obtained.

[0133] In other words, in signal-ground-signal mode, the width required for a single metal layer to fan out a signal line. for:

[0134] (7)

[0135] In the third possible implementation, the wiring pattern is a ground-signal-ground pattern, and the signal line parameters include the number of interconnecting signal lines. Signal line width Ground wire width Ground wire spacing and group spacing .

[0136] Correspondingly, in the case of a ground-signal-ground wiring pattern, the required width of a single-layer metal fan-out signal line is calculated based on the signal line parameters and width calculation formula, including:

[0137] The third reference width is determined based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing. The fourth reference width is determined based on the number of interconnect signal lines and group spacing.

[0138] For example, when the wiring pattern is ground-signal-ground, the third reference width is determined based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing, including:

[0139] The fourth candidate parameter is obtained by summing the signal line width, twice the ground spacing, and twice the ground width; the product of half the number of interconnect signal lines and the fourth candidate parameter is used as the third reference width.

[0140] That is, the fourth candidate parameter = .

[0141] Third reference width = .

[0142] In addition, the fourth reference width is determined based on the number of interconnect signal lines and the group spacing, including: obtaining a fifth candidate parameter based on half the number of interconnect signal lines and 1; and using the product of the fifth candidate parameter and the group spacing as the fourth reference width.

[0143] That is, the fifth candidate parameter = .

[0144] Fourth reference width = .

[0145] Then, based on the sum of the third reference width and the fourth reference width, the required width of the single-layer metal fan-out signal line is obtained.

[0146] In other words, when the wiring pattern is ground-signal-ground, the width required for a single metal layer to fan out the signal line is... for:

[0147] (8)

[0148] In summary, when different wiring patterns are selected, the required width of the fan-out signal line for a single metal layer can be calculated based on the corresponding formula and signal line parameters.

[0149] and then, (9)

[0150] This refers to the height of the chip.

[0151] Therefore, it can be concluded that

[0152] The minimum number of second metal layers can be determined based on the ratio of the width and size parameters required for the signal lines fanned out by a single metal layer. .

[0153] Similarly, (11)

[0154] This refers to the width of the chip.

[0155] Therefore, it can be concluded that (12)

[0156] In addition, it should be noted that the width and height of the chip are calculated using the following formula:

[0157] (13)

[0158] (14)

[0159] The spacing between the transverse micro-bumps in the top layer micro-bumps; The spacing between the longitudinal micro-bumps in the top layer micro-bumps; The vertical column number of the top micro-bumps; X is the number of horizontal columns of the top micro-bumps; optional, X equals Y.

[0160] Based on this, in calculating the number of the first metal layers Second metal layer number After that, the total number of metal layers can be obtained. :

[0161] (15)

[0162] In this embodiment, as mentioned above, a metal layer prediction model can be pre-deployed in the computer device. This model includes the formulas described above. The computational data required for formula calculation is input into the metal layer prediction model, which then performs calculations according to the formulas to obtain the number of the first metal layer and the number of the second metal layer. Adding these two numbers directly outputs the total number of metal layers. This embodiment does not specifically limit the order in which the computational data is input. The computational data may also include wiring patterns and chip size parameters, etc., which are not fully exemplified here but can be determined based on the formulas described above. Different wiring patterns can be represented by different numbers or letters; therefore, by inputting the corresponding numbers or letters, the computer device can determine the selected wiring pattern.

[0163] In summary, the method provided in this application, considering the multi-dimensional layout and routing design space of the interposer layer, constructs a layered metal layer prediction framework by decoupling the physical requirements of the power ground network (PG) and the signal network (SIG), proposes a three-modal quantization model for three routing modes, comprehensively considers the metal layer requirements of silicon interposer routing for multiple design variables, and constructs a layered decoupled modeling and routing mode-aware metal layer prediction model. This allows for the analysis and consideration of various factors affecting the number of metal layers required for silicon interposer routing on silicon substrate chips, accurately calculating the required number of metal layers for the silicon interposer. It offers greater comprehensiveness, can cover various configurations, and has strong versatility; simultaneously, the model has higher accuracy and lower error, which is beneficial for subsequent silicon substrate interconnect design and manufacturing processes.

[0164] For ease of understanding, the following describes the silicon substrate interposer wiring overhead calculation method provided in this application using a complete embodiment. This method aims to provide a method for calculating the metal wiring overhead of a passive interposer layer on a silicon substrate chip, calculating the number of metal layers required to meet the chip wiring requirements, comprehensively considering the characteristics of different types of signals and various factors such as chip layout, improving the accuracy of the calculation results, thereby optimizing the design of the passive interposer layer of the chip and greatly improving design efficiency through advance model calculation.

[0165] The core lies in the layered dynamic calculation model, which achieves accurate prediction of the number of metal layers by decoupling the physical requirements of the power / ground network and the signal network. First, a dedicated layer number calculation is performed for the power / ground (PG) network. This process rigorously quantifies the bump carrying capacity of a single metal layer and follows key design rules: each dedicated PG layer actually consists of two independent metal layers—one pure power layer and one pure ground layer. This physical mapping ensures the integrity of the current transmission path and avoids chip performance degradation due to power supply noise. Second, in the signal layer (SIG) calculation, based on the physical size constraints of the logic chip and the routing pattern requirements, a differentiated correction mechanism for three routing patterns is introduced: the all-signal parallel mode is suitable for low-frequency control signals to maximize routing density; the signal-ground-signal mode balances the integrity and efficiency of the medium-speed data bus; and the ground-signal-ground mode provides electromagnetic shielding for high-speed interfaces. The differences in routing space occupancy of different routing patterns are accurately quantified through dynamic coefficient adjustment. Finally, the requirements of the PG and SIG layers are dynamically integrated.

[0166] like Figure 5 The flowchart illustrates the method for calculating the interconnect overhead of a silicon substrate interposer. The metal layer calculation process first processes the layer requirements of the power ground network (PG) and signal network (SIG) in parallel, specifically calculating the first metal layer required for PG routing and the second metal layer required for signal network routing. For the PG, the merging factor is calculated based on the ratio of C4 bumps to microbumps, and the dedicated merging extreme values ​​determined by the process are used to derive the number of dedicated PG layers (two metal layers per PDN). For the SIG layers, a reference size (chip height or width) is selected based on the chip layout pattern, and the total signal line width requirement is calculated based on the signal line routing pattern (SSS / SGS / GSG). Finally, the minimum number of signal layers is determined by the ratio of the total signal width to the reference size. Finally, the number of dedicated metal layers for the PG and the number of dedicated metal layers for the SIG are added to obtain the total number of metal layers required to achieve the desired interconnect functionality. This process comprehensively considers key factors such as power integration efficiency, signal fan-out density, and process characteristics.

[0167] Specifically, the number of metal layers specific to PG can be calculated using Formula 1 and Formula 2. Since each PG dedicated layer corresponds to one power layer and one GND layer, the number of the first metal layer of the corresponding PG network is obtained according to Formula 3.

[0168] Then, the width and height of the logic chip, i.e. the chip's base dimensions, can be obtained according to formulas 13 and 14.

[0169] Considering the known height of the logic chip, a classification and discussion of different routing patterns reveals that, when the routing pattern is all-signal parallel mode, signal-to-ground-signal mode, or ground-to-signal-ground mode, the required width of the fan-out signal line in a single metal layer can be calculated using formulas 6, 7, or 8 respectively. Therefore, the number of second metal layers required for signal network routing can be calculated using Formula 10. Similarly, considering the known width of the logic chip, different routing modes can be classified and discussed. When the routing mode is all-signal parallel mode, signal-ground-signal mode, or ground-signal-ground mode, the width required for a single metal layer fan-out signal line can be calculated using Formula 6, Formula 7, or Formula 8 respectively. Then, according to Formula 12, the number of second metal layers required for signal network cabling can be calculated. According to Formula 15, the number of first metal layers and the number of second metal layers are added together to obtain the total number of metal layers.

[0170] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0171] Based on the same inventive concept, this application also provides a metal wiring overhead calculation device for implementing the metal wiring overhead calculation method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more metal wiring overhead calculation device embodiments provided below can be found in the limitations of the metal wiring overhead calculation method described above, and will not be repeated here.

[0172] In one embodiment, such as Figure 6 As shown, a metal wiring overhead calculation device is provided, including: a power / ground calculation module 601, a signal calculation module 602, and a total layer count calculation module 603, wherein:

[0173] The power ground calculation module 601 is used to determine the number of first metal layers required for power ground network cabling based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer.

[0174] The signal calculation module 602 is used to determine the number of second metal layers required for signal network routing based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer.

[0175] The total number of layers calculation module 603 is used to obtain the total number of metal layers required for silicon interposer wiring based on the first number of metal layers and the second number of metal layers.

[0176] In one embodiment, the power ground calculation module 601 is specifically used to: determine the number of candidate metal layers based on the first bump number corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer; and obtain the first metal layer number based on the product of the number of candidate metal layers and the layer level multiple; wherein the layer level multiple is determined based on the number of sub-wiring layers corresponding to the power ground network.

[0177] In one embodiment, the power ground calculation module 601 is specifically used to: obtain intermediate calculation parameters based on the ratio of the first bump number to the reference bump number; wherein the first bump number is the number of micro-bumps on the top layer used for voltage transmission, and the reference bump number is the number of C4 bumps on the bottom layer used for voltage transmission; and calculate the ratio of the logarithm of the intermediate calculation parameters to the logarithm of the bump carrying capacity value to obtain the candidate metal layer number.

[0178] In one embodiment, the signal calculation module 602 is specifically used to: determine the width required for the fan-out signal line of a single metal layer according to the wiring pattern; and determine the number of second metal layers according to the ratio of the width to the size parameter; wherein the size parameter is the width or height of the chip.

[0179] In one embodiment, the signal calculation module 602 is specifically used to: determine the width calculation formula corresponding to the wiring pattern according to the wiring pattern; and calculate the width required for the single-layer metal layer fan-out signal line according to the signal line parameters and the width calculation formula.

[0180] In one embodiment, the signal calculation module 602 is specifically used to: if the wiring mode is a full-signal parallel mode, the signal line parameters include the number of interconnect signal lines, the signal line width, and the signal line spacing, wherein the number of interconnect signal lines is the number of interconnect signal lines fanned out from the convex points of the signal network to opposite sides; determine a first reference width based on the number of interconnect signal lines and the signal line width; determine a second reference width based on the number of interconnect signal lines and the signal line spacing; and obtain the width required for the single-layer metal layer to fan out signal lines based on the sum of the first reference width and the second reference width.

[0181] In one embodiment, the signal calculation module 602 is specifically used to: take half of the product of the number of interconnect signal lines and the signal line width as a first reference width; obtain a first candidate parameter based on the sum of half of the number of interconnect signal lines and 1; and take the product of the first candidate parameter and the signal line spacing as a second reference width.

[0182] In one embodiment, the signal calculation module 602 is specifically used to: if the wiring mode is a signal-to-ground-signal mode or a ground-to-signal-ground mode, then the signal line parameters include the number of interconnect signal lines, the signal line width, the ground line width, the ground line spacing, and the group spacing, wherein the group spacing is the spacing between two GSG groups; determine a third reference width based on the number of interconnect signal lines, the signal line width, the ground line width, and the ground line spacing; determine a fourth reference width based on the number of interconnect signal lines and the group spacing; and obtain the width required for the single-layer metal layer fan-out signal line based on the sum of the third reference width and the fourth reference width.

[0183] In one embodiment, the signal calculation module 602 is specifically configured to: if the wiring pattern is a signal-ground-signal pattern, obtain a second candidate parameter based on twice the signal line width, twice the ground line spacing, and the sum of the ground line widths; multiply a quarter of the interconnect signal line count by the second candidate parameter as a third reference width; obtain a third candidate parameter based on a quarter of the interconnect signal line count and 1; and multiply the third candidate parameter by the group spacing as a fourth reference width.

[0184] If the wiring pattern is ground-signal-ground, the fourth candidate parameter is obtained by summing the signal line width, twice the ground spacing, and twice the ground width; the product of half the number of interconnect signal lines and the fourth candidate parameter is used as the third reference width; the fifth candidate parameter is obtained by summing half the number of interconnect signal lines and 1; the product of the fifth candidate parameter and the group spacing is used as the fourth reference width.

[0185] Each module in the aforementioned metal wiring overhead calculation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0186] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores metal wiring overhead calculation data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a metal wiring overhead calculation method.

[0187] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0188] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0189] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0190] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0191] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0192] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0193] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for calculating the overhead of metallic wiring, characterized in that, The method includes: The number of first metal layers required for power ground network cabling is determined based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer. The number of second metal layers required for signal network routing is determined based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer. The total number of metal layers required for the silicon interposer wiring is obtained based on the first number of metal layers and the second number of metal layers.

2. The method according to claim 1, characterized in that, The step of determining the number of first metal layers required for power ground network cabling based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer includes: The number of candidate metal layers is determined based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer. The first number of metal layers is obtained by multiplying the candidate number of metal layers and the layer multiplier; wherein the layer multiplier is determined based on the number of sub-wiring layers corresponding to the power ground network.

3. The method according to claim 2, characterized in that, Based on the number of first bumps corresponding to the power and ground network of the silicon interposer and the bump carrying capacity value of a single metal layer, the number of candidate metal layers is determined, including: Intermediate calculation parameters are obtained based on the ratio of the first number of bumps to the reference number of bumps; wherein, the first number of bumps is the number of micro-bumps on the top layer used for voltage transmission, and the reference number of bumps is the number of C4 bumps on the bottom layer used for voltage transmission. The number of candidate metal layers is obtained by calculating the ratio of the logarithm of the intermediate calculation parameter (base 10) to the logarithm of the convex bearing capacity value (base 10).

4. The method according to claim 1, characterized in that, The step of determining the number of second metal layers required for signal network routing based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer includes: Based on the wiring pattern, determine the required width of the single-layer metal fan-out signal line; The number of the second metal layers is determined based on the ratio of the width to the size parameter; wherein the size parameter is the width or height of the chip.

5. The method according to claim 4, characterized in that, Determining the required width of the single-layer metal fan-out signal line according to the wiring pattern includes: Based on the wiring pattern, determine the width calculation formula corresponding to the wiring pattern; Based on the signal line parameters and the width calculation formula, the required width of the single-layer metal fan-out signal line is calculated.

6. The method according to claim 5, characterized in that, If the wiring mode is a full-signal parallel mode, the signal line parameters include the number of interconnect signal lines, the signal line width, and the signal line spacing. The number of interconnect signal lines is the number of interconnect signal lines fanned out from the convex points of the signal network to opposite sides. The step of calculating the required width of the single-layer metal fan-out signal line based on the signal line parameters and the width calculation formula includes: The first reference width is determined based on the number of interconnect signal lines and the signal line width; The second reference width is determined based on the number of interconnect signal lines and the spacing between the signal lines; The required width of the single-layer metal fan-out signal line is obtained based on the sum of the first reference width and the second reference width.

7. The method according to claim 6, characterized in that, Determining the first reference width based on the number of interconnect signal lines and the signal line width includes: The first reference width is the product of half the number of interconnect signal lines and the width of the signal line. Determining the second reference width based on the number of interconnect signal lines and the signal line spacing includes: The first candidate parameter is obtained by summing half the number of interconnect signal lines with 1; The product of the first candidate parameter and the signal line spacing is used as the second reference width.

8. The method according to claim 6, characterized in that, If the wiring mode is a signal-ground-signal mode or a ground-signal-ground mode, then the signal line parameters include the number of interconnect signal lines, the signal line width, the ground line width, the ground line spacing and the group spacing, wherein the group spacing is the spacing between two GSG groups; The step of calculating the required width of the single-layer metal fan-out signal line based on the signal line parameters and the width calculation formula includes: The third reference width is determined based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing. The fourth reference width is determined based on the number of interconnect signal lines and the group spacing; The required width of the single-layer metal fan-out signal line is obtained based on the sum of the third reference width and the fourth reference width.

9. The method according to claim 8, characterized in that, If the wiring pattern is a signal-ground-signal pattern, then determining the third reference width based on the number of interconnecting signal lines, signal line width, ground line width, and ground line spacing includes: The second candidate parameter is obtained by combining twice the signal line width, twice the ground line spacing, and the sum of the ground line width. The third reference width is the product of one-quarter of the number of interconnect signal lines and the second candidate parameter. And, determining the fourth reference width based on the number of interconnect signal lines and the group spacing includes: The third candidate parameter is obtained by summing one-quarter of the number of interconnect signal lines with 1; The product of the third candidate parameter and the group spacing is used as the fourth reference width; If the wiring pattern is a ground-signal-ground pattern, then determining the third reference width based on the number of interconnect signal lines, signal line width, ground line width, and ground line spacing includes: The fourth candidate parameter is obtained by summing the signal line width, twice the ground line spacing, and twice the ground line width; The product of half the number of interconnect signal lines and the fourth candidate parameter is used as the third reference width; And, determining the fourth reference width based on the number of interconnect signal lines and the group spacing includes: The fifth candidate parameter is obtained by summing half the number of interconnect signal lines with 1; The product of the fifth candidate parameter and the group spacing is used as the fourth reference width.

10. A metal wiring overhead calculation device, characterized in that, The device includes: The power ground calculation module is used to determine the number of first metal layers required for power ground network cabling based on the number of first bumps corresponding to the power ground network of the silicon interposer and the bump carrying capacity value of a single metal layer. The signal calculation module is used to determine the number of second metal layers required for signal network routing based on the size parameters of the chip to which the silicon interposer belongs and the routing pattern of the signal network of the silicon interposer. The total number of layers calculation module is used to obtain the total number of metal layers required for the silicon interposer wiring based on the first number of metal layers and the second number of metal layers.

Images