Silicon interposer backside aluminum routing process and alignment method

Abstract

The application provides a silicon adapter back aluminum wiring process and alignment method, and belongs to the technical field of microelectronic packaging. In the traditional back aluminum wiring process, two photoetching and etching processes are needed, and the process is relatively complex. In the application, the TSV is polished, the aluminum metal layer is deposited, the TSV copper mark is obtained during deposition, and the subsequent aluminum wiring photoetching can be directly aligned with the TSV. The preparation of the aluminum wiring layer can be completed through one photoetching and etching process. The whole preparation method is compatible with the existing process flow, the steps are simple, and the preparation time and cost can be reduced.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic packaging technology, and particularly relates to an aluminum wiring process and alignment method on the back of a silicon adapter board. Background Technology

[0002] 2.5D Through Silicon Via (TSV) adapter board technology is one of the key technologies in advanced packaging processes. It enables high-density integration between chips and vertical interconnection between chips and substrates, reducing overall system latency and power consumption. With the rapid development of industries such as artificial intelligence, 5G, and big data, 2.5D TSV adapter board technology has been widely used.

[0003] 2.5D TSV adapter boards typically consist of TSV vias, multi-layer wiring on the front side, and a single-layer wiring structure on the back side. Normally, the back side wiring is copper. However, since TSV adapter boards are generally manufactured by the front-end foundry and then transferred to the packaging plant for subsequent processes such as bump fabrication, copper is prone to oxidation during transportation and while awaiting processing, causing reliability issues. Therefore, there is a demand to replace the copper wiring on the back side with aluminum wiring to prevent oxidation.

[0004] Currently, the back TSV is flat after copper exposure during the process. It is difficult to align it with the TSV after aluminum deposition. Therefore, it is necessary to perform a photolithography, blind exposure, etching to remove part of the aluminum and expose the photolithography alignment mark area for subsequent alignment processes. However, the process steps are complicated, the processing cycle is longer, and the cost is also relatively high. Summary of the Invention

[0005] The purpose of this invention is to provide a process and alignment method for aluminum wiring on the back of a silicon adapter board, which can directly align TSVs and is compatible with the original process flow, and the process flow is simple.

[0006] To solve the above-mentioned technical problems, the present invention provides a specific technical solution for the aluminum wiring process and alignment method on the back side of a silicon adapter board as follows:

[0007] Step 1: Thinning of the silicon substrate on the back of the TSV adapter board; The silicon substrate on the back of the TSV adapter board is thinned by three grinding processes: rough grinding, fine grinding, and chemical mechanical polishing. The remaining thickness is related to the depth of the TSV, and is usually 10 to 20 μm thicker than the depth of the TSV.

[0008] Step 2: Exposing the through-silicon via (TSV); Use dry or wet etching to remove the silicon substrate on top of the TSV, exposing the TSV to 2–10 μm.

[0009] Step 3: Growing a SiN / SiO2 dielectric layer; A SiN / SiO2 dielectric layer is grown on the back side of the silicon substrate, mainly to prevent direct contact between copper and silicon in the TSV;

[0010] Step 4: Chemical mechanical grinding + over polishing; the SiN / SiO2 dielectric layer is ground by chemical mechanical grinding to expose the head copper of the TSV, at this time the height of the copper in the TSV and the SiN / SiO2 dielectric layer is consistent, and the height difference is generally not more than 50nm-100nm; then the copper is over polished for 5-20 seconds to make the copper of the TSV recess 100-500nm relative to the surface of the SiN / SiO2 dielectric layer;

[0011] The copper over polishing of the TSV cannot be too small, which will affect the signal of the aluminum deposition mark (MARK); at the same time, it cannot be too large, otherwise the subsequent AL will not be filled, resulting in a broken circuit.

[0012] Step 5: Aluminum metal deposition; metal aluminum is deposited on the surface of the SiN / SiO2 dielectric layer by PVD, the thickness of the aluminum is 1-5μm, and the back aluminum wiring layer is formed;

[0013] Step 6: Aluminum wiring photoetching and etching; photoetching, gluing, developing and etching are performed on the back aluminum wiring layer to realize the patterning of the aluminum wiring; when photoetching and gluing, according to the photoetching mark of the TSV copper, the photoetching alignment between the back aluminum wiring layer and the TSV copper is realized.

[0014] As an embodiment, step 4 is replaced by: HF / HNO3 mixed acid is used to corrode the Cu to make the copper of the TSV recess 100-500nm relative to the surface of the SiN / SiO2 dielectric layer;

[0015] As an embodiment, step 4 is replaced by: the SiN / SiO2 dielectric layer is ground by chemical mechanical grinding to expose the head copper of the TSV, at this time the height of the copper in the TSV and the SiN / SiO2 dielectric layer is consistent, and the height difference is generally not more than 50nm; then the SiN / SiO2 dielectric layer is over polished by SiO2 over polishing to make the Cu of the TSV protrude 100-500nm relative to the surface of the SiN / SiO2 dielectric layer;

[0016] As an embodiment, the SiO2 over polishing is replaced by using acid to wet etch SiO2, and the acid can be DHF, HF, BOE and other acids that can etch SiO2 and cannot etch metal copper.

[0017] The beneficial effects of the present application are as follows: after the traditional through-silicon via adapter back through-silicon via copper exposure process is completed, the copper and the adjacent medium are at the same horizontal plane, and the height difference does not exceed 50-100 nm, the present application needs the copper in the through-silicon via and the adjacent medium not to be at the same horizontal plane, and needs the copper to be higher than the adjacent medium by 100-500 nm, or the copper to be lower than the adjacent medium by 100-500 nm; the present application polishes the TSV to make the aluminum metal layer deposited in the TSV copper mark during deposition, and enables direct photolithography alignment with the TSV in the subsequent aluminum wiring photolithography, and the preparation of the aluminum wiring layer can be completed through one-time photolithography and etching, the entire preparation method is compatible with the existing process flow, and the steps are simple, which can reduce the preparation time and preparation cost. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The process flow chart of the method of the present application is shown in the figure.

[0019] Figure 2 The TSV structure prepared by the method of the present application is shown in the figure.

[0020] Figure 3 The cross-sectional view and top view after aluminum deposition are shown in the figure.

[0021] Figure 4 The cross-sectional view and top view after TSV copper exposure are shown in the figure.

[0022] Figure 5 The backside photolithography, glue coating and development are shown in the figure.

[0023] Figure 6 The backside aluminum wiring etching is shown in the figure.

[0024] Figure 7 The figure after the backside copper exposure of the TSV of Example 3 is shown.

[0025] Mark explanation in the figure: 11, wafer carrier; 12, temporary bonding glue; 13, front copper wiring; 14, front silicon oxide / silicon nitride medium layer; 15, SV adapter substrate; 16, TSV through-silicon via; 17, backside silicon oxide / silicon nitride medium layer; 18, backside aluminum wiring layer. DETAILED DESCRIPTION

[0026] In order to better understand the purpose, structure and function of the present application, the present application provides a silicon adapter backside aluminum wiring process and alignment method, which is further described in detail below in combination with the drawings.

[0027] Example 1

[0028] Step 1: TSV interposer backside silicon substrate thinning; the TSV interposer backside silicon substrate is ground three times by rough grinding, fine grinding and chemical mechanical grinding, and the remaining thickness is related to the depth of the TSV, and is usually 10-20 μm more than the depth of the TSV; in this embodiment, the TSV depth is 100 μm, and the thickness of the silicon substrate after thinning is 105-115 μm;

[0029] Step 2: TSV exposure; the silicon substrate at the top of the TSV is removed by dry or wet etching to expose the TSV by 3-8 μm;

[0030] Step 3: Growth of SiN / SiO2 dielectric layer; a layer of SiN / SiO2 dielectric layer is grown on the backside of the silicon substrate, mainly for preventing direct contact between copper and silicon in the TSV;

[0031] Step 4: Chemical mechanical grinding + over polishing; the SiN / SiO2 dielectric layer is ground by chemical mechanical grinding to expose the copper at the head of the TSV, at this time the height of the copper in the TSV and the SiN / SiO2 dielectric layer is consistent, and the height difference is generally not more than 50 nm; then the copper is over polished for 10-20 seconds to make the copper of the TSV recessed 100-500 nm relative to the surface of the SiN / SiO2 dielectric layer as shown in Figure 3

[0032] The copper over polishing of the TSV cannot be too small, which will affect the signal of the aluminum lithography alignment mark (MARK); at the same time, it cannot be too large, otherwise the subsequent AL will not be filled, resulting in open circuit.

[0033] Step 5: Aluminum metal deposition; aluminum metal is deposited on the surface of the SiN / SiO2 dielectric layer by PVD (physical vapor deposition), and the thickness of the aluminum is 1-5 μm to form a backside aluminum wiring layer; as shown in Figure 4 After the deposition of aluminum, the original TSV area will have a 100-500 nm recess, so that the lithography alignment mark of the TSV can be identified in the subsequent lithography process, and the lithography alignment between the backside aluminum wiring layer and the TSV copper is realized;

[0034] Step 6: Aluminum wiring lithography and etching; photoresist coating, developing and etching are performed on the backside aluminum wiring layer to realize the patterning of the aluminum wiring. As shown in Figure 5 When photoresist coating is performed, the lithography alignment between the backside aluminum wiring layer and the TSV copper is realized according to the lithography mark of the TSV copper. The final backside aluminum wiring layer after etching is shown in Figure 6

[0035] Embodiment 2

[0036] ​​The difference between this embodiment and embodiment 1 is that step 4 is replaced by etching Cu with a mixed acid of HF / HNO3, so that the copper of TSV is recessed by 100-500nm relative to the surface of the SiN / SiO2 dielectric layer.

[0037] Example 3

[0038] The difference between this embodiment and Embodiment 1 is that step 4 is replaced by: using chemical mechanical polishing to grind the SiN / SiO2 dielectric layer to expose the copper at the head of the TSV. At this point, the height of the copper in the TSV is the same as that of the SiN / SiO2 dielectric layer, and the height difference generally does not exceed 50 nm; then, using SiO2 overpolishing, the SiN / SiO2 dielectric layer is overpolished so that the Cu of the TSV protrudes 100-500 nm relative to the surface of the SiN / SiO2 dielectric layer, as shown in the schematic diagram. Figure 7 As shown.

[0039] Example 4

[0040] The difference between this embodiment and Embodiment 3 is that the over-polishing of SiO2 is replaced by wet etching of SiO2 with acid, wherein the acid can be DHF, HF, BOE, or other acids.

[0041] Example 5

[0042] like Figure 2 The diagram shown is a schematic of the structure of the TSV adapter board after aluminum wiring prepared in Example 1, including a carrier wafer 11, temporary bonding adhesives 12 and 13, a front silicon oxide / silicon nitride dielectric layer 14, a TSV adapter board substrate 15, a TSV through-silicon via 16, a back silicon oxide / silicon nitride dielectric layer 17, and a back aluminum wiring layer 18.

[0043] The upper surface of the carrier wafer is a temporary bonding adhesive, and the upper surface of the temporary bonding adhesive is a front silicon oxide / silicon nitride dielectric layer. The front copper wiring is located inside the front silicon oxide / silicon nitride dielectric layer. The upper surface of the front silicon oxide / silicon nitride dielectric layer is a TSV adapter substrate. The TSV adapter substrate has a plurality of TSV silicon vias in the middle. The upper surface of the TSV adapter substrate is a back silicon oxide / silicon nitride dielectric layer. The via pattern of the back silicon oxide / silicon nitride dielectric layer corresponds to the TSV silicon vias. The upper surface of the back silicon oxide / silicon nitride dielectric layer is a back aluminum wiring layer.

[0044] As can be seen, the back aluminum wiring in the method of the present invention can be directly aligned with the TSV and is compatible with conventional process flow, making the process flow simpler.

[0045] Example 6

[0046] This embodiment provides a method for fabricating the structure of the TSV adapter board after aluminum wiring obtained in Embodiment 5, such as... Figure 1As shown:

[0047] Step 1: Through Silicon Via (TSV) formation; TSV structure preparation needs to go through the main process steps of TSV lithography, etching, sidewall insulation layer deposition, seed layer deposition, copper electroplating, annealing and chemical mechanical polishing, etc., to obtain a TSV adapter substrate;

[0048] Step 2: Copper wiring; on the TSV adapter substrate, the front copper wiring process is carried out, and the process of each layer of wiring is: wiring SiN / SiO2 medium deposition, lithography, etching, seed layer deposition, electroplating, chemical mechanical polishing, and the subsequent repeated process forms multiple layers of copper wiring, and then the copper wiring is electrically connected with the TSV. Generally, the number of wiring layers is 1-8, and the top layer is an aluminum PAD layer;

[0049] Step 3: Temporary bonding; the TSV adapter substrate with good front copper wiring process is bonded with a carrier wafer, which is mainly used to support the subsequent back wafer thinning and subsequent processes. Temporary bonding usually includes temporary bonding glue coating, debonding glue coating, temporary bonding and temporary bonding detection. The carrier can be made of silicon or glass. The thickness of the temporary bonding glue is generally 10-50 μm, and the thickness of the debonding glue is generally <1 μm;

[0050] Step 4: TSV adapter back silicon substrate thinning; the TSV adapter back silicon substrate is thinned by three times of grinding, fine grinding and chemical mechanical polishing. The remaining thickness is related to the depth of the TSV, and is usually 10-20 μm more than the depth of the TSV. In this embodiment, the TSV depth is 100 μm, and the thickness of the thinned silicon substrate is 105-115 μm

[0051] Step 5: TSV exposure; the silicon substrate at the top of the TSV is removed using dry or wet etching method, and the TSV is exposed by 3-8 μm

[0052] Step 6: Growth of SiN / SiO2 dielectric layer; a layer of SiN / SiO2 dielectric layer is grown on the back of the silicon substrate, which is mainly used to prevent direct contact between copper and silicon in the TSV;

[0053] Step 7: Chemical mechanical polishing + over polishing; the SiN / SiO2 dielectric layer is polished by chemical mechanical polishing to expose the copper at the head of the TSV. At this time, the height of the copper in the TSV is consistent with that of the SiN / SiO2 dielectric layer, and the height difference is generally not more than 50 nm. Then the copper is over polished for 10-20 seconds to make the copper of the TSV recessed 100-500 nm relative to the surface of the SiN / SiO2 dielectric layer as shown: Figure 3

[0054] The copper over polishing of the TSV cannot be too small, which will affect the signal of the aluminum lithography alignment mark (MARK); at the same time, it cannot be too large, otherwise the subsequent AL will not be able to fill, resulting in a broken circuit.​

[0055] Step 8: Aluminum metal deposition; PVD (Physical Vapor Deposition) is used to deposit aluminum on the surface of SiN / SiO2 dielectric layer, and the thickness of the aluminum is 1-5 μm to form the backside aluminum wiring layer; as shown in Figure 4 After the deposition of aluminum, the area of the original TSV will have a 100-500 nm recess, so that the lithography alignment mark of the TSV can be identified in the subsequent lithography process, and the lithography alignment between the backside aluminum wiring layer and the TSV copper is realized;

[0056] Step 9: Aluminum wiring lithography and etching; the photoresist is coated, developed and etched on the backside aluminum wiring layer to realize the patterning of the aluminum wiring; as shown in Figure 5 When the photoresist is coated, the lithography alignment between the backside aluminum wiring layer and the TSV copper is realized according to the lithography mark of the TSV copper. The final backside aluminum wiring layer after etching is shown in Figure 6 .

[0057] It can be understood that the present application is described by some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the present application without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.

Claims

1. A process and alignment method for aluminum wiring on the back of a silicon adapter board, characterized in that, Includes the following steps: Step 1: Thinning the silicon substrate on the back of the TSV adapter board; The silicon substrate on the back of the TSV adapter board is thinned through three grinding processes: rough grinding, fine grinding, and chemical mechanical polishing, resulting in a depth 10–20 μm greater than that of the TSV. Step 2: Exposing the through-silicon via (TSV); Use dry or wet etching to remove the silicon substrate on the back of the TSV adapter plate on top of the TSV, exposing the TSV to 2–10 μm. Step 3: Growing a SiN / SiO2 dielectric layer; A SiN / SiO2 dielectric layer is grown on the back side of the silicon substrate; Step 4: Chemical mechanical polishing + overpolishing; The SiN / SiO2 dielectric layer is polished by chemical mechanical polishing to expose the copper at the head of the TSV. At this time, the height difference between the copper in the TSV and the SiN / SiO2 dielectric layer does not exceed 50nm to 100nm; Then the copper is overpolished for 5 to 20 seconds, so that the copper of the TSV is recessed by 100 to 500nm relative to the surface of the SiN / SiO2 dielectric layer. Step 5: Aluminum metal deposition; Aluminum metal is deposited on the surface of the SiN / SiO2 dielectric layer by PVD or evaporation, with an aluminum thickness of 1-5 μm, to form the back aluminum wiring layer; Step 6: Aluminum wiring photolithography and etching; Photolithography, resist coating, development, and etching are performed on the back aluminum wiring layer to achieve patterning of the aluminum wiring; during photolithography, photolithographic alignment between the back aluminum wiring layer and the TSV copper is achieved according to the photolithographic markings of the TSV copper.

2. The aluminum wiring process and alignment method on the back of a silicon adapter board according to claim 1, characterized in that, In step 4, the copper over-polishing process is replaced by etching Cu with a mixed acid of HF / HNO3, so that the copper of the TSV is recessed by 100-500 nm relative to the surface of the SiN / SiO2 dielectric layer.

3. The aluminum wiring process and alignment method on the back of a silicon adapter board according to claim 1, characterized in that, In step 4, the copper over-polishing process is replaced by: using chemical mechanical polishing to polish the SiN / SiO2 dielectric layer to expose the copper at the head of the TSV. At this time, the height of the copper in the TSV and the SiN / SiO2 dielectric layer are the same, and the height difference generally does not exceed 50nm. Then, the SiN / SiO2 dielectric layer is over-polished using SiO2 to make the Cu of the TSV protrude 100-500nm relative to the surface of the SiN / SiO2 dielectric layer.

4. The aluminum wiring process and alignment method on the back of a silicon adapter board according to claim 1, characterized in that, In step 4, the copper over-polishing process is replaced by wet etching of the SiN / SiO2 dielectric layer with acid, so that the Cu of the TSV protrudes 100-500 nm relative to the surface of the SiN / SiO2 dielectric layer.

5. The aluminum wiring process and alignment method on the back of a silicon adapter board according to claim 4, characterized in that, The acid used in step 4 for wet etching of the SiN / SiO2 dielectric layer is DHF, HF, or BOE.

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