Silicon interposers, packaging structures and semiconductor devices

Abstract

This utility model discloses a silicon interposer, a packaging structure, and a semiconductor device, relating to the field of semiconductor technology. The silicon interposer is formed within a silicon interposer layer and specifically includes: a memory cell layer, comprising at least one memory cell embedded within the silicon interposer; a bottom circuit layer located on one side of the memory cell layer and connected to the memory cell; the bottom circuit layer is used to control the memory cell; and a metal wiring layer located on the side of the memory cell layer away from the bottom circuit layer; the metal wiring layer is connected to the memory cell and is used to achieve signal interconnection between external circuitry and the memory cell. This utility model achieves a collaborative technical solution of a silicon interposer structure without through-silicon vias (TSVs) and an embedded memory cell.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a silicon interposer, packaging structure, and semiconductor device. Background Technology

[0002] In the semiconductor technology field, packaging technology has evolved from DIP to QFP to BGA to FCBGA to 2.5D / 3D / SiP, achieving comprehensive improvements in density and speed, as well as further reductions in thickness. 2.5D packaging mounts multiple chips side-by-side on a silicon interposer, interconnecting them via TSVs (Through-Silicon Vias). 3D packaging directly stacks multiple chips; specifically, after thinning the silicon wafer, TSVs act as vertical conductors for face-to-face or back-to-back chip stacking. Simultaneously, with the development of packaging technology, heterogeneous integration of several chips with different functions and processes has been proposed. However, existing technologies suffer from issues related to packaging cost, product reliability, signal transmission speed, and incompatibility with thinner packaging thickness. Utility Model Content

[0003] This invention provides a silicon interposer, a packaging structure, and a semiconductor device that can balance packaging cost, product reliability, signal transmission speed, and packaging thickness reduction.

[0004] According to one aspect of the present invention, a silicon interposer core is provided, which is formed in a silicon interposer layer, specifically comprising:

[0005] A storage cell layer, the storage cell layer including at least one storage cell, the storage cell being embedded in the silicon interposer;

[0006] A bottom-level circuit layer is located on one side of the memory cell layer and is connected to the memory cell; the bottom-level circuit layer is used to control the memory cell.

[0007] A metal wiring layer is located on the side of the memory cell layer away from the underlying circuit layer; the metal wiring layer is connected to the memory cell and is used to realize signal interconnection between the external circuit and the memory cell.

[0008] Optionally, the storage unit includes a phase-change memory.

[0009] Optionally, the phase change memory includes a heated bottom electrode, a phase change material layer, and a top electrode stacked together.

[0010] Optionally, the heating bottom electrode is a TiN layer;

[0011] And / or, the phase change material layer is a Ge-Sb-Te alloy layer;

[0012] And / or, the top electrode is a TiN layer or a W layer.

[0013] Optionally, the storage cell is connected to the underlying circuit layer via a via;

[0014] Furthermore, the storage unit is connected to the metal wiring layer via vias.

[0015] Optionally, the via is a W-type via.

[0016] Optionally, the underlying circuit layer includes CMOS and interconnects; wherein the CMOS is used to form selection transistors and / or control logic circuits.

[0017] Optionally, the CMOS includes:

[0018] Base;

[0019] A well layer and an active region are located on the substrate. The well layer includes alternately arranged N-well regions and P-well regions. An N-type active region is disposed in the N-well region, and a P-type active region is disposed in the P-well region. The N-type active region corresponds to an N-type transistor, and the P-type active region corresponds to a P-type transistor.

[0020] The gate, source, and drain are located on the side of the active region away from the substrate;

[0021] A deep well layer, the deep well layer being located between the substrate and the well layer of a portion of the CMOS.

[0022] Optionally, the metal wiring layer includes:

[0023] Multilayer metal wiring and multilayer rewiring vias, with adjacent layers of metal wiring electrically connected through the rewiring vias;

[0024] A top via exposes the metal wiring located on the top layer to bring out the signals of the memory cell; wherein the metal wiring located on the top layer is the metal wiring layer furthest from the memory cell layer.

[0025] According to another aspect of the present invention, a packaging structure is provided, comprising:

[0026] Packaging substrate;

[0027] The silicon interposer core as described in any embodiment of the present invention is located on the packaging substrate;

[0028] A functional chip is located on the side of the silicon interposer away from the packaging substrate; wherein the functional chip is interconnected with the memory cell through the metal wiring layer in the silicon interposer.

[0029] According to another aspect of the present invention, a semiconductor device is provided, comprising: a packaging structure as described in any embodiment of the present invention.

[0030] This embodiment of the invention integrates the memory cell into a silicon interposer, enabling integration with embedded memory cells via a TSV-free interconnect architecture, thereby achieving at least the following beneficial effects:

[0031] Firstly, compared with the existing technology that uses TSV to interconnect multiple dies, the present invention uses a metal wiring layer to replace the TSV structure, eliminating deep hole etching and copper filling processes in the fabrication process, which helps to reduce packaging costs, for example, by more than 67%; and helps to avoid stress concentration caused by the difference in thermal expansion coefficients between copper and silicon, for example, it can ensure that silicon intermediate samples do not have microcracks after 2000 temperature cycles, thus improving reliability.

[0032] Secondly, compared with the existing Fanout RDL solution, the memory cell provided in this embodiment is directly interconnected with the metal wiring layer. In the packaging structure, the metal wiring layer can be used for interconnection via metal bonding wires, or the metal wiring layer in the silicon interposer can be used as the connection medium between the packaging substrate and the functional chip. This solution can achieve a micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns and no high-frequency loss, thereby supporting PCIe 5.0 and higher high-speed interfaces. Therefore, this embodiment is beneficial for improving the problems of signal delay and high-frequency loss.

[0033] Thirdly, compared with the existing SIP-encapsulated memory cell solution, this embodiment of the invention achieves a thickness increase of <0.2mm by embedding the memory cell inside the silicon interposer, thereby controlling the total package thickness within 1.5mm. Furthermore, in the package structure, the metal wiring layer can be used for interconnection via metal bonding wires. This solution enables a micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns with no high-frequency loss, thus supporting PCIe 5.0 and higher high-speed interfaces. Therefore, this embodiment of the invention not only achieves a thin package thickness but also meets the real-time data access requirements of industrial control.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of the structure of a silicon interposer core provided in an embodiment of this utility model;

[0037] Figure 2 A schematic diagram of another silicon interposer core provided in this embodiment of the present invention;

[0038] Figure 3 A schematic diagram of another silicon interposer core provided in this embodiment of the present invention;

[0039] Figure 4 A schematic diagram of another silicon interposer core provided in this embodiment of the present invention;

[0040] Figure 5 A schematic diagram of another silicon interposer core provided in this embodiment of the present invention;

[0041] Figure 6 A schematic flowchart illustrating a method for preparing silicon interposer cores according to an embodiment of this utility model;

[0042] Figure 7 This is a schematic diagram of a packaging structure provided in an embodiment of the present utility model;

[0043] Figure 8 A partial structural schematic diagram of a functional core provided in an embodiment of this utility model;

[0044] Figure 9 This is a schematic flowchart illustrating a method for preparing a packaging structure according to an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] As mentioned in the background section, existing technologies suffer from incompatibility issues regarding packaging costs, product reliability, signal transmission speed, and packaging thickness reduction. Research has revealed the following reasons for this problem:

[0048] In existing heterogeneous integration solutions, one approach is to achieve multi-die interconnection using TSVs, such as the 2.5D interconnect architecture. Specifically, the 2.5D interconnect architecture employs a high-resistivity silicon interposer, forming 5-10 μm diameter vias through deep reactive ion etching (DRIE) followed by copper plating. Tin-silver microbumps are then fabricated on the surface to connect the memory chips to the substrate, achieving high-density vertical interconnection. This approach suffers from high manufacturing costs and difficulty in improving the yield of the TSV silicon interposer. Specifically, the TSV silicon interposer process is complex and expensive. For example, TSV fabrication requires deep reactive ion etching (10:1 aspect ratio) and copper plating on a thick silicon substrate, resulting in a long process route, high unit cost of silicon interposer, and low yield. Furthermore, the difference in thermal expansion coefficients between copper and silicon easily induces interfacial stress concentration during temperature cycling. Experimental results show that after 500 cycles at -55℃ to 125℃, 15% of the samples exhibited microcracks. Therefore, this solution suffers from issues of packaging reliability and high cost, which limits its application in industrial control high and low temperature scenarios.

[0049] Another approach is the Fanout Redistribution Layer (RDL) solution. Specifically, a multi-layer copper redistribution layer (RDL) is constructed on the surface of the epoxy molding compound (EMC) package. Heterogeneous chips from different processes are connected to the RDL pads via 50μm high copper pillar bumps, extending the signal horizontally to the package perimeter. Typical linewidth / spacing is 2μm / 2μm. In this solution, the heterogeneous chips from different processes and the RDL pads need to be connected horizontally via 50μm high copper pillar bumps, extending the signal path to the millimeter level, leading to increased data transmission delay. Furthermore, when the RDL linewidth / spacing shrinks to 2μm / 2μm, the skin effect and crosstalk loss of high-frequency signals intensify, failing to meet the integrity requirements of high-speed interfaces. Therefore, this solution suffers from signal delay and high-frequency loss issues.

[0050] Another approach is to integrate embedded memory cells within the System-on-a-Chip (SoC). Specifically, floating-gate Flash (or eFlash) memory cells are directly integrated during the SoC wafer fabrication stage. The memory array within these cells is located beneath the SoC's metal layers and directly connected to the processor core via an on-chip bus, resulting in a read latency of 100ns. However, this approach requires an additional 6-10 layers of photomasks during SoC fabrication, increasing manufacturing costs. Furthermore, the floating-gate transistors in the Flash memory cells require a 12V programming voltage, incompatible with the 1.8V operating voltage of advanced process core devices. This necessitates a separately designed charge pump circuit, occupying additional chip area and leading to a simultaneous increase in chip size and leakage power consumption. Additionally, the floating-gate oxide layer of the floating-gate transistors... 4 The breakdown probability after a single erase / write cycle reaches 0.1%, posing a reliability risk to long-life applications such as industrial control. Therefore, this solution suffers from process conflicts and durability defects.

[0051] Another approach is to use a system-in-package (SIP) solution to encapsulate the memory cells. Specifically, this involves stacking 150-200μm thick Flash dies on the surface of the main chip, using 20μm gold wire bonding or 30μm micro-bump connections. This requires an SPI serial interface protocol, supporting only 6.4GB / s bandwidth, which presents a performance bottleneck in industrial control scenarios requiring real-time data access. In this solution, the thicker package and the physical separation between the main chip and the Flash die result in a longer signal path, creating a bandwidth bottleneck and introducing additional transmission delay.

[0052] This utility model provides a silicon interposer chip suitable for three-dimensional packaging structures and chip heterogeneous integrated packaging structures. Figure 1 A schematic diagram of the structure of a silicon interposer core provided in an embodiment of this utility model. See also... Figure 1 The silicon interposer 10 is formed in the silicon interposer layer, specifically including:

[0053] Storage cell layer 110, storage cell layer 110 includes at least one storage cell ( Figure 1 (Not shown in the image), the memory cell is embedded within the silicon interposer 10;

[0054] The bottom circuit layer 120 is located on one side of the memory cell layer 110 and is connected to the memory cell; the bottom circuit layer 120 is used to control the memory cell.

[0055] Metal wiring layer 130 is located on the side of memory cell layer 110 away from the underlying circuit layer 120; metal wiring layer 130 is connected to memory cell and is used to realize signal interconnection between external circuit and memory cell.

[0056] Among them, the silicon interposer chip uses an active silicon interposer as a substrate, or simply a silicon substrate. The silicon substrate can be, for example, a 55nm process silicon substrate. The 55nm process silicon substrate is a silicon substrate adapted to the manufacturing of 55nm process chips. The bottom circuit layer 120, memory cell layer 110 and metal wiring layer 130 are fabricated in the silicon substrate. It has the advantages of more mature manufacturing process, lower defect rate, shorter chip development cycle, no need for complex process adjustment, suitability for mass production, and the ability to balance performance and cost.

[0057] The external circuitry interconnecting the memory cells can be, for example, a functional chip or a packaging substrate. The functional chip can be, for example, an Application-Specific Integrated Circuit (ASIC) chip or other chip with computing capabilities. In this embodiment, the functional chip can be interconnected with the metal wiring layer 130; for example, the functional chip can be directly interconnected with the memory cells in the silicon interposer chip 10 via microbumps. And / or, in this embodiment, the packaging substrate can be interconnected with the metal wiring layer 130; for example, the packaging substrate can be directly interconnected with metal bonding wires (…). Figure 1 (Not shown) is connected to the metal wiring layer 130, thereby interconnecting with the memory cells in the silicon interposer 10. And / or, in this embodiment of the invention, the metal wiring layer 130 in the silicon interposer 10 can also serve as a connection medium between the packaging substrate and the functional chip.

[0058] This embodiment of the invention integrates the memory cell within the silicon interposer 10, enabling integration with the embedded memory cell via a TSV-free interconnect architecture, thereby achieving at least the following beneficial effects:

[0059] Firstly, compared with the existing technology that uses TSV to interconnect multiple dies, this embodiment of the invention uses a metal wiring layer 130 to replace the TSV structure, eliminating deep hole etching and copper filling processes in the fabrication process, which helps to reduce packaging costs, for example, by more than 67%; and helps to avoid stress concentration problems caused by the difference in thermal expansion coefficients between copper and silicon, for example, it can ensure that silicon interposer samples still have no microcracks after 2000 temperature cycles, thus improving reliability.

[0060] Secondly, compared with the existing Fanout RDL solution, the memory cell provided in this embodiment is directly interconnected with the metal wiring layer 130. In the package structure, the metal wiring layer 130 can be used for interconnection via metal bonding wires, or the metal wiring layer 130 in the silicon interposer 10 can be used as the connection medium between the package substrate and the functional chip. This solution can achieve a micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns and no high-frequency loss, thereby supporting high-speed interfaces of PCIe 5.0 and above. Therefore, this embodiment is beneficial for improving the problems of signal delay and high-frequency loss.

[0061] Thirdly, compared with the existing SIP-encapsulated memory cell solution, this embodiment of the invention achieves a thickness increase of <0.2mm by embedding the memory cell inside the silicon interposer 10, thereby controlling the total package thickness within 1.5mm. Furthermore, in the package structure, the metal wiring layer 130 can be used for interconnection via metal bonding wires. This solution enables a micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns with no high-frequency loss, thus supporting high-speed interfaces of PCIe 5.0 and above. Therefore, this embodiment of the invention not only achieves a thin package thickness but also meets the real-time data access requirements of industrial control.

[0062] Based on the above embodiments, optionally, the storage unit includes a phase-change memory (PCM). The PCM achieves state switching by heating the phase-change material with current pulses. Compared with existing technologies that embed storage units within a SoC or directly bond and package storage chips with functional chips, this embodiment integrates the PCM into a silicon interposer. This not only solves the imbalance between process technology, yield, and cost in embedded storage, but also allows the functional chip to be positioned on the silicon interposer. This facilitates the connection between the integrated PCM and the functional chip via the metal wiring layer 130, significantly shortening the transmission path length between the functional chip and the storage unit. Furthermore, the data bus in the silicon interposer can directly operate the storage unit, improving data read / write speed. Therefore, this embodiment avoids the process conflicts and durability defects inherent in existing floating-gate storage units. Specifically, this embodiment eliminates the need for a high-voltage charge pump design, allowing its operating voltage to be as low as 0.7V, achieving 10kJ / bit ultra-low power consumption. 9 The phase-change memory (PCM) exhibits excellent write endurance, enabling it to operate at voltage levels up to 1.8V. Furthermore, due to its crystallization mechanism, PCM is relatively stable compared to other types of memory cells (e.g., floating-gate or electron tunneling memory cells), improving storage reliability. Additionally, PCM requires no loading upon power-up and employs a data overwrite method without erasure operations, resulting in faster write and erase speeds compared to other types of memory cells. Therefore, this embodiment of the invention achieves beneficial effects such as accelerated power-up, increased write access speed, enhanced power-loss protection, and improved overall reliability.

[0063] Figure 2 A schematic diagram of another silicon interposer core provided in an embodiment of this utility model. See also... Figure 2Based on the above embodiments, optionally, the storage unit 111 is a phase change memory (PCM). The PCM includes a heated bottom electrode 1111, a phase change material layer 1112, and a top electrode 1114 stacked together. The heated bottom electrode 1111 is located near the bottom circuit layer 120, and the top electrode 1114 is located near the metal wiring layer 130. The heated bottom electrode has both the conductivity function of a bottom electrode and the Joule heating function of a heater. This arrangement eliminates the need to separate the bottom electrode and heater into two layers, simplifying the structure of the PCM and reducing energy consumption during current transmission by simplifying the film structure, thus improving energy efficiency. The phase change material layer 1112 is the core of the PCM, capable of switching between polycrystalline and amorphous states. These two states have different resistivities, and data is stored based on this resistivity difference; for example, a high-resistivity amorphous state writes 1, and a low-resistivity polycrystalline state writes 0. The top electrode 1114, in conjunction with the heated bottom electrode 1111, provides a current path for the PCM. The phase-change memory provided in this embodiment of the invention has a simple structure and high energy efficiency.

[0064] Figure 3 A schematic diagram of another silicon interposer core provided in an embodiment of this utility model. See also... Figure 3 Based on the above embodiments, optionally, the phase change memory further includes a first insulating layer 1113 and a second insulating layer 1115. The first insulating layer 1113 is located between the phase change material layer 1112 and the top electrode 1114, and the second insulating layer 1115 is located on the side of the top electrode 1114 away from the first insulating layer 1113. The first insulating layer 1113's proximity to the phase change material layer 1112 serves several purposes: firstly, it helps prevent crosstalk between the operating currents of adjacent phase change memories that are close together, ensuring independent operation of each phase change memory; secondly, it reduces heat loss from the Joule heating generated by the bottom electrode 1111 towards the top electrode, concentrating the heat transfer to the phase change material layer 1112, thereby improving heat utilization efficiency; and thirdly, it isolates the top electrode 1114 from direct contact with the phase change material layer 1112, preventing atomic interdiffusion during the high-temperature phase change process, avoiding changes in the phase change material composition and electrode material failure, thus extending the service life of the silicon interposer 10. The second insulating layer 1115 is located on the outermost layer of the phase change memory. It helps to isolate external dust, moisture, and corrosive gases, thereby preventing the top electrode 1114 from being oxidized or corroded. It also serves as a buffer layer on the outermost layer of the phase change memory, reducing the risk of damage to the phase change memory from subsequent processes.

[0065] Based on the above embodiments, optionally, the heating bottom electrode 1111 is a titanium nitride (TiN) layer. TiN has good electrical conductivity, can stably generate Joule heat when energized, excellent high-temperature resistance, and can withstand the high temperatures required for phase transition in phase-change memory. The fabrication process of TiN is mature and can be seamlessly integrated with the fabrication process of the underlying circuit layer 120, which helps reduce costs.

[0066] Based on the above embodiments, optionally, the phase change material layer 1112 is a ternary germanium-antimony-tellurium (Ge-Sb-Te) alloy layer, such as Ge2Sb2Te5 or other Ge-Sb-Te alloys. The Ge-Sb-Te alloy exhibits low resistivity in its polycrystalline state and high resistivity in its amorphous state, with a resistivity difference reaching 4 to 6 orders of magnitude, enabling stable differentiation between data 0 and data 1. The Ge-Sb-Te alloy has a moderate phase change temperature, allowing for rapid phase change (e.g., nanosecond-level) through low-power current pulses. Furthermore, the Ge-Sb-Te alloy has good interfacial compatibility with the TiN-based heating bottom electrode 1111, preventing significant atomic interdiffusion and thus improving the cycle life of the phase change memory.

[0067] Based on the above embodiments, the top electrode 1114 may optionally be a titanium nitride (TiN) layer or a tungsten (W) layer. TiN possesses excellent high-temperature resistance and chemical stability, effectively isolating the top electrode 1114 from external oxidation and corrosion, and helping to prevent atomic interdiffusion with the phase change material layer 1112. Furthermore, when both the bottom heating electrode 1111 and the top electrode 1114 are made of TiN, their material system is unified, which simplifies the process steps. W has a high melting point, capable of withstanding the instantaneous high temperatures during the phase change process of the phase change memory without melting or structural deformation; and low resistivity, which facilitates rapid current conduction and reduces the energy loss of the electrode itself.

[0068] Based on the above embodiments, optionally, the material of the first insulating layer 1113 includes silicon oxide (SiO) or silicon nitride (SiN). SiO and SiN have high insulation resistivity and high temperature resistance, which can confine heat diffusion to the top electrode 1114, and they have good process compatibility with electrode materials such as TiN or W, thus fulfilling the requirements of the phase-change memory for the first insulating layer 1113.

[0069] In addition, the material of the first insulating layer 1113 includes SiO or SiN, and the top electrode 1114 includes titanium TiN or W, which makes the adhesion between the top electrode 1114 and the material of the first insulating layer 1113 strong, the interface stability good, and the delamination or peeling problem not easy to occur.

[0070] Based on the above embodiments, optionally, the material of the second insulating layer 1115 includes SiO or SiN. SiO and SiN have high insulation resistivity and high temperature resistance, which can confine heat diffusion to the top electrode 1114, and they have good process compatibility with electrode materials such as TiN or W, thus fulfilling the requirements of the phase-change memory for the second insulating layer 1115.

[0071] See also Figure 2 and Figure 3 Based on the above embodiments, optionally, the storage unit 111 is connected to the bottom circuit layer 120 through a via 6 (specifically, a first via 61); and the storage unit 111 is connected to the metal wiring layer 130 through a via 6 (specifically, a second via 62). For example, the storage unit 111 is a phase-change memory (PCM). The heating bottom electrode 1111 of the PCM is connected to the bottom circuit layer 120 through the first via 61, which is used to interconnect the storage unit 111 and the bottom circuit layer 120. The top electrode 1114 of the PCM is connected to the metal wiring layer 130 through the second via 62, which is used to interconnect the storage unit 111 and the metal wiring layer 130. The via 6 can be formed by deposition, etching, electroplating, polishing, etc., which has a simple fabrication process and helps reduce costs.

[0072] Based on the above embodiments, via 6 may optionally be a tungsten (W) via. W vias have a high melting point, enabling them to withstand the instantaneous high temperatures during the phase change process of the phase change memory without melting or structural deformation; they also have low resistivity, which facilitates rapid current conduction and reduces the energy loss of the electrode itself. Furthermore, if the top electrode 1114 is also made of W, consistent with the material system of the top electrode 1114, the interfacial contact resistance can be reduced.

[0073] Figure 4 This is a schematic diagram of another silicon interposer core provided in an embodiment of the present invention. Figure 5 A schematic diagram of another silicon interposer core provided in an embodiment of this utility model. See also... Figure 4 and Figure 5Based on the above embodiments, optionally, the bottom circuit layer 120 includes a CMOS 121 and interconnects 122; wherein, the CMOS 121 is used to form selection transistors and / or control logic circuits. The selection transistors are used to select the corresponding memory cell 111 for reading and writing, and the control logic refers to logic circuits containing functions such as address decoding, read / write driving, status detection, error correction, and protection, which are mainly composed of CMOS. The interconnects 122 are used to interconnect the bottom circuit layer 120 with the memory cell 111; for example, one end of the interconnect 122 is connected to the transistor, and the other end is connected to the first via 61. The fabrication process of the CMOS 121 and the corresponding interconnects 122 is compatible with the fabrication process of the memory cell 111. For example, a 55nm CMOS semiconductor manufacturing process is used, specifically oxidation growth, photolithography, etching, ion implantation, physical and chemical deposition, annealing, etc., to form the bottom circuit layer 120. This configuration facilitates the integration of the underlying circuit layer 120 and the memory cell layer 110 within the silicon interposer 10, thereby enabling integration with embedded memory cells via a TSV-free interconnect architecture.

[0074] See also Figure 4 and Figure 5 Based on the above embodiments, optionally, CMOS 121 includes the following film layers stacked together:

[0075] Substrate 123, wherein substrate 123 is a silicon substrate;

[0076] The deep well layer 1211 is located between the substrate 123 and the well layer of a portion of the CMOS, and is used to achieve electrical isolation of the portion of the CMOS. It can be understood that only a portion of the CMOS has the deep well layer 1211, and this portion of the CMOS is used to form modules that require electrical isolation, such as radio frequency circuits or low noise circuits.

[0077] Well layer 1212 and active region. Well layer 1212 includes alternately arranged N-well region and P-well region. N-type active region is arranged in N-well region and P-type active region is arranged in P-well region. The N-type active region corresponds to N-type transistor and the P-type active region corresponds to P-type transistor.

[0078] Electrode 1213, including gate, source and drain, is located on the side of the active region away from deep well layer 1211. In other words, electrode 1213 is located on the side of the active region away from substrate 123.

[0079] The deep well layer 1211 is formed in the substrate 123 by ion implantation. This deep well layer 1211 is a deeply doped region used to prevent current from flowing through the substrate 123, avoiding signal interference and circuit failure, and reducing parasitic capacitance and leakage current in the substrate 123, thereby improving the anti-interference capability and reliability of the underlying circuit layer 120. For example, the deep well layer 1211 is a deep N-well, with N-well regions connected to each other. The active regions (including N-type and P-type active regions) are defined by photolithography and etching. The N-type active region, along with its connected gate, source, and drain, constitutes an N-type transistor; the P-type active region, along with its connected gate, source, and drain, constitutes a P-type transistor. The N-type and P-type transistors are combined to form CMOS 121. A dielectric layer 1214 is also provided between adjacent transistors and between the gate and the active region to isolate different conductive regions and to isolate the gate and the active region.

[0080] The bottom circuit layer 120 also includes a plurality of bottom vias 1221, which are electrically connected to the gate, source, or drain of the transistor, respectively, to bring out the signal of the transistor. The memory cell layer 110 is electrically connected to the source or drain of the transistor through the bottom vias 1221. The bottom vias 1211 are one type of interconnect 122, and the interconnect 122 may also include horizontal traces, cross-lines, and other connecting lines. This configuration in this embodiment of the invention facilitates the formation of the bottom circuit layer 120 within the silicon substrate, resulting in a simple structure, stable performance of the formed CMOS 121, and reduced cost of the silicon interposer 10.

[0081] See also Figure 4 and Figure 5 Based on the above embodiments, the metal wiring layer 130 may optionally include the following structure:

[0082] Multilayer metal wiring 131 and multilayer rewiring via 132, with adjacent layers of metal wiring 131 electrically connected through rewiring via 132;

[0083] The top via 133 exposes the metal wiring 131 located on the top layer to bring out the signal of the memory cell 111; wherein, the metal wiring 131 located on the top layer is the metal wiring layer furthest from the memory cell layer 110.

[0084] The redistribution via 132 connects metal wiring 131 on different layers. Signals from the memory cell 111 are routed through multiple layers of metal wiring 131 and redistribution via 132, ultimately exiting through the top via 133. Specifically, the exposed metal wiring 131 on the top layer of the top via 133 is used to connect to the microbumps of the ASIC chip, or to the packaging substrate via metal bonding wires. Furthermore, metal filling can be performed within the top via 133 as a pad for soldering to the microbumps or metal bonding wires of the ASIC chip. This configuration eliminates the need for vertical interconnection between the memory cell 111 and external circuitry via a TSV, allowing the use of a planar metal wiring layer 130 to replace the TSV. This eliminates deep-hole etching and copper filling processes in the fabrication process, thereby reducing packaging costs.

[0085] It should be noted that multiple dielectric layers are also provided in the storage cell layer 110 to achieve isolation between different conductive areas.

[0086] Figure 6 This is a schematic flowchart illustrating a method for preparing silicon interposer cores according to an embodiment of the present invention. (Combined with...) Figures 1 to 6 Based on the above embodiments, optionally, a method for preparing the silicon interposer 10 provided in this utility model embodiment includes the following steps:

[0087] S101, Step of providing substrate 123;

[0088] Specifically, substrate 123 is a silicon substrate.

[0089] S102, the step of forming a bottom circuit layer 120 on the substrate 123;

[0090] Specifically, a bottom circuit layer 120 is formed on a substrate 123 using a 55nm CMOS semiconductor manufacturing process; for example, the bottom circuit layer 120 containing transistors and interconnects is formed by an oxidation growth process, a photolithography process, an etching process, an ion implantation process, a physical and chemical deposition process, and an annealing process.

[0091] S103, the step of forming a memory cell layer 110 on the bottom circuit layer 120;

[0092] Specifically, a first via 61 is formed on the bottom circuit layer 120; for example, a dielectric layer is deposited on the bottom circuit layer 120; the dielectric layer is etched to form an etched hole, the etched hole exposing the connection end of the bottom circuit layer 120; a metal material (e.g., W) is formed in the etched hole by an electroplating process, and the excess metal material is removed by a grinding process to form the first via 61.

[0093] Multiple heating bottom electrodes 1111 corresponding to multiple memory cells are formed on the first via 61. For example, a whole layer of heating bottom electrodes 1111 (e.g., TiN) is formed on the first via 61 by a deposition process (e.g., physical vapor deposition PVD). A photoresist pattern corresponding to the multiple heating bottom electrodes 1111 is formed by a photolithography process, and the whole layer of heating bottom electrodes 1111 is patterned by an etching process to form multiple heating bottom electrodes 1111.

[0094] Multiple phase change material layers 1112 are formed on the top of the heating bottom electrode 1111, each corresponding to a plurality of heating bottom electrodes 1111. The phase change material layers 1112 are aligned with the heating bottom electrodes 1111. For example, the entire phase change material layer is uniformly deposited by DC or magnetron sputtering process. Photoresist patterns corresponding to the multiple phase change material layers 1112 are formed by photolithography process. The entire phase change material layer is patterned by etching process to form multiple phase change material layers 1112. The deposition thickness of the phase change material layers 1112 is uniform, the composition is accurate, the stress is well controlled, there are no defects, and there is no oxygen contamination, so as to ensure the performance and reliability of the silicon interposer 10.

[0095] A first insulating layer 1113 is formed on top of the phase change material layer 1112, and the first insulating layer 1113 covers the area of ​​the memory cell. For example, the entire first insulating material layer (e.g., silicon dioxide SiO2 or silicon nitride Si3N4) is covered on top of the phase change material layer 1112. Excess portions of the first insulating material layer are removed by grinding or photolithography + etching processes, leaving only the portion in the area of ​​the memory cell.

[0096] A plurality of top electrodes 1114 corresponding to a plurality of phase change material layers 1112 are formed on the top of the first insulating layer 1113. For example, a whole layer of top electrodes 1114 (e.g., titanium nitride TiN or tungsten W) is formed on the first insulating layer 1113 by a deposition process. A photoresist pattern corresponding to the plurality of top electrodes 1114 is formed by a photolithography process. The whole layer of top electrodes 1114 is patterned by an etching process to form a plurality of top electrodes 1114.

[0097] A second insulating layer 1115 is formed on top of the top electrode 1114, and the second insulating layer 1115 covers the area of ​​the memory cell; for example, a whole layer of second insulating material (e.g., silicon dioxide SiO2 or silicon nitride Si3N4) is formed on top of the top electrode 1114; the excess part of the second insulating material layer is removed by grinding or photolithography + etching process, leaving only the part in the area of ​​the memory cell.

[0098] A plurality of second vias 62 corresponding to a plurality of memory cells are formed on the second insulating layer 1115; exemplarily, a dielectric layer is deposited on the second insulating layer 1115; the dielectric layer is etched to form etched holes, the etched holes exposing the top electrode 1114; a metal material is formed in the etched holes by an electroplating process; excess metal material (e.g., W) is removed by a grinding process to form the second vias 62.

[0099] S104, the step of forming a metal wiring layer 130 on the memory cell layer 110;

[0100] The metal wiring layer 130 is connected to the memory cell and is used for signal interconnection with the memory cell. For example, the steps of forming metal wiring 131 and forming rewiring vias 132 on metal wiring 131 are performed cyclically to form multiple layers of metal wiring 131 and multiple layers of rewiring vias 132; a top dielectric layer is formed on the top metal wiring layer 130, and a top via 133 is formed on the top dielectric layer. The top via 133 exposes the metal wiring 131 located on the top layer to bring out the signals of the memory cell 111.

[0101] The silicon interposer 10 for the embedded phase change memory cell 111 was fabricated through steps S101 to S104.

[0102] This utility model embodiment also provides a packaging structure, which includes the silicon interposer 10 provided in any embodiment of this utility model and has corresponding beneficial effects. Specifically, this utility model can be used for multi-chip three-dimensional integrated packaging structures, belonging to advanced packaging and integration technologies in the field of semiconductor technology, with a particular focus on three-dimensional packaging and heterogeneous chip integration. Figure 7 This is a schematic diagram of a packaging structure provided in an embodiment of the present invention. See also... Figure 7 Specifically, the packaging structure includes the following components:

[0103] Packaging substrate 20;

[0104] The silicon interposer 10, as provided in any embodiment of the present invention, is located on the packaging substrate 20;

[0105] Functional chip 30 is located on the side of silicon interposer 10 away from the packaging substrate 20; wherein, functional chip 30 is interconnected with the memory cell through metal wiring layer 130 in silicon interposer 10.

[0106] The functional chip 30 can be, for example, an ASIC chip or other chip with computing capabilities. The functional chip 30 is interconnected with the memory cells embedded in the silicon interposer chip 10 via a metal wiring layer 130. For example, this package structure includes a first functional chip 31 and a second functional chip 32, both of which can be directly interconnected with the memory cells in the silicon interposer chip 10 via microbumps 310. For example, Figure 8 This is a partial structural schematic diagram of a functional core provided in an embodiment of the present invention. (See attached diagram.) Figure 8 As shown, the functional core includes a functional core substrate 301 and a functional layer ( ) stacked together. Figure 8 (Not shown in the image), functional core passivation layer 302, photosensitive polyimide layer 303, pad 304, microbump metal layer 305 (Under Bump Metallurgy, UBM), first structure 306 in the microbump, second structure 307 in the microbump and third structure 308 in the microbump. For example, the functional chip 30 is an ASIC chip, and its fabrication process is as follows: ASIC chip fabrication is completed using CMOS technology; photosensitive polyimide material is coated on the top layer of the ASIC chip to form a photosensitive polyimide layer 303, and the solder pads 304 of the ASIC chip are exposed through exposure and development processes; metals such as titanium (Ti), nickel (Ni), or gold (Au) of different thicknesses are deposited on the surface of the ASIC chip to form a bottom metal layer 305 of microbumps; photoresist is coated, and the position and size of the solder joints are defined through exposure and development processes; a first structure 306 (e.g., copper pillar) in the microbumps is formed at the solder joint positions through electroplating; a second structure 307 (e.g., nickel (Ni) layer) and a third structure 308 (e.g., tin (Sn) layer or tin-silver SnAg alloy layer) in the microbumps are further electroplated on the first structure 306 in the microbumps; the photoresist is removed, and excess UBM is removed by etching, finally forming the microbumps.

[0107] See also Figure 7 Based on the above embodiments, optionally, the packaging substrate 20 can be interconnected with the memory cells in the silicon interposer 10 via metal bonding wires 40, or the metal wiring layer 130 in the silicon interposer 10 can be used as the connection medium between the packaging substrate 20 and the functional chip 30. This configuration enables a micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns with no high-frequency loss, thereby supporting high-speed interfaces of PCIe 5.0 and above.

[0108] See also Figure 7Based on the above embodiments, optionally, the packaging structure further includes conductive adhesive 50, which is located between the packaging substrate 20 and the silicon interposer 10. Optionally, the conductive adhesive 50 can be replaced by a die-attach film (DAF).

[0109] See also Figure 7 Based on the above embodiments, the packaging structure may optionally include solder balls 60 located at the bottom of the packaging substrate 20, which are used to connect to circuits outside the packaging structure.

[0110] See also Figure 7 Based on the above embodiments, optionally, the encapsulation structure further includes an encapsulation layer 70 covering the silicon interposer 10 and the functional chip 30. For example, the encapsulation layer 70 is made of epoxy resin molding compound to provide mechanical strength support and moisture and corrosion protection.

[0111] In summary, this utility model embodiment provides a heterogeneous integrated packaging structure based on an active silicon interposer. By integrating the bottom circuit layer and the memory cell layer 110 in the silicon substrate, and using the metal wiring layer 130 (i.e., the surface redistribution layer) to replace the TSV interconnect in the prior art, the three-in-one integration of storage, computing and interconnection is achieved.

[0112] Figure 9 This is a schematic flowchart illustrating a method for fabricating a packaging structure according to an embodiment of the present invention. (See also: [link to related documentation]). Figures 7 to 9 Based on the above embodiments, optionally, a method for preparing the packaging structure provided in the embodiments of this utility model includes the following steps:

[0113] S201, the step of providing a whole wafer of silicon interposer 10 as provided in any embodiment of the present invention;

[0114] S202, the step of bonding the functional chip 30 to the whole wafer by hot-press bonding process;

[0115] For example, the first functional chip 31 and the second functional chip 32 are simultaneously bonded to the entire wafer containing multiple silicon interposer chips 10 by a hot-press bonding process, i.e., chip-to-wafer (C2W) bonding.

[0116] S203, Perform a dicing process to obtain multiple integrated units containing silicon interposer 10 and functional granules 30 after dicing;

[0117] S204, the step of mounting the integrated unit onto the packaging substrate 20.

[0118] For example, the cut integrated unit is precisely mounted onto the packaging substrate 20 using conductive adhesive 50 or DAF film; after mounting, the pads on the silicon interposer 10 are electrically connected to the corresponding solder points on the packaging substrate 20 by wire bonding using gold wire or copper palladium wire; after wire bonding, an epoxy resin molding compound is applied to the outside of the packaging structure by epoxy resin injection molding; after molding, the packaging structure is inverted, and solder balls 60 are placed at the solder points of the bottom pins using a pre-molded stencil; the solder balls 60 are then soldered and fixed by reflow soldering.

[0119] The packaging structure was fabricated using S201~S204.

[0120] In summary, this utility model embodiment provides a collaborative technical solution between a TSV-free silicon interposer structure and an embedded phase-change memory, which can achieve at least the following beneficial effects:

[0121] Firstly, breakthroughs in cost and reliability: This utility model uses a metal wiring layer 130 to replace the TSV structure, eliminating deep hole etching and copper filling processes in the fabrication process, which helps to reduce packaging costs, for example, by more than 67%; and helps to avoid stress concentration problems caused by the difference in thermal expansion coefficients between copper and silicon, for example, it can ensure that silicon interposer samples still have no microcracks after 2000 temperature cycles, thus improving reliability.

[0122] Secondly, regarding access speed optimization, this embodiment of the invention embeds a phase-change memory structure within the silicon interposer 10. The data transmission path between the ASIC chip and the memory cell is transformed from a planar two-dimensional connection to a vertical connection, resulting in a shorter data transmission path. Specifically, the metal wiring layer 130 can be used for interconnection via metal bonding wires, or the metal wiring layer 130 in the silicon interposer 10 can serve as the connection medium between the packaging substrate 20 and the functional chip 30. This solution enables micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns with no high-frequency loss, thereby supporting high-speed interfaces of PCIe 5.0 and above. Therefore, this embodiment of the invention is beneficial in improving the problems of signal delay and high-frequency loss.

[0123] Furthermore, due to the crystallization mechanism of phase-change memory (PCM), it is relatively stable compared to other types of memory cells (e.g., floating-gate or electron tunneling memory cells), thus improving storage reliability. Additionally, PCM requires no loading upon power-up and employs a data overwrite method without erasure operations, resulting in faster write and erase speeds compared to other types of memory cells. Therefore, this embodiment of the invention achieves beneficial effects such as accelerating the power-up process, improving write access speed, enhancing power-loss protection, and improving overall reliability.

[0124] Furthermore, by embedding the memory cell inside the silicon interposer 10, this embodiment of the invention achieves a thickness increment of <0.2mm, thereby keeping the total package thickness within 1.5mm. In the package structure, the metal wiring layer 130 can be used for interconnection via metal bonding wires. This solution enables a micro-pitch interconnect design of ≤35μm, shortening the overall signal path to within 0.8mm, achieving a transmission delay of <1ns with no high-frequency loss, thus supporting PCIe 5.0 and higher high-speed interfaces. Therefore, this embodiment of the invention not only achieves a thin package thickness but also meets the real-time data access requirements of industrial control.

[0125] Thirdly, this embodiment of the invention can integrate phase-change memory using a 55nm CMOS process, which is equivalent to integrating memory cells at the package level, while existing technologies integrate memory cells at the wafer level. Therefore, this embodiment of the invention can avoid the process conflicts and durability defects that exist in existing technologies using floating-gate memory cells. Specifically, this embodiment of the invention does not require a high-voltage charge pump design, and its operating voltage can be as low as 0.7V, achieving 10kJ / bit ultra-low power consumption. 9 It has high write endurance, thus enabling it to operate at voltage levels such as 1.8V.

[0126] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0127] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A silicon interposer, characterized in that, Formed in the silicon interposer, including: A storage cell layer, the storage cell layer including at least one storage cell, the storage cell being embedded in the silicon interposer; A bottom-level circuit layer is located on one side of the memory cell layer and is connected to the memory cell; the bottom-level circuit layer is used to control the memory cell. A metal wiring layer is located on the side of the memory cell layer away from the underlying circuit layer; the metal wiring layer is connected to the memory cell and is used to realize signal interconnection between the external circuit and the memory cell.

2. The silicon interposer core according to claim 1, characterized in that, The storage unit includes a phase-change memory.

3. The silicon interposer core according to claim 2, characterized in that, The phase change memory includes a heated bottom electrode, a phase change material layer, and a top electrode stacked together.

4. The silicon interposer core according to claim 3, characterized in that, The heating bottom electrode is a TiN layer; And / or, the phase change material layer is a Ge-Sb-Te alloy layer; And / or, the top electrode is a TiN layer or a W layer.

5. The silicon interposer core according to claim 1, characterized in that, The storage unit is connected to the underlying circuit layer via a via; Furthermore, the storage unit is connected to the metal wiring layer via vias.

6. The silicon interposer according to claim 1, characterized in that, The underlying circuit layer includes CMOS and interconnects; wherein the CMOS is used to form selection transistors and / or control logic circuits.

7. The silicon interposer according to claim 6, characterized in that, The CMOS includes: Base; A well layer and an active region are located on the substrate. The well layer includes alternately arranged N-well regions and P-well regions. An N-type active region is disposed in the N-well region, and a P-type active region is disposed in the P-well region. The N-type active region corresponds to an N-type transistor, and the P-type active region corresponds to a P-type transistor. The gate, source, and drain are located on the side of the active region away from the substrate; A deep well layer, the deep well layer being located between the substrate and the well layer of a portion of the CMOS.

8. The silicon interposer core according to claim 1, characterized in that, The metal wiring layer includes: Multilayer metal wiring and multilayer rewiring vias, with adjacent layers of metal wiring electrically connected through the rewiring vias; A top via exposes the metal wiring located on the top layer to bring out the signals of the memory cell; wherein the metal wiring located on the top layer is the metal wiring layer furthest from the memory cell layer.

9. A packaging structure, characterized in that, include: Packaging substrate; The silicon interposer die as described in any one of claims 1-8 is located on the packaging substrate; A functional chip is located on the side of the silicon interposer away from the packaging substrate; wherein the functional chip is interconnected with the memory cell through the metal wiring layer in the silicon interposer.

10. A semiconductor device, characterized in that, include: The packaging structure as described in claim 9.

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