A dynamic power shaping method for a memory controller chip

Abstract

A dynamic power consumption shaping method for a memory controller chip includes: acquiring the channel enable signal vector of the current physical layer interface; extracting the corresponding equivalent admittance matrix based on the enable signal vector; calculating the instantaneous power density characteristic value of the silicon interposer in conjunction with the current operating voltage; statistically analyzing the arrival rate of memory read / write instructions according to a set long clock window and a short clock window respectively, obtaining a long-period moving average reference value and a short-period transient characteristic value, and calculating the statistical deviation; triggering a load burst interrupt signal when the statistical deviation exceeds the value of a hardware threshold register; and, in response to the load burst interrupt signal, forcibly splitting continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions, and inserting a programmable number of clock idle cycles between the send enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses. This method enables fine-grained power consumption shaping during load bursts.

Description

Technical Field

[0001] This application relates to the field of storage media technology, and in particular to a dynamic power consumption shaping method for a storage controller chip. Background Technology

[0002] In the post-Moore's Law era, to overcome the "memory wall" limitation, the integrated circuit field has widely adopted 2.5D advanced packaging technology. This involves high-density integration of logic dies and high-bandwidth memory dies through a silicon interposer. The silicon interposer integrates tens of thousands of microbumps and a high-density redistribution layer to achieve extremely high-speed data interconnection between the two.

[0003] In existing technologies, temperature sensors are typically deployed on the system-on-chip to prevent chip overheating. When the sensor reading exceeds a threshold, the power management unit triggers a dynamic voltage and frequency adjustment mechanism to reduce the operating frequency or voltage and thus reduce power consumption. Summary of the Invention

[0004] This application provides a dynamic power consumption shaping method for a storage controller chip, which can eliminate the hysteresis of the control loop by intervening in advance during the heat accumulation latency period and performing fine power consumption shaping during the load burst period.

[0005] In a first aspect, this application provides a dynamic power consumption shaping method for a memory controller chip. The method includes: obtaining the channel enable signal vector of the current physical layer interface of the memory controller chip; inputting the enable signal vector into a preset impedance lookup table configured on-chip to extract the equivalent admittance matrix corresponding to the currently active channel combination; calculating the instantaneous power density characteristic value of the two-dimensional grid array of the silicon interposer using on-chip multiply-add units combined with the current operating voltage; using a flow monitoring counter within the memory controller chip to statistically analyze the arrival rate of memory read / write instructions according to a set long clock window and a short clock window, respectively, to obtain a long-period moving average reference value and a short-period transient characteristic value; and calculating the statistical deviation between the short-period transient characteristic value and the long-period moving average reference value using on-chip comparison logic. When the statistical deviation exceeds a preset hardware threshold register value, a high-confidence load burst interrupt signal is triggered. In response to the load burst interrupt signal, the instruction scheduler forcibly splits continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions, and inserts a programmable number of clock idle cycles between the transmit enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses. The cache management unit of the on-chip static random access memory of the storage controller chip maximizes the data hit probability to reduce the access frequency of the external physical interface to the silicon interposer. Based on the load trend prediction results and temperature data, corresponding hardware adjustment instructions are calculated and executed. The hardware adjustment instructions are used to eliminate the oscillation effect caused by heat conduction.

[0006] The equivalent admittance matrix of the silicon interposer is generated jointly by the on-chip stored static configuration matrix and the real-time acquired bus enable signal. Specifically, the static configuration matrix is ​​pre-programmed in the non-volatile memory of the memory controller chip, recording the primary / secondary impedance parameters of the microstrip lines, vias, and microbumps on the corresponding physical layout. The physical layer interface status monitoring logic within the memory controller chip extracts the current DDR channel activation mask in real time as the real-time load input vector. A dedicated multiply-accumulate coprocessor is configured within the memory controller chip, which performs a hardware lookup-based Schur complement approximation operation on the static configuration matrix based on the real-time load input vector, outputting an equivalent admittance matrix representing the equivalent transmission impedance of each node in the silicon interposer plane.

[0007] Among them, the hotspot prediction arithmetic logic unit of the storage controller chip reads the equivalent admittance matrix and, in combination with the current system power supply voltage value, calculates the instantaneous power density characteristic value of the corresponding node through the hardware exponentiation unit, thereby reconstructing the flag bit of the power density distribution map in the internal register.

[0008] The memory controller chip's flow monitoring counters, operating within a set long and short clock window, respectively, count the arrival rate of memory read / write commands to obtain a long-term moving average baseline value and a short-term transient characteristic value. This includes: using a first hardware counter driven by a long clock cycle to count the arrival rate of memory requests and performing an exponential moving average calculation, with the output value serving as the long-term moving average baseline value representing steady-state cognition; using a second hardware counter driven by a short clock cycle to count the arrival rate of memory requests in the current transient state, with the output value serving as the short-term transient characteristic value; and calculating the statistical deviation between the short-term transient characteristic value and the long-term moving average baseline value using on-chip comparison logic, including: calculating the difference between the short-term transient characteristic value and the long-term moving average baseline value using on-chip comparison logic to obtain the statistical deviation.

[0009] The memory controller chip has a prediction frequency control register at its front end. When the statistical deviation output by the comparison logic circuit is less than or equal to the set hardware threshold register value, a low-frequency configuration word is written to the prediction frequency control register to reduce the sampling clock frequency of the second hardware counter. When the statistical deviation is greater than the hardware threshold register value, a hardware interrupt signal is generated and a high-frequency configuration word is written to the prediction frequency control register to force the system to output the load burst prediction flag bit in real time with the shortest time step.

[0010] Specifically, the instruction scheduler forcibly splits continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions, and inserts a programmable number of idle clock cycles between the transmit enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses. This includes: separating memory access bus transactions into a prefetch stream via the address / command channel of the logic controller and a load transmission stream via the data channel; when a prediction result indicating high thermal risk is received, the bus arbitrator intercepts continuous write transactions exceeding the set burst length threshold and forcibly splits them into multiple short burst sub-transactions at the protocol layer; between sending the data valid signals of adjacent short burst sub-transactions to the physical layer, the hardware scheduler forcibly inserts multiple idle clock cycles defined by the time slot register, thereby shaping the continuous current waveform into discontinuous pulses.

[0011] If the address / command channel prefetch stream generates a speculative data read request while the channel is in a high-risk state, the bus arbiter will discard the identifier of the prefetch request directly in the transmit queue according to the configuration policy, so as to release the physical layer occupancy of the data transmission stream.

[0012] The cache management unit of the on-chip static random access memory includes a dynamic step size control register. In the cache management unit of the on-chip static random access memory of the storage controller chip, the probability of data hit is maximized by: when a cache hit occurs, the cache controller reads the value of the dynamic step size control register and modifies the corresponding step size value displacement of the cache line priority line pointer of the hit data block in the direction of higher priority, instead of directly setting it to the top; when a cache miss occurs, the priority pointer of the newly read data block from the outside is initialized to the lowest priority, and the value in the dynamic step size control register is slightly increased through the hardware feedback loop.

[0013] The calculation and execution of hardware adjustment instructions are performed by the power and clock management state machine on the memory controller chip: the power and clock management state machine receives readings from distributed on-chip physical temperature sensors, extracts the first derivative of the temperature through a hardware differentiating circuit, and weights and superimposes the two to form an advance warning control word; the power and clock management state machine has a pre-set mapping table, and the output of the mapping table is a joint control word containing voltage frequency adjustment field and channel power gating field to perform diagonal adjustment based on a two-dimensional plane.

[0014] After the power and clock management state machine issues a joint control word, the internal performance monitoring unit monitors the back pressure signal of the bus interface. If the back pressure signal ratio exceeds the preset delay violation threshold, the power and clock management state machine triggers a backoff compensation mechanism to modify the voltage and frequency adjustment field to adjust the operating frequency by one level.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the dynamic power consumption shaping method for a memory controller chip provided in this application includes: obtaining the channel enable signal vector of the current physical layer interface of the memory controller chip; inputting the enable signal vector into a preset impedance lookup table configured on-chip to extract the equivalent admittance matrix corresponding to the currently active channel combination; calculating the instantaneous power density characteristic value of the two-dimensional grid array of the silicon interposer using on-chip multiply-add units combined with the current operating voltage; the flow monitoring counter within the memory controller chip statistically analyzes the arrival rate of memory read / write instructions according to a set long clock window and a short clock window respectively, obtaining a long-period moving average reference value and a short-period transient characteristic value; and calculating the short-period transient characteristic value and the long-period moving average reference value using on-chip comparison logic. The system measures the statistical deviation of the value; when the statistical deviation exceeds a preset hardware threshold register value, a high-confidence load burst interrupt signal is triggered; in response to the load burst interrupt signal, the instruction scheduler forcibly splits continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions, and inserts a programmable number of clock idle cycles between the send enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses; it maximizes the data hit probability in the cache management unit of the on-chip static random access memory of the storage controller chip to reduce the access frequency of the external physical interface to the silicon interposer; it calculates and executes corresponding hardware adjustment instructions based on load trend prediction results and temperature data; the hardware adjustment instructions are used to eliminate the oscillation effect caused by heat conduction. It can eliminate the hysteresis of the control loop by intervening early during the heat accumulation latency period and performing fine-grained power shaping during the load burst period. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating an embodiment of the dynamic power consumption shaping method for a memory controller chip provided in this application; Figure 2 yes Figure 1 A flowchart of an embodiment of step 11; Figure 3 yes Figure 1 A flowchart illustrating an embodiment of step 14; Figure 4 yes Figure 1 A flowchart of an embodiment of step 15. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] The technical problem to be solved by this application is the "thermal-performance low-frequency oscillation" problem, which is common in existing 2.5D packaged storage systems, is simple but extremely difficult to eradicate.

[0020] Specifically, physical heat conduction inherently exhibits a "time lag effect" between the silicon interposer and the sensor (i.e., a delay between the instantaneous heat generation and the sensor's detection of the temperature rise), while sudden bursts of storage access load are often instantaneous. This time-scale mismatch leads to severe phase lag in traditional temperature control mechanisms: when the sensor detects overheating, heat has already accumulated excessively, forcing the system to take aggressive frequency reduction measures (such as directly halving the frequency), causing a sudden drop in data throughput; when the temperature returns to a safe level, the system quickly resumes full speed, causing heat to accumulate rapidly again. This repeated "sudden braking-rapid acceleration" process causes the storage controller's performance curve to exhibit sawtooth-shaped low-frequency oscillations, significantly reducing the average effective bandwidth and introducing power supply ripple due to frequent voltage jumps, affecting the signal integrity of data transmission.

[0021] See Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the dynamic power consumption shaping method for a memory controller chip provided in this application. The method includes: Step 11: Calculate the current equivalent interconnect characteristics using the analytical pixel mapping model to reconstruct the power density distribution map of the silicon interposer plane.

[0022] The analytical pixel mapping model is used to characterize the physical interconnect characteristics inside the silicon interposer; the power density distribution map is used to show the electromagnetic coupling strength and potential thermal accumulation distribution inside the silicon interposer.

[0023] This step aims to establish a mathematical model that can quickly and accurately reflect the complex physical interconnect characteristics within the silicon interposer. This model abandons traditional methods that require significant computational resources for real-time full-wavelength simulations or rely on uninterpretable neural network predictions, instead employing an analytical computational path based on microwave multiport network theory. By discretizing the physical structure into configurable impedance units, millisecond-level predictions of the thermal-electric coupling characteristics of interconnects under different data transmission modes are achieved.

[0024] In some embodiments, the parsed pixel mapping model includes a plurality of primary virtual pixel units, a plurality of secondary diagonal pixel units, horizontal / vertical virtual ports, and diagonal virtual ports; each primary virtual pixel unit corresponds to a microstrip line, a via, or a microbump connection point on the physical layout; secondary diagonal pixel units are located at the intersection corners of every four adjacent primary virtual pixel units; horizontal / vertical virtual ports are located between any adjacent primary virtual pixel units, and diagonal virtual ports are located between primary virtual pixel units and secondary diagonal pixel units.

[0025] That is, a discretized mesh mapping of the silicon interposer physical structure needs to be performed in advance. First, the high-density interconnect region of the silicon interposer between the memory controller and the memory die (including the redistribution layer RDL and the microbump array) is defined as the "target design space". This three-dimensional space is divided into several tiny rectangular grids on the planar projection, defined as "primary virtual pixel units". Each primary virtual pixel unit corresponds to a microstrip line, a via, or a microbump connection point on the physical layout. In order to capture the significant diagonal crosstalk effect in high-density wiring, smaller "secondary diagonal pixel units" are embedded at the intersection corners of every four adjacent primary virtual pixel units. Thus, the continuous physical silicon interposer is transformed into a discretized array composed of interwoven primary and secondary pixels. This array can express arbitrarily complex actual wiring structures through the combination of pixel "presence" or "absence" states.

[0026] This includes the design, deployment, and full connectivity characterization of virtual coupling ports. Based on the aforementioned discretized array, a "virtual port network" is constructed to capture electromagnetic energy transmission and thermal coupling paths. This mainly involves port implantation and full connectivity characterization.

[0027] Port implantation mainly involves inserting "horizontal / vertical virtual ports" and "diagonal virtual ports" between any adjacent primary virtual pixel units and between a primary virtual pixel unit and a secondary diagonal pixel unit, respectively. Simultaneously, a "ground virtual port" is inserted between each pixel unit and the reference ground plane.

[0028] The full connectivity is characterized primarily by the fact that these virtual ports constitute a vast multi-port network. The relationship between the voltage across the port and the current flowing through it fully describes the physical characteristics of signal transmission within the silicon interposer, including horizontal transmission vias, vertical coupling, diagonal coupling, and return to ground.

[0029] In some embodiments, see Figure 2 Step 11 can be the following process: Step 111: Generate the global intrinsic impedance matrix during the characterization stage of the memory controller chip design or the preprocessing stage of the memory controller chip initialization.

[0030] The global intrinsic impedance matrix contains information about the electromagnetic coupling and thermal conductivity inherent in the silicon interposer under all possible wiring combinations.

[0031] In some embodiments, a high-precision physical field extraction is performed during the characterization phase of chip design or the preprocessing phase of controller initialization. This mainly involves full-configuration simulation and matrix extraction processes.

[0032] The full configuration simulation mainly involves setting all virtual pixel units to a "metal-filled" state (i.e., physically connected state) and using an industrial-grade electromagnetic field simulation tool to perform a full-wave scan of the fully connected structure.

[0033] The matrix extraction process primarily involves extracting the simulation results to generate a high-dimensional "global intrinsic impedance matrix" (Z-Matrix). This matrix is ​​permanently stored in the controller's non-volatile memory. It contains the inherent electromagnetic coupling and thermal conductivity information of the silicon interposer under all possible wiring combinations, serving as the mathematical foundation for all subsequent real-time calculations.

[0034] Step 112: When the storage controller chip is running, generate a real-time load diagonal matrix that dynamically changes over time based on the current DDR channel activation status.

[0035] In some embodiments, when the storage controller is running, real-time physical constraints are generated based on the current DDR channel activation status. This mainly involves processes such as status monitoring and load mapping algorithms.

[0036] Status monitoring mainly involves reading the channel mask of the memory controller in real time to determine which data channels are currently transmitting signals (active state) and which are in an idle or off state (quiet state).

[0037] The load mapping algorithm primarily involves mapping the active / quiet state of a physical channel to the load conditions of virtual pixel units. Specifically: For the pixel unit corresponding to the active channel, its associated virtual port load is set to "short circuit state" (i.e., impedance approaches zero), which means that the signal is unobstructed and current and heat can be conducted.

[0038] For silent channels or areas where there is no physical wiring, the associated virtual port load is set to "open circuit state" (i.e., impedance approaches infinity), which means that the transmission path is cut off.

[0039] This generates a "real-time load diagonal matrix" that changes dynamically over time.

[0040] Step 113: Calculate the current equivalent interconnect characteristics based on the global intrinsic impedance matrix and the real-time load diagonal matrix, and reconstruct the power density distribution map of the silicon interposer plane.

[0041] In some embodiments, based on the block inversion of the matrix and the Schur complement operation, the equivalent transmission impedance between the input / output ports in the current active state is calculated according to the global intrinsic impedance matrix and the real-time load diagonal matrix; based on the equivalent transmission impedance and the estimated current flowing through each virtual port, the power density distribution map of the silicon interposer plane is reconstructed.

[0042] In some embodiments, the current equivalent interconnect characteristics are calculated using a matrix operation unit, combining a static "global intrinsic impedance matrix" with a dynamic "real-time load diagonal matrix". This mainly involves analytical calculations and hotspot prediction.

[0043] The analytical calculation mainly involves using the closed-loop analytical formula in multi-port network theory (based on block inversion of the matrix and Schur complement operation) to directly calculate the equivalent transmission impedance between the input / output ports in the current activation mode.

[0044] Hotspot prediction mainly involves: based on the calculated real part of the equivalent impedance (resistive component) and the estimated current flowing through each virtual port, using Joule's law. The power density distribution map of the silicon interposer plane can be quickly reconstructed.

[0045] Through the above steps, this scheme transforms the complex physical field simulation problem into deterministic linear algebra matrix operations. The controller (storage controller chip) can accurately calculate the electromagnetic coupling strength and potential thermal accumulation distribution inside the silicon interposer within microseconds, based solely on the current channel activation pattern (power density distribution map), without waiting for the hysteresis feedback from the temperature sensor. This provides a physical layer input variable with zero delay for subsequent "phase lead control".

[0046] That is, obtain the channel enable signal vector of the current physical layer interface of the memory controller chip; input the enable signal vector into the preset impedance lookup table configured on the chip to extract the equivalent admittance matrix corresponding to the current active channel combination; and calculate the instantaneous power density characteristic value of the silicon interposer two-dimensional mesh array by combining the on-chip multiply-add unit with the current operating voltage.

[0047] The equivalent admittance matrix of the silicon interposer is generated jointly by the on-chip stored static configuration matrix and the real-time acquired bus enable signal; where: A static configuration matrix is ​​pre-programmed into the non-volatile memory of the storage controller chip. The static configuration matrix records the primary / secondary impedance parameters of the microstrip lines, vias and microbumps on the corresponding physical layout. The physical layer interface status monitoring logic within the storage controller chip extracts the current DDR channel activation mask in real time as the real-time load input vector. The memory controller chip is equipped with a dedicated multiply-accumulate coprocessor. The multiply-accumulate coprocessor performs a hardware lookup table-based Schur complement approximation operation on the static configuration matrix based on the real-time load input vector, and outputs an equivalent admittance matrix representing the equivalent transmission impedance of each node in the silicon interposer plane.

[0048] The hotspot prediction arithmetic logic unit of the storage controller chip reads the equivalent admittance matrix and, in conjunction with the current system power supply voltage, calculates the instantaneous power density characteristic value of the corresponding node through the hardware exponentiation unit, thereby reconstructing the flag bit of the power density distribution map in the internal register.

[0049] In the specific System-on-Chip (SoC) hardware implementation, the pixel mapping in this step does not rely on the processor running complex electromagnetic field differential equation software code. Instead, it is achieved through the collaboration of hardware look-up table (LUT) and a dedicated coprocessor. The specific process is as follows: Static substrate configuration: The global intrinsic impedance matrix is ​​pre-programmed in the non-volatile read-only memory (ROM) or one-time programmable (OTP) memory of the storage controller chip. This matrix is ​​static configuration data generated offline by extracting the parasitic resistance and capacitance (RC) parameters of the silicon interposer layout before chip design and tape-out.

[0050] Real-time load acquisition: The on-chip physical layer interface (PHY) status monitoring logic acquires the DDR controller's channel enable mask (defined as a vector) in real time during each clock cycle. The high and low levels of this vector directly reflect which physical microbumps are currently undergoing signal flipping.

[0051] Hardware coprocessor computation: The memory controller is internally configured with a dedicated multiply-accumulate coprocessor (MACCoprocessor). This coprocessor operates in vector... As the input address, the corresponding dynamic load matrix is ​​retrieved from a preset impedance lookup table. Subsequently, the MAC coprocessor invokes the internally hardwired Schur complement approximation logic to calculate the equivalent admittance matrix. .

[0052] Hotspot flag generation: On-chip hotspot prediction arithmetic and logic unit (ALU) extraction The diagonal elements, combined with real-time voltage measurements of the current power supply network. The instantaneous power density characteristic values ​​of each discrete grid are directly output through a hardware multiplier. .like If the threshold value in the preset register is exceeded, the "Hotspot Flag" for the corresponding area in the internal status register is set to 1. This pure hardware data path has extremely low computation latency, typically completed within tens of system clock cycles, perfectly overcoming the physical heat conduction lag problem of external temperature sensors.

[0053] Step 12: Whenever a new memory access request arrives or completes within a tiny sampling period, the memory access load is predicted using a dual load state baseline model to obtain the load trend prediction results.

[0054] The load trend prediction results include load trend prediction values ​​and confidence levels; the confidence level is used to identify the reliability of the load trend prediction values; and the dual load state benchmark model is used to describe memory access characteristics.

[0055] This step involves building a lightweight hardware prediction logic at the front end of the storage controller, aiming to resolve the technical contradiction that traditional fixed-period sampling cannot simultaneously achieve both "burst response speed" and "noise immunity". This method does not rely on complex deep neural networks, but instead employs an adaptive clock domain adjustment mechanism based on statistical differences to achieve "zoom-like" prediction of memory access load.

[0056] In some embodiments, the dual load state baseline model includes a static baseline model and a dynamic transition model; the static baseline model is used to characterize the steady-state perception of the current business load; the dynamic transition model is used to extrapolate the expected load at the current moment.

[0057] In some embodiments, two sets of mathematical models describing memory access characteristics are maintained in real time in the controller's register group, representing the system's "steady-state cognition" and "transient changes," respectively: Static benchmark model construction: A relatively long time window (e.g., milliseconds) is set, and key metrics of memory read / write requests (including instruction arrival rate, read / write switching frequency, line buffer hit rate, etc.) are statistically analyzed within this window. The mean and variance of these metrics are calculated using hardware logic to construct a "long-period steady-state distribution model" that follows the assumption of a normal distribution. This model represents the controller's "inherent perception" or "inertial expectation" of the current business load.

[0058] Dynamic transition model construction: A very short time window (e.g., microseconds or nanoseconds) is defined, and based on the load state at the previous moment, linear regression or lightweight state transition equations are used to extrapolate the expected load at the current moment. This model represents a "short-period change expectation" formed based on the most recent observation.

[0059] In some embodiments, step 12 may be the following process: Step 121: Whenever a new memory access request arrives or completes within a tiny sampling period, the actual load feature vector collected at the current instant is compared with the static benchmark model to obtain the statistical distance between the two.

[0060] In some embodiments, whenever a new memory access request arrives or completes within a tiny sampling cycle, the hardware computing unit performs a "surprise" assessment to quantify the degree of abrupt change in the current load relative to steady-state perception: Deviation metric: The actual load feature vector collected at the current instant is compared with the aforementioned "long-period steady-state distribution model". A simplified relative entropy algorithm or a weighted Euclidean distance algorithm is used to calculate the statistical distance between the two.

[0061] Indicator definition: This statistical distance is defined as "surprise" (i.e., the degree of unexpectedness in information theory).

[0062] If the surprise index is low, it indicates that the current load fluctuation is normal statistical noise and the system is in a stable period. If the surprise index suddenly increases, it indicates that the current load characteristics have fundamentally changed (such as a sudden large-scale continuous write stream), and the system's original steady-state perception has failed.

[0063] Step 122: Dynamically adjust the frequency and time span of the prediction update based on the statistical distance, and then perform load trend prediction on the memory access load to obtain the load trend prediction result.

[0064] In some embodiments, the controller dynamically adjusts the "subjective timescale" of the load prediction module, i.e. the frequency and time span of prediction updates, based on the real-time calculated "surprise" value.

[0065] In response to a statistical distance below or equal to a preset threshold, the prediction update time span is extended and the prediction update frequency is reduced. Low surprise (stable) mode: When the surprise level is below a preset threshold, the prediction logic enters a "low-frequency, long-step" state. The system determines that it only needs to maintain the established strategy, therefore automatically extending the prediction update time interval and reducing the clock gating frequency of the prediction circuit. This not only filters out the interference of high-frequency random jitter on the control strategy but also significantly reduces the power consumption of the prediction circuit itself.

[0066] In response to statistical distances exceeding a preset threshold, the prediction update time span is shortened, and the prediction update frequency is increased. High Surprise (Burst) Mode: When the surprise level exceeds the threshold, the prediction logic immediately switches to a "high-frequency, short-step" state. The system determines that an "unexpected" event has occurred, forcibly shortens the prediction time window to the nanosecond level, and frequently triggers updates to the "dynamic transfer model." At this time, the controller essentially performs a "magnified observation" of load changes on the timeline, enabling it to capture energy consumption increases over extremely short periods.

[0067] Based on the above calculations, the prediction unit outputs a control signal containing two dimensions (load trend prediction value and confidence level) for use by the subsequent power shaping unit: Trend forecast (load trend forecast): This is a future load estimate based on a "subjective timescale" weighted average. In sudden events, this value is mainly determined by the short-cycle model, with the weights rapidly shifting towards transient changes; in steady-state conditions, it is mainly determined by the long-cycle model.

[0068] Confidence level marker (confidence level): Indicates the reliability of the current prediction. A high surprise level usually corresponds to a low initial confidence level, suggesting that subsequent control units (such as voltage regulators) need to allow for a larger safety margin or take more aggressive suppression measures when taking action.

[0069] Through the above steps, the storage controller acquires an "attention mechanism" similar to that of a biological nervous system. Instead of mechanically sampling at a fixed frequency, it automatically adjusts the sensing timeline based on the "unexpectedness" of load changes. This mechanism ensures that it remains stable during data quiet periods (energy saving, voltage stabilization) and can instantly sense and react in the first few clock cycles before a sudden storm (hysteresis resistance), perfectly solving the control challenges caused by physical heat conduction hysteresis.

[0070] Specifically, the flow monitoring counter within the storage controller chip counts the arrival rate of memory read / write commands according to set long and short clock windows, respectively, to obtain a long-term moving average baseline value and a short-term transient characteristic value. The statistical deviation between the short-term transient characteristic value and the long-term moving average baseline value is calculated using on-chip comparison logic. When the statistical deviation exceeds a preset hardware threshold register value, a high-confidence load burst interrupt signal is triggered. For example, a first hardware counter driven by a long clock cycle counts the arrival rate of memory requests and performs an exponential moving average calculation; its output value serves as the long-term moving average baseline value representing steady-state perception. A second hardware counter driven by a short clock cycle counts the current transient memory request arrival rate; its output value serves as the short-term transient characteristic value. The difference between the short-term transient characteristic value and the long-term moving average baseline value is calculated using on-chip comparison logic to obtain the statistical deviation. The memory controller chip is equipped with a prediction frequency control register at the front end. When the statistical deviation output by the comparison logic circuit is less than or equal to the set hardware threshold register value, a low-frequency configuration word is written to the prediction frequency control register to reduce the sampling clock frequency of the second hardware counter. When the statistical deviation is greater than the hardware threshold register value, a hardware interrupt signal is generated and a high-frequency configuration word is written to the prediction frequency control register to force the system to output the load burst prediction flag bit in real time with the shortest time step.

[0071] To achieve burst load prediction without introducing the overhead of complex machine learning inference chips, this embodiment abandons pure software algorithms and designs a dual-clock-window traffic monitoring hardware circuit, which is implemented as follows: Dual Hardware Counter Monitoring: A first hardware counter and a second hardware counter are deployed at the bus interface unit (BIU) entry point. The first hardware counter is driven by a long clock cycle (e.g., a frequency divider triggered every 1ms), and implements exponential moving average (EMA) filtering through a hardware shift register to output a long-period baseline characteristic value of the current memory request arrival rate. (Represents the system steady-state baseline); the second hardware counter consists of a short clock cycle (e.g., Triggered by the current short-cycle transient characteristic value, it directly outputs the current short-cycle transient characteristic value. (Represents a transient spike in the system).

[0072] Hardware calculation of statistical deviation: The on-chip comparator logic circuit calculates the ratio of the absolute value of the difference between the two values ​​to the steady-state variance in real time, thus obtaining the statistical deviation. (Equivalent to hardware-based Z-Score).

[0073] Interrupt triggering and clock gating switching: The chip front end is equipped with a predictive frequency control register. When the compare logic detects... When the preset threshold register value indicates a stable period, a low-frequency configuration word is written to the frequency control register, and the sampling frequency of the second hardware counter is reduced by the gated clock to save dynamic power consumption; once... This indicates the arrival of a sudden high load. The comparison logic immediately raises the load sudden hardware interrupt signal and writes a high-frequency configuration word to the frequency control register, forcing the system to output a high-confidence thermal risk prediction flag in real time with the shortest time step (nanosecond level), thus gaining a crucial lead time for subsequent power shaping.

[0074] Step 13: Based on the load trend prediction results, execute a hierarchical traffic scheduling strategy inside the storage controller chip to segment transmission commands and achieve proactive power consumption waveform reconstruction.

[0075] This step, based on the load trend prediction and confidence signal generated in step 12, executes a hierarchical traffic scheduling strategy within the storage controller. This strategy aims to address the problem of instantaneous heat accumulation caused by continuous burst transmissions in the traditional controller's "best-effort" mode. By decoupling logic processing from physical transmission and micro-segmenting transmission commands, proactive power waveform reconstruction is achieved.

[0076] In some embodiments, step 13 may be the following process: Step 131: Divide the transmission command into an address prefetch stream and a data transmission stream.

[0077] In some embodiments, the address prefetch stream handles computation-related tasks, including virtual-to-physical address translation, metadata lookup, page hit determination, and command reordering. The data transfer stream drives the physical interface and the microbumps on the silicon interposer to perform the actual electrical signal switching and data transfer.

[0078] In some embodiments, at the controller's instruction scheduling level, a memory request is no longer treated as a single atomic operation, but is instead broken down and diverted to two independent and asynchronous hardware execution pipelines (address prefetch stream and data transfer stream): Address prefetching pipeline (logic flow): This pipeline is dedicated to handling computation-related tasks, including virtual-to-physical address translation, metadata lookup, page hit determination, and command reordering. This part of the operation mainly consumes the computational power of the logic die and has a relatively small thermal contribution to the silicon interposer interconnects.

[0079] Constructing the data transmission flow (physical flow): This pipeline is specifically responsible for driving the physical interface (PHY) and the microbumps on the silicon interposer to perform the actual electrical signal switching and data transfer. This part of the operation directly generates Joule heating and is the main source of temperature rise in the silicon interposer.

[0080] Step 132: Adjust the throughput ratio of the address prefetch stream and the data transmission stream based on the load trend prediction results.

[0081] In response to load trend prediction results indicating that the thermal risk is lower than or equal to the preset risk, the address prefetching stream and data transmission stream run synchronously at full speed. When the predicted thermal risk is low, both run synchronously at full speed to pursue maximum bandwidth.

[0082] In response to load trend predictions indicating a higher thermal risk than a preset risk level, the scheduler suppresses the data transmission stream's emission rate while maintaining the address prefetch stream's operation, and pre-calculates and caches metadata for subsequent tasks. When a high surprise factor (high thermal accumulation risk) is predicted, the scheduler proactively suppresses the data transmission stream's emission rate while maintaining the address prefetch stream's high-speed operation, pre-calculating and caching metadata for subsequent tasks. This mechanism ensures that even when physical layer heat dissipation is limited, the logic layer can still preprocess a large number of instructions, and seamless transmission can be initiated instantly after the heat dissipates, avoiding the overall pipeline stagnation caused by traditional frequency reduction.

[0083] Step 133: For continuous read and write requests of the data transmission stream, divide the task corresponding to the continuous read and write request into task blocks to obtain several sub-tasks.

[0084] In some embodiments, a mandatory fine-grained fragmentation strategy is implemented for large-scale continuous read / write requests entering the "data transfer stream" (e.g., continuous writing of 4KB data blocks) to break long-term continuous high-power states. This mainly involves operations such as task segmentation and state saving and restoration. Task chunking is mainly reflected in setting a dynamic "maximum transfer unit threshold". Any continuous burst transfer request exceeding this threshold will be forcibly broken down by the hardware into several tiny "atomic transfer subtasks" within the limits allowed by the DDR protocol. For example, a continuous 16-burst-length long write operation can be broken down into four independent 4-burst-length operations.

[0085] State preservation and restoration are mainly reflected in: assigning an independent context identifier to each decomposed subtask to ensure that even if an interruption occurs during the block execution process or other high-priority instructions are inserted, the data can be accurately pieced together during restoration to ensure data integrity.

[0086] Step 134: Insert a programmable number of idle clock cycles or no-operation instructions between subtasks.

[0087] In some embodiments, a nanosecond-level "micro-sleep" insertion mechanism is introduced between the aforementioned fragmented subtasks to "reshape" the originally sharp rectangular power consumption waveform into a smooth waveform. The "micro-sleep" insertion mechanism includes micro-slot injection and pulse width modulation temperature control operation.

[0088] Microslot injection is mainly manifested in the forced insertion of a programmable number of idle clock cycles or no-operation instructions (NOPs) between two adjacent "atomic transport subtasks" based on the current thermo-electric coupling prediction value.

[0089] Pulse width modulation temperature control is mainly characterized by: During periods of extreme overheating risk, the width of the micro-sleep time slot is increased (i.e., the idle period is extended), and the effective signal switching density per unit time is reduced, thereby lowering the effective value of the average current. During the temperature drop period, the micro-sleep time slots are compressed until they are completely eliminated, restoring the high-speed back-to-back transmission.

[0090] This adjustment is completed on a microsecond timescale, while keeping the physical connection in an "active state" at all times, inserting only tiny gaps on the data bus. Compared to traditional methods of directly shutting down the channel or reducing the clock frequency, this approach avoids the significant latency penalties associated with re-handshaking or re-locking the phase-locked loop (PLL).

[0091] Step 135: When a prefetch request generated by the address prefetch stream attempts to enter the data transmission stream, but the system is in a high-risk state, assess the cost of acquiring the data and decide whether to discard the prefetch request based on the assessment result.

[0092] In some embodiments, an opportunistic recompute and discard strategy can be adopted. For example, to further reduce storage bandwidth pressure during peak periods, a "recompute for bandwidth" mechanism is introduced for some non-critical path data flows (mainly for speculative prefetch data). The "recompute for bandwidth" mechanism includes prefetch data discarding and on-demand retransmission operations: Prefetch data discarding primarily occurs when a prefetch request generated by the "address prefetch stream" attempts to enter the "data transmission stream," but the system is in a high-risk state for overheating. The controller assesses the cost of acquiring this data. If the data can subsequently be recalculated at a lower cost or retrieved again from the low-speed cache, the prefetch request is discarded directly, without consuming valuable silicon interposer physical transmission time slots.

[0093] On-demand retransmission is mainly reflected in the fact that when the data is indeed needed later and the hot state has eased, the prefetch logic is retried. This strategy sacrifices a small amount of power consumption in logic computation in exchange for valuable thermal margin in the physical transmission channel, ensuring that the transmission of core business data is not blocked.

[0094] By decoupling the two currents, the system achieves asynchronous peak reduction for computation and transmission. Through fine-grained segmentation and micro-sleep insertion, the system transforms the "continuous high current" that would otherwise cause instantaneous overheating and shutdown into a series of "safe current pulses" with controllable intervals. This method maximizes the utilization of the physical heat dissipation limit of the silicon interposer without triggering system-level frequency reduction protection, achieving high-efficiency transmission "running on the edge of a cliff".

[0095] In response to a load burst interruption signal, the instruction scheduler forcibly splits continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions. A programmable number of idle clock cycles are inserted between the transmit enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses. For example, memory access bus transactions can be separated into a prefetch stream via the address / command channel of the logic controller and a load transfer stream via the data channel. When a prediction indicating high thermal risk is received, the bus arbitrator intercepts continuous write transactions exceeding the set burst length threshold and forcibly splits them into multiple short burst sub-transactions at the protocol layer. Between sending the data valid signals of adjacent short burst sub-transactions to the physical layer, the hardware scheduler forcibly inserts multiple idle clock cycles defined by the time slot register, thereby shaping the continuous current waveform into discontinuous pulses. If a high thermal risk state exists, but the address / command channel prefetch stream generates a speculative data read request, the bus arbitrator directly discards the prefetch request identifier in the transmit queue according to the configuration policy to release the physical layer occupancy of the data transmission stream.

[0096] The flow scheduling and active power shaping in this step directly affect the underlying protocol of the chip's Advanced Scalable Interface (AXI) bus arbiter. The specific operations are as follows: Burst splitting based on the AXI protocol: When the bus arbiter receives a load burst interrupt signal and the hotspot flag is set to 1, the hardware congestion prevention logic is activated. If a continuous memory write transaction with an extremely large burst length (e.g., AWLEN = 0x0F in the AXI protocol, i.e., 16 consecutive writes) appears in the instruction queue at this time, allowing it directly would result in continuous high-intensity current. The arbiter will forcibly truncate and split it into 4 independent sub-transactions with a burst length of 4 (AWLEN = 0x03) at the protocol layer, and assign them independent transaction IDs (AWIDs) to ensure data integrity in case of out-of-order returns.

[0097] Micro-idle period (NOP) injection waveform shaping: During the aforementioned adjacent short burst sub-transaction transmissions, the state machine intervenes in the AXI bus handshake signal, forcibly suspending and inserting the data into the slot defined by the time slot register before pulling the write data valid signal (WVALID) high. One idle clock cycle (NOP). From the macroscopic current waveform of the physical layer pins, the originally continuous rectangular DC current is "shaped" by the hardware into a discrete high-frequency pulse current with an adjustable duty cycle. This forcibly "squeezes out" nanosecond-level heat dissipation gaps for the microbumps of the silicon interposer without breaking the AXI / DDR handshake timing protocol.

[0098] Hardware Drop for Speculative Prefetch Streams: For speculative prefetch requests generated by the Address / Command Channel (AR / AW), if the data transmission stream's watermark is full and the hot risk is high, the bus arbiter will directly remove the identifier of the prefetch request from the transmit queue (perform a Drop action), releasing the physical layer bus occupancy. After the hot alarm is cleared, the upper-layer cache miss logic will re-initiate on-demand refetching.

[0099] At the specific bus scheduling level, the transmission command segmentation and idle cycle insertion mechanism is as follows: When a high risk of overheating is predicted, if there is a continuous AXI write transaction with a burst length of 16 (i.e., AWLEN = 0xF) in the instruction scheduling queue, direct execution will result in continuous high-intensity current. In this case, the flow scheduling logic truncates and splits it into four independent 4-Burst write transactions.

[0100] During reassembly transmission, the state machine forcibly inserts an idle state (NOP instruction) of N clock cycles, set by the micro-sleep register, between the WVALID (write valid) signals of two adjacent 4-Burst sub-transactions. This operation reshapes the originally continuous rectangular high-current waveform into high-frequency discrete current pulses with adjustable duty cycles on the physical layer pins. Without disrupting the DDR protocol handshake timing, nanosecond-level heat dissipation gaps are provided for the silicon interposer and microbumps, achieving active electro-thermal waveform shaping.

[0101] Step 14: Maximize the data hit probability in the cache management unit of the on-chip static random access memory of the storage controller chip to reduce the access frequency to the external physical interface of the silicon interposer.

[0102] This step is implemented in the on-chip static random access memory (SRAM) cache management unit of the memory controller. Its aim is to directly reduce the access frequency to the external physical interface (PHY) of the silicon interposer by maximizing the hit probability of on-chip data, thereby reducing signal switching power consumption and heat buildup on the silicon interposer interconnects from the source. This step abandons the rigid logic of traditional fixed rules (such as the least recently used algorithm) and introduces a dynamic data location management mechanism with "flexible step size".

[0103] In some embodiments, see Figure 3 Step 14 can be the following process: Step 141: When a read / write request from the logic computing die arrives at the storage controller chip, if the requested data block already exists in the cache, the storage controller chip reads the current promotion step value and moves the data block forward from the current logical position by the distance defined by the promotion step value.

[0104] The promotion step size represents the distance a data block moves towards a higher priority end in the cache queue when it is accessed again in the cache; the promotion step size is negatively correlated with the cache hit rate of the data block.

[0105] In some embodiments, a dedicated read / write register is allocated in the register file of the cache controller to store a "promotion step value". The value of the "promotion step value" represents the distance that a data block moves to the higher priority end of the cache queue logical position when it is accessed (hit) again in the cache.

[0106] The initialization process is as follows: when the system is powered on, the "promotion step size value" is set to the middle value of the total number of cached lines or the preset default value.

[0107] The logical mapping relationship is as follows: The cache queue does not physically move data, but maintains the "logical popularity order" of data through linked list pointers or matrix indices. The head of the queue represents the highest priority (least likely to be replaced), and the tail of the queue represents the lowest priority (about to be replaced).

[0108] Based on this, a hardware feedback loop is constructed to dynamically adjust control parameters according to the real-time performance of the cache and the thermal risks predicted by previous steps. For example, negative feedback adjustment of the step size parameter: The hit feedback is mainly reflected in the following: whenever a cache hit occurs, the hardware logic will slightly decrease the "promotion step size" (e.g., decrease by 1, until the minimum threshold is reached). The logic is based on the fact that if the current hit rate is acceptable, it means that the hot data has been relatively stable, and the change should be reduced to lock the "working set".

[0109] The main feedback for a cache miss is that whenever a cache miss occurs, the hardware logic slightly increases the "promotion step size". The logic is that a miss means that the current cache content cannot meet the demand (a working set switch may have occurred), and the step size needs to be increased to allow new data to "climb" to the high-priority area more quickly, so as to accelerate the adaptation to the new load.

[0110] Step 142: If the requested data needs to be read from external DDR, the new data block read back is inserted into the logical tail of the cache queue.

[0111] In some embodiments, when a read / write request from a logic computing die arrives at the storage controller, the following traffic splitting logic is executed: operations such as "elastic jump" when a cache hit occurs and "end insertion" when a cache miss occurs.

[0112] The "elastic jump" during a cache hit is mainly manifested in: If the requested data block already exists in the cache, the controller reads the current "promotion step size" and moves the data block directly forward from its current logical position by the distance defined by that step size.

[0113] Comparison: Traditional methods typically move directly to the front of the queue (step size = current position) or only move forward one position (step size = 1). This method allows data blocks to "drop" into the middle of the queue based on the step size parameter.

[0114] Technical objective: To prevent occasionally accessed "cold data" from taking the head of the queue due to a single random access (cache pollution), while also ensuring that truly "hot data" can climb to the safe zone at a reasonable rate and avoid being prematurely eliminated.

[0115] The "end-of-line insertion" during a cache miss is mainly manifested in: If the requested data needs to be read from external DDR (which consumes silicon interposer power), the new data block read back is inserted into the logical tail of the cache queue (i.e., the eviction edge), not the head. This ensures that new data must be verified by subsequent accesses (i.e., hit again and skip) to prove its long-term retention value.

[0116] This application also provides dynamic scaling of the effective cache capacity, such as by introducing a "shadow tag monitoring" mechanism. In addition to the physical cache, a set of shadow queues that only store metadata (not actual data) are maintained to simulate hit scenarios under larger or smaller capacities.

[0117] Capacity expansion is mainly reflected in the following: if the theoretical hit rate of the shadow queue (representing a larger capacity) is detected to be significantly higher than that of the current physical cache, and the silicon interposer is in a high-temperature risk state, the controller will dynamically borrow nearby free SRAM blocks or compressed data to expand the effective cache capacity.

[0118] Capacity reduction is mainly reflected in the following: if it is found that increasing the capacity does not significantly improve the hit rate (the data flow has traversal characteristics and no repeated access characteristics), the power gating of part of the SRAM array is actively turned off and the logic queue length is reduced to save the static leakage current power consumption of the SRAM itself.

[0119] Through this mechanism, the storage controller can automatically find a balance between "aggressive replacement" and "conservative retention" based on the locality of the load. Experiments show that this mechanism can effectively filter the impact of one-time scan traffic on the cache, significantly improving the cache hit rate under mixed loads. For the silicon interposer, each improvement in cache hit rate means reducing one high-energy physical transmission through the microbumps and redistribution layers, thereby reducing the heat dissipation of the physical layer directly from the data source without degrading system bus performance.

[0120] The on-chip static random access memory (SRAM) cache management unit includes a dynamic step size control register. When a cache hit occurs, the cache controller reads the value of the dynamic step size control register and modifies the cache line priority line pointer of the hit data block by the corresponding step size value shift towards higher priority, instead of setting it to the top. When a cache miss occurs, the priority pointer of the newly read data block is initialized to the lowest priority, and the value in the dynamic step size control register is slightly increased through a hardware feedback loop.

[0121] In this embodiment, the cache management unit (CMU) of the on-chip static random access memory (SRAM) does not use the traditional rigid Least Recently Used (LRU) method to move physical data blocks, but instead uses the logical shift of the hardware tag index pointer, as follows: The CMU is internally configured with a Dynamic Step Register.

[0122] Logical transition upon cache hit: When the processor initiates a read / write request and a cache hit occurs, the cache controller does not directly set the priority pointer of the data block to the most recently used bit (Most Recently Used bit) as in traditional LRU. Instead, it reads the value of the current dynamic step size control register. Subsequently, the control logic modifies the priority pointer of the hit data block forward. An offset.

[0123] Hardware feedback during a cache miss: When a cache miss occurs and triggers an external DDR access, the priority pointer of the newly fetched data block is initialized to the lowest priority end (tail of the queue, most easily replaced area). Simultaneously, this miss event triggers an internal hardware feedback loop, causing the value in the dynamic step control register to... Automatically increment by 1.

[0124] Through the aforementioned pure hardware pointer operations and adaptive step size feedback, the system can automatically prevent "occasional cold data" from polluting the high-priority areas of the cache under mixed loads, significantly improving the resident hit rate of the core working set, thereby directly reducing the number of physical activations of the external PHY interface of the silicon interposer. Step 15: Calculate and execute the corresponding hardware adjustment instructions based on the load trend prediction results and temperature data; the hardware adjustment instructions are used to eliminate the oscillation effect caused by heat conduction.

[0125] This step, as the final execution stage of the entire control system, is responsible for combining the load prediction signal generated in the previous steps with the current physical temperature feedback to calculate and execute specific hardware adjustment instructions. This step abandons the traditional single-dimensional dynamic voltage-frequency adjustment (DVFS) mechanism and adopts a closed-loop control strategy that integrates anti-hysteresis algorithms and multi-variable collaborative adjustment to eliminate the oscillation effect caused by heat conduction within a microsecond time scale.

[0126] In some embodiments, see Figure 4 Step 15 can be the following process: Step 151: Generate a virtual synthetic temperature signal based on the temperature data and the weighted rate of temperature change.

[0127] The weight of the rate of temperature change is determined by the positive phase angle.

[0128] In some embodiments, a model-free phase-lead computational logic is deployed in the thermal management unit of the controller to process raw temperature sensor data from the silicon interposer and logic die. The computational logic mainly includes operations such as temperature change rate extraction, lead signal synthesis, and phase compensation.

[0129] The extraction of temperature change rate is mainly reflected in the following: the system reads the values ​​of the on-chip distributed temperature sensor at a fixed high-frequency sampling rate, and extracts the first derivative (rate of change) of the current temperature in real time through differential calculation.

[0130] The advanced signal synthesis mainly involves linearly superimposing the current absolute temperature value with a weighted rate of temperature change to generate a "virtual synthetic temperature signal." When the temperature has not yet reached the alarm threshold but is rising at an extremely rapid rate, this synthetic signal will be significantly higher than the actual physical temperature, thus triggering suppression actions ahead of time. When the temperature is high but begins to show a downward inflection point, this synthetic signal will be lower than the actual physical temperature, thus releasing suppression ahead of time and allowing performance recovery.

[0131] Phase compensation is mainly reflected in: by adjusting the weighting coefficient of the rate of change, a positive phase angle is introduced into the frequency response of the control loop, thereby offsetting the inherent phase lag in the physical heat conduction path and ensuring that the control signal and the moment of heat source generation are synchronized on the time axis.

[0132] Step 152: When the virtual synthetic temperature signal indicates that power consumption needs to be adjusted, execute the diagonal scaling strategy based on the preset two-dimensional scaling plane.

[0133] In the coordinate system of the two-dimensional scalable plane, the vertical axis represents the intensity dimension, the horizontal axis represents the parallelism dimension, and the coordinate system has several equivalent heat dissipation curves and equivalent bandwidth curves.

[0134] In some embodiments, a two-dimensional scaling plane of "voltage frequency - channel bit width" is established. A two-dimensional resource configuration coordinate system is preset in the lookup table of the power management unit to describe all feasible operating states of the controller: Vertical axis definition (intensity dimension): corresponds to the voltage and clock frequency combination of the physical layer interface (PHY) and core logic of the memory controller. The more refined this dimension is, the smoother the power consumption control.

[0135] The horizontal axis (parallelism dimension) is defined as the number of active data channels (Channel Count) or the effective data bit width within a single channel. This dimension represents the degree to which physical connections are enabled.

[0136] Equivalent energy efficiency surface: In this coordinate system, based on the impedance model established in step 11, several "equivalent heat dissipation curves" and "equivalent bandwidth curves" are pre-calibrated. The intersections of these curves constitute the set of optimal operating points of the system under different thermal budgets.

[0137] In some embodiments, when it is predicted that thermal accumulation is about to exceed the limit, an optimal diagonal path from the current operating point toward the origin is calculated.

[0138] In some embodiments, when performance needs to be restored after the thermal risk is eliminated, the device moves in the opposite direction along the diagonal; during the diagonal movement, a fine-tuning algorithm based on local search is introduced for compensation.

[0139] In some embodiments, this application performs diagonal joint adjustment along the optimal gradient. When the "virtual synthetic temperature signal" indicates a need to adjust power consumption, the controller no longer performs rigid adjustment in a single dimension, but instead executes a "diagonal scaling" strategy: The degradation path is mainly reflected in the following: when it is predicted that heat buildup is about to exceed the limit, the controller calculates an optimal diagonal path from the current operating point to the origin. For example, it not only reduces the frequency (which may lead to a sharp increase in latency), but also slightly reduces the frequency and temporarily shuts down some non-critical data channels (or enters a low-power standby mode). By taking a two-pronged approach, the total power consumption is rapidly reduced while maintaining optimal energy efficiency per unit.

[0140] The upgrade path is mainly reflected in the following: when the thermal risk is eliminated and performance needs to be restored, the controller moves in the opposite direction diagonally. For example, it simultaneously increases the voltage and reactivates the hibernation channel.

[0141] The anti-oscillation logic is mainly reflected in the introduction of a fine-tuning algorithm based on local search during diagonal movement. If it is found that an adjustment in one dimension will cause unacceptable latency (such as SLA violation), the algorithm will automatically shift to another dimension for compensation, ensuring a smooth performance transition and avoiding step-like performance precipitates.

[0142] Step 153: Calculate the tail risk value of the temperature distribution over a period of time in real time, and dynamically shrink the feasible domain boundary of the two-dimensional stretching plane based on the tail risk value.

[0143] In some embodiments, this application introduces boundary locking protection based on Conditional Value at Risk (CVaR). To prevent algorithm failure under extreme conditions, a layer of rule-based hard protection logic is superimposed on top of the aforementioned closed-loop control. This mainly includes tail risk assessment and dynamic saturation boundary operations.

[0144] Tail risk assessment is mainly reflected in: real-time calculation of the tail risk value of temperature distribution over a period of time (i.e., the probability of thermal runaway in the worst case).

[0145] The dynamic saturation boundary is mainly reflected in the dynamic shrinking of the feasible domain boundary of the two-dimensional stretching plane based on the risk value. Once the system state touches this dynamic boundary, regardless of how the phase lead logic is calculated, a "safety clamping" operation based on hardware rules is forcibly executed, that is, the maximum allowable voltage level and number of channels are unconditionally locked to ensure physical safety first, until the risk value falls back.

[0146] The calculation and execution of hardware adjustment instructions are performed by the power and clock management state machine on the memory controller chip. The power and clock management state machine receives readings from distributed on-chip physical temperature sensors and extracts the first derivative of the temperature using a hardware differentiating circuit. The two are then weighted and summed to form a pre-warning control word. The power and clock management state machine has a pre-built mapping table. The output of the mapping table is a joint control word containing voltage / frequency adjustment fields and channel power gating fields to perform diagonal adjustment based on a two-dimensional plane. After the power and clock management state machine issues the joint control word, the internal performance monitoring unit monitors the backvoltage signal of the bus interface. If the backvoltage signal ratio exceeds a preset delay violation threshold, the power and clock management state machine triggers a backoff compensation mechanism, modifying the voltage / frequency adjustment fields to adjust the operating frequency by one level.

[0147] To completely eliminate control oscillations caused by physical heat conduction delays, the final execution stage in this embodiment is handled by the on-chip power and clock management state machine (PMU State Machine) for closed-loop control. Phase lead compensation signal generation: The PMU's built-in hardware differentiating circuit performs high-frequency sampling on the digital signals acquired by the distributed temperature sensors and extracts the first derivative. The ALU sums the current absolute temperature value with the weighted derivative to generate an advance warning control word. When the temperature rises sharply but has not yet reached the threshold, the advance warning control word will trigger a state machine transition prematurely due to the large derivative component.

[0148] Two-dimensional diagonal degradation state transition: The PMU's configuration word register has two independent control fields: the voltage-frequency regulation field (VF Field, controlling the PLL and LDO) and the channel power gating field (Power Gating Field, controlling the PHY channel switching). When the state machine receives an advance warning, it does not simply pull down the frequency, but instead looks up a table and outputs a combined control word. For example, while lowering the frequency level by one step (5%), it sends ClockGating and Power Gating signals to some idle PHY channels to put them into sleep mode. This combined contraction along the diagonal of the "frequency-channel number" two-dimensional coordinate system maximizes power consumption reduction while minimizing the impact on latency.

[0149] Hardware fine-tuning based on bus backpressure (local search): After the state machine issues a joint control word, the chip's internal performance monitoring unit (PMU Counters) continuously monitors the backpressure signal on the AXI data bus (such as the percentage of cycles during which the AWREADY or WREADY signal is pulled low by the downstream slave device) over the following dozens of clock cycles. If this duty cycle exceeds a preset delay violation threshold (indicating excessive degradation leading to severe system congestion), the state machine will trigger a hardware interrupt for rollback compensation, modifying the voltage frequency adjustment field to revert to a half-step or one-step operating frequency. This achieves dynamic optimization and anti-oscillation control at the hardware level without CPU software intervention.

[0150] The technical effects of this application are as follows: 1. Transforming "sawtooth" into "smooth" operation, eliminating thermal oscillations: By using phase lead control to offset physical lag and micro-time-slice shaping technology, this invention enables the memory controller to adjust power consumption at high frequencies with extremely small amplitudes when approaching the thermal threshold, rather than drastically switching between full speed and throttling. Actual measurements show that the fluctuation amplitude of the core temperature curve is reduced by more than 80%, eliminating low-frequency thermal oscillations.

[0151] 2. Counterintuitive throughput improvement in thermally constrained scenarios: Although this invention introduces seemingly slowing-down methods such as "micro-sleep" and "task decomposition", the average effective bandwidth of the system during long-term operation is actually increased by 25% to 30% because it eliminates the forced large frequency reduction time caused by overheating.

[0152] 3. Design margin release: Due to the accurate hot spot prediction based on the analytical pixel model, chip designers do not need to reserve excessive heat dissipation design margin to deal with unknown hot spots, allowing for the integration of higher density memory interface wiring within the same package volume.

[0153] Example 1: Large-scale AI model parameter loading scenario in a high-performance computing center.

[0154] 1. Scenario Description: In this scenario, the storage controller needs to continuously move massive amounts of data (such as weight matrices of tens of gigabytes) from DDR memory to the logic computing unit. At this time, all data channels are under full load for a long period of time, and the current density on the silicon interposer is extremely high and lasts for a long time, which can easily trigger heat accumulation, making it a typical "thermally confined" operating condition.

[0155] 2. The collaborative execution process is as follows: Step 1 (Establishing Physical Constraints): During controller initialization, a pre-stored parsed pixel mapping model is invoked. The model calculates that when the 1024-bit width is flipped at full speed, the microbump array in the central region of the silicon interposer will form a high heat flux density area. Based on this, the controller generates a "static thermal risk map," marking the areas with the slowest physical heat dissipation.

[0156] Step Two (Trend Locking): The load prediction unit detects a continuous sequential read command stream. Due to the extremely stable data stream characteristics and minimal statistical deviation, the calculated "surprise" value remains consistently low. The system automatically enters a "low-frequency, long-step" prediction mode, determining that the system will be in a high-power state for the next few milliseconds.

[0157] Step 3 (Active Shaping): Based on the "continuous high load" prediction in Step 2, the scheduler activates a fine-grained time-slice shaping strategy. Instead of attempting to change the instruction order (because it's a sequential read), it forcibly breaks down the continuous data transmission stream into several tiny transmission chunks. After each chunk is transmitted, a nanosecond-level "micro-sleep" instruction is forcibly inserted based on the thermal risk map from Step 1. This changes the current waveform from "continuous DC" to "high-frequency trapezoidal pulses," providing a very brief microscopic heat dissipation gap for the silicon interposer material.

[0158] Step 4 (Bypassing and Load Reduction): Due to the sequential scan, the cache hit rate is extremely low. The adaptive cache replacement logic detects a surge in "miss feedback" and automatically increases the "jump step" to accelerate the removal of old data. It also configures the SRAM in streaming buffer mode, which is only used to smooth the data rate and is not retained for long periods to avoid unnecessary cache lookup power consumption.

[0159] Step 5 (Steady-state control): The phase lead compensation logic detects that although the absolute temperature is rising slowly, the rate of temperature rise (derivative) is suppressed due to the micro-sleep intervention in Step 3. The controller performs multidimensional diagonal scaling: instead of reducing the clock frequency (to maintain the burst speed of a single transmission), it slightly reduces the drive voltage of the physical layer interface and relies on the micro-sleep in Step 3 to balance the total power consumption.

[0160] 3. The resulting technical effect is that, through the combination of "micro-sleep" in step three and "voltage fine-tuning" in step five, the system clamps the core temperature below a safe threshold without triggering the forced frequency reduction threshold. This avoids the sawtooth oscillation of "full speed operation -> overheating and frequency reduction -> speed halving -> temperature drop -> full speed recovery" in traditional solutions, achieving continuous and smooth extreme bandwidth output.

[0161] Example 2: In-memory database query scenario of a high-frequency trading system.

[0162] 1. Scenario Characteristics Description: This scenario is characterized by extremely uneven load distribution. It remains mostly silent, but experiences random bursts of small data packet read / write operations (burst traffic) within very short periods. This pulsed heating causes localized hotspots to form before the temperature sensor can even respond, leading to misjudgments due to heat diffusion.

[0163] 2. The collaborative execution process is as follows: Step 1 (Hotspot Location): The pixel mapping model identifies that only a portion of DDR channels (corresponding to specific memory address ranges) are frequently activated. Real-time model calculations indicate that although the total power consumption is not high, the current density in specific areas is approaching the electromigration limit.

[0164] Step 2 (Transient Capture): A sudden transaction request causes the load feature vector to deviate from the baseline instantaneously, and the "surprise" value spikes. The prediction unit immediately switches to "high-frequency short step" mode to capture the load ramp-up slope with nanosecond-level resolution and sets the "high confidence burst" flag.

[0165] Step 3 (Priority Decoupling): Upon receiving a high-surprise signal, the scheduler performs dual-stream decoupling. It temporarily suspends all non-critical "address prefetch streams" (such as background log processing) and concentrates all logical resources on the "data transmission stream" to ensure that sudden transaction data can be processed instantly. Simultaneously, due to the short duration of the surge, time-slicing is not activated to guarantee minimal latency.

[0166] Step 4 (Hot Data Locking): The adaptive cache replacement logic detects that certain key values ​​are repeatedly accessed (high-frequency trading hotspots). Based on the hit feedback, the "promotion step size" of this data block is dynamically increased, quickly locking it into a high-priority area of ​​SRAM. Subsequent accesses are completed directly on-chip, eliminating the need to flip external I / O interfaces on the silicon interposer and directly cutting off the physical heat source.

[0167] Step 5 (Predictive Suppression): Although the temperature sensor reading has not yet risen, the phase lead compensation logic calculates a large virtual synthetic temperature based on the burst signal from Step 2 and the local hotspot warning from Step 1. The controller immediately performs diagonal scaling: maintaining high frequency and high voltage (ensuring low transaction latency), but temporarily shutting down unaccessed idle channels (Dark Silicon strategy), concentrating all thermal budget on active channels.

[0168] 3. The technical effect of this collaboration is that the combination of the keen detection in step two and the cache locking in step four eliminates most external access requests before the system's physical temperature actually rises. The precise resource allocation in step five ensures low latency for critical business operations during periods of instability, while avoiding system-level false alarms and performance fluctuations caused by the spread of local hotspots.

[0169] Example 3: Complex multitasking scenarios of mobile terminal SoC.

[0170] 1. Scenario Characteristics: Users are simultaneously playing large-scale 3D games (high bandwidth) and updating background applications (low-priority writes). The load exhibits obvious periodic fluctuations, accompanied by random disturbances. This is the scenario most likely to induce "thermal-performance oscillations" due to limited heat dissipation and complex load.

[0171] 2. The collaborative execution process is as follows: Step 1 (Global Modeling): Analyze the pixel mapping model to calculate in real time the composite interference impedance generated by game texture loading (reading) and background installation (writing) on ​​the silicon interposer, and predict the thermal superposition area that may be generated when the two occur simultaneously.

[0172] Step Two (Period Recognition): The prediction unit identifies the periodic characteristics of GPU rendering requests (e.g., one frame every 16ms). During the frame rendering intervals, the "surprise" level periodically decreases. Based on this, the predictor generates a sinusoidal load expectation curve.

[0173] Step 3 (Valley Filling and Shaping): The scheduler uses predicted idle gaps (frame intervals) to perform fine-grained time-slice shaping. It forcibly breaks up background application write tasks and fills them into low-load gaps in GPU rendering (valley filling), while pausing background writes during peak rendering periods (peak clipping), thereby smoothing out power fluctuations on the timeline.

[0174] Step 4 (Capacity Scaling): Given the large amount of texture data in game scenes, the "shadow tag monitoring" mechanism discovered that expanding the cache significantly improves the hit rate. The controller dynamically borrows some unused SRAM blocks to expand the cache capacity, reducing repeated reads from DDR.

[0175] Step 5 (Inverse Cancellation): The control signal calculated by the phase lead compensation logic is exactly opposite in phase to the physical temperature change. When the game scene is complex and the temperature is about to rise, the controller makes a slight adjustment in advance along the diagonal direction: slightly reducing the bit width of the background channel while maintaining the frequency of the GPU channel. When the scene is simplified and the temperature is about to drop, the bit width of the background channel is restored in advance.

[0176] 3. The resulting technical effects are as follows: Step 3, "peak shaving and valley filling," smooths the load at the source, while Step 5, "phase cancellation," cancels thermal hysteresis at the control end. The combination of these two processes results in a smooth straight line in the SoC's core temperature curve, rather than a sine wave that fluctuates wildly with the game's frame rate, even under conditions of limited heat dissipation in mobile devices. This completely eliminates frame drops (janks) caused by temperature fluctuations and achieves a dynamic balance between performance and power consumption.

[0177] Example Effect Testing and Data Analysis: To verify the actual effect of the dynamic power shaping method described in this application, a memory controller SoC model containing this control logic was built in an RTL (Register Transfer Level) simulation environment, and a standard DDR4 behavioral timing model was mounted. The thermal resistance parameter of the silicon interposer mesh was set to 0.5 K / mW, the initial ambient temperature was 45℃, and the forced frequency reduction (Throttling) protection threshold was 85℃.

[0178] Test stimulus: Inject a typical burst-intensive write load (Burst Write, lasting 50μs, with the system load duty cycle jumping from 10% to 95%) into the controller.

[0179] Control group (traditional sensor-based fixed-threshold DVFS): Simulation waveforms show that approximately 20μs after the sudden load occurred, the physical temperature sensor detected 85℃. Subsequently, the system triggered a hard frequency reduction, with the clock speed plummeting from 1600MHz to 800MHz. This resulted in severe congestion on the AXI bus for the next 30μs, with the effective bandwidth utilization dropping to 45%. Frequency recovery after the temperature dropped to 70℃ triggered another temperature rise. Throughout the test cycle, the temperature curve exhibited severe sawtooth oscillations between 70℃ and 87℃, and triggered three ground bounce noise exceeding-limit alarms.

[0180] Experimental group (using the method of this application): At 2μs after the burst load occurs, the 'dual load state baseline model' of this application calculates the deviation S exceeding the limit and triggers an early warning 18μs in advance. The instruction scheduler immediately initiates fine-grained time-slice segmentation, inserting 3 clock cycles of NOP between every 8 Burst transmissions. In the subsequent multidimensional diagonal adjustment, the state machine only reduces the voltage by 5% and shuts down 2 slave channels that are in a quiescent state.

[0181] Test Results: Throughout the 50μs burst period, the highest temperature in the experimental group was smoothly and stably clamped at 82℃, never touching the forced frequency reduction threshold of 85℃. No low-frequency oscillations occurred in the system, and the average effective bus bandwidth utilization remained stable at 78%. Compared to the control group, the average effective throughput increased by approximately 33% (78% vs 45%), validating the effectiveness of the early intervention and proactive shaping mechanism proposed in this application.

[0182] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0183] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0184] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for dynamic power consumption shaping of a memory controller chip, characterized in that, The method includes: Obtain the channel enable signal vector of the current physical layer interface of the memory controller chip; input the enable signal vector into the preset impedance lookup table configured on the chip, and extract the equivalent admittance matrix corresponding to the current active channel combination; calculate the instantaneous power density characteristic value of the silicon interposer two-dimensional mesh array by combining the on-chip multiply-add unit with the current operating voltage; The flow monitoring counter in the storage controller chip counts the arrival rate of memory read and write instructions according to the set long clock window and short clock window respectively, to obtain the long-term moving average reference value and the short-term transient characteristic value; the statistical deviation between the short-term transient characteristic value and the long-term moving average reference value is calculated by the on-chip comparison logic; when the statistical deviation is greater than the preset hardware threshold register value, a high-confidence load burst interrupt signal is triggered. In response to the load burst interrupt signal, the instruction scheduler forcibly splits the continuous memory access bus transactions that exceed the preset burst length threshold into several sub-transactions, and inserts a programmable number of clock idle cycles between the transmit enable signals of adjacent sub-transactions to shape the continuous current pulses into discontinuous pulses. In the cache management unit of the on-chip static random access memory of the storage controller chip, the data hit probability is maximized to reduce the access frequency to the external physical interface of the silicon interposer. Based on the load trend prediction results and temperature data, corresponding hardware adjustment instructions are calculated and executed; the hardware adjustment instructions are used to eliminate the oscillation effect caused by heat conduction.

2. The method according to claim 1, characterized in that, The equivalent admittance matrix of the silicon interposer is generated jointly by an on-chip stored static configuration matrix and a real-time acquired bus enable signal; wherein: The static configuration matrix is ​​pre-programmed in the non-volatile memory of the memory controller chip. The static configuration matrix records the primary / secondary impedance parameters of the microstrip lines, vias and microbumps on the corresponding physical layout. The physical layer interface status monitoring logic within the storage controller chip extracts the current DDR channel activation mask in real time as the real-time load input vector. The storage controller chip is equipped with a dedicated multiply-accumulate coprocessor. The multiply-accumulate coprocessor performs a hardware lookup table-based Schur complement approximation operation on the static configuration matrix based on the real-time load input vector, and outputs an equivalent admittance matrix representing the equivalent transmission impedance of each node in the silicon interposer plane.

3. The method according to claim 2, characterized in that, The hotspot prediction arithmetic logic unit of the storage controller chip reads the equivalent admittance matrix and, in conjunction with the current system power supply voltage, calculates the instantaneous power density characteristic value of the corresponding node through the hardware exponentiation unit, thereby reconstructing the flag bit of the power density distribution map in the internal register.

4. The method according to claim 1, characterized in that, The flow monitoring counter within the storage controller chip counts the arrival rate of memory read / write commands according to a set long clock window and a short clock window, respectively, to obtain a long-term moving average baseline value and a short-term transient characteristic value, including: The arrival rate of memory requests is statistically analyzed using a first hardware counter driven by a long clock cycle, and an exponential moving average is calculated. The output value is used as the long-period moving average benchmark value characterizing steady-state cognition. The arrival rate of memory requests in the current transient state is counted using a second hardware counter driven by a short clock cycle, and its output value is used as the short-cycle transient characteristic value. The calculation of the statistical deviation between the short-period transient characteristic value and the long-period moving average benchmark value through on-chip comparison logic includes: The statistical deviation is obtained by calculating the difference between the short-period transient characteristic value and the long-period moving average benchmark value using the on-chip comparison logic.

5. The method according to claim 4, characterized in that, The memory controller chip is equipped with a prediction frequency control register at its front end. When the statistical deviation output by the comparison logic circuit is less than or equal to the set value of the hardware threshold register, a low-frequency configuration word is written to the prediction frequency control register to reduce the sampling clock frequency of the second hardware counter. When the statistical deviation is greater than the value of the hardware threshold register, a hardware interrupt signal is generated, and a high-frequency configuration word is written to the prediction frequency control register, forcing the system to output the load burst prediction flag bit in real time with the shortest time step.

6. The method according to claim 1, characterized in that, The step of forcibly splitting continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions via an instruction scheduler, and inserting a programmable number of clock idle cycles between the transmit enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses, includes: Separate memory access bus transactions into a prefetch stream via the address / command channel of the logic controller and a payload transfer stream via the data channel; When a prediction result representing a high risk of heat is received, the bus arbiter intercepts consecutive write transactions whose length exceeds the set burst length threshold and forcibly splits them into multiple short burst sub-transactions at the protocol layer. Between sending valid data signals for adjacent short burst subtransactions to the physical layer, the hardware scheduler forcibly inserts multiple idle clock cycles defined by the time slot register, thereby shaping the continuous current waveform into discontinuous pulses.

7. The method according to claim 6, characterized in that, If the address / command channel prefetch stream generates a speculative data read request while the channel is in a high-risk state, the bus arbiter will directly discard the identifier of the prefetch request in the transmit queue according to the configuration policy, so as to release the physical layer occupancy of the data transmission stream.

8. The method according to claim 1, characterized in that, The cache management unit of the on-chip static random access memory includes a dynamic step size control register. Maximizing the data hit probability in the cache management unit of the on-chip static random access memory of the memory controller chip includes: When a cache hit occurs, the cache controller reads the value of the dynamic step size control register and modifies the corresponding step size value of the cache line priority line pointer of the hit data block by shifting it towards a higher priority direction, instead of setting it to the top directly; When a cache miss occurs, the priority pointer of the newly read data block is initialized to the lowest priority, and the value in the dynamic step control register is slightly increased through a hardware feedback loop.

9. The method according to claim 1, characterized in that, The calculation and execution of hardware adjustment instructions are performed by the power and clock management state machine on the memory controller chip: The power and clock management state machine receives readings from distributed on-chip physical temperature sensors, extracts the first derivative of the temperature through a hardware differentiating circuit, and weights and superimposes the two to form an advance warning control word. The power and clock management state machine has a pre-set mapping table. The output of the mapping table is a joint control word containing a voltage frequency adjustment field and a channel power gating field to perform diagonal adjustment based on a two-dimensional plane.

10. The method according to claim 9, characterized in that, After the power and clock management state machine issues the joint control word, the internal performance monitoring unit monitors the back pressure signal of the bus interface; if the back pressure signal ratio exceeds the preset delay violation threshold, the power and clock management state machine triggers a backoff compensation mechanism to modify the voltage frequency adjustment field to adjust the operating frequency by one level.

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