Three-dimensional stacked on-chip system power supply structure voltage adjustment method and apparatus

Abstract

Embodiments of the present disclosure disclose a three-dimensional stacked on-chip system power supply structure voltage adjustment method and device. A specific embodiment of the method comprises: integrating a deep trench capacitor array, a through-silicon via and a plurality of voltage pads in a wafer-level silicon interposer; controlling the wafer-level silicon interposer to transmit an input preset high-voltage power supply to a power supply reconstruction layer; according to a programmable voltage adjustment module chip in the power supply reconstruction layer, supplying power to a functional core particle layer, and integrating the functional core particle layer to the front of the wafer-level silicon interposer; in response to the functional core particle layer sending a data signal to the outside, monitoring the power consumption change information of the functional core particle layer in real time, and feeding back the power consumption change information to the power supply reconstruction layer; based on the power consumption change information, dynamically adjusting the output voltage of the programmable voltage adjustment module chip of the power supply reconstruction layer. The embodiment improves power supply noise and decoupling, improves power supply capacity, and enhances system flexibility.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of system-on-a-chip (SoC) technology, and more specifically to a voltage regulation method and apparatus for a SoC power supply structure based on three-dimensional stacking. Background Technology

[0002] In existing technologies, System on Wafer (SOB) employs a vertical power supply method, and its structure is as follows: Figure 1 As shown. Figure 1 This diagram illustrates a prior art on-chip system power supply structure, including the following components: Figure 1As shown, the wafer-level silicon interposer 101 serves as the core carrier, with multiple functional chips 104, such as computing chips and storage chips, mounted on its back side 102 via microbumps 103. The wafer-level silicon interposer integrates deep trench capacitors 105 and through-silicon vias 106. The deep trench capacitors provide local decoupling for stable power supply; the through-silicon vias (TSVs) enable vertical electrical connections, transmitting power from the back side to the front side. The power supply (Printed Circuit Board, PCB) module 109 is located on the front side 107 of the wafer-level silicon interposer and is connected to the interposer via C4 pads 108. The power supply PCB module has a multi-layer structure, including a voltage regulation module (VRM) circuit 110 and a capacitor layer 111. The Voltage Regulator Module (VRM) is responsible for converting a large external voltage (e.g., 12V) with a small current into a small voltage (e.g., 1V) with a large current to meet the power supply requirements of the functional chips. The capacitor layer provides remote decoupling to suppress noise coupling in the power supply link. There are two common methods for connecting the power supply PCB module to the back of the wafer-level silicon interposer: Soft connection: using elastic elements such as spring pins to achieve electrical contact through pressure. This method requires the power supply PCB to have sufficient mechanical strength to withstand pressure and ensure reliable crimping. Hard connection: directly fixing the power supply PCB to the back of the interposer by soldering (e.g., C4 soldering). This method requires high soldering precision, and the C4 pads cannot be too dense to avoid soldering defects. Existing technology relies on deep trench capacitors on the wafer-level silicon interposer for decoupling, but due to the limited DTC density of deep trench capacitors, it cannot completely solve the power supply noise problem for high-power systems. Furthermore, the power supply PCB needs to integrate the VRM and decoupling capacitors, resulting in a complex structure and requiring a multi-layer board design. In general, there are four main issues: 1. Connection problems caused by wafer warpage: Warpage is unavoidable during the manufacturing process of wafer-level silicon interposers. For soft connections, each spring pin requires a certain pressure to ensure contact. When there are many C4 pads, the power supply PCB must withstand greater concentrated pressure. However, due to the multi-layer structure of the power supply PCB, its mechanical strength is limited, making it difficult to balance pressure resistance and electrical performance (such as impedance control). For hard connections, warpage makes soldering alignment difficult, requiring that the C4 pad spacing not be too small (usually greater than 100μm), and that the power supply PCB not be too large or too heavy, otherwise the soldering equipment cannot accurately grasp and position it. These limitations restrict the number of C4 pads, thereby reducing the power supply current carrying capacity. 2. Insufficient power supply capacity: Due to the small number of C4 pads, the current carrying capacity of the power supply PCB is limited, which cannot meet the needs of high-power chips (such as high-performance computing chips). At the same time, the size and weight limitations of the power supply PCB reduce the number of VRM components (such as inductors and capacitors), further limiting voltage conversion efficiency and output current.3. Limited decoupling effect: While deep trench capacitors provide local decoupling, their low density results in insufficient high-frequency noise suppression. Although capacitor layers on the power supply PCB provide far-end decoupling, their equivalent series inductance is relatively large due to the connection method, thus reducing the decoupling effect. 4. Complex manufacturing process: Back-side processes (such as connecting the power supply PCB) are affected by warpage, requiring high-precision equipment, increasing manufacturing costs and yield risks. These drawbacks stem from the inherent contradiction between wafer warpage and vertical power supply structures, preventing the power supply PCB from achieving high-performance power supply within a limited space. Summary of the Invention

[0003] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0004] Some embodiments of this disclosure propose a voltage regulation method and apparatus for a system-on-a-chip power supply structure based on three-dimensional stacking, in order to solve the technical problems mentioned in the background section above.

[0005] In a first aspect, some embodiments of this disclosure provide a voltage regulation method for a system-on-a-chip power supply structure based on three-dimensional stacking. The method includes: integrating a deep trench capacitor array, through-silicon vias (TSVs), and multiple voltage pads in a wafer-level silicon interposer, wherein the voltage pads are used to receive signals from a preset high-voltage power supply; controlling the wafer-level silicon interposer to transmit the input preset high-voltage power supply to a power supply reconfiguration layer, wherein the power supply reconfiguration layer includes multiple programmable voltage regulation module chips and is interconnected through a redistribution layer to form a power supply network, and the wafer-level silicon interposer layer and the power supply reconfiguration layer are connected via a three-dimensional stacking layer. The circuit is connected to the wafer via circular bonding; power is supplied to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer, and the functional chip layer is integrated onto the front side of the wafer-level silicon interposer, wherein the functional chip layer is electrically connected to the wafer-level silicon interposer through microbumps; in response to the functional chip layer sending data signals to the outside, the power consumption change information of the functional chip layer is monitored in real time, and the power consumption change information is fed back to the power supply reconfiguration layer; based on the power consumption change information, the output voltage of the programmable voltage regulation module chip in the power supply reconfiguration layer is dynamically adjusted.

[0006] Secondly, some embodiments of this disclosure provide a voltage regulation device for a three-dimensional stacked on-chip system power supply structure. The device includes: an integrated unit configured to integrate a deep trench capacitor array, through-silicon vias (TSVs), and multiple voltage pads in a wafer-level silicon interposer, wherein the voltage pads are used to receive signals from a preset high-voltage power supply; and a control unit configured to control the wafer-level silicon interposer to transmit the input preset high-voltage power supply to a power supply reconfiguration layer, wherein the power supply reconfiguration layer includes multiple programmable voltage regulation module chips interconnected through a redistribution layer to form a power supply network, and the wafer-level silicon interposer layer and the power supply reconfiguration layer are wafer-to-wafer bonded. The system includes: a power supply unit configured to supply power to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer, and to integrate the functional chip layer onto the front side of the wafer-level silicon interposer, wherein the functional chip layer is electrically connected to the wafer-level silicon interposer via microbumps; a monitoring unit configured to monitor the power consumption change information of the functional chip layer in real time in response to the functional chip layer sending data signals to the outside, and to feed back the power consumption change information to the power supply reconfiguration layer; and a dynamic adjustment unit configured to dynamically adjust the output voltage of the programmable voltage regulation module chip in the power supply reconfiguration layer based on the power consumption change information.

[0007] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0009] The various embodiments of this disclosure have the following beneficial effects: The voltage regulation method for on-chip system power supply structure based on three-dimensional stacking, as described in some embodiments of this disclosure, specifically addresses wafer warpage issues. Firstly, it solves the problem by using W2W (wafer-to-wafer) bonding or 3D integration, avoiding the dependence on C4 pad density and the mechanical strength of the power supply PCB in traditional vertical connections. W2W bonding is performed at the wafer level, offering high alignment accuracy, compensating for warpage, and reducing equipment requirements for back-side processes. Since bonding is performed in a flat wafer state, the impact of warpage is reduced, and the number of C4 pads is decreased, lowering the difficulty of soldering or crimping. The power supply chip uses semiconductor technology, enabling high-density integration, reducing the size of VRM components (such as switches and capacitors), and allowing for more power domains and higher current output. The power supply chip is programmable, flexibly adapting to different power consumption requirements, especially suitable for high-power systems; the back-side C4 pads only transmit high voltage and low current, reducing overcurrent requirements, and while the number of pads is reduced, the current capacity is actually increased (due to the power supply chip's proximity in switching). Power supply chips are integrated close to functional chips or connected via short paths using RDL (Redistributed Line Layout) processes, reducing parasitic inductance and resistance in the power supply path and improving decoupling. Deep trench capacitors assist in decoupling, but primary decoupling is achieved by capacitors integrated into the power supply chip, resulting in more effective noise coupling suppression. Power supply reconfigurable wafers or composite chips are integrated using standard wafer-level processes, reducing assembly steps on discrete power supply PCBs and improving yield and reliability. Back-side processes are simplified, and the power supply PCB may require only a simple substrate, reducing cost and weight. Programmable power supply chips support dynamic power management, adapting to heterogeneous integration scenarios with multiple chips. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0011] Figure 1 This is a diagram of a vertical power supply structure for a system-on-a-chip (SoC) according to some embodiments of the voltage regulation method for a SoC power supply structure based on three-dimensional stacking disclosed herein.

[0012] Figure 2(a) is a front view of a three-layer stacked structure diagram of some embodiments of the voltage regulation method for on-chip power supply structure based on three-dimensional stacking according to the present disclosure;

[0013] Figure 2(b) is a front view of a three-layer stacked structure diagram of some embodiments of the voltage regulation method for on-chip power supply structure based on three-dimensional stacking according to the present disclosure; Figure 3(a) is a front view structural diagram of the 3D integration of a power supply chip and functional chip according to some embodiments of the voltage regulation method of the on-chip power supply structure based on three-dimensional stacking according to the present disclosure; Figure 3(b) is a back view structural diagram of the power supply chip and functional chip 3D integration according to some embodiments of the voltage regulation method of the on-chip power supply structure based on three-dimensional stacking of the present disclosure;

[0014] Figure 4 This is a flowchart of some embodiments of the voltage regulation method for a power supply structure based on three-dimensional stacking of the present disclosure for a system-on-a-chip.

[0015] Figure 5 This is a schematic diagram of some embodiments of the voltage regulation device for a power supply structure based on three-dimensional stacking of a crystal on-chip according to the present disclosure;

[0016] Figure 6 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0018] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0019] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0020] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0021] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0022] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] Figure 4A flow 400 is shown illustrating some embodiments of a voltage regulation method for a three-dimensional stacked on-chip system power supply structure according to this disclosure. This voltage regulation method for a three-dimensional stacked on-chip system power supply structure includes the following steps:

[0024] Step 401: Integrate a deep trench capacitor array, through-silicon vias, and multiple voltage pads in a wafer-level silicon interposer.

[0025] In some embodiments, the execution subject (e.g., a computing device) of the on-chip system power supply structure voltage regulation method based on three-dimensional stacking can integrate deep trench capacitor arrays, through-silicon vias and multiple voltage pads in a wafer-level silicon interposer.

[0026] The voltage pads mentioned above are used to receive signals from a preset high-voltage power supply. Deep trench capacitors (DTC), through-silicon vias (TSVs), and high-voltage (e.g., 12V) C4 pads enable vertical interconnection between layers, providing decoupling and voltage regulation. The DTCs offer high-capacity local decoupling and voltage regulation, providing high Q-factor capacitance within the same wafer, suppressing transient noise, reducing reliance on external surface-mount capacitors, and their structure is coplanar with the TSVs, facilitating subsequent metal sidewall bonding for reliable electrical connections. The TSVs penetrate the entire stack structure, directly transmitting high voltage (e.g., 12V) from the external power supply to the power dies of each layer. Furthermore, the TSV technology creates an insulating / barrier layer between the via and adjacent materials, preventing contamination and enhancing mechanical reliability.

[0027] Optionally, the aforementioned implementing entity can integrate a deep trench capacitor array, through-silicon vias, and multiple voltage pads in a wafer-level silicon interposer using the following steps:

[0028] The first step is to etch a deep trench capacitor array on the aforementioned wafer-level silicon interposer.

[0029] As an example, the aforementioned execution entity can employ a deep reactive ion etching (DRIE) process to form deep trenches with an aspect ratio greater than 10:1 in a wafer-level silicon interposer, and then fill them with a high dielectric constant material (such as Ta2O5) to form a distributed capacitor network, i.e., a deep trench capacitor array.

[0030] The second step is to drill holes in the aforementioned wafer-level silicon adapter board to obtain through-silicon vias.

[0031] As an example, the aforementioned execution entity can use a laser to drill holes in the wafer-level silicon interposer or use the Bosch process to form through-silicon vias (TSVs), then deposit an insulating layer (such as SiO2) and a barrier layer (such as TiN), and then electroplate copper to form a conductive channel, thus obtaining a TSV.

[0032] The third step is to design multiple voltage pads on the back of the aforementioned wafer-level silicon adapter board.

[0033] As an example, the aforementioned implementation could design the C4 pad spacing to be ≥150μm and use a thick-film dielectric layer (such as polyimide) beneath the pads to prevent high-voltage breakdown. The pad spacing and dielectric layer thickness are optimized based on the high-voltage input (e.g., 12V). Figure 1 As shown, the wafer-level silicon interposer (201) has a structure similar to existing technologies, including deep trench capacitors (202) and TSVs (203), but the back C4 pad (204) is designed to support high voltage (e.g., 12V) low current input, rather than low voltage high current. Before the back-side processing of the wafer-level silicon interposer, two wafers are bonded together using bonding adhesive or bonding film to form a complete stacked structure. This step is usually performed under thermo-compression bonding or photonic bonding conditions to ensure flatness between the two layers. After bonding, back-side processing (such as thinning and through-silicon via exposure) is performed, and finally, functional chips (208) are bonded to the wafer (D2W) on the front side, and underfill and molding are completed.

[0034] Optionally, after "step 401" above, the method further includes:

[0035] The wafer-level silicon adapter board is controlled to transmit the preset high-voltage power supply to the functional core layer, and to shorten the internal traces between the functional core layers to supply power to the functional core layer.

[0036] The preset high-voltage power supply can be a high-voltage power supply introduced through external pins or PCB traces (such as the 12V power supply described).

[0037] As an example, the aforementioned execution entity can directly connect multiple VRM chips in parallel or series through VRM chip interconnects to achieve a unified power supply network. The spacing between VRM chips and between VRM and functional chips is small, greatly shortening the internal wiring, which is key to significantly reducing electromagnetic interference. The VRM is integrated with the functional chips in the chip layer as chips, improving the integration of the entire system while completing the division of power domains of each chip. As shown in Figure 3, the VRM circuit is fabricated as a programmable power supply chip (301), which is integrated with the functional chip (302) through 3D IC technology to form a composite chip (303). The power supply chip can be configured with power domain parameters (voltage, current). The VRM (voltage regulation module) circuit, which originally occupied a large PCB area, is integrated into an independent chip (301) through CMOS technology, and vertically integrated with the functional chip (302) through 3D IC technology. For the design and manufacturing of the programmable power supply chip (301), since the VRM needs to have both high voltage (power input) and low voltage (internal logic control) characteristics, this is usually achieved through a "dual voltage domain" design in CMOS technology. The high voltage domain is used for power conversion circuits, and the low voltage domain is used for microcontrollers or configuration registers. The functional chip (302) and the power supply chip (301) are vertically electrically interconnected through through-silicon vias (TSVs). This structure is similar to a "chip-on-chip," which shifts the power supply path from horizontal traces on the PCB to vertical channels inside the chip, greatly shortening the power transmission distance. At the wafer level, the I / O bumps of the two chips are aligned and connected by bonding (such as W2W) and redistribution layers (RDLs) to form a complete composite chip (303). The composite chip is mounted to the front side of a wafer-level silicon adapter board (304) via D2W bonding. The C4 pad on the back side of the adapter board only needs to provide a high voltage and low current input. The wafer-level silicon interposer retains DTC (305) and TSV (306), but power supply decoupling is mainly handled by the integrated power supply chip.

[0038] Step 402: Control the wafer-level silicon adapter board to transmit the preset high-voltage power supply to the power supply reconfiguration layer.

[0039] In some embodiments, the aforementioned execution entity can control the aforementioned wafer-level silicon adapter to transmit the input preset high-voltage power supply to the power supply reconfiguration layer.

[0040] The aforementioned power reconfiguration layer includes multiple programmable voltage regulation module chips, which are interconnected through a redistribution layer to form a power supply network. The aforementioned wafer-level silicon interposer layer and the aforementioned power reconfiguration layer are connected via wafer-to-wafer bonding. The power reconfiguration layer uses integrated programmable VRM power supply chips to form a wafer and performs redistribution to complete voltage conversion and distribution across multiple power domains.

[0041] As an example, the aforementioned execution entity can directly transmit high voltage (e.g., 12V) to the power reconfiguration layer via a TSV deeply embedded in a wafer-level silicon interposer. The power reconfiguration layer can receive external control commands or register setting signals to program the output characteristics of the VRM. For example... Figure 1 As described above, the VRM and control circuit of the power supply PCB are fabricated separately as power supply chips (205), and multiple power supply chips are integrated through a redistribution layer (RDL) (206) to form a power supply reconfiguration wafer (207). The power supply chips are programmable and support multi-power domain output. Function of power supply chip (205): This chip integrates the VRM (Voltage Regulator Module) and control circuit. It is similar to the power supply module on the motherboard, but here it is down-shifted to the power supply layer close to the chip. The redistribution layer (RDL, 206) is on the wafer-level power supply layer, and interconnections between power supply chips (205) are formed through photolithography and metal deposition processes (such as MLO or electroplating). Multiple power supply chips are connected together through the RDL to form a power supply reconfiguration wafer (207). This is similar to using multiple power planes and power planes on a PCB, but here it is achieved through wafer-level metallization.

[0042] Step 403: Power is supplied to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer, and the functional chip layer is integrated onto the front side of the wafer-level silicon interposer.

[0043] In some embodiments, the aforementioned execution entity may supply power to the functional chip layer based on the programmable voltage regulation module chip in the power supply reconfiguration layer, and integrate the aforementioned functional chip layer onto the front side of the aforementioned wafer-level silicon interposer.

[0044] The functional core layer is electrically connected to the aforementioned wafer-level silicon interposer via microbumps. The functional core layer consists of various functional cores and carries the main on-chip business. The first two layers are formed into a single structure using wafer-to-wafer bonding (W2W), while the core layer and the wafer-level silicon interposer are formed into a single structure using die-to-wafer bonding (D2W).

[0045] Optionally, the aforementioned execution entity can supply power to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer through the following steps, and integrate the aforementioned functional chip layer onto the front side of the aforementioned wafer-level silicon interposer:

[0046] The first step is to control the aforementioned programmable voltage regulation module chip to convert the received preset high-voltage power supply into multiple low-voltage power supplies.

[0047] As an example, the aforementioned execution entity can convert the received high-voltage power supply into multiple low-voltage power supplies (such as 0.8V, 1.2V, and 1.8V) through a programmable VRM power supply chip (programmable voltage regulation module chip).

[0048] The second step is to transmit the aforementioned multiple low-voltage power supplies to the functional core layer to supply power to the functional core layer, and to integrate the aforementioned functional core layer onto the front side of the aforementioned wafer-level silicon interposer.

[0049] As an example, the aforementioned execution entity can receive power domain voltages (e.g., 0.8V, 1.2V, 1.8V) from the functional core layer conversion output to provide power to various functional cores (CPU, GPU, memory, etc.) inside the functional core layer.

[0050] Optionally, after "step 403" above, the method further includes:

[0051] In response to the aforementioned functional core layer sending data signals to the outside, the power consumption change information of the aforementioned functional core layer is monitored in real time, and the power consumption change information is fed back to the aforementioned functional core layer.

[0052] As an example, the aforementioned execution entity can send processed data signals to external layers or other layers. The power consumption of the functional core layer affects the voltage fluctuations of the entire power network, which is then fed back to the functional core layer for dynamic adjustment.

[0053] Therefore, vertically stacking the power supply chip with the functional chips can reduce the power supply path length and improve noise. The number of C4 pads on the back is reduced, simplifying the power supply PCB (potentially eliminating the need for multi-layer VRM circuitry), requiring only the provision of basic voltage conversion.

[0054] Step 404: In response to the above-mentioned functional core layer sending data signals to the outside, monitor the power consumption change information of the above-mentioned functional core layer in real time, and feed back the power consumption change information to the above-mentioned power supply reconfiguration layer.

[0055] In some embodiments, the execution entity may, in response to the functional core layer sending a data signal to the outside, monitor the power consumption change information of the functional core layer in real time, and feed back the power consumption change information to the power reconfiguration layer.

[0056] As an example, the aforementioned execution entity can send processed data signals to external layers or other layers. The power consumption of the aforementioned functional core layer affects the voltage fluctuations of the entire power network, which is fed back to the power reconfiguration layer for dynamic adjustment (such as dynamic adjustment of the VRM).

[0057] Step 405: Based on the power consumption change information mentioned above, dynamically adjust the output voltage of the programmable voltage regulation module chip of the power supply reconfiguration layer.

[0058] In some embodiments, the execution entity may dynamically adjust the output voltage of the programmable voltage regulation module chip of the power supply reconfiguration layer based on the power consumption change information.

[0059] As an example, the aforementioned execution entity can convert the power consumption changes into voltage fluctuation signals. These voltage fluctuation signals are then fed back to the voltage regulation module chip. The voltage regulation module chip dynamically adjusts the output voltage based on the feedback signal to suppress power network fluctuations.

[0060] Optionally, after "step 405" above, the method further includes:

[0061] The stacked structure formed by the above-mentioned wafer-level silicon interposer, the above-mentioned power supply reconfiguration layer and the above-mentioned functional core layer is encapsulated to generate a sealed power supply structure.

[0062] As an example, the aforementioned actuator can inject underfill between the aforementioned functional core layer and the aforementioned wafer-level silicon interposer. The stacked structure is placed in a mold, epoxy molding compound is injected, and it is then thermoformed. This yields a sealed power supply structure.

[0063] Further reference Figure 5 As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of a voltage regulation device for a three-dimensional stacked on-chip system power supply structure. These device embodiments are similar to... Figure 1 Corresponding to the method embodiments shown, this voltage regulation device based on a three-dimensional stacked on-chip system power supply structure can be specifically applied to various electronic devices.

[0064] like Figure 5As shown, a voltage regulation device 500 for a three-dimensional stacked on-chip system power supply structure in some embodiments includes: an integration unit 501, a control unit 502, a power supply unit 503, a monitoring unit 504, and a dynamic adjustment unit 505. The integration unit 501 is configured to integrate a deep trench capacitor array, through-silicon vias (TSVs), and multiple voltage pads in a wafer-level silicon interposer, wherein the voltage pads are used to receive signals from a preset high-voltage power supply. The control unit 502 is configured to control the wafer-level silicon interposer to transmit the input preset high-voltage power supply to a power supply reconfiguration layer, wherein the power supply reconfiguration layer includes multiple programmable voltage regulation module chips interconnected through a redistribution layer to form a power supply network, and the wafer-level silicon interposer layer and the power supply reconfiguration layer are connected via wafer-to-wafer bonding. The power supply unit 503 is configured to adjust the voltage according to the voltage regulation in the power supply reconfiguration layer. The programmable voltage regulation module chip supplies power to the functional chip layer and integrates the functional chip layer onto the front side of the wafer-level silicon interposer. The functional chip layer is electrically connected to the wafer-level silicon interposer via microbumps. The monitoring unit 504 is configured to monitor the power consumption change information of the functional chip layer in real time in response to the functional chip layer sending data signals to the outside, and to feed back the power consumption change information to the power supply reconfiguration layer. The dynamic adjustment unit 505 is configured to dynamically adjust the output voltage of the programmable voltage regulation module chip of the power supply reconfiguration layer based on the power consumption change information.

[0065] It is understandable that the units described in the voltage regulation device 500 for the power supply structure of the three-dimensional stacked on-chip system are similar to the reference units. Figure 4 The steps in the described method correspond accordingly. Therefore, the operations, features, and beneficial effects described above for the method also apply to the voltage regulation device 500 of the on-chip system power supply structure based on three-dimensional stacking and the units contained therein, and will not be repeated here.

[0066] The following is for reference. Figure 6 It shows a schematic diagram of the structure of an electronic device 600 (e.g., a computing device) suitable for implementing some embodiments of the present disclosure. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0067] As shown in Figure 3, the electronic device 600 may include a processing unit 601 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device 600. The processing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0068] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 6 Each box shown can represent a device or multiple devices as needed.

[0069] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a storage device 608, or installed from a ROM 602. When the computer program is executed by the processing device 601, it performs the functions defined above in the methods of some embodiments of this disclosure.

[0070] It should be noted that, in some embodiments of this disclosure, the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0071] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0072] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: integrate a deep trench capacitor array, through-silicon vias, and multiple voltage pads in a wafer-level silicon interposer, wherein the voltage pads are used to receive signals from a preset high-voltage power supply; and control the wafer-level silicon interposer to transmit the input preset high-voltage power supply to a power supply reconfiguration layer, wherein the power supply reconfiguration layer includes multiple programmable voltage regulation module chips and is interconnected through a redistribution layer to form a power supply network, and the wafer-level silicon interposer layer and the power supply reconfiguration layer are connected via… Wafer-to-wafer bonding; power supply to the functional chip layer based on the programmable voltage regulation module chip in the power supply reconfiguration layer, and integration of the functional chip layer onto the front side of the wafer-level silicon interposer, wherein the functional chip layer is electrically connected to the wafer-level silicon interposer via microbumps; in response to the functional chip layer sending data signals to the outside, real-time monitoring of the power consumption change information of the functional chip layer, and feedback of the power consumption change information to the power supply reconfiguration layer; based on the power consumption change information, dynamically adjusting the output voltage of the programmable voltage regulation module chip in the power supply reconfiguration layer.

[0073] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0074] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0075] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0076] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A voltage regulation method for a system-on-a-chip power supply structure based on three-dimensional stacking, characterized in that, include: A deep trench capacitor array, through-silicon vias, and multiple voltage pads are integrated in a wafer-level silicon interposer, wherein the voltage pads are used to receive signals from a preset high-voltage power supply. The wafer-level silicon interposer is controlled to transmit the input preset high voltage power supply to the power supply reconfiguration layer. The power supply reconfiguration layer includes multiple programmable voltage regulation module chips, which are interconnected through a redistribution layer to form a power supply network. The wafer-level silicon interposer layer and the power supply reconfiguration layer are connected by wafer-to-wafer bonding. According to the programmable voltage regulation module chip in the power supply reconfiguration layer, power is supplied to the functional chip layer, and the functional chip layer is integrated onto the front side of the wafer-level silicon interposer, wherein the functional chip layer is electrically connected to the wafer-level silicon interposer through microbumps; In response to the functional core layer sending data signals to the outside, the power consumption change information of the functional core layer is monitored in real time, and the power consumption change information is fed back to the power supply reconfiguration layer; Based on the power consumption change information, the output voltage of the programmable voltage regulation module chip of the power supply reconfiguration layer is dynamically adjusted.

2. The method according to claim 1, characterized in that, The integration of a deep trench capacitor array, through-silicon vias, and multiple voltage pads in a wafer-level silicon interposer includes: A deep trench capacitor array is etched on the wafer-level silicon interposer. Holes are drilled in the wafer-level silicon adapter to obtain through-silicon vias; Multiple voltage pads are designed on the back side of the wafer-level silicon adapter board.

3. The method according to claim 1, characterized in that, The step of supplying power to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer, and integrating the functional chip layer onto the front side of the wafer-level silicon interposer includes: The programmable voltage regulation module chip is controlled to convert the received preset high-voltage power supply into multiple low-voltage power supplies; The multiple low-voltage power supplies are transmitted to the functional core layer to power the functional core layer, and the functional core layer is integrated onto the front side of the wafer-level silicon interposer.

4. The method according to claim 1, characterized in that, After integrating the deep trench capacitor array, through-silicon vias, and multiple voltage pads in the wafer-level silicon interposer, the method further includes: The wafer-level silicon adapter board is controlled to transmit the preset high-voltage power supply to the functional core layer, and to shorten the internal traces between the functional core layers to supply power to the functional core layer.

5. The method according to claim 1, characterized in that, After supplying power to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer, and integrating the functional chip layer onto the front side of the wafer-level silicon interposer, the method further includes: In response to the functional core layer sending a data signal to the outside, the power consumption change information of the functional core layer is monitored in real time, and the power consumption change information is fed back to the functional core layer.

6. The method according to claim 1, characterized in that, The method further includes: The stacked structure formed by the wafer-level silicon interposer, the power supply reconfiguration layer, and the functional chip layer is encapsulated to generate a sealed power supply structure.

7. A voltage regulation device for a system-on-a-chip power supply structure based on three-dimensional stacking, characterized in that, include: An integrated unit is configured to integrate a deep trench capacitor array, through-silicon vias, and multiple voltage pads in a wafer-level silicon interposer, wherein the voltage pads are used to receive signals from a preset high-voltage power supply. The control unit is configured to control the wafer-level silicon interposer to transmit the input preset high-voltage power supply to the power reconfiguration layer, wherein the power reconfiguration layer includes multiple programmable voltage regulation module chips and interconnects them through a redistribution layer to form a power supply network, and the wafer-level silicon interposer layer and the power reconfiguration layer are connected by wafer-to-wafer bonding. The power supply unit is configured to supply power to the functional chip layer according to the programmable voltage regulation module chip in the power supply reconfiguration layer, and to integrate the functional chip layer to the front side of the wafer-level silicon interposer, wherein the functional chip layer is electrically connected to the wafer-level silicon interposer via microbumps. The monitoring unit is configured to monitor the power consumption change information of the functional core layer in real time in response to the data signal sent to the outside by the functional core layer, and to feed back the power consumption change information to the power reconfiguration layer. The dynamic adjustment unit is configured to dynamically adjust the output voltage of the programmable voltage regulation module chip of the power supply reconfiguration layer based on the power consumption change information.

8. An electronic device, characterized in that, include: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 6.

9. A computer-readable medium, characterized in that, It stores a computer program thereon, wherein the computer program, when executed by a processor, implements the method as described in any one of claims 1 to 6.

Images