Fan-out silicon interposers, chip package structures, and methods of forming the same

Abstract

A fan-out silicon interposer and a chip package structure including the same, a method of forming the chip package structure including forming an array of silicon via structures through a silicon substrate and forming package side metal pads on backside surfaces of the array of silicon via structures. A silicon substrate is disposed over a carrier substrate and an epoxy mold compound interposer frame is formed around the silicon substrate. A die side redistribution structure is formed over the silicon substrate and the epoxy mold compound interposer frame and at least one semiconductor die is attached to the die side redistribution structure. The carrier substrate is removed from under the package side metal pads. A package side redistribution structure is formed on the package side metal pads and the epoxy mold compound interposer frame. An overlay tolerance between the package side redistribution structure and the package side metal pads is increased due to an increase in area of the package side metal pads.

Description

Technical Field

[0001] The present invention relates to a fan-out silicon interposer, a chip packaging structure, and a method for forming the same. Background Technology

[0002] During the fabrication of a fan-out wafer-level package (FOWLP), pick-and-place operations are used to position the die or interposer before forming the epoxy molding compound (EMC) framework and redistribution layer. These pick-and-place operations are mechanical processes that can cause lateral variations during the placement of dies or interposers of approximately 5 micrometers or larger. Because the pitch of the substrate via structure is close to approximately 10 micrometers, placement errors during pick-and-place operations can lead to defective electrical connections between the substrate via structure and the redistribution layer, thus resulting in yield losses during semiconductor die packaging. Summary of the Invention

[0003] This invention provides a fan-out silicon interposer comprising: a bridging die including an array of silicon through-hole structures extending through a silicon substrate; an encapsulation interposer frame laterally surrounding the bridging die; a die-side redistribution structure including a die-side bonding pad; a package-side metal pad contacting a package-side end face of the array of silicon through-hole structures; and a package-side redistribution structure located on the package-side metal pad on the opposite side of the die-side redistribution structure relative to the bridging die.

[0004] This invention provides a fan-out silicon interposer comprising: a bridging die including an array of through-silicon via (TSV) structures; a package-side metal pad contacting the end face of the array of TSV structures; an encapsulation interposer frame laterally surrounding the bridging die; an integrated fan-out through-silicon via (TIV) structure extending vertically through the encapsulation interposer frame; a package-side redistribution structure located on the package-side metal pad; and a die-side redistribution structure electrically connected to the array of TSV structures and including a die-side bonding pad.

[0005] This invention provides a method for forming a chip package structure, comprising: forming a through-hole structure through an upper portion of a silicon substrate; forming a die-side metal interconnect structure above the through-hole structure; forming an array of through-silicon via (TSV) structures through the silicon substrate by thinning the rear side of the silicon substrate, wherein the through-hole structures extend vertically through the entire thickness of the thinned silicon substrate to form the array of TSV structures; forming package-side metal pads on the rear surface of the array of TSV structures, thereby forming a bridging die; disposing the bridging die on a carrier substrate such that the package-side metal pads are closer to the carrier substrate than the TSV structures; forming an encapsulation intermediate frame around the bridging die and on the carrier substrate; forming a die-side redistribution structure on the bridging die and the encapsulation intermediate frame; and attaching at least one semiconductor die to the die-side redistribution structure. Attached Figure Description

[0006] A thorough understanding of the various aspects of this disclosure is best achieved by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1H These are a series of vertical sectional views forming the structure of the bridge pipe core according to an embodiment of the present invention.

[0008] Figure 2A This is a vertical cross-sectional view of a region of an exemplary structure according to an embodiment of the present invention, the exemplary structure including a first carrier substrate, a sacrificial matrix layer, and an array of via cavities extending through the sacrificial matrix layer.

[0009] Figure 2B yes Figure 2A Top view of the exemplary structure shown.

[0010] Figure 2C yes Figure 2A and Figure 2B The diagram shows a top view of one section of the exemplary structure. Vertical plane A–A' is... Figure 2A The plane of the vertical sectional view shown.

[0011] Figure 3A This is a vertical cross-sectional view of a region of an exemplary structure after forming an integrated fan-out via (TIV) structure according to an embodiment of the present invention.

[0012] Figure 3B yes Figure 3A Top view of the exemplary structure shown.

[0013] Figure 3C yes Figure 3A and Figure 3B The diagram shows a top view of one section of the exemplary structure. Vertical plane A–A' is... Figure 3A The plane of the vertical sectional view shown.

[0014] Figure 4A This is a vertical cross-sectional view of a region of an exemplary structure after the bridge tube core has been attached to a first carrier substrate, according to an embodiment of the present invention.

[0015] Figure 4B yes Figure 3A Top view of the exemplary structure shown.

[0016] Figure 4C yes Figure 4A and Figure 4B The diagram shows a top view of one section of the exemplary structure. Vertical plane A–A' is... Figure 4A The plane of the vertical sectional view shown.

[0017] Figure 5 This is a vertical cross-sectional view of a region of an exemplary structure following the formation of an epoxy molding compound (EMC) intermediary framework around each bridge pipe core according to an embodiment of the present invention.

[0018] Figure 6 This is a vertical cross-sectional view of a region of an exemplary structure after the formation of the die-side overlay structure according to an embodiment of the present invention.

[0019] Figure 7 This is a vertical cross-sectional view of a region of an exemplary structure following the application of solder material, according to an embodiment of the present invention.

[0020] Figure 8 This is a vertical cross-sectional view of a region of an exemplary structure after a semiconductor die has been bonded to a die-side bonding pad, according to an embodiment of the present invention.

[0021] Figure 9 This is a vertical cross-sectional view of a region of an exemplary structure following the formation of an epoxy molding compound (EMC) core frame, according to an embodiment of the present invention.

[0022] Figure 10 This is a vertical cross-sectional view of a region of an exemplary structure after the second carrier substrate has been attached to the semiconductor die and after the first carrier substrate has been removed, according to an embodiment of the present invention.

[0023] Figure 11 This is a vertical cross-sectional view of a region of an exemplary structure after the formation of the package-side redistribution structure and the package-side C4 solder ball, according to an embodiment of the present invention.

[0024] Figure 12This is a vertical cross-sectional view of a region of an exemplary structure to be divided during the monomerization of a fan-out silicon interposer according to an embodiment of the present invention.

[0025] Figure 13 This is a vertical cross-sectional view of the assembly of a fan-out silicon interposer and a semiconductor die according to an embodiment of the present invention.

[0026] Figure 14 This is a vertical cross-sectional view of the assembly of the fan-out silicon interposer, semiconductor die, packaging substrate, and ring structure according to an embodiment of the present invention.

[0027] Figure 15 This is a vertical cross-sectional view of a structure formed by bonding an assembly of a fan-out silicon interposer, a packaging substrate, and a ring structure to a printed circuit board (PCB) according to an embodiment of the present invention.

[0028] Figure 16 This is a first flowchart illustrating the steps of forming a chip packaging structure according to an embodiment of the present invention.

[0029] Figure 17 This is a second flowchart illustrating the steps of forming a chip package structure according to an embodiment of the present invention. Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or examples to implement various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" are used herein to describe the relationship between one element or feature illustrated in the figures and another element or feature. In addition to the orientations shown in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Unless explicitly stated otherwise, elements with the same reference number are assumed to have the same material composition and thickness within the same thickness range.

[0032] This disclosure relates to semiconductor devices, and more specifically to chip package structures containing silicon interposers and methods for forming the same, said silicon interposers including substrate through-hole structures and having increased overlay tolerance.

[0033] Typically, the methods and structures disclosed herein can be used to provide fan-out silicon interposers that are not easily affected by overlay variations during assembly when bridging dies are placed on a carrier wafer. The bridging dies include an array of through-silicon via (TSV) structures and package-side metal pads that contact the package-side end surface of the TSV structure array. The package-side metal pads provide a larger area than the end surface of the TSV structures, so that even if large overlay variations may occur during the placement of the bridging dies onto the wafer carrier to form a reconfigured wafer, the alignment of the package-side redistribution structure with the package-side metal pads is less prone to accidental electrical disconnection (electrical connection breakage) or accidental electrical short circuit (electrical connection). An encapsulation interposer frame (e.g., an epoxy molding compound (EMC) interposer frame) laterally surrounds each bridging dies in the reconfigured wafer, allowing the reconfigured wafer to be processed to form a die-side redistribution structure on one side. At least one semiconductor die can be attached to each reconfigured wafer, and the carrier wafer can subsequently be stripped. The package-side emphasis wiring structure can be formed directly on the package-side metal pads on the reconfigurable wafer. This increases the tolerance for overlap variations between the package-side emphasis wiring and the TSV structure array due to the intermediate package-side metal pads. Fan-out silicon interposers can be formed on each assembly of at least one semiconductor die. The reconfigurable wafer can be diced to individualize each assembly of the fan-out silicon interposers and at least one semiconductor die. The process yield and reliability of the fan-out silicon interposers can be improved by using package-side metal pads. Various aspects of the methods and structures of embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0034] refer to Figure 1A The present invention describes a structure for forming a bridging core. The bridging core is an intermediate structure including a silicon substrate 410 and a front insulating layer 420 formed on the front surface of the silicon substrate 410. The front insulating layer 420 comprises an insulating material, such as silicon oxide, and can be formed by depositing a dielectric material or by thermally oxidizing a portion of the surface of the silicon substrate 410. The thickness of the silicon substrate 410 can range from 20 nanometers to 400 nanometers, but smaller or larger thicknesses are also possible. A conductive structure extending vertically into the silicon substrate 410 can be formed. This conductive structure includes a substrate through-hole structure 414. The substrate through-hole structure 414 is surrounded by a corresponding substrate through-insulating spacer 412. The substrate through-hole structure 414 can be first formed in the silicon substrate 410 in the form of a through-hole structure, wherein the vertical dimension of the through-hole structure is smaller than the thickness of the silicon substrate 410. Subsequently, the back side of the silicon substrate 410 can be removed so that the thickness of the silicon substrate 410 after thinning is less than the thickness of the substrate through-hole structure 414, thereby providing a "substrate through" configuration for the substrate through-hole structure 414.

[0035] The silicon substrate 410 provided initially can be a commercially available silicon wafer with a diameter of 150 mm, 200 mm, 300 mm, or 450 mm and a thickness ranging from 675 micrometers to 825 micrometers. The silicon substrate 410 may contain an atomic concentration of less than 1.0 × 10⁻⁶. 14 / cm 3 Electrical doping (e.g., p-type or n-type doping) is used to provide low conductivity and minimize eddy currents that may be induced by inductive coupling caused by high-frequency electrical signals traveling between or between semiconductor dies or redistribution interconnects that will subsequently be placed close to each other.

[0036] The silicon substrate 410 may include a two-dimensional array (e.g., a rectangular array) of die regions. Each die region may correspond to a region of a bridging die that may be subsequently formed. An array of deep trenches with a depth greater than 20 micrometers may be formed in each die region of the silicon substrate 410. For example, a hard mask layer (e.g., a silicon nitride layer and / or a borosilicate glass layer) may be formed on the front insulating layer 420, and a photoresist layer may be applied over the hard mask layer. The photoresist layer may be photolithographically patterned to form an array of openings through the photoresist layer, and the pattern of the openings may be transferred into the hard mask layer. Anisotropic etching may be performed using the hard mask (and optionally, the patterned photoresist layer) as an etching mask to form deep trenches extending through the front insulating layer 420 and perpendicularly from the front surface of the silicon substrate 410 toward the rear side of the silicon substrate 410. The photoresist layer can be consumed during anisotropic etching processes and can subsequently be removed, for example, using a wet etching process. An array of openings, referred to herein as deep trenches, extends vertically through the front insulating layer 420 and from the front surface of the silicon substrate 410 toward the rear surface of the silicon substrate 410.

[0037] The depth of the deep trenches can range from 10 micrometers to 100 micrometers (e.g., 20 micrometers to 60 micrometers), but smaller and larger depths are also possible. The maximum lateral dimension (e.g., diameter) of each deep trench can range from 3 micrometers to 30 micrometers (e.g., 6 micrometers to 15 micrometers), but smaller and larger maximum lateral dimensions are also possible. Typically, the maximum lateral dimension of the deep trench is chosen to be large enough to allow deep etching in the silicon substrate 410, and small enough to allow the combination of the substrate through-insulating spacer 412 and the substrate through-substrate via (TSV) structure 414 to fill the deep trench. The deep trenches can be formed as rows with one-dimensional periodicity (i.e., a one-dimensional array), or as a two-dimensional array, which can be a periodic two-dimensional array (e.g., a rectangular array or a hexagonal array). The center-to-center distance between adjacent pairs of deep trenches can range from 6 micrometers to 60 micrometers.

[0038] Reference Figure 1B A die-side dielectric material layer 426 is deposited over the array of front insulating layer 420 and TSV structure 414. Each layer of the die-side dielectric material layer 426 may include a dielectric material, such as silicon oxide, porous or non-porous silicone glass, silicon carbonitride, silicon nitride, or other interconnecting layer dielectric materials well known in the art. The total thickness of the die-side dielectric material layer 426 may range from 200 nanometers to 10,000 nanometers, for example, from 400 nanometers to 5,000 nanometers, but smaller or larger thicknesses may also be used.

[0039] A die-side metal interconnect structure 424 can be formed within the die-side dielectric material layer 426. The formation of the die-side metal interconnect structure 424 includes, for example, forming line cavities, via cavities, and / or integrated line and via cavities at each level of the die-side dielectric material layer; depositing at least one conductive material in the various cavities located at each level; and planarizing the at least one conductive material located at each level. The die-side metal interconnect structure 424 may include metal line structures, metal via structures, metal pad structures, and / or integrated metal line and via structures. Back-end-of-line (BEOL) processing steps can be performed to form the die-side metal interconnect structure 424 in the die-side dielectric material layer 426. Back-end processing steps include, for example, deep ultraviolet (DUV) lithography and dual damascene metal deposition, as well as planarization processes. The linewidth of the metal lines in the die-side dielectric layer 426 can be in the range of 50 nanometers to 500 nanometers, for example, 100 nanometers to 250 nanometers, but smaller or larger widths can also be used. The spacing between the minimum-pitch lines can be in the range of 50 nanometers to 500 nanometers, for example, 100 nanometers to 250 nanometers, but smaller or larger widths can also be used. Die-side metal pads 428 can be formed at the topmost layer of the die-side dielectric layer 426. In one embodiment, die-side metal pads 428

[0040] It may include copper pads or copper pillars that can be used as microbumps. In one embodiment, the die-side metal pad 428 may have a maximum lateral dimension (e.g., diameter) in the range of 10 micrometers to 50 micrometers and a height in the range of 5 micrometers to 50 micrometers.

[0041] refer to Figure 1C The carrier substrate 300 can be bonded to Figure 1B The front surface of the structure shown Figure 1B The front surface of the structure shown includes the surface of the die-side metal pad 428. An adhesive layer 301 can be used to attach the carrier substrate 300 to the surface of the die-side metal pad 428. The carrier substrate 300 may have the same size as the silicon substrate 410.

[0042] In one embodiment, the carrier substrate 300 may comprise an optically transparent material, such as glass or sapphire. In these embodiments, the adhesive layer 301 may comprise a light-to-heat conversion (LTHC) layer, which may be deposited on a flat surface including the top surface of the die-side metal pad 428 and the top surface of the die-side dielectric material layer 426. The LTHC layer is a solvent-based coating applied using a spin-coating method and forms a layer that converts ultraviolet light into heat, causing the material to lose its adhesiveness. For example, the LTHC layer may comprise materials available from 3M... Purchased photothermal conversion (LTHC) release coating ink TM Alternatively, adhesive layer 301 may comprise a thermally degradable adhesive material. For example, adhesive layer 301 may comprise an acrylic pressure-sensitive adhesive that degrades at high temperatures. The peel temperature of the thermally degradable adhesive material may be in the range of 150 to 200 degrees Celsius.

[0043] refer to Figure 1D The backside of the silicon substrate 410 can be thinned until the bottom surface of the TSV structure 414 is exposed in solid form. Thinning of the silicon substrate 410 can be achieved, for example, by grinding, polishing, isotropic etching, anisotropic etching, or a combination thereof. For example, a combination of grinding, isotropic etching, and polishing processes can be used to thin the backside of the silicon substrate 410. The thickness of the silicon substrate 410 after thinning can be in the range of 10 micrometers to 100 micrometers (e.g., 20 micrometers to 60 micrometers). The thickness of the silicon substrate 410 after thinning is sufficient to provide sufficient mechanical strength, and thin enough to expose the backside surface (i.e., the bottom surface) of the TSV structure 414 in solid form.

[0044] refer to Figure 1E The rear surface of the silicon substrate 410 may be recessed in the vertical direction relative to the physically exposed end face of the TSV structure 414 and the cylindrical portion of the substrate-through insulating spacer 412 that laterally surrounds the respective TSV structure 414. In one embodiment, a wet etching process may be used to selectively etch silicon in the silicon substrate 410 relative to the metallic material of the TSV structure 414 and the dielectric material of the substrate-through insulating spacer 412. In an exemplary example, a wet etching process using a potassium hydroxide (KOH) solution may be used to recess the rear surface of the silicon substrate 410 in the vertical direction. The vertical recess distance of the rear surface of the silicon substrate 410 may be in the range of 100 nm to 1,000 nm (e.g., 200 nm to 500 nm), but smaller and larger vertical recess distances may also be used.

[0045] refer to Figure 1FAt least one dielectric material, such as silicon nitride and / or silicon oxide, may be deposited on the recessed rear surface of the silicon substrate 410 and on the exposed end faces of the TSV structure 414. The at least one dielectric material may be planarized, for example, by chemical mechanical planarization, to expose the end faces of the TSV structure 414 on the solid. The remaining portion of the at least one dielectric material forms a rear insulating layer 431. The exposed horizontal surface of the rear insulating layer 431 may lie in the same horizontal plane as the exposed end faces of the TSV structure 414. The thickness of the rear insulating layer 431 may be in the range of 100 nm to 1,000 nm (e.g., 200 nm to 500 nm), but smaller and larger thicknesses may also be used.

[0046] A package-side dielectric layer 432 may be deposited over the array of the back insulating layer 431 and the TSV structure 414. The package-side dielectric layer 432 may comprise a dielectric material such as silicon oxide, porous or non-porous silicate glass, silicon nitride carbon, silicon nitride, or any other interconnect-level dielectric material known in the art. The thickness of the package-side dielectric layer 432 may be in the range of 200 nm to 10,000 nm (e.g., 400 nm to 5,000 nm), but smaller and larger thicknesses are also possible.

[0047] Package-side metal pads 438 may be formed through a rear-side insulating layer 431 on the rear surface of an array of TSV structures 414. In one embodiment, package-side metal pads 438 may include copper pads or copper pillars that can be used as microbumps. In one embodiment, package-side metal pads 438 may have a maximum lateral dimension (e.g., diameter) in the range of 10 micrometers to 50 micrometers and a height in the range of 5 micrometers to 50 micrometers.

[0048] refer to Figure 1GThe adhesive layer 301 can be decomposed, for example, by ultraviolet radiation or by thermal annealing at a peel temperature. In embodiments where the carrier substrate 300 comprises an optically transparent material and the adhesive layer 301 comprises an LTHC layer, the adhesive layer can be decomposed by allowing ultraviolet light to pass through the transparent carrier substrate. The LTHC layer absorbs ultraviolet radiation and generates heat, which decomposes the material of the LTHC layer and allows the transparent carrier substrate to be peeled off from the assembly including the silicon substrate 410. In embodiments where the adhesive layer 301 comprises a thermally decomposable adhesive material, a thermal annealing process can be performed at a peel temperature to peel off the assembly including the silicon substrate 410 from the carrier substrate 300. The carrier substrate 300 can be peeled off from the assembly including the silicon substrate 410, the TSV structure 414, the substrate through-insulating spacer 412, the back insulating layer 431, the die-side metal pad 428, the die-side dielectric layer 426, the package-side metal pad 438, and the package-side dielectric layer 432. Subsequently, the assembly including the silicon substrate 410 can be sawn by performing a sawing process along a sawing groove. The sawn grooves are schematically represented by dashed lines. The sawn grooves correspond to the boundary between adjacent pairs of core regions DA.

[0049] refer to Figure 1H Each sawn portion of the assembly including the silicon substrate 410 constitutes a bridging die 405. A die bonding film (DAF) 321 may be bonded to the physically exposed flat surfaces of the package-side metal pads 438 and the package-side dielectric layer 432 of each bridging die 405. In an alternative embodiment, the DAF 321 may be applied to the flat surfaces of the package-side metal pads 438 and the package-side dielectric layer 432 before the assembly including the silicon substrate 410 is sawn into the bridging die 405.

[0050] In one embodiment, a double-side thermal release tape can be used to provide DAF 321. For example, the double-side thermal release tape can be configured as a five-layer stack including a first release pad, a pressure-sensitive adhesive, a polyester film, a thermal release adhesive, and a second release pad. The first release pad can be peeled off and discarded, and the pressure-sensitive adhesive of DAF 321 can be adhered to the solidly exposed flat surface of the package-side metal pad 438 and the solidly exposed flat surface of the package-side dielectric material layer 432 by pressing down. The second release layer can then be removed. The DAF may comprise a stack of pressure-sensitive adhesive, polyester film, and thermal release adhesive from bottom to top. In an exemplary example, the thickness of the pressure-sensitive adhesive may be about 10 micrometers, the thickness of the polyester film may be in the range of 50 to 100 micrometers, and the thickness of the thermal release adhesive may be in the range of 30 to 60 micrometers. The peel temperature of the thermal release adhesive may be about 170 degrees Celsius. Examples of commercially available double-sided heat release tapes are from Nitto Denko. TM Revalpha provided TM Each bridging die 405 may include a silicon substrate 410, a TSV structure 414, a substrate through-insulation spacer 412, a back insulating layer 431, a die-side metal pad 428, a die-side dielectric layer 426, a package-side metal pad 438, a package-side dielectric layer 432, and a DAF 321. As discussed above, in some embodiments, the package-side dielectric layer 432 and the back insulating layer 431 may be a unitary structure. The first surface of each DAF 321 may be attached to the package-side metal pad 438 of the corresponding bridging die 405.

[0051] refer to Figures 2A to 2C The diagram illustrates a first carrier substrate 350, which may be a transparent carrier substrate (e.g., a glass substrate or a sapphire substrate). In one embodiment, the first carrier substrate 350 may have a diameter in the range of 150 mm to 450 mm, or may be configured as a panel, such as a rectangular panel. A sacrificial matrix layer 360 may be formed on the first carrier substrate 350. The sacrificial matrix layer 360 may contain a material that can be selectively removed relative to the material of the first carrier substrate 350. For example, if the first carrier substrate 350 contains a transparent dielectric material or a metal, the sacrificial matrix layer 360 may contain a semiconductor material such as polysilicon, or a polymer material. The thickness of the sacrificial matrix layer 360 may be approximately the same as the thickness of the bridging core 405. For example, the thickness of the sacrificial matrix layer 360 may be in the range of 50 micrometers to 400 micrometers (e.g., 100 micrometers to 200 micrometers), but smaller and larger thicknesses may also be used.

[0052] A photoresist layer (not shown) may be applied over the top surface of the sacrificial substrate layer 360, and the photoresist layer may be patterned by photolithography to form an array of openings within each die region DA. The die regions DA may be arranged in a rectangular periodic array spanning the first carrier substrate 350. The opening pattern within each die region DA may be arranged such that the openings laterally surround the region where the bridging die 405 will subsequently be placed. The opening pattern in the photoresist layer may be transferred to the sacrificial substrate layer 360 using an anisotropic etching process that selectively etches the material of the sacrificial substrate layer 360 relative to the material of the first carrier substrate 350. An array of via cavities 359 through the sacrificial substrate layer 360 may be formed within each die region. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0053] In one embodiment, the through-hole cavities 359 within each die region DA can be arranged such that the through-hole cavities 359 laterally surround a rectangular region, the size of which is larger than that in the die region DA. Figure 1G The dimensions of the bridge tube core provided at the processing step. The lateral dimensions (e.g., diameter) of each through-hole cavity 359 can be in the range of 10 micrometers to 120 micrometers (e.g., 20 micrometers to 60 micrometers), but smaller and larger lateral dimensions can also be used.

[0054] refer to Figures 3A to 3C At least one conductive material, such as a combination of a metal nitride liner material (e.g., TiN, TaN, WN, or a combination thereof) and a metal filler material (e.g., W, Mo, Co, Ru, Cu, or any other transition metal), can be deposited in the via cavity 359 through the sacrificial matrix layer 360. Excess portions of the at least one conductive material can be removed from a horizontal plane including the top surface of the sacrificial matrix layer 360 by performing a planarization process (e.g., a chemical mechanical planarization process). The remaining portion of the at least one conductive material filling the via cavity 359 constitutes an integrated fan-out via (TIV) structure 486, which is a conductive via structure extending vertically through a fan-out silicon interposer to be subsequently completed.

[0055] Subsequently, the sacrificial matrix layer 360 can be selectively removed relative to the first carrier substrate 350 and the TIV structure 486. For example, if the first carrier substrate 350 includes a glass substrate or a sapphire substrate, and if the sacrificial matrix layer 360 contains a semiconductor material such as polysilicon, a wet etching process using a KOH solution can be performed to selectively remove the sacrificial matrix layer 360 relative to the first carrier substrate 350 and the TIV structure 486.

[0056] refer to Figures 4A to 4C It can be in Figure 1G The bridging core 405 provided at the processing step is attached to the first carrier substrate 350 so that the DAF 321 contacts the top surface of the first carrier substrate 350. The second surface of each DAF 321 can be attached to the first carrier substrate 350. Each bridging core 405 can be placed within a corresponding die region DA and can be laterally surrounded by a corresponding array of TIV structures 486. Each bridging core 405 can be disposed on the first carrier substrate 350 such that the package-side metal pad 438 is closer to the first carrier substrate 350 interposer than the TSV structure 414.

[0057] A pick-and-place device can be used to place the bridging die 405 onto the first carrier substrate 350. The overlay variation in alignment between the bridging die 405 and the array of TIV structures 486 within the die region DA where the bridging die 405 is placed is determined by the overlay accuracy of the pick-and-place device. Typical commercially available pick-and-place devices provide approximately 5 micrometers of overlay variation, but more expensive devices can provide even smaller variations. Each bridging die 405 can be attached to the first carrier substrate 350 using a corresponding DAF 321.

[0058] refer to Figure 5 An encapsulation (e.g., an epoxy molding compound (EMC)) can be applied to the gap between the bridge core 405 and the TIV structure 486. The EMC comprises an epoxy resin-containing compound that can be cured (i.e., hardened) to provide a dielectric portion with sufficient hardness and mechanical strength. The EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. The EMC can be provided in liquid or solid form depending on its viscosity and flowability. Liquid EMC typically offers better handling, good flowability, fewer voids, better filling properties, and fewer flow marks. Solid EMC typically offers less cure shrinkage, better stand-off, and less core drift. High filler content (e.g., 85% by weight) in the EMC can shorten molding time, reduce molding shrinkage, and decrease molding warpage. Uniform filler size distribution in the EMC can reduce flow marks and enhance flowability. The curing temperature of EMC can be lower than the release (peel) temperature of DAF 321. For example, the curing temperature of EMC can be in the range of 125°C to 150°C.

[0059] The EMC can be cured at a curing temperature to form an EMC matrix that laterally surrounds each of the bridging core 405 and the TIV structure 486. The EMC matrix comprises a plurality of epoxy molding compound (EMC) intermediate frames 460 laterally adjacent to each other. Each EMC intermediate frame 460 is located within a corresponding core region DA and laterally surrounds and can be formed around a corresponding array of the bridging core 405 and the TIV structure 486. Excess EMC can be removed above a horizontal plane including the top surfaces of the bridging core 405 and the TIV structure 486 using a planarization process, which may employ chemical mechanical planarization.

[0060] refer to Figure 6 A die-side redistribution structure 470 can be formed on the bridging die 405 and the TIV structure 486. Specifically, the die-side redistribution structure 470 can be formed in each die region DA of the assembly including the bridging die 405, the EMC dielectric frame 460, and the TIV structure 486. The die-side redistribution structure 470 is a redistribution structure formed on the die side (i.e., the side facing the semiconductor die to be subsequently bonded) relative to the assembly of the bridging die 405, the EMC dielectric frame 460, and the TIV structure 486.

[0061] Each die-side redistribution wiring structure 470 may include a die-side redistribution wiring dielectric layer 472, a die-side redistribution wiring interconnect 474, and a die-side bonding pad 478. The die-side redistribution wiring dielectric layer 472 comprises a suitable dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Each die-side redistribution wiring dielectric layer 472 can be formed by spin-coating and drying the suitable dielectric polymer material. The thickness of each die-side redistribution wiring dielectric layer 472 may be in the range of 2 micrometers to 40 micrometers (e.g., 4 micrometers to 20 micrometers). Each die-side emphasis dielectric layer 472 can be patterned, for example, by applying a corresponding photoresist layer over each die-side emphasis dielectric layer 472 and patterning the corresponding photoresist layer, and transferring the pattern in the photoresist layer into the die-side emphasis dielectric layer 472 using an etching process (e.g., anisotropic etching). Subsequently, the photoresist layer can be removed, for example, by ashing.

[0062] Each of the die-side overlay interconnect 474 and the die-side bonding pad 478 can be formed by: depositing a metal seed layer by sputtering; applying a photoresist layer over the metal seed layer and patterning the photoresist layer to form a pattern of openings through the photoresist layer; electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching the portion of the metal seed layer between the electroplated metal filler portions. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness in the range of 50 nm to 300 nm, and the copper seed layer may have a thickness in the range of 100 nm to 500 nm. The metal filler material for the die-side overlay interconnect 474 may include copper, nickel, or a stack of copper and nickel. The thickness of the metal filler material deposited to form each die-side emphasis wiring 474 can range from 2 micrometers to 40 micrometers (e.g., 4 micrometers to 10 micrometers), but smaller or larger thicknesses can also be used. The total number of wiring levels (i.e., the levels of die-side emphasis wiring 474) in each die-side emphasis wiring structure 470 can range from 1 to 10.

[0063] The metal filler material of the die-side bonding pad 478 may include copper. The thickness of the metal filler material deposited to form the die-side bonding pad 478 may be in the range of 5 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used. The die-side bonding pad 478 may have a rectangular, rounded rectangular, or circular horizontal cross-sectional shape. If the die-side bonding pad 478 is formed as a controlled collapse chip connection (C4) pad, the thickness of the die-side bonding pad 478 may be in the range of 5 micrometers to 50 micrometers, but smaller or larger thicknesses may also be used. Alternatively, the die-side bonding pad 478 may be configured for microbump bonding (i.e., C2 bonding) and may have a thickness in the range of 30 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used. In this embodiment, the die-side bonding pad 478 may be formed as an array of microbumps (e.g., copper pillars) with lateral dimensions in the range of 10 micrometers to 25 micrometers and pitches in the range of 20 micrometers to 50 micrometers.

[0064] refer to Figure 7Solder material portion 490 can be attached to die-side bonding pad 478. In embodiments where die-side bonding pad 478 includes a C4 bonding pad, solder material portion 490 can be a C4 solder ball, i.e., a spherical portion of solder material available for C4 bonding. In embodiments where die-side bonding pad 478 includes an array of microbumps for C2 bonding, solder material portion 490 can be a solder cap that wets the entire flat end face of the corresponding microbump and has a generally hemispherical shape. In one embodiment, solder material portion 490 can include an array of cylindrical copper pillars, each having a circular horizontal cross-sectional shape with a diameter ranging from 10 micrometers to 25 micrometers. While this disclosure is illustrated using embodiments representing solder material portion 490 as a spherical C4 solder ball, embodiments where solder material portion 490 is a solder cap having a hemispherical shape are clearly covered herein.

[0065] refer to Figure 8 At least one semiconductor die (701, 702) can be attached to each die-side rewiring structure 470, each die-side rewiring structure 470 being located within a corresponding die region DA. Therefore, at least one semiconductor die (701, 702) can be electrically connected to a corresponding bridging die 405 located within the corresponding die region DA. Each semiconductor die (701, 702) can be bonded to a corresponding subset of die-side bonding pads 478 via a corresponding subset of solder material portions 490. In one embodiment, at least one semiconductor die (701, 702) can be attached to the die-side rewiring structure 470 via an array of microbumps. In one embodiment, multiple semiconductor dies (701, 702) can be attached to the die-side rewiring structure 470 via an array of one or more microbumps. In this embodiment, at least one of the semiconductor dies (701, 702) includes an array of microbumps 778 with the same pitch as the die-side bonding pad 478, and the die-side bonding pad 478 includes another array of microbumps. A C2 bonding process for reflowing the solder material portion 490 can be performed after the array of each microbump 778 of at least one of the semiconductor dies (701, 702) is disposed over the array of solder material portions 490.

[0066] At least one underfill portion 492 may be formed around each array of bonded solder material portions 490. Each underfill portion 492 may be formed by injecting underfill material around the array of solder material portions 490 after reflow soldering. Any known underfill material application method may be used, such as a capillary underfill method, a molding underfill method, or a printed underfill method. In one embodiment, a plurality of semiconductor dies (701, 702) may be attached to a die-side wiring structure 470 within each die region DA, and a single underfill portion 492 may extend continuously beneath the plurality of semiconductor dies (701, 702).

[0067] The at least one semiconductor die (701, 702) may include any semiconductor die known in the art. In one embodiment, the at least one semiconductor die (701, 702) may include a system-on-chip (SoC) die, such as an application processor die. In one embodiment, the at least one semiconductor die (701, 702) may include multiple semiconductor dies (701, 702). In one embodiment, the multiple semiconductor dies (701, 702) may include a first semiconductor die 701 and at least one second semiconductor die 702. In one embodiment, the first semiconductor die 701 may be a central processing unit die, and the at least one second semiconductor die 702 may include a graphics processing unit (GPU) die. In another embodiment, the first semiconductor die 701 may include a system-on-a-chip (SoC) die, and the at least one second semiconductor die 702 may include at least one high-bandwidth memory (HBM) die, each of the at least one high-bandwidth memory die comprising a vertical stack of static random access memory dies and providing high bandwidth as defined under the Joint Electron Device Engineering Council (JEDEC) standard (i.e., the standard defined by the JEDEC Solid State Technology Association). The top surfaces of the semiconductor dies (701, 702) attached to the die-side wiring structure 470 may be located in the same horizontal plane.

[0068] The die-side metal interconnect structure 424 can be used as a segment of a high-speed inter-die conductive path between semiconductor dies (701, 702). Specifically, a combination of die-side redistributed interconnect 474 and die-side metal interconnect structure 424 can be used to achieve high-speed signal transmission between semiconductor dies (701, 702). In one embodiment, semiconductor dies (701, 702) may include a system-on-a-chip (SoC) die and at least one high-bandwidth memory die, and a combination of die-side redistributed interconnect 474 and die-side metal interconnect structure 424 can be used to provide high-speed communication between the SoC die and the at least one high-bandwidth memory die. Alternatively, in one embodiment, semiconductor dies (701, 702) may include a graphics processing unit (GPU) and at least one high-bandwidth memory die, and a combination of die-side redistributed interconnect 474 and die-side metal interconnect structure 424 can be used to provide high-speed communication between the GPU and the at least one high-bandwidth memory die.

[0069] refer to Figure 9 Another encapsulation (e.g., epoxy molding compound (EMC)) is applied to the gap between the semiconductor dies (701, 702). The EMC applied at this processing step can be any of the EMC materials that can be used to form the EMC intermediate frame 460 described above. The EMC is cured at a curing temperature to form an EMC matrix that laterally surrounds each of the semiconductor dies (701, 702). The EMC matrix comprises a plurality of epoxy molding compound (EMC) die frames 760 that are laterally adjacent to each other. Each EMC die frame 760 is located within a corresponding die region DA and laterally surrounds and may be formed around a corresponding set of at least one semiconductor die (701, 702) bonded to the underlying die-side redistribution structure 470. Excess portions of the EMC can be removed above a horizontal plane including the top surface of the semiconductor dies (701, 702) by a planarization process that may use chemical mechanical planarization. Typically, each EMC die frame 760 surrounds at least one semiconductor die (701, 702) in the lateral direction.

[0070] refer to Figure 10The second carrier substrate 370 can be bonded to the semiconductor dies (701, 702) and the EMC die frame 760. A suitable temporary adhesive layer 371 can be used. If the second carrier substrate 370 contains an optically transparent material, the temporary adhesive layer 371 may include a photothermal conversion (LTHC) layer. Alternatively, the temporary adhesive layer 371 may contain a thermally deactivated adhesive material. Subsequently, the die bonding film 321 between the bridging die 405 and the first carrier substrate 350 can be peeled off, for example, by performing a thermal annealing process at a temperature that deactivates the thermally released adhesive. Once the die bonding film 321 has been peeled off, the first carrier substrate 350 can be removed, for example, by cleave from the assembly including the bridging die 405, the EMC intermediate frame 460, the die-side wiring structure 470, and the semiconductor dies (701, 702).

[0071] refer to Figure 11 The die bonding film 321 can be removed, for example, using a wet cleaning process. The physically exposed surface of the bridging die 405 can be recessed vertically from the horizontal surface including the horizontal surface of the EMC mediator frame 460 and the horizontal surface of the TIV structure 486 by a vertical recess distance, which can be the same as the thickness of the die bonding film 321 before removal. For example, the vertical recess distance can be in the range of 50 micrometers to 200 micrometers.

[0072] Package-side redistribution structures 440 can be formed on the bridging die 405, EMC interposer frame 460, and TIV structure 486. Specifically, the package-side redistribution structure 440 can be formed within each die region DA of the assembly including the bridging die 405, EMC interposer frame 460, and TIV structure 486. The package-side redistribution structure 440 is a redistribution structure formed on the substrate side (i.e., the side facing the package substrate to be subsequently bonded) relative to the assembly of the bridging die 405, EMC interposer frame 460, and TIV structure 486.

[0073] Each package-side emphasis wiring structure 440 may include a package-side emphasis wiring dielectric layer 442, package-side emphasis wiring in-line interconnects 444, and package-side bonding pads 448. The package-side emphasis wiring dielectric layer 442 comprises a corresponding dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO). Each package-side emphasis wiring dielectric layer 442 can be formed by spin-coating and drying the corresponding dielectric polymer material. The thickness of each package-side emphasis wiring dielectric layer 442 may be in the range of 2 micrometers to 40 micrometers (e.g., 4 micrometers to 20 micrometers). Each package-side emphasis wiring dielectric layer 442 may be patterned, for example, by applying a corresponding photoresist layer over each package-side emphasis wiring dielectric layer 442 and patterning the corresponding photoresist layer, and transferring the pattern in the photoresist layer into the package-side emphasis wiring dielectric layer 442 using an etching process (e.g., anisotropic etching). Subsequently, the photoresist layer may be removed, for example, by ashing.

[0074] Each of the package-side interconnect 444 and the package-side bonding pad 448 can be formed by: depositing a metal seed layer by sputtering; applying a photoresist layer over the metal seed layer and patterning the photoresist layer to form an opening pattern through the photoresist layer; electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching the portion of the metal seed layer between the electroplated metal filler portions. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness in the range of 50 nm to 300 nm, and the copper seed layer may have a thickness in the range of 100 nm to 500 nm. The metal filler material of the package-side interconnect 444 may include copper, nickel, or a stack of copper and nickel. The thickness of the metal filler material deposited to form each package-side wiring inlay 444 can range from 2 micrometers to 40 micrometers (e.g., 4 micrometers to 10 micrometers), but smaller or larger thicknesses can also be used. The total number of wiring levels (i.e., the levels of package-side wiring inlays 444) in each package-side wiring structure 440 can range from 1 to 10.

[0075] The metal filler material of the package side bonding pad 448 may include copper. The thickness of the metal filler material deposited to form the package side bonding pad 448 may be in the range of 5 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used. The package side bonding pad 448 may have a rectangular, rounded rectangular, or circular horizontal cross-sectional shape. If the package side bonding pad 448 is formed as a C4 (controlled collapse die connection) pad, the thickness of the package side bonding pad 448 may be in the range of 5 micrometers to 50 micrometers, but smaller or larger thicknesses may also be used.

[0076] Typically, the package-side emphasis wiring structure 440 can be formed on each combination of the bridging die 405 and the encapsulation medium frame (e.g., the EMC medium frame 460, which is part of a continuous EMC matrix located within the respective die region DA). The package-side emphasis wiring structure can be formed directly on the package-side metal pad 438 of the respective bridging die 405 and directly on the respective EMC medium frame 460. Each combination of the bridging die 405, the EMC medium frame 460, the TIV structure 486, the die-side emphasis wiring structure 470, and the package-side emphasis wiring structure 440 within the die region DA constitutes a fan-out silicon medium 400.

[0077] Within each die region DA, the horizontal plane of the interface between the package-side metal pad 438 and the TSV structure 414 is closer than the horizontal plane of the interface between the EMC interposer frame 460 and the package-side redistribution structure 440 to the sum of the thickness of the die bonding film 321 and the thickness of the package-side metal pad 438 of at least one semiconductor die (701, 702). The horizontal plane of the interface between the package-side metal pad 438 and the package-side redistribution structure 440 is closer than the horizontal plane of the interface between the EMC interposer frame 460 and the package-side redistribution structure 440 to the at least one semiconductor die (701, 702) to the die bonding film 321 (which is located in...). Figure 8 The thickness (removed at the processing step) is [missing information].

[0078] Each fan-out silicon interposer 400 includes an integrated fan-out through-via (TIV) structure 486 that extends vertically through the EMC interposer frame 460 and electrically connects a corresponding package-side overlay interconnect 444 in the package-side overlay structure 440 to a corresponding die-side overlay interconnect 474 in the die-side overlay structure 470. In one embodiment, the horizontal plane of the interface between the package-side metal pad 438 and the TSV structure 414 is closer to the sum of the thickness of the die-side bonding film 321 and the thickness of the package-side metal pad 438 than the horizontal plane of the interface between the TIV structure 486 and the package-side overlay structure 440. The horizontal plane of the interface between the package-side metal pad 438 and the package-side redistribution structure 440 is closer to the horizontal plane of the interface between the TIV structure 486 and the package-side redistribution structure 440 than the horizontal plane of the at least one semiconductor die (701, 702) reaching the die bonding film 321 (which is in Figure 8 The thickness of the die bonding film 321 is adjusted by removing the layer at the processing step. Therefore, the interface between the TIV structure 486 and the package-side heavy wiring structure 440 in the vertical direction and the interface between the package-side metal pad 438 and the package-side heavy wiring structure 440 are biased to adjust the thickness of the die bonding film 321.

[0079] Within each die region DA, the fan-out silicon interposer 400 includes a die-side metal pad 428 that contacts the TSV structure 414 and is located between the TSV structure 414 and the at least one semiconductor die (701, 702). The die-side metal pad 428 may contact the die-side redecorated interconnect 474. The interface between the TIV structure 486 and the die-side redecorated structure 470 and the interface between the die-side metal pad 428 and the die-side redecorated structure 470 are located in the same horizontal plane.

[0080] Solder material portion 450 can be attached to package-side bonding pad 448. In embodiments where the package-side bonding pad 448 includes a C4 bonding pad, the solder material portion 450 can be a C4 solder ball, i.e., a spherical portion of solder material suitable for C4 bonding. In embodiments where the package-side bonding pad 448 includes an array of microbumps for C2 bonding, the solder material portion 450 can be a solder cap that wets the entire flat end face of the corresponding microbump and has a generally hemispherical shape.

[0081] refer to Figure 12 The assembly of the two-dimensional arrays of the fan-out silicon interposer 400, the semiconductor dies (701, 702), and the EMC die frame 760 can be peeled off from the second carrier substrate 370. A temporary adhesive layer (not shown) located between the second carrier substrate 370 and the two-dimensional arrays of the EMC die frame 760 can be peeled off by a suitable method, such as irradiating the temporary adhesive layer with ultraviolet light or using thermal annealing. Subsequently, the assembly of the two-dimensional arrays of the fan-out silicon interposer 400, the semiconductor dies (701, 702), and the EMC die frame 760 can be sawn along the saw grooves.

[0082] refer to Figure 13 , showing by Figure 12The structure shown is a sawed unit formed by monolithization. The sawed unit includes: a fan-out silicon interposer 400; at least one semiconductor die (701, 702) which is attached to the fan-out silicon interposer 400 by an array of solder material portions 490; and an EMC die frame 760. Typically, the fan-out silicon interposer 400 may include: a bridging die 405 including an array of through-silicon via (TSV) structures 414; an epoxy molding compound (EMC) interposer frame 460 laterally surrounding the bridging die 405; a die-side redistribution structure 470 including a die-side bonding pad 478 attached to at least one semiconductor die (701, 702); a package-side metal pad 438 contacting a package-side end face of the array of TSV structures 414; and a package-side redistribution structure 440 located on the package-side metal pad 438 on the opposite side of the die-side redistribution structure 470 relative to one side of the bridging die 405.

[0083] Each sidewall of the fan-out silicon interposer 400 and each sidewall of the EMC die frame 760 can be formed by sawing (e.g., by cutting through the material of the EMC interposer frame 460 and the material of the EMC die frame 760). Thus, the sidewall of the EMC die frame 760 can coincide with the sidewall of the EMC interposer frame 460 in the vertical direction. In other words, each sidewall of the EMC die frame 760 can lie entirely within a two-dimensional Euclidean vertical plane including the sidewall of the EMC interposer frame 460, and each sidewall of the EMC interposer frame 460 can lie entirely within a two-dimensional Euclidean vertical plane including the sidewall of the EMC die frame 760.

[0084] refer to Figure 14 A packaging substrate 200 may be provided. The packaging substrate 200 may be a cored packaging substrate including a core substrate 210, or a coreless packaging substrate excluding a packaging core. The core substrate 210 may include a glass epoxy sheet including an array of through-holes. An array of core through-hole structures 214 containing a metallic material may be provided in the through-holes. Each core through-hole structure 214 may or may not include a cylindrical hollow portion. Optionally, a dielectric pad 212 may be used to electrically isolate the core through-hole structure 214 from the core substrate 210.

[0085] The package substrate 200 may include a board-side surface laminate (SLC) 240 and a chip-side surface laminate (SLC) 260. The board-side SLC 240 may include a board-side insulating layer 242 in which board-side interconnects 244 are formed. The chip-side SLC 260 may include a chip-side insulating layer 262 in which chip-side interconnects 264 are formed. The board-side insulating layer 242 and the chip-side insulating layer 262 may contain a photosensitive epoxy material that can be patterned by photolithography and subsequently cured. The board-side interconnects 244 and the chip-side interconnects 264 may contain copper that can be deposited by electroplating within the patterns in the board-side insulating layer 242 or the chip-side insulating layer 262. An array of board-side bonding pads 248 may be electrically connected to the board-side interconnects 244 and may be configured to allow bonding via solder balls. An array of chip-side bonding pads 268 can be electrically connected to chip-side interconnects 264 and can be configured to allow bonding via C4 solder balls.

[0086] Solder material portions 450 of the package-side bonding pads 448 of the assembly of the fan-out silicon interposer 400, at least one semiconductor die (701, 702), and EMC die frame 760 may be disposed on an array of chip-side bonding pads 268 of the package substrate 200. A reflow process may be performed to reflow the solder material portions 450, thereby inducing bonding between the fan-out silicon interposer 400 and the package substrate 200. In one embodiment, the solder material portions 450 may include C4 solder balls, and an array of C4 solder balls may be used to bond the assembly of the fan-out silicon interposer 400, the at least one semiconductor die (701, 702), and EMC die frame 760 to the package substrate 200. Underfill portions 292 may be formed around the solder material portions 450 by applying and shaping the underfill material. Optionally, the stabilization structure 294 (e.g., a top cover structure or a ring structure) may be attached to the assembly of the fan-out silicon interposer 400, the at least one semiconductor die (701, 702), the EMC die frame 760, and the packaging substrate 200 to reduce deformation of the assembly during subsequent processing steps and / or during use of the assembly.

[0087] refer to Figure 15A printed circuit board (PCB) 100 including a PCB substrate 110 and PCB bonding pads 180 can be provided. The PCB 100 includes a printed circuit system (not shown) on at least one side of the PCB substrate 110. An array of solder joints 190 can be formed to bond an array of board-side bonding pads 248 to the array of PCB bonding pads 180. The solder joints 190 can be formed by placing an array of solder balls between the array of board-side bonding pads 248 and the array of PCB bonding pads 180, and reflowing the array of solder balls. An underfill portion 192 can be formed around the solder joints 190 by applying an underfill material and shaping the underfill material. A package substrate 200 is attached to the PCB 100 through the array of solder joints 190.

[0088] refer to Figure 16 According to embodiments of the present invention, a set of steps for a general process for forming a chip package structure is described. Referring to step 1610, an array of through-silicon via (TSV) structures 414 through a silicon substrate 410 is formed. Referring to step 1620, package-side metal pads 438 are formed on the rear surface of the array of TSV structures 414. A bridging die 405 is provided. Referring to step 1630, the bridging die 405 is disposed on a carrier substrate 350 such that the package-side metal pads 438 are closer to the carrier substrate 350 than the TSV structures 414. Referring to step 1640, an epoxy molding compound (EMC) interposer framework 460 is formed around the bridging die 405 and on the carrier substrate 350. Referring to step 1650, a die-side redistribution structure 470 is formed on the bridging die 405 and the EMC interposer framework 460. Referring to step 1660, at least one semiconductor die (701, 702) is attached to the die-side redistribution structure 470. Referring to step 1670, the carrier substrate 350 is removed from the assembly including the bridging die 405, the die-side redistribution structure 470, and the at least one semiconductor die (701, 702). Referring to step 1680, the package-side redistribution structure 440 is formed on the package-side metal pad 438 and on the EMC interposer frame 460.

[0089] refer to Figure 17This illustrates another set of general processing steps for forming a chip package structure according to an embodiment of the present disclosure. Referring to step 1601, a through-hole structure 414 is formed through the upper portion of the silicon substrate 410. Referring to step 1602, a die-side metal interconnect structure 424 is formed above the through-hole structure 414. Referring to step 1610, an array of substrate through-hole (TSV) structures 414 through the silicon substrate 410 may be formed. Referring to step 1620, package-side metal pads 438 are formed on the back surface of the array of TSV structures 414. A bridging die 405 is provided. Referring to step 1630, the bridging die 405 is disposed above a carrier substrate 350 such that the package-side metal pads 438 are closer to the carrier substrate 350 than the TSV structures 414. Referring to step 1640, an epoxy molding compound (EMC) interposer framework 460 is formed around the bridging die 405 and above the carrier substrate 350. Referring to step 1650, a die-side rewiring structure 470 is formed over the bridging die 405 and the EMC dielectric frame 460. Referring to step 1660, at least one semiconductor die (701, 702) is attached to the die-side rewiring structure 470. Then, selective execution may be performed as needed. Figure 16 Steps 1670 and 1680 in the process.

[0090] Referring to all figures and various embodiments of the present disclosure, a fan-out silicon dielectric 400 is provided. The fan-out silicon dielectric 400 includes: a bridging die 405 including an array of through-silicon via (TSV) structures 414 extending through a silicon substrate 410; an encapsulation dielectric frame, such as an epoxy molding compound (EMC) dielectric frame 460, laterally surrounding the bridging die 405; a die-side redistribution structure 470 including a die-side bonding pad 478 attached to at least one semiconductor die (701, 702); a package-side metal pad 438 contacting a package-side end face of the array of TSV structures 414; and a package-side redistribution structure 440 located on the package-side metal pad 438 on the opposite side of the die-side redistribution structure 470 relative to one side of the bridging die 405.

[0091] In the aforementioned fan-out silicon interposer, each of the package-side metal pads contacts the end face of a corresponding one of the silicon through-hole structures and has a larger horizontal cross-sectional area than the end face of the corresponding one of the silicon through-hole structures.

[0092] In the aforementioned fan-out silicon interposer, the encapsulation interposer frame is an epoxy molding compound (EMC) interposer frame, and the horizontal plane of the interface between the package-side metal pad and the silicon through-hole structure is closer to the die-side bonding pad than the horizontal plane of the interface between the epoxy molding compound interposer frame and the package-side redistribution structure.

[0093] In the aforementioned fan-out silicon interposer, the horizontal plane of the interface between the package-side metal pad and the package-side redistribution structure is closer to the die-side bonding pad than the horizontal plane of the interface between the epoxy molding compound interposer frame and the package-side redistribution structure.

[0094] In the aforementioned fan-out silicon interposer, the encapsulation interposer frame is an epoxy molding compound (EMC) interposer frame, and the fan-out silicon interposer includes an integrated fan-out through-via (TIV) structure that extends vertically through the epoxy molding compound interposer frame and electrically connects a corresponding package-side overlay interconnect in the package-side overlay wiring structure to a corresponding die-side overlay interconnect in the die-side overlay wiring structure.

[0095] In the aforementioned fan-out silicon interposer, the horizontal plane of the interface between the package-side metal pad and the silicon via structure is closer to the die-side bonding pad than the horizontal plane of the interface between the integrated fan-out silicon via structure and the package-side redistribution structure.

[0096] In the aforementioned fan-out silicon interposer, the horizontal plane of the interface between the package-side metal pad and the package-side redistribution structure is closer to the die-side bonding pad than the horizontal plane of the interface between the integrated fan-out through-hole structure and the package-side redistribution structure.

[0097] The aforementioned fan-out silicon interposer further includes: a die-side metal pad, which contacts the silicon through-hole structure and is located between the silicon through-hole structure and the die-side bonding pad; and the interface between the integrated fan-out through-hole structure and the die-side redistribution structure and the interface between the die-side metal pad and the die-side redistribution structure are located in the same horizontal plane.

[0098] In the aforementioned fan-out silicon interposer, each of the silicon through-hole structures is laterally surrounded by a corresponding cylindrical portion of a substrate-through-insulating spacer; and the silicon substrate is vertically spaced from a horizontal plane including the interface between the package-side metal pad and the silicon through-hole structure by a rear insulating layer, the rear insulating layer laterally surrounding the cylindrical portion of the substrate-through-insulating spacer.

[0099] In the aforementioned fan-out silicon interposer, the die-side bonding pads comprise an array of microbumps; and the package-side bonding pads comprise an array of controlled-collapse chip-connecting solder balls.

[0100] In the aforementioned fan-out silicon dielectric, the bridging die includes a die-side metal interconnect structure that electrically connects a corresponding TSV structure to a corresponding die-side redistribution structure.

[0101] In the aforementioned fan-out silicon interposer, the die-side metal interconnect structure includes a combination of a metal wire structure and a metal via structure, or an integrated metal wire and via structure.

[0102] According to an embodiment of the present invention, a fan-out silicon interposer 400 is provided. The fan-out silicon interposer 400 includes: a bridging die 405 including an array of through-silicon via (TSV) structures 414; a package-side metal pad 438 contacting an end face of the array of TSV structures 414; an encapsulation, such as an epoxy molding compound (EMC) interposer frame 460, laterally surrounding the bridging die 405; an integrated fan-out through-via (TIV) structure 486 extending vertically through the EMC interposer frame 460; a package-side redistribution structure 440 located on the package-side metal pad 438; and a die-side redistribution structure 470 located between the bridging die 405 and the at least one semiconductor die (701, 702) and including a die-side bonding pad 478 attached to the at least one semiconductor die (701, 702).

[0103] In the aforementioned fan-out silicon interposer, the interface between the integrated fan-out through-hole structure and the package-side heavy wiring structure is offset in the vertical direction from the interface between the package-side metal pad and the package-side heavy wiring structure.

[0104] This invention provides a method for forming a chip package structure, comprising: forming a through-hole structure through an upper portion of a silicon substrate; forming a die-side metal interconnect structure above the through-hole structure; forming an array of through-silicon via (TSV) structures through the silicon substrate by thinning the rear side of the silicon substrate, wherein the through-hole structures extend vertically through the entire thickness of the thinned silicon substrate to form the array of TSV structures; forming package-side metal pads on the rear surface of the array of TSV structures, thereby forming a bridging die; disposing the bridging die on a carrier substrate such that the package-side metal pads are closer to the carrier substrate than the TSV structures; forming an encapsulation intermediate frame around the bridging die and above the carrier substrate; forming a die-side redistribution structure above the bridging die and the encapsulation intermediate frame; and attaching at least one semiconductor die to the die-side redistribution structure.

[0105] In the above method, each of the package-side metal pads is directly formed on the end face of the corresponding one in the silicon through-hole structure and has a larger horizontal cross-sectional area than the end face of the corresponding one in the silicon through-hole structure.

[0106] The above method further includes: removing the carrier substrate from the assembly including the bridge die, the die-side wiring structure and the at least one semiconductor die; and forming the package-side wiring structure on the package-side metal pad and on the encapsulation intermediate frame.

[0107] In the above method, the following are included: the die-side metal interconnect structure includes a die-side metal pad located at the topmost layer; the bridge die is attached to the carrier substrate by providing a die attachment film between the carrier substrate and the bridge die; and the die attachment film is removed after the at least one semiconductor die is attached to the die-side redistribution structure.

[0108] In the above method, the encapsulation intermediate frame is an epoxy molding compound (EMC) intermediate frame, and the package-side rewiring structure is directly formed on the epoxy molding compound intermediate frame and the package-side metal pad; and the horizontal plane including the interface between the package-side metal pad and the package-side rewiring structure is recessed toward the at least one semiconductor die by the thickness of the die bonding film relative to the horizontal plane including the interface between the epoxy molding compound intermediate frame and the package-side rewiring structure.

[0109] The above method also includes: using controlled collapse chip-connecting solder balls to bond the structure including the assembly and the package-side wiring structure to the package substrate.

[0110] Various structures and methods disclosed herein can be used to provide a fan-out silicon interposer 400, in which a bridging die 405 containing an array of TSV structures 414 and an array of TIV structures 486 may be formed. Since the bridging die 405 is placed within the array of TIV structures 486 via a pick-and-place operation, alignment variations between the array of TSV structures 414 and the array of TIV structures 486 are inherent. The effects of these alignment variations can be minimized during the formation of the package-side redistribution structure 440 by using package-side metal pads 438. The package-side metal pads 438 contact the end faces of the array of TSV structures 414 and have a larger area than the end faces of the array of TSV structures 414. Therefore, during the formation of the package-side redistribution interconnects 444, the package-side metal pads 438 provide a larger contact area than the corresponding end faces of the underlying TSV structures 414. The impact of overlap variations between the bridging die 405 and the TIV structure 486 is reduced by using package-side metal pads 438. The fan-out silicon interposer 400 can be manufactured with higher process yields and provides enhanced reliability throughout its lifespan.

[0111] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A chip packaging structure, characterized in that it includes a fan-out silicon interposer and at least one semiconductor die bonded to the fan-out silicon interposer, wherein the fan-out silicon interposer comprises: Bridge core, comprising an array of silicon through-hole structures extending through a silicon substrate; An encapsulating intermediate frame surrounds the bridge tube core laterally; A die-side wiring structure includes a die-side bonding pad, wherein the at least one semiconductor die is attached to the die-side bonding pad. The package-side metal pad contacts the package-side end face of the array of through-silicon via structures; as well as The package-side emphasis wiring structure is located on the package-side metal pad on the opposite side of the die-side emphasis wiring structure relative to the bridging die. The horizontal surface between the bridging die and the package-side wiring structure is closer to the at least one semiconductor die than the horizontal surface between the encapsulation interposer frame and the package-side wiring structure. This includes the fact that the horizontal plane of the interface between the package-side metal pad and the package-side rewiring structure is closer to the at least one semiconductor die than the horizontal plane of the interface between the encapsulation intermediate frame and the package-side rewiring structure.

2. The chip packaging structure of claim 1, wherein each of the package-side metal pads contacts the end face of a corresponding one of the through-silicon via structures and has a larger horizontal cross-sectional area than the end face of the corresponding one of the through-silicon via structures.

3. The chip packaging structure according to claim 1, wherein the encapsulation intermediate frame is an epoxy molding compound intermediate frame, and the horizontal plane including the interface between the package-side metal pad and the silicon through-hole structure is closer to the at least one semiconductor die than the horizontal plane including the interface between the encapsulation intermediate frame and the package-side redistribution structure.

4. The chip packaging structure according to claim 1, wherein the encapsulation intermediate frame is an epoxy molding compound intermediate frame, and wherein the fan-out silicon intermediate includes an integrated fan-out through-hole structure, the integrated fan-out through-hole structure extending vertically through the epoxy molding compound intermediate frame and electrically connecting a corresponding package-side wiring in the package-side wiring structure to a corresponding die-side wiring in the die-side wiring structure.

5. The chip packaging structure according to claim 4, wherein the horizontal plane of the interface between the package-side metal pad and the through-silicon via structure is closer to the at least one semiconductor die than the horizontal plane of the interface between the integrated fan-out through-silicon via structure and the package-side redistribution structure.

6. The chip packaging structure of claim 5, wherein the horizontal plane of the interface between the package-side metal pad and the package-side redistribution structure is closer to the at least one semiconductor die than the horizontal plane of the interface between the integrated fan-out via structure and the package-side redistribution structure.

7. The chip packaging structure according to claim 4, wherein: The fan-out silicon interposer includes a die-side metal pad that contacts the through-silicon via structure and is located between the through-silicon via structure and the at least one semiconductor die; and The interface between the integrated fan-out perforated structure and the die-side heavy wiring structure and the interface between the die-side metal pad and the die-side heavy wiring structure are located in the same horizontal plane.

8. The chip packaging structure according to claim 1, wherein: Each of the aforementioned through-silicon via structures is laterally surrounded by a corresponding cylindrical portion of a substrate-through insulating spacer; and The silicon substrate is vertically spaced from the horizontal plane, which includes the interface between the package-side metal pad and the silicon through-hole structure, by a rear insulating layer, and the rear insulating layer laterally surrounds the cylindrical portion of the insulating spacer around the substrate.

9. The chip packaging structure according to claim 1, wherein: The at least one semiconductor die is attached to the die-side wiring structure via an array of microbumps; and The chip packaging structure also includes a packaging substrate, and the fan-out silicon interposer is attached to the packaging substrate through an array of controlled collapse chip-connected solder balls.

10. The chip packaging structure according to claim 9, wherein the packaging substrate is attached to the printed circuit board via an array of solder joints.

11. The chip packaging structure of claim 1, further comprising an epoxy molding compound die frame laterally surrounding the at least one semiconductor die, wherein the sidewalls of the epoxy molding compound die frame coincide with the sidewalls of the epoxy molding compound intermediate frame in the vertical direction.

12. A chip packaging structure, characterized in that... It includes at least one semiconductor die and a fan-out silicon interposer, the fan-out silicon interposer comprising: Bridged tube die, including an array of through-silicon via structures; The package-side metal pad contacts the end face of the array of through-silicon via structures; An encapsulating intermediate frame surrounds the bridge tube core laterally; An integrated fan-out perforated structure extends vertically through the encapsulation mediator frame; The package side wiring structure is located on the package side metal pads; and The die-side wiring structure is located between the bridging die and the at least one semiconductor die and includes a die-side bonding pad that is attached to the at least one semiconductor die. The horizontal surface between the bridge die and the package-side heavy-wire structure is closer to the at least one semiconductor die than the horizontal surface between the encapsulation interposer frame and the package-side heavy-wire structure, including the horizontal surface of the interface between the integrated fan-out via structure and the package-side heavy-wire structure being further away from the die-side heavy-wire structure in the vertical direction than the horizontal surface of the interface between the package-side metal pad and the package-side heavy-wire structure.

13. A method for forming a chip package structure, characterized in that... include: An array of silicon through-hole structures is formed that penetrate the silicon substrate; A package-side metal pad is formed on the rear surface of the array of silicon through-hole structures, thereby forming a bridge die; The bridge tube is disposed on the carrier substrate, such that the package-side metal pad is closer to the carrier substrate than the silicon through-hole structure; An encapsulation medium framework is formed around the bridge tube core and on the carrier substrate; A core-side wiring structure is formed on the bridge tube core and the encapsulation intermediate frame; At least one semiconductor die is attached to the die-side wiring structure, while the carrier substrate is attached to the bridge die and the encapsulation intermediate frame. as well as Remove the carrier substrate from the assembly including the bridge die, the die-side wiring structure and the at least one semiconductor die; as well as A package-side heavy-wire structure is formed on the bridge die and the encapsulation intermediate frame, wherein the horizontal plane of the interface between the package-side metal pad and the package-side heavy-wire structure is closer to the at least one semiconductor die than the horizontal plane of the interface between the encapsulation intermediate frame and the package-side heavy-wire structure.

14. The method for forming a chip package structure according to claim 13, further comprising: An array of openings extending from the front surface of the silicon substrate toward the rear surface of the silicon substrate; The array of the silicon through-hole structure is formed by depositing at least one conductive material in the array of the openings; as well as The back side of the silicon substrate is thinned, wherein the bottom surface of the silicon through-hole structure is solidly exposed.

15. The method for forming a chip package structure according to claim 13, further comprising: The first surface of the die bonding film is bonded to the metal pad on the packaging side; Before forming the encapsulation intermediate framework, the second surface of the die bonding film is bonded to the carrier substrate; as well as After removing the carrier substrate from the assembly, the die bonding film is removed.

16. The method for forming a chip package structure according to claim 15, wherein: The encapsulation intermediate framework is an epoxy molding compound intermediate framework, and the encapsulation-side wiring structure is directly formed on the epoxy molding compound intermediate framework and the encapsulation-side metal pad. as well as The horizontal plane of the interface between the package-side metal pad and the package-side redistribution structure is recessed toward the at least one semiconductor die by the thickness of the die bonding film relative to the horizontal plane of the interface between the epoxy molding compound intermediate frame and the package-side redistribution structure.

17. The method of forming a chip package structure according to claim 13, wherein each of the package-side metal pads is formed directly on the end face of a corresponding one in the through-silicon via structure and has a larger horizontal cross-sectional area than the end face of the corresponding one in the through-silicon via structure.

18. The method for forming a chip package structure according to claim 13, further comprising: A package-side heavy wiring structure is formed on the package-side metal pads and the encapsulation intermediate frame; as well as The structure, including the assembly and the package-side wiring structure, is bonded to the package substrate using controlled collapse chip-connecting solder balls.

19. A fan-out silicon interposer, characterized in that... include: The bridging die includes an array of silicon through-hole structures extending through a silicon substrate, a package-side metal pad contacting the package-side end face of the array of silicon through-hole structures, and a package-side dielectric material layer laterally surrounding the package-side metal pad. An encapsulating intermediate frame surrounds the bridge tube core laterally; The die-side wiring structure includes die-side bonding pads; as well as The package-side heavy wiring structure is located on the package-side metal pad and in contact with the package-side dielectric material layer of the bridge tube on the opposite side of the die-side heavy wiring structure relative to the bridge tube die. This includes a horizontal plane of the interface between the package-side metal pad and the package-side heavy wiring structure that is closer to the die-side bonding pad than the horizontal plane of the interface between the encapsulation intermediate frame and the package-side heavy wiring structure.

20. The fan-out silicon interposer of claim 19, wherein each of the package-side metal pads contacts the end face of a corresponding one of the silicon through-hole structures and has a larger horizontal cross-sectional area than the end face of the corresponding one of the silicon through-hole structures.

21. The fan-out silicon interposer of claim 19, wherein the encapsulation interposer frame is an epoxy molding compound interposer frame, and the horizontal plane including the interface between the package-side metal pad and the silicon through-hole structure is closer to the die-side bonding pad than the horizontal plane including the interface between the epoxy molding compound interposer frame and the package-side redistribution structure.

22. The fan-out silicon interposer of claim 19, wherein the encapsulation interposer frame is an epoxy molding compound interposer frame, and wherein the fan-out silicon interposer includes an integrated fan-out through-hole structure that extends vertically through the epoxy molding compound interposer frame and electrically connects a corresponding package-side overlay interconnect in the package-side overlay wiring structure to a corresponding die-side overlay interconnect in the die-side overlay wiring structure.

23. The fan-out silicon interposer of claim 22, wherein the horizontal plane of the interface between the package-side metal pad and the silicon via structure is closer to the die-side bonding pad than the horizontal plane of the interface between the integrated fan-out silicon via structure and the package-side redistribution structure.

24. The fan-out silicon interposer of claim 23, wherein the horizontal plane of the interface between the package-side metal pad and the package-side redistribution structure is closer to the die-side bonding pad than the horizontal plane of the interface between the integrated fan-out through-hole structure and the package-side redistribution structure.

25. The fan-out silicon interposer according to claim 22, further comprising: A die-side metal pad, the die-side metal pad contacting the through-silicon via structure and located between the through-silicon via structure and the die-side bonding pad; and The interface between the integrated fan-out perforated structure and the die-side heavy wiring structure and the interface between the die-side metal pad and the die-side heavy wiring structure are located in the same horizontal plane.

26. The fan-out silicon interposer according to claim 19, wherein: Each of the aforementioned through-silicon via structures is laterally surrounded by a corresponding cylindrical portion of a substrate-through insulating spacer; and The silicon substrate is vertically spaced from the horizontal plane, which includes the interface between the package-side metal pad and the silicon through-hole structure, by a rear insulating layer, and the rear insulating layer laterally surrounds the cylindrical portion of the insulating spacer around the substrate.

27. The fan-out silicon interposer of claim 19, wherein the die-side bonding pad comprises an array of microbumps; and The package-side bonding pads include an array of controlled-collapse chip-connecting solder balls, wherein the package-side bonding pads are located on the package-side redistribution structure and electrically connected to a corresponding one of the package-side metal pads.

28. The fan-out silicon interposer of claim 19, wherein the bridging die includes a die-side metal interconnect structure that electrically connects a corresponding silicon via structure to a corresponding die-side redistribution structure.

29. The fan-out silicon interposer of claim 28, wherein the die-side metal interconnect structure comprises a combination of a metal wire structure and a metal via structure, or an integrated metal wire and via structure.

30. A fan-out silicon interposer, characterized in that... include: The bridge die includes an array of through-silicon via structures, with package-side metal pads contacting the end faces of the package-side metal pads of the array of through-silicon via structures, and a package-side gold dielectric material layer laterally surrounding the contact package-side metal pads. An encapsulating intermediate frame surrounds the bridge tube core laterally; An integrated fan-out perforated structure extends vertically through the encapsulation mediator frame; The package focuses on the wiring structure, and the package-side gold dielectric material layer is located on the package-side metal pad and contacts the bridge tube core; as well as A die-side heavy-wire structure is electrically connected to an array of silicon through-hole structures and includes die-side bonding pads, wherein the horizontal plane of the interface between the integrated fan-out through-hole structure and the package-side heavy-wire structure is further away from the die-side heavy-wire structure in the vertical direction than the horizontal plane of the interface between the package-side metal pads and the package-side heavy-wire structure.

31. A method for forming a chip package structure, characterized in that... include: Forming a through-hole structure that penetrates the upper portion of the silicon substrate; A core-side metal interconnect structure is formed above the through-hole structure; An array of through-silicon via structures is formed by thinning the back side of the silicon substrate, wherein the via structures extend vertically through the entire thickness of the thinned silicon substrate to form the array of through-silicon via structures. A package-side metal pad, which is laterally surrounded by a package-side dielectric layer, is formed on the rear surface of the array of silicon through-hole structures, thereby forming a bridge-side die. The bridge tube core is disposed on the carrier substrate; An encapsulation medium framework is formed around the bridge tube core and on the carrier substrate; A core-side wiring structure is formed on the bridge tube core and the encapsulation intermediate frame; At least one semiconductor die is attached to the die-side wiring structure; as well as A packaged test wiring structure is formed, wherein the packaged test wiring structure includes a packaged side dielectric material layer located on the packaged side metal pad and in contact with the bridge die, wherein the horizontal plane of the interface between the packaged side metal pad and the packaged side test wiring structure is closer to the at least one semiconductor die than the horizontal plane of the interface between the encapsulation intermediate frame and the packaged side test wiring structure.

32. The method of forming a chip package structure according to claim 31, wherein each of the package-side metal pads is formed directly on the end face of a corresponding one in the through-silicon via structure and has a larger horizontal cross-sectional area than the end face of the corresponding one in the through-silicon via structure.

33. The method for forming a chip package structure according to claim 31, further comprising: Remove the carrier substrate from the assembly including the bridge die, the die-side wiring structure, and the at least one semiconductor die.

34. The method for forming a chip package structure according to claim 33, wherein: The core-side metal interconnect structure includes a core-side metal pad located at the topmost level. The bridge tube core is attached to the carrier substrate by providing a die attachment film between the carrier substrate and the bridge tube core. as well as The die attachment film is removed after the at least one semiconductor die is attached to the die-side redistribution structure.

35. The method for forming a chip package structure according to claim 34, wherein... The encapsulation intermediate framework is an epoxy molding compound intermediate framework, and the encapsulation-side wiring structure is directly formed on the epoxy molding compound intermediate framework and the encapsulation-side metal pads; and The horizontal plane of the interface between the package-side metal pad and the package-side redistribution structure is recessed toward the at least one semiconductor die by the thickness of the die attachment film relative to the horizontal plane of the interface between the epoxy molding compound intermediate frame and the package-side redistribution structure.

36. The method for forming a chip package structure according to claim 33, further comprising: The structure, including the assembly and the package-side wiring structure, is bonded to the package substrate using controlled collapse chip-connecting solder balls.

37. A fan-out silicon interposer, characterized in that... include: Bridge core, comprising an array of silicon through-hole structures extending through a silicon substrate and including metal pads; The integrated fan-out perforated structure is located next to the bridge tube core; The encapsulation body laterally surrounds the bridge tube core and the integrated fan-out perforated structure; The first layer of wiring structure is located on the bridge pipe core; as well as The second rewiring structure is located on the opposite side of the first rewiring structure relative to the bridge connector core, wherein the metal pads are located between the array of silicon via structures and the second rewiring structure, including that the horizontal plane of the interface between the metal pads and the first rewiring structure is closer to the second rewiring structure than the horizontal plane of the interface between the encapsulation and the first rewiring structure.

38. The fan-out silicon interposer of claim 37, wherein the integrated fan-out through-hole structure extends vertically through the encapsulation and electrically connects a corresponding first-layer interconnect in the first rewiring structure to a corresponding second-layer interconnect in the second rewiring structure.

39. The fan-out silicon interposer of claim 37, wherein the bridging core includes a metal interconnect structure electrically connecting a corresponding one of the silicon through-hole structures and a corresponding one of the metal pads.

40. The fan-out silicon interposer of claim 39, wherein the metal interconnect structure comprises a combination of a metal wire structure and a metal via structure, or an integrated metal wire and via structure.

41. The fan-out silicon interposer of claim 37, wherein the bridging core includes an additional metal pad having a width greater than the end face of the silicon through-hole structure.

42. The fan-out silicon interposer of claim 41, wherein the interface between the integrated fan-out through-hole structure and the second rewiring structure lies in the same horizontal plane as the interface between the additional metal pad and the second rewiring structure.

43. The fan-out silicon interposer according to claim 41, wherein: Each of the aforementioned through-silicon via structures is laterally surrounded by a corresponding cylindrical portion of a substrate-through insulating spacer; and The silicon substrate is vertically spaced from the horizontal plane, which includes the interface between the metal pad and the silicon via structure, by a rear insulating layer, the rear insulating layer laterally surrounding the cylindrical portion of the insulating spacer.

44. A fan-out silicon interposer, characterized in that... include: The bridge core includes an array of through-silicon via structures extending through a silicon substrate, a first metal pad contacting a first end face of the array of through-silicon via structures, and a first dielectric material layer laterally surrounding the first metal pad. Encapsulation body, laterally surrounding the bridge tube core; The first layer of wiring structure includes interconnects within the first layer of wiring, with non-zero alignment covering and contacting the first metal pad. as well as The second rewiring structure includes a second metal pad located on the opposite side of the first rewiring structure relative to the bridge tube core, wherein the horizontal plane of the interface between the first metal pad and the first rewiring structure is closer to the second rewiring structure than the horizontal plane of the interface between the encapsulator and the first rewiring structure.

45. The fan-out silicon interposer of claim 44, wherein one of the first metal pads contacts the end face of a corresponding one of the silicon through-hole structures and has a horizontal cross-sectional area greater than that of the end face of the corresponding one of the silicon through-hole structures.

46. ​​The fan-out silicon interposer of claim 44, wherein the horizontal plane of the interface between the first metal pad and the silicon through-hole structure is closer to the second rewiring structure than the horizontal plane of the interface between the encapsulator and the first rewiring structure.

47. The fan-out silicon interposer of claim 44 further includes an integrated fan-out through-hole structure that extends vertically through the encapsulation and electrically connects a corresponding first-layer interconnect in the first rewiring structure to a corresponding second-layer interconnect in the second rewiring structure.

48. The fan-out silicon interposer of claim 47, wherein the horizontal plane of the interface between the first metal pad and the first rewiring structure is closer to the second rewiring structure than the horizontal plane of the interface between the integrated fan-out via structure and the first rewiring structure.

49. The fan-out silicon interposer of claim 44, wherein the bridging core includes a metal interconnect structure providing an electrical connection between a corresponding one of the silicon through-hole structures and a corresponding one of the second metal pads.

50. The fan-out silicon interposer according to claim 44, wherein: The second metal pad includes an array of microbumps; as well as The first rewiring structure includes an array of first pads comprising controlled collapse chip connection pads, wherein the first pads are electrically connected to a corresponding one of the first metal pads via first rewiring interconnects of the first rewiring structure.

51. A fan-out silicon interposer, characterized in that... include: The bridge core includes an array of through-silicon via structures extending through a silicon substrate, a first metal pad contacting a first end face of the array of through-silicon via structures, and a first dielectric material layer laterally surrounding the first metal pad. The encapsulation body laterally encapsulates the bridge pipe core and the first metal pad; The first wiring structure is located on the first metal pad and contacts the first dielectric material layer of the bridge tube core; as well as The second rewiring structure includes a second pad located on the opposite side of the first rewiring structure relative to the bridge tube core, wherein the horizontal plane of the interface between the first metal pad and the first rewiring structure is closer to the second rewiring structure than the horizontal plane of the interface between the encapsulation and the first rewiring structure.

52. The fan-out silicon interposer of claim 51, wherein each of the first metal pads contacts the end face of a corresponding one of the silicon through-hole structures and has a horizontal cross-sectional area greater than the end face of the corresponding one of the silicon through-hole structures.

53. The fan-out silicon interposer of claim 52, wherein the sidewall of the first dielectric material layer is in direct contact with the encapsulation.

54. The fan-out silicon interposer of claim 52, wherein the first rewiring structure includes first rewiring interconnects that are non-zero aligned and cover the first metal pad.

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