High-speed multi-port cache arbiter with variable word length

Abstract

The invention discloses a high-speed multi-port cache arbiter with a variable word length. Along with the high-speed development of the modern network technology, storage management and scheduling take up most of time in the processing of data packets by network equipment, so that the low-speed caching capability of most memories becomes a bottleneck for limiting the further improvement of a network processor. Therefore, by managing the shared cache of not less than 32 blocks of 256Kbit SRAM units and supporting simultaneous cache writing of a plurality of ports through an arbitration mechanism, write scheduling and read scheduling can be realized without mutual influence, and concurrent read-write conflicts are avoided; meanwhile, each port supports eight priority queues, so that the data transmission bandwidth of each port can reach 1G bps; by processing a data packet, caching and data scheduling according to packets are supported, the length of the data packet is 64-1024 bytes variable, and the influence of the length of the data packet on memory resources can be avoided; and the purpose of storing resources can be achieved by dynamically adjusting space saving through memory recovery, and the data storage efficiency is improved.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design, computer architecture, and high-performance data storage technology. Specifically, it relates to the design and implementation method of a high-speed, multi-port cache arbitrator with variable word length for use in scenarios requiring high-concurrency data access, such as multi-core processors, network switching chips, graphics processors, and artificial intelligence accelerators. Background Technology

[0002] With the rapid development of network technology and the continuous improvement of data transmission rates, the demand for high-speed data processing and storage is also increasing. High-speed cache multi-port management modules have emerged in this context, and their underlying technologies can be summarized as the need for high-speed data processing, storage system optimization, and cache management challenges.

[0003] Traditional single-port caching struggles to meet the demands of multi-core processors or high-bandwidth networks. To support simultaneous access to the cache by multiple processors or ports, multi-port caching technology has emerged. Multi-port caching offers higher bandwidth and lower latency, meeting the needs of high-speed data processing; it can also optimize the storage system to meet the demands of increasingly high-speed networks. As a bridge between the CPU and main memory, cache significantly improves data access speed; however, in multi-port caching systems, the fair and efficient allocation of cache resources is a significant challenge. Factors such as request priority, packet priority, and cache resource utilization must be considered. When multiple ports access the cache simultaneously, an effective concurrency control mechanism needs to be designed to avoid data conflicts and access bottlenecks, while ensuring that the data in the cache remains consistent with the data in main memory or other caches. Summary of the Invention

[0004] In view of this, the present invention addresses the problems existing in the prior art by proposing a high-speed, multi-port cache arbitrator with variable word length to meet the needs of high-speed data processing and optimize cache management. It avoids the impact of packet length and the number of memory data channels on memory resources, and can dynamically adjust space through memory reclamation to save storage resources and improve data storage efficiency.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: a high-speed multi-port cache arbitrator with variable word length, the architecture of which mainly includes six parts: an input data FIFO module, a write-to-SRAM decision module, a write-to-SRAM control module, a status table module, a priority FIFO module, and a write-to-SRAM control module.

[0006] After the data stream enters, it is first stored in a FIFO, and the data length of each frame is calculated simultaneously. Then, the decision module (JUDGE) allocates the data to the corresponding SRAM based on the information in the control frame (output port, data length), while ensuring that writes to the SRAM of the 16 input ports do not conflict. The allocation is based on the real-time SRAM status table, and the status table information is updated promptly. The address and length information of the data after decision are stored in the priority FIFO. The design module is described below:

[0007] 1. Input buffer FIFO design

[0008] In the Vivado tool, the read / write latency of the FIFO instantiated in the IP core is one clock cycle. The read signal for the control frame is derived from the write arbitration and then passed to the SRAM write control module, which then retrieves the corresponding information from the input buffer FIFO. Each data write to SRAM requires a one-clock-cycle delay before being loaded. To eliminate this latency, a contiguous space consisting of registers is defined. Writes and reads are performed according to the read / write pointers, preparing the information for the next output in advance. When the read enable signal arrives, the data is output.

[0009] 2. Include in arbitration

[0010] A control frame status table is set up, initially set to 0, indicating that no control frame data has been read. Therefore, the first input data is directly read from the output. Each time the IDLE state is entered, the current input control information is captured. Then, a judgment state is entered: if the output port has corresponding input port data, the control frame data is updated, and the system enters the arbitration state; otherwise, it returns to IDLE to re-judge. In the arbitration state, the corresponding SRAM status table is selected based on the previously obtained data for judgment, choosing an idle position. If no idle position is found, the system continues until a successful selection is made before moving to the next state. Finally, all information obtained from the arbitration is output to the SRAM control module for data extraction. In the next cycle, the system waits for the priority FIFO to become writable before writing the data. After the entire process is complete, the system returns to the initial IDLE state.

[0011] 3. SRAM Write Control

[0012] The focus of this module is the mapping between output ports, input ports, and SRAM serial numbers. To enhance code readability and conciseness, we will discuss the SRAM serial numbers in terms of odd and even cases. First, we will bind the output ports to the SRAM serial numbers: taking the output port i as an example, its corresponding SRAM serial numbers are two (2*i, 2*(i+1)).

[0013] 4. Status Table

[0014] The write and read signals are processed synchronously to obtain summary information, including an SRAM occupancy table and an SRAM status table, indicating whether the RAM is readable or writable.

[0015] 5. Priority FIFO

[0016] Based on the length of temporary data stored in the queue, priority level, and SRAM location information.

[0017] 6. SRAM read control

[0018] The QoS scheduling of priority FIFOs supports both strict priority and WRR scheduling, and allows selection of the scheduling method via parameters. Strict priority scheduling: This involves iterating through the eight priority FIFOs corresponding to a port from the highest priority (1) to the lowest priority (8). After a high-priority FIFO is emptied, lower-priority FIFOs are read sequentially. Only after all high-priority queues have been scheduled can low-priority queues have a chance to be scheduled. This scheduling method is relatively simple and intuitive, ensuring that high-priority urgent tasks are processed as quickly as possible, and is suitable for scenarios with high real-time requirements. WRR polling scheduling: WRR is implemented by setting a counter for each priority queue and initializing it according to its weight. Each time a priority FIFO is polled, the FIFO outputs the corresponding data and the counter is decremented. When the counter reaches 0, scheduling of that priority queue stops, but scheduling of other queues with non-zero counters continues. When all queue counters reach 0, all counters are re-initialized according to their weights, and a new round of scheduling begins. This scheduling method ensures that every task has a chance to be processed, avoiding the starvation problem where low-priority tasks are constantly preempted by high-priority tasks.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] Compared to existing technologies, this solution supports simultaneous read and write operations on multiple ports without mutual interference, significantly improving read and write efficiency and avoiding data conflicts and access bottlenecks. It also supports managing at least 32 256K-bit SRAM cells, achieving a capacity of 8M-bit. Each port supports 8 priority queues, caching data according to the queue. Data packet length is controlled at the byte level, supporting packet-based caching and scheduling. Data packet lengths range from 64 to 1024 bytes, avoiding the impact of data packet length and the number of memory data channels on memory resources. Read parameters can be set, allowing selection of strict priority or WRR scheduling. Memory reclamation is supported, reallocating read-out memory space and greatly improving SRAM resource utilization. Attached Figure Description

[0021] Figure 1This is a diagram illustrating the overall architecture of a high-speed multi-port cache arbitrator with variable word length proposed in this invention.

[0022] Figure 2 This invention relates to a frame format within a data packet of a high-speed multi-port buffered arbitrator with variable word length.

[0023] Figure 3 This is a write / read timing diagram of a high-speed multi-port cache arbitrator with variable word length proposed in this invention;

[0024] Figure 4 This is a flowchart of the write arbitration module of a high-speed multi-port cache arbitrator with variable word length proposed in this invention;

[0025] Figure 5 This is a flowchart of the read arbitration module of a high-speed multi-port cache arbitrator with variable word length proposed in this invention.

[0026] The diagram illustrates:

[0027] The SRAM module contains at least 32 256K-bit SRAM cells; the JUDGE module is the arbitration write management module; SRAM_STATE is the SRAM status table indicator module, which is the core implementation for memory reclamation. IN_FIFO indicates that 16 input ports store data frames and control frames into their respective FIFOs; DATA_FIFO is the temporary data frame storage module, and CONTOL_FIFO is the temporary control frame storage module. SRAM_WR_CONTROL and SRAM_RD_CONTROL are the core arbitration modules of this invention.

[0028] Figure 3 The interfaces in the timing diagram include: clk (clock), wr_sop (write flag signal), wr_vld (data packet valid flag signal), wr_data (data packet signal), and wr_eop (read signal). Detailed Implementation

[0029] To enhance understanding of the present invention, the following detailed description of the embodiment is provided in conjunction with the accompanying drawings:

[0030] Example 1 ： The resource configuration includes 16 input / output ports and a shared cache consisting of 32 256kb SRAM chips; see [link / reference] Figure 2 Data may be written and written simultaneously, and follows the rules. Figure 3 Timing standards. See [link / reference]. Figure 1 A high-speed multi-port cache arbitrator with variable word length, whose core architecture mainly includes: an input data FIFO module, a write-to-SRAM decision module, a write-to-SRAM control module, a status table module, and a priority FIFO module.

[0031] The method of using a high-speed multi-port cache arbitrator with variable word length as described in this embodiment includes the following steps:

[0032] Step 1: When the data input flag wr_sop is detected in the initial state IDLE, the control information of the first frame is temporarily stored in the register. The data frame is first stored in DATA_FIFO, and the length information of the data is calculated. After the storage is completed, the length information is combined with the control information and written into CONTOL_FIFO.

[0033] Step 2, see Figure 4 When a control frame is ready at an input port, the system enters the decision state. In DECIDE1, the 16 input port numbers are mapped to the output port numbers, and the successfully matching input ports are selected. The system then jumps to DECIDE2 to determine the location of the data stored in the SRAM and to select the appropriate SRAM granularity. In DECIDE3, the system determines whether the arbitration in the SRAM was successful and the storage address was successfully determined. After successful arbitration, in the JUDEGE1 state, four pieces of information are obtained: the SRAM (odd / even) sequence number, the specific absolute address of the selected SRAM granularity, the data packet length, and the data priority. The absolute address for storing the data in the SRAM can be calculated based on this information. After successfully selecting the absolute address, the system enters the JUDGE2 state, where an SRAM control information valid signal is sent to the SRAM for writing. In the PUT_IN state, the control information is written to PRIOTY_FIFO, waiting to be read when the output port is idle.

[0034] Step 3: In the JUDGE2 state described in step 2, the SRAM that receives the control signal is written, and the write is completed by using a counter based on the data length.

[0035] Step 4, see Figure 5 As long as the FIFO of any priority on each port is not empty, packet output can begin. After priority scheduling (FIFO_PRIORITY_RD state) is completed, the output data of the currently selected priority FIFO is parsed to determine which of the two SRAMs under that port the current packet is stored in, at what granularity, and with the starting address and read length. Then, in the BLOCK1_RD state, the corresponding SRAM is enabled and the corresponding length of data is read out. During packet output, a valid signal is sent to the status table module after each granularity block is emptied or after the last frame of data is output, updating the SRAM occupancy information at the corresponding location.

[0036] The decision-making process mentioned above requires the use of SRAM_STATE to indicate the available SRAM, which can reflect the current write occupancy status of each SRAM region in real time, as well as whether valid data has been stored, thereby guiding the writing end to select the target SRAM region for writing.

[0037] In summary, the variable-length high-speed multi-port cache arbitrator of this invention has the following main features: 1. The shared cache consists of multiple SRAM cells, which are managed in a unified manner by the variable-length high-speed multi-port cache arbitrator of this invention; 2. The SRAM is internally divided into 8 granularities, with the granularities of the 256kb SRAM being 1024B, 896B, 768B, 640B, 512B, 384B, 256B, and 128B respectively. The appropriate granularity is selected for storage based on the length of the input data; 3. The read / write occupancy status of the SRAM is indicated through a dual SRAM status table; 4. Two read scheduling methods are supported: strict priority and WRR scheduling; 5. Simultaneous read and write operations on input and output ports are supported without interference.

[0038] The criteria for distinguishing whether something belongs to this architecture design are as follows:

[0039] (a) The architecture mainly consists of six parts: an input data FIFO module, a write-to-SRAM decision module, a write-to-SRAM control module, and a write-to-SRAM control module.

[0040] The module includes a control module, a status table module, a priority FIFO module, and a read SRAM control module.

[0041] (b) The shared cache consists of multiple SRAM blocks of the same capacity to provide temporary storage for high-speed input data;

[0042] (c) Divide the shared SRAM cells into odd and even blocks, and ping-pong map the free SRAM in the odd or even blocks according to the write port number. The SRAM storage granularity is divided into 8 storage levels.

[0043] (d) During arbitration writing, the closest granularity in SRAM is selected for storage based on the data length of the data packet;

[0044] (e) Supports data packet input with a single-byte step size and a packet length between 64B and 1024B.

[0045] (f) The SRAM status table module updates two aspects of information in real time: the input port number and whether it is occupied for each SRAM, and the detailed occupancy of each SRAM (the storage status of the corresponding 8 granularities in each SRAM block).

[0046] (g) Reclaim memory based on the SRAM status table.

[0047] (h) Supports simultaneous reading and writing of input and output ports without interference.

[0048] (i) During reading, the QoS scheduling of priority FIFO supports scheduling according to strict priority and WRR.

[0049] A structure that meets the above nine conditions should be considered a high-speed, multi-port cache arbiter with variable word length.

[0050] Any aspects of this invention not described in detail are well-known to those skilled in the art.

[0051] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A high-speed multi-port cache arbitrator with variable word length, characterized in that, The architecture mainly includes six parts: input data FIFO module, write SRAM decision module, write SRAM control module, state table module, priority FIFO module and read SRAM control module.

2. A variable word length high speed multi-port cache arbiter, characterized by, Multiple blocks of SRAM with the same capacity constitute a part of shared space for temporary storage of input data.

3. The variable word length high speed multi-port cache arbiter of claim 1, wherein, When arbitrating writing, the closest granularity in the SRAM is selected for storage according to the data length of the data packet.

4. The variable word length high speed multi-port cache arbiter of claim 1, wherein, The packet length of the data packet is variable, and the data packet composed of 8-bit frames supports packet lengths of 64B-1024B.

5. The variable word length high speed multi-port cache arbiter of claim 1, wherein, The SRAM state table module updates two aspects of information, including the input port number corresponding to each SRAM and whether it is occupied, and the internal details of each SRAM (the storage status of the corresponding 8 granularities in each SRAM block).

6. The variable word length high speed multi-port cache arbiter of claim 1, wherein, Memory recycling is performed according to the SRAM state table.

7. The variable word length high speed multi-port cache arbiter of claim 1, wherein, When reading from the shared cache, the Qos scheduling parameters of the priority FIFO are optional, supporting scheduling according to strict priority and WRR. Each port supports 8 priorities.

8. The variable word length high speed multi-port cache arbiter of claim 2, wherein, The shared cache part maps odd or even number SRAM according to the sequence number of the write port. The storage granularity of the SRAM is divided into 8. For example, the granularity of 256k SRAM is divided into: 1024B, 896B, 768B, 640B, 512B, 384B, 256B, 128B.

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