Bus access right allocation method, apparatus, device, medium, and product

Abstract

The application relates to the chip technical field and provides a bus access permission allocation method, device, equipment, medium and product.The method comprises the following steps: acquiring all source units initiating access requests for a target interface; generating a random number, the random number falling within a numerical range determined by the number of the source units; establishing a mapping relationship between the physical identifiers of the source units and the continuous index values within the numerical range; searching the mapping relationship according to the random number, selecting the source unit with the consistent index value and the random number as a target source unit according to the mapping relationship, and allocating the bus access permission to the target source unit.The application avoids the problem that the performance of individual cores is limited due to the fixed polling sequence, eliminates the damage of the barrel effect to the overall performance of the GPU, and improves the bus bandwidth utilization and the cooperative operation efficiency of the multi-core processor under complex working conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a bus access permission allocation method, device, equipment, medium and product. BACKGROUND

[0002] In the multi-core architecture of a graphics processing unit (GPU), simultaneous read and write of a plurality of cores to a memory unit can easily cause bus conflicts, and an arbitration device such as a crossbar switch is usually used to select a core unit that can access the bus to allocate access permission.

[0003] At present, a plurality of source units (Src) are usually connected to a bus interface by a crossbar switch, and resources are allocated in a fixed order in a round-robin arbitration. Although the round-robin arbitration can prevent long-term inability to obtain bus access permission, when multiple cores cooperate to complete a task, if a specific memory access mode occurs, this method can cause uneven bandwidth allocation among the cores. For example, in a 4x4 crossbar switch simulation, a specific access order can cause the request processing time of an individual Src to be much higher than that of other Srcs, and this performance difference can seriously damage the overall performance of the GPU according to the principle of the weakest link. SUMMARY

[0004] The present application provides a bus access permission allocation method, device, equipment, medium and product to solve the defects in the related art.

[0005] The present application provides a bus access permission allocation method, comprising the following steps:

[0006] Obtaining all source units that initiate access requests for a target interface;

[0007] Generating a random number, the random number falling within a numerical range determined by the number of source units;

[0008] Establishing a mapping relationship between the physical identifiers of the source units and the consecutive index values within the numerical range;

[0009] According to the random number, the mapping relationship is searched, a source unit with a mapped index value consistent with the random number is selected as a target source unit, and bus access permission is allocated to the target source unit.

[0010] According to the bus access permission allocation method provided by the present application, each source unit is configured with a request queue, and the request queue includes a first-level register for storing a current access request and a second-level register for storing a subsequent access request;

[0011] The bus access permission allocated to the target source unit includes:

[0012] allocating a first-level bus access right to a first-level register of the target source unit, and determining whether to allocate a second-level bus access right to a second-level register of the target source unit.

[0013] According to the bus access right allocation method provided in the application, the determining whether to allocate the second-level bus access right to the second-level register of the target source unit comprises:

[0014] determining a second target interface in an idle state except for a first target interface occupied by the first-level bus access right;

[0015] allocating the second-level bus access right to the second-level register in a case where an access request in the second-level register of the target source unit is directed to the second target interface.

[0016] According to the bus access right allocation method provided in the application, the allocating the second-level bus access right to the second-level register comprises:

[0017] in a case where access requests in second-level registers of multiple target source units are all directed to the same second target interface, arbitrating the multiple target source units, selecting one target source unit from the multiple target source units, and allocating the second-level bus access right to the second-level register of the selected target source unit.

[0018] According to the bus access right allocation method provided in the application, after the allocating the bus access right to the target source unit, the method further comprises:

[0019] in a case where the target source unit acquires the first-level bus access right and the second-level bus access right, writing a new access request into the first-level register and the second-level register of the target source unit in parallel;

[0020] in a case where the target source unit acquires only the first-level bus access right, moving an access request in the second-level register into the first-level register, and writing a new access request into the second-level register.

[0021] According to the bus access right allocation method provided in the application, the generating the random number comprises:

[0022] generating an original random sequence by using a linear feedback shift register;

[0023] performing a truncation operation to a specified bit number or a modulo operation to a specified range on the original random sequence to generate the random number.

[0024] The application further provides a bus access right allocation device comprising the following modules:

[0025] an acquisition module configured to acquire all source units that initiate access requests for a target interface;

[0026] a generation module configured to generate a random number, the random number falling within a numerical range determined by the number of source units;

[0027] an establishment module configured to establish a mapping relationship between the physical identifiers of the source units and the consecutive index values within the numerical range;

[0028] an allocation module configured to find the mapping relationship according to the random number, select a source unit with a mapped index value consistent with the random number as a target source unit, and allocate bus access rights to the target source unit.

[0029] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the bus access right allocation method according to any one of the above when executing the program.

[0030] The application further provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program is executable by a processor to implement the bus access right allocation method according to any one of the above.

[0031] The application further provides a computer program product comprising a computer program, wherein the computer program is executable by a processor to implement the bus access right allocation method according to any one of the above.

[0032] The bus access right allocation method, device, equipment, medium, and product provided by the application achieve randomization and equalization of arbitration strategies by acquiring all current source unit requests, dynamically generating a random number based on the number of source units, and then using a mapping mechanism of physical identifiers and consecutive index values to randomly allocate bus rights to one of the source units. Since the random number breaks the fixed priority order in traditional polling arbitration, the specific interleaved memory access mode that occurs in multi-core collaborative tasks can be effectively addressed, the problem of limited performance of individual cores caused by fixed polling order is avoided, the damage of the bucket effect to the overall performance of the GPU is eliminated, and the bus bandwidth utilization and collaborative operation efficiency of the multi-core processor under complex working conditions are improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0034] Figure 1 is one of flow diagrams of the bus access right allocation method provided by the present application.

[0035] Figure 2 is another flow diagram of the bus access right allocation method provided by the present application.

[0036] Figure 3 is a two-level arbitration flow diagram provided by the present application.

[0037] Figure 4 is a structural diagram of the bus access right allocation device provided by the present application.

[0038] Figure 5 is a structural diagram of the electronic device provided by the present application.

[0039] Reference signs:

[0040] 410: acquisition module; 420: generation module; 430: establishment module; 440: allocation module; 510: processor; 520: communication interface; 530: memory; 540: communication bus. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0042] In the current GPU architecture, most of them adopt the architecture of multi-core processors. When multiple cores simultaneously access the storage unit for reading and writing, there may be bus conflicts, at which time an arbitrator is needed to arbitrate the multiple cores that are performing storage unit reading and writing, and the winner can get the bus access right. Especially when multiple cores access multiple bus interfaces, multiple arbitrators or cross switches are usually used to select the core unit that can access the bus. For example, in a 4x4 cross switch structure, 4 arbitrators are used to select 4 Srcs, i.e. the above-mentioned core units, each of which can access 4 bus interfaces.

[0043] Under the above architecture, the commonly used arbiter currently adopts a polling arbitration algorithm, that is, in a fixed order, each Src is allocated resource use right in a cycle. In most cases, polling arbitration can achieve fairness of each source. However, when the GPU multi-core needs to cooperate to complete a task, according to the characteristics of the current GPU software and hardware, there may be a case that the performance of some cores is significantly less than that of other cores, resulting in that the bandwidth cannot be fully utilized.

[0044] Specifically, through simulation, it is found that when multiple cores cooperate to complete a memory read-write task, the access order of each core may appear a specific interleaving mode. In this mode, if a 4x4 arbiter is used and the polling arbitration algorithm is adopted, when each Src performs 1000 bus requests, the time consumption of a certain Src may be much higher than that of other Srcs. According to the principle of the weakest link, this unfairness caused by the fixed polling order will make the speed of a certain core significantly slower than that of other cores, thereby seriously damaging the overall performance of the GPU.

[0045] To this end, the application provides a bus access right allocation method, which aims to obtain all source units that initiate access requests to a target interface, establish a mapping of physical identifiers and continuous index values, and select a target source unit from the source units by using a generated random number, so as to break the fixed order limitation of traditional polling arbitration, eliminate the performance bottleneck under a specific access mode, and thus improve the fairness and overall operation performance when multiple cores work cooperatively.

[0046] Wherein, Figure 1 is one of the flowcharts of the bus access right allocation method provided by the application, Figure 2 is another flowchart of the bus access right allocation method provided by the application, as shown in Figure 1 and Figure 2 The method comprises steps 110, 120, 130 and 140.

[0047] Step 110, obtaining all source units that initiate access requests to a target interface.

[0048] Here, the target interface can be understood as an access entrance of a shared resource, which can be a storage unit interface, a cache interface, or other forms of bus slave device interface. The target interface is used to receive read-write instructions from core units and provide a data channel. The source unit can be understood as an active component that initiates bus access, which can be a streaming multiprocessor in a GPU, a CPU core, etc.

[0049] The source unit refers to a source unit that actually sends an access request and the request is valid in the current arbitration period. The source unit can be determined by detecting the bus request signal level state of each source unit. For example, if the access requests of source unit 0 (Src0) and source unit 2 (Src2) are high level, and the access requests of source unit 1 (Src1) and source unit 3 (Src3) are low level, it is determined that the current source unit is Src0 and Src2.

[0050] It should be noted that when performing a multi-core cooperative processing task, not all cores will initiate an access request in each clock cycle. Therefore, obtaining the source unit is the basis for subsequent fair and dynamic arbitration, which can filter out idle cores and avoid resource waste.

[0051] Step 120, generating a random number, the random number falls within a value range determined by the number of source units.

[0052] Specifically, the random number is generated to break the order restriction of the fixed priority in the traditional polling arbitration. The random number can be generated by a pseudo-random number generator (such as a linear feedback shift register) or a true random number generator.

[0053] Considering that the number of source units participating in the competition is dynamically changing in different clock cycles, if the generation range of the random number is fixed, it may cause the generated random number to point to an idle port that does not initiate a request, resulting in invalid arbitration or clock cycle waste. Therefore, the random number in this embodiment falls within a value range determined by the number of source units. The value range here can be understood as covering the logical sequence interval of all candidates participating in the current competition, which can be a continuous integer interval.

[0054] For example, if there are N source units, considering that computer logic processing usually starts counting from 0 and in order to facilitate subsequent compact index mapping, the value range of the generated random number R is usually set to integers between 0 and N-1.

[0055] As an optional embodiment, assuming that there are currently 3 source units (such as Src0, Src1 and Src3) simultaneously requesting access to the same target interface, the number of source units is 3, and the above value range is [0, 2], that is, the random number is generated in the three values 0, 1 and 2.

[0056] Step 130, establishing a mapping relationship between the physical identifiers of each source unit and the continuous index values in the value range.

[0057] Specifically, the physical identifier refers to the fixed number or address of the source unit in the hardware circuit. For example, in a 4-port system, the physical identifiers of the 4 source units are usually 0 (00b), 1 (01b), 2 (10b), and 3 (11b), respectively.

[0058] The continuous index value refers to a logical number of a re-compact arrangement of discrete source units for adapting to a range of continuous random numbers generated in step 120.

[0059] Since the physical identifiers of the source units can be discontinuous, for example, only SrcO and Src3 initiate access requests, the physical IDs are 0 and 3, and the middle 1 and 2 are missing, while the generated random numbers are continuous. If the random numbers are directly used to match the physical IDs, it can cause no match or matching errors. Therefore, a compression mapping from the physical identifiers to the continuous index values needs to be established.

[0060] For example, when SrcO (physical ID=0), Src2 (physical ID=2), and Src3 (physical ID=3) initiate access requests, the physical identifier "0" of SrcO is mapped to the index value "0", the physical identifier "2" of Src2 is mapped to the index value "1", and the physical identifier "3" of Src3 is mapped to the index value "2". In this way, no matter which source units are in an active state, the logical index values thereof are always continuously increased from 0, which exactly corresponds to the value range of the random numbers.

[0061] Step 140: According to the mapping relationship, a source unit with a mapped index value consistent with the random number is selected as a target source unit, and the target source unit is allocated a bus access right.

[0062] Specifically, the target source unit refers to a source unit determined to obtain a bus use right in a current arbitration period, and thus allowed to transmit data or send a command to a target interface. Considering that the random number itself represents a winning position in a valid request queue, rather than a physical port number, in this embodiment, according to the random number, the mapping relationship is looked up, and a source unit with a mapped index value consistent with the random number is selected as the target source unit.

[0063] As an optional embodiment, the generated random number can be used as a selection signal to index the corresponding physical identifier in the established mapping relationship through a hardware lookup table or a multiplexer logic, so as to determine the target source unit. In this step, the arbitrator uses the random number as an index of a winning position to look up the corresponding target source unit through the mapping relationship established in step 130, and sends an access request permission to the target source unit.

[0064] Continuing the above example, if the random number generated in step 120 is "1", according to the mapping relationship in step 130, the index value "1" corresponds to Src2 with a physical identifier "2". Therefore, Src2 is selected as the target source unit, and Src2 obtains the bus access right this time.

[0065] This embodiment employs random arbitration, primarily to address the performance bottleneck issue of polling arbitration in specific modes in related technologies. In related technologies, when using fixed-order polling arbitration, if multiple source units collaborate to complete tasks and the access order exhibits a specific interleaved pattern, the waiting time for some source units can significantly increase. According to the "weakest link" principle, the overall performance of a GPU depends on its slowest core.

[0066] This embodiment introduces randomness through steps 120 and 140, ensuring that the probability of each source unit obtaining bus access is dynamic and tends to be equal in each arbitration, no longer subject to a fixed polling order. This means that even if the access request order of a specific source unit is interleaved or partially reversed with the access request order of other source units, such as a temporal reversal of the request target sequence of a certain source unit compared to other source units, causing its access requests to continuously conflict with the fixed priority order of polling arbitration, the random arbitration of this embodiment can still distribute bus access in a dispersed manner.

[0067] Since the generated random numbers are uniformly distributed within a numerical range determined by the number of source units, and each source unit uniquely corresponds to an index value within the numerical range through a mapping relationship, each source unit has an equal probability of being selected as the target source unit in a single arbitration process. Therefore, in the long run, each source unit has an equal chance of obtaining allocation authority, thereby eliminating the situation where any source unit is blocked by a specific order and its performance drops significantly. This keeps the processing progress of each source unit synchronized and maximizes the utilization of bandwidth.

[0068] The bus access permission allocation method provided in this embodiment obtains all current source unit requests, dynamically generates random numbers based on the number of source units, and then uses a mapping mechanism between physical identifiers and consecutive index values ​​to randomly allocate bus permissions to one of the source units, thus achieving randomization and fairness in the arbitration strategy. Because the use of random numbers breaks the fixed priority order in traditional polling arbitration, it can effectively cope with specific interleaved memory access patterns that occur in multi-core collaborative tasks, avoiding the problem of individual core performance limitations caused by a fixed polling order, eliminating the bottleneck effect that damages the overall GPU performance, and improving the bus bandwidth utilization and collaborative computing efficiency of multi-core processors under complex working conditions.

[0069] Considering that in the high-speed bus transmission scenario of the GPU, there is a loss of clock cycles between the completion of arbitration logic judgment by the arbiter and the actual start of data transmission on the bus. If only the current request is processed, and the next round of request and arbitration is re-initiated after each data transmission is completed, idle bubbles can be generated on the bus, resulting in that the bandwidth cannot be utilized to the extreme. Especially when a certain source unit is limited in performance due to a specific interleaving mode, if the internal continuous instruction stream of the source unit cannot be responded quickly, the bucket effect will be further aggravated.

[0070] Based on this, in order to further improve the data throughput efficiency of the winning source unit and mask the arbitration delay, each source unit is configured with a request queue, which includes a first-level register for storing a current access request and a second-level register for storing a subsequent access request.

[0071] Here, the request queue can be understood as a cache structure arranged at the output end of the source unit. The first-level register can be understood as a register directly interacting with the input end of the arbiter, which is used to store the access request at the head of the queue which needs to be processed urgently. The second-level register can be understood as a backup register behind the first-level register, which is used to store the next access request following the current access request. For example, when the source unit (Src1) needs to continuously write two pieces of data to the storage unit, the first write request is stored in the first-level register, and the second write request is stored in the second-level register.

[0072] Correspondingly, after the target source unit is determined in step 140, the process of allocating bus access rights to the target source unit in the embodiment specifically includes: allocating first-level bus access rights to the first-level register of the target source unit, and determining whether to allocate second-level bus access rights to the second-level register of the target source unit.

[0073] First, the arbiter allocates first-level bus access rights to the first-level register of the target source unit, which means that the arbiter sends the first grant signal to the source unit, allowing it to send the address and control signal in the first-level register to the bus to start the current read / write operation.

[0074] Then, at the same time or immediately after the allocation of the first-level rights, the arbiter does not immediately disconnect or turn to the next round of indiscriminate random arbitration, but further determines whether to allocate resources predictively, that is, whether to allocate second-level bus access rights to the second-level register of the target source unit.

[0075] As an optional embodiment, the determining process can be based on the status bit of the second-level register. If the second-level register of the target source unit is empty (i.e. invalid), the second-level privilege is not allocated, the arbiter ends the current process after completing the first-level request processing, and prepares to enter the next arbitration cycle. If the second-level register of the target source unit is not empty (i.e. valid), it indicates that the source unit has continuous access requirements. At this time, in order to reduce the overhead of context switching, the arbiter can determine to allocate the second-level bus access privilege to the second-level register.

[0076] For example, in a certain cooperative task, Src1 as the target source unit accumulates a large number of tasks, and its performance becomes a bottleneck. When Src1 is selected as the target source unit in step 140 according to the random arbitration mechanism of the above embodiment, the first-level register of Src1 stores an access request A, and the second-level register stores an access request B. This embodiment first allows the access request A to access the bus. Then, it is detected that there is an access request B in the second-level register, and the target interface of the access request B is the same as or compatible with the access request A. Therefore, the arbiter can directly approve the access request B to use the bus immediately after the end of the access request A, without the need for the access request B to return to the random pool of all source units again to compete for the bus.

[0077] This embodiment realizes the pipeline processing of continuous bus requests by configuring two-level request queues in the source unit and introducing the pre-judgment allocation mechanism for the second-level register when allocating the privilege. Since the target source unit can continuously process two-level requests when it gets the opportunity to access the bus, the frequency of repeated intervention of the arbitration logic is reduced, the bus transmission gap is effectively filled, and the bus bubble problem caused by frequent arbitration switching is avoided.

[0078] Considering that in a multi-core processor using a crossbar architecture, multiple source units can access different target interfaces at the same time to realize parallel transmission. However, when two continuous access requests initiated by a source unit point to different target interfaces, if the target interface occupied by the first access request and the target interface pointed to by the second access request are both in a busy state, or the parallel degree is insufficient due to simple sequential processing, the bus utilization rate will be reduced. In order to fully tap the parallel processing potential between multi-level requests and improve the throughput performance under the two-level arbitration architecture while ensuring data consistency.

[0079] Based on this, this embodiment further refines the step of determining whether to allocate the second-level bus access privilege to the second-level register of the target source unit, which specifically includes:

[0080] determining a second target interface in an idle state other than the first target interface occupied by the first-level bus access privilege;

[0081] In the case that the access request in the second level register of the target source unit is directed to the second target interface, the second level bus access right is allocated to the second level register.

[0082] In particular, the first target interface refers to the bus interface that is being accessed or will be accessed by the current access request in the first level register of the target source unit. The second target interface refers to the bus interface that is in an idle state at the current time, in addition to the first target interface and not being locked by other high priority operations. The idle state can be determined by detecting the busy / idle signals of the target interfaces or the occupation mask of the arbiter.

[0083] For example, assume that the source unit 1 (Src 1) obtains the first level bus access right and is accessing the first target interface (dst 1). At this time, the states of the remaining interfaces (e.g., dst 2, dst 3 and dst 4) are checked. If the dst 3 and the dst 4 are not currently occupied by other source units, the dst 3 and the dst 4 are the second target interfaces in the idle state.

[0084] After the second target interface is determined, the target address of the subsequent access request stored in the second level register of the target source unit is checked. The target address is matched with the identifier of the second target interface, and then it can be determined whether the access request in the second level register is directed to the second target interface. If yes, it indicates that the current access request and the subsequent access request access different target interfaces and do not conflict with each other, and have the condition of parallel processing.

[0085] At this time, the second level bus access right is allocated to the second level register of the target source unit, and the target source unit is allowed to immediately start the access operation, so as to realize the parallel execution of the current access request and the subsequent access request.

[0086] Table 1 is a list of the access interfaces of the registers of the source units. As shown in Table 1, in the arbitration of the first level register, the first level registers of the source unit 1, the source unit 2 and the source unit 3 simultaneously compete for the interface 0, and the source unit 1 is selected as the target source unit by the random arbitration of the above embodiment. At this time, the first level register of the source unit 1 obtains the access right of the interface 0. Meanwhile, the first level register of the source unit 0 requests to apply for the access to the interface 1. At this time, there is no other competing source unit, and the first level register of the source unit 0 obtains the access right of the interface 1. At this time, the arbitration of the first level register ends, the interface 0 and the interface 1 are occupied, and the interface 2 is idle.

[0087] Next, the second level registers of the source unit 0 and the source unit 1 are checked. The second level register of the source unit 0 requests to access the interface 2, and the second level register of the source unit 1 requests to access the interface 1. The interface 1 is in the occupied state, and the interface 2 is in the idle state. Therefore, the second level bus access right is allocated to the second level register of the source unit 0.

[0088] After the above permission assignment, source unit 0 can send the current access request to interface 1 and the subsequent access request to interface 2 in the same pipeline cycle.

[0089] Table 1: List of access interfaces of each level register of source unit

[0090]

[0091] The embodiment realizes parallel requests in a single source unit by acquiring the second target interface in an idle state and assigning the second-level bus access permission to the second-level register in the case that the access request in the second-level register of the target source unit points to the second target interface, so that the access requests in the first-level register and the second-level register of the target source unit can be written or forwarded in parallel, greatly improving the utilization rate of the bus bandwidth and avoiding the problem that the subsequent request pointing to the idle interface is unnecessarily blocked due to the occupation of a single interface by the previous request.

[0092] wherein, Figure 3 is a two-level arbitration flowchart provided by the embodiment, as shown in Figure 3 First, each source unit (such as source unit 0, source unit 1, source unit 2 and source unit 3) is configured with a request queue, which includes a first-level register for storing a current access request and a second-level register for storing a subsequent access request. The first-level arbiter arbitrates the access requests in the first-level register of each source unit, determines a target source unit that obtains the first-level bus access permission, and identifies a first target interface occupied by the first-level bus access permission, such as source unit 1 as the target source unit and access interface 0, interface 0 being the first target interface.

[0093] Then, according to the arbitration result of the first-level arbiter, a state mask is generated to determine a second target interface in an idle state other than the first target interface occupied by the first-level bus access permission.

[0094] Next, the second-level arbiter is controlled according to the state of the second target interface. If the subsequent access request in the second-level register of the target source unit points to the second target interface, the second-level arbiter will arbitrate these requests and assign the second-level bus access permission to the winning second-level register.

[0095] Finally, the arbitration result is routed to the corresponding interface through the multiplexer of the output terminal. If the second-level bus access permission is assigned, the multiplexer allows the access request of the second-level register to be transmitted through the idle interface. In this way, when both the first-level register and the second-level register are authorized, two access requests can be written or processed simultaneously, thereby realizing parallel processing of the access requests in the first-level register and the second-level register and optimizing the bus performance.

[0096] Considering that after determining the second target interface in the idle state, there can be a concurrent conflict scenario, i.e., multiple different target source units in the second level register, which happen to request access to the same idle second target interface. Since a bus interface can only respond to the read / write operation of one source unit at the same time, if the permission is directly assigned without distinction, it will lead to data conflict or bus error. In order to effectively solve the conflict problem of multiple sources competing for the same idle resource while improving parallelism by using the idle interface, and ensure the orderliness of bus transmission.

[0097] Based on this, the embodiment further refines the step of assigning the second level bus access permission to the second level register, specifically comprising:

[0098] In the case where the access requests of multiple target source units in the second level register all point to the same second target interface, arbitrating the multiple target source units, selecting one target source unit from the multiple target source units, and assigning the second level bus access permission to the second level register of the selected target source unit.

[0099] Specifically, the multiple target source units refer to the source unit set in which the second level register stores an effective access request, and the target address of the access request points to the same second target interface in the idle state within the current arbitration period.

[0100] For this specific second target interface, the corresponding arbiter logic is activated to select between the above multiple competing target source units. Specifically, the arbitration strategy can follow the random arbitration mechanism of steps 110-140, or other strategies, which are not specifically limited by the embodiment.

[0101] For example, after the first level arbitration ends, interface 0 and interface 1 are in the occupied state, and interface 2 is in the idle state. The second level register of source unit 0 requests to access interface 2, and the second level register of source unit 1 also requests to access interface 2. In this case, although interface 2 is idle, source unit 0 and source unit 1 both request access. The arbiter intervenes and arbitrates source unit 0 and source unit 1. Assuming that the arbitration result selects source unit 0, the arbiter only assigns the second level bus access permission to the second level register of source unit 0, allowing the access request of the second level register of source unit 0 to occupy interface 2, while the access request of the second level register of source unit 1, although pointing to interface 2, fails in arbitration and cannot obtain permission in this period, and needs to wait for the next period.

[0102] The embodiment introduces a secondary arbitration mechanism for idle interfaces in the second level permission allocation stage, solves the conflict problem of multiple subsequent requests competing for the same idle resource. Since the competition source can be accurately identified and the arbitrator can be used to select a unique winner, the bus idle time slots are filled to the maximum extent under the premise of ensuring that data transmission does not interfere with each other, safe and efficient instruction level parallel processing is realized, and the overall throughput performance of the multi-core processor under complex cooperative tasks is further improved.

[0103] Considering that under the architecture of two-level request queues, the request processing speed of the source unit directly affects the emptying efficiency of its internal queue. In order to ensure that the source unit can continuously initiate requests, and avoid blocking the upstream instruction stream due to full queue, the content in the register needs to be updated in time after the current request is arbitrated and sent to the bus, so as to maintain the efficient operation of the pipeline. Especially when the source unit has higher bandwidth write capability, this capability should be fully utilized to match the parallel transmission efficiency of the bus end.

[0104] Based on this, the embodiment further includes register updating and pipeline management steps for different authorization conditions after allocating bus access permissions to the target source unit:

[0105] In the case that the target source unit obtains the first level bus access permission and the second level bus access permission, the new access request is written to the first level register and the second level register of the target source unit in parallel;

[0106] In the case that the target source unit only obtains the first level bus access permission, the access request in the second level register is moved to the first level register, and a new access request is written to the second level register.

[0107] Specifically, the target source unit obtaining the bus access permission includes two cases: one is that the target source unit obtains the first level bus access permission and the second level bus access permission at the same time, that is, the access requests in the first level register and the second level register of the target unit are both approved to be sent in the same period. Two is that the target source unit only obtains the first level bus access permission, and the second level bus access permission is not allocated.

[0108] Specifically, when the target source unit can send requests at a higher bandwidth, if it is detected that the first level and the second level register have been authorized, that is, the access requests in the two registers have been successfully transmitted to the bus, then the positions of the two registers will be idle after the current period ends.

[0109] At this time, the instruction distribution logic inside the target source unit can take advantage of the high bandwidth characteristic, while taking out two new access requests from the instruction cache, writing them into the first-level register and the second-level register respectively, achieving a double launch effect, so that the request queue always remains full, maximizing the throughput of the source unit.

[0110] When only the access request in the first-level register is authorized to be sent, the first-level register becomes idle, but the access request in the second-level register is stranded because it is not authorized. In order to maintain the first-in-first-out order and make room to receive new access requests, the access request stranded in the second-level register is moved to the first-level register, so that it becomes the first processing object in the next round of arbitration. At this time, the second-level register is vacated, and the control logic takes out a new access request from the instruction cache and writes it into the second-level register, maintaining the standard pipeline flow and ensuring that the requests are sequentially advanced, and the entire queue will not be stalled because the access request in the second-level register is temporarily blocked.

[0111] Considering that in hardware circuit design, the implementation cost and generation speed of the random number generator directly affect the overall performance of the arbiter. If a complex true random number generation algorithm is used, although the randomness is better, it will consume a large number of logic gate resources and increase the clock delay, and may not meet the timing requirements of the GPU high-frequency bus access, while the linear feedback shift register has the characteristics of simple structure, fast speed and small area occupation, and the pseudo-random sequence generated by it is sufficient to break the fixed dead loop of the polling arbitration in statistical characteristics.

[0112] Based on this, the embodiment further refines the steps of generating random numbers, specifically including:

[0113] Generating an original random sequence using a linear feedback shift register;

[0114] Truncating the original random sequence to a specified number of bits or performing a modulo operation to a specified range to generate a random number.

[0115] Specifically, the linear feedback shift register is a pseudo-random number generator composed of a shift register and an XOR logic gate, which uses a part of the current state of the register to perform an XOR operation and then feeds back to the input end, thereby generating a series of pseudo-random binary sequences.

[0116] The original random sequence refers to the binary value directly output by the linear feedback shift register. Since the bit width of the linear feedback shift register is usually fixed, the range of the values it generates is usually [1, 2 k -1], k is the bit width.

[0117] Since the number of source units is dynamically changed and usually small, the range of the generated original random sequence is usually much larger than the number of source units, and direct use will cause index out of bounds. Therefore, it is necessary to compress the value of the original random sequence into a value range determined by the number of source units.

[0118] wherein, the truncation to the specified number of bits means that when the number of source units is exactly a power of 2, a number of least significant bits in the binary representation of the original random sequence is directly selected as the result. The modulo to the specified range means that the value of the original random sequence is divided by the number of source units, and the remainder is taken as the result. The operation of truncating the original random sequence to the specified number of bits or taking the modulo to the specified range can map the large range of original random values to the small interval of [0, N-1], so as to generate a random number falling in the value range determined by the number of source units. Wherein, N represents the number of source units.

[0119] Wherein, Table 2 is a list of request completion time of each source unit when the related art and the invention allocate permissions, as shown in Table 2, the random arbitration mechanism in the invention has a large reduction in the request completion time of each source unit compared with the polling arbitration mechanism of the related art. Especially for source unit 1, the request completion time in the related art is 1500 unit time, and the request completion time in the invention is 990 unit time, the performance improvement is large, and the long tail delay phenomenon caused by the specific access mode is eliminated, thereby effectively avoiding the drag of the overall performance of the system caused by the bucket effect, and realizing efficient parallel processing under multi-core cooperative task.

[0120] Table 2 list of request completion time of each source unit when the related art and the invention allocate permissions

[0121]

[0122] The bus access permission allocation device provided by the invention is described below. The bus access permission allocation device described below can be referred to in conjunction with the bus access permission allocation method described above.

[0123] Based on any of the above embodiments, Figure 4 is a structural schematic diagram of the bus access permission allocation device provided by the invention, as Figure 4 shown, the device comprises:

[0124] The acquisition module 410 is configured to acquire all source units initiating access requests for the target interface.

[0125] The generation module 420 is configured to generate a random number falling in a value range determined by the number of source units.

[0126] Module 430 is established to establish the mapping relationship between the physical identifiers of each source unit and the continuous index values ​​within the numerical range;

[0127] The allocation module 440 is used to find the mapping relationship based on the random number, select the source unit whose index value matches the random number as the target source unit, and allocate bus access permissions to the target source unit.

[0128] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 5 As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a bus access permission allocation method.

[0129] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0130] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer is able to execute the bus access permission allocation method provided by the above methods.

[0131] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the bus access permission allocation methods provided by the methods described above.

[0132] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0133] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0134] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for allocating bus access permissions, characterized in that, include: Retrieve all source units that have initiated access requests to the target interface; Generate random numbers that fall within a numerical range determined by the number of source units; Establish a mapping relationship between the physical identifier of each source unit and the consecutive index values ​​within the numerical range; The mapping relationship is found based on the random number, and the source unit whose index value matches the random number is selected as the target source unit, and bus access permissions are assigned to the target source unit.

2. The bus access permission allocation method according to claim 1, characterized in that, Each source unit is configured with a request queue, which includes a first-level register for storing the current access request and a second-level register for storing subsequent access requests; The process of allocating bus access permissions to the target source unit includes: First-level bus access permissions are assigned to the first-level registers of the target source unit, and it is determined whether to assign second-level bus access permissions to the second-level registers of the target source unit.

3. The bus access permission allocation method according to claim 2, characterized in that, The step of determining whether to allocate second-level bus access permissions to the second-level register of the target source unit includes: Identify a second target interface that is idle, excluding the first target interface occupied by the first-level bus access permission. If the access request in the second-level register of the target source unit points to the second target interface, second-level bus access permissions are assigned to the second-level register.

4. The bus access permission allocation method according to claim 3, characterized in that, The allocation of second-level bus access permissions to the second-level register includes: When multiple target source units have access requests in their second-level registers that all point to the same second target interface, arbitration is performed on the multiple target source units, one target source unit is selected from the multiple target source units, and second-level bus access permissions are assigned to the second-level register of the selected target source unit.

5. The bus access permission allocation method according to claim 2, characterized in that, After allocating bus access permissions to the target source unit, the process also includes: When the target source unit obtains the first-level bus access permission and the second-level bus access permission, a new access request is written to the first-level register and the second-level register of the target source unit in parallel. If the target source unit only obtains access to the first-level bus, the access request in the second-level register is moved into the first-level register, and a new access request is written into the second-level register.

6. The bus access permission allocation method according to any one of claims 1 to 5, characterized in that, The generation of random numbers includes: The original random sequence is generated using a linear feedback shift register; The original random sequence is truncated to a specified number of bits or moduloed to a specified range to generate the random number.

7. A bus access permission allocation device, characterized in that, include: The acquisition module is used to acquire all source units that have initiated access requests to the target interface; A generation module is used to generate random numbers, which fall within a numerical range determined by the number of source units; A module is established to establish a mapping relationship between the physical identifiers of each source unit and consecutive index values ​​within the numerical range; The allocation module is used to find the mapping relationship based on the random number, select the source unit whose index value matches the random number as the target source unit, and allocate bus access permissions to the target source unit.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the bus access permission allocation method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the bus access permission allocation method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the bus access permission allocation method as described in any one of claims 1 to 6.

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