Multi-bit reconstruction design method and system based on FPGA

Abstract

The invention provides a multi-bit reconstruction design method and system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of embedding. The method comprises the following steps of: determining a situation change trend by acquiring an external environment signal and an internal task demand signal of the FPGA, and determining a task demand vector and a plurality of bit files matched with the task demand vector according to the situation change trend; and screening the candidate bit files of which the matching degrees exceed a preset matching degree threshold value to form a high-priority bit file list. If candidate bit files which are not in place exist in the list, the candidate bit files are transmitted to the first-level cache of the multi-level cache to determine a bit file priority calling sequence. Obtaining a server resource utilization rate index to determine a load environment early warning probability value, if the load environment early warning probability value exceeds a preset early warning probability value, triggering high-load early warning, and distributing a standby bit file in a second-stage cache of the multi-stage cache to generate resource contention relieving confirmation so as to generate a final multi-bit file reconstruction priority sequence; efficient prefetching of the bit file and self-adaptive relieving of resource contention are achieved, and the stable performance in a high-load environment is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of embedded technology, and specifically to a design method and system for multi-bit reconstruction based on FPGA. Background Technology

[0002] Currently, in modern embedded systems, FPGAs, as highly flexible programmable hardware, utilize multi-bit reconfiguration technology. This technology allows bit files for different tasks to share internal logic resources through time-division multiplexing, enabling the loading of different functional modules at different times to meet system requirements. This is particularly effective in applications with high real-time requirements, significantly improving resource utilization and system responsiveness. However, current FPGA-based multi-bit reconfiguration methods largely rely on instantaneous response mechanisms. While this approach can load bit files, it ignores the suddenness and uncertainty of task switching. This leads to increased resource contention under high load conditions, frequent interruptions to system operation during bit file loading, and consequently, significant fluctuations in overall performance.

[0003] The information disclosed in the background section is only for enhancing the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, this disclosure provides a design method for multi-bit reconstruction based on FPGA, which can achieve efficient bit file prefetching and adaptive mitigation of resource contention, ensuring stable performance under high load conditions.

[0005] In a first aspect, embodiments of this application provide a design method for multi-bit reconfiguration based on an FPGA. The method includes: acquiring external environmental signals and internal task requirement signals of the FPGA; determining a situational change trend based on an ARIMA time series model, according to the external environmental signals and internal task requirement signals; determining a task requirement vector and multiple bit files matching the task requirement vector based on the situational change trend; determining whether the matching degree between the bit files and the task requirement vector exceeds a preset matching degree threshold; if the threshold is exceeded, using the current bit file as a candidate bit file and determining a high-priority bit file list based on the candidate bit files; determining whether there are any unread candidate bit files in the high-priority bit file list; if such unread candidate bit files exist, transmitting the unread candidate bit files. The system first caches the multi-level cache and generates a cache in-place flag. Based on the cache in-place flag, it updates the in-place status of candidate bit files corresponding to the high-priority bit file list and determines the bit file priority call sequence according to the updated high-priority bit file list. Based on the bit file priority call sequence, it obtains the server's resource utilization index and optimizes the scenario change trend according to the resource utilization index. Based on the optimized scenario change trend, it determines the load environment warning probability value according to external environmental signals. It determines whether the load environment warning probability value exceeds the preset warning probability value. If it exceeds the preset warning probability value, it triggers a high load environment warning and allocates a spare bit file in the second-level cache of the multi-level cache to generate a resource contention mitigation confirmation. Based on the genetic algorithm, it generates a multi-bit file reconstruction priority sequence according to the resource contention mitigation confirmation.

[0006] Secondly, embodiments of this application provide a multi-bit reconfiguration design system based on FPGA. This system includes: an acquisition module, a first determination module, a second determination module, a first judgment module, a second judgment module, a third determination module, an optimization module, a fourth determination module, a third judgment module, and a generation module. The acquisition module is used to acquire external environmental signals and internal task requirement signals of the FPGA. The first determination module is used to determine the situational change trend based on the ARIMA time series model and the external environmental signals and internal task requirement signals. The second determination module is used to determine the task requirement vector and multiple bit files matching the task requirement vector based on the situational change trend. The first judgment module is used to determine whether the matching degree between the bit file and the task requirement vector exceeds a preset matching degree threshold. If the threshold is exceeded, the current bit file is used as a candidate bit file, and a high-priority bit file list is determined based on the candidate bit files. The second judgment module is used to determine whether there are any unread candidate bit files in the high-priority bit file list. If such unread candidate bit files exist, they are transferred to the first-level cache of the multi-level cache, and a cache generation module is generated. The system includes: a bit marker module; a third determination module, used to update the availability status of candidate bit files corresponding to the high-priority bit file list based on the cache availability marker, and to determine the bit file priority call sequence based on the updated high-priority bit file list; an optimization module, used to obtain the server's resource utilization index based on the bit file priority call sequence, and to optimize the situation change trend based on the resource utilization index; a fourth determination module, used to determine the load environment warning probability value based on the optimized situation change trend and external environmental signals; a third judgment module, used to judge whether the load environment warning probability value exceeds the preset warning probability value. If the judgment exceeds the preset warning probability value, a high load environment warning is triggered, and a spare bit file is allocated in the second-level cache of the multi-level cache to generate a resource contention mitigation confirmation; and a generation module, used to generate a multi-bit file reconstruction priority sequence based on the resource contention mitigation confirmation using a genetic algorithm.

[0007] This application provides a design method and system for multi-bit reconfiguration based on FPGA. By synchronously acquiring external environmental signals and internal task requirement signals during FPGA operation, and using the ARIMA time series model to deeply mine the correlation patterns between the two types of signals, the system accurately predicts the trend of situational changes, breaking the limitation of unpredictable situational changes in traditional methods and providing a basis for advance preparation of bit files. Based on the trend of situational changes, a task requirement vector that matches the current and future task requirements is constructed, and multiple bit files that match the task requirement vector are selected. If the matching degree between the bit file and the task requirement vector exceeds a preset matching degree threshold, the current bit file is used as a candidate bit file, thereby forming a high-priority bit file list to ensure the relevance and effectiveness of bit file adaptation. For candidate bit files that are not in the high-priority bit file list, they are pre-transmitted to the first level of the multi-level cache and a cache ready mark is generated, solving the loading delay problem caused by the bit file not being ready when the situation changes, and significantly shortening the bit file call time. By combining the cache readiness flags with the readiness status updates of files in the high-priority list, the priority call sequence of bit files is determined, ensuring the orderliness and efficiency of bit file calls. Simultaneously, based on this priority call sequence, server resource utilization metrics are obtained to optimize the scenario change trend prediction model, further improving the accuracy of scenario change trend prediction. Based on the optimized scenario change trend, the load environment warning probability value is quantified by combining external environmental signals. When this value exceeds the preset warning probability value, a high-load environment warning is triggered, and a spare bit file is pre-allocated in the second-level cache of the multi-level cache to adaptively alleviate resource contention under high load and avoid frequent system interruptions during bit file loading. Finally, using a genetic algorithm, the optimal multi-bit file reconstruction priority sequence is generated based on the resource contention mitigation confirmation results, ensuring that the FPGA system maintains stable operating performance under high-load scenarios. This enables precise control over the timing of bit file preparation and dynamic optimization of bit file call priority in multi-level cache, significantly reducing task switching latency, improving FPGA response speed and resource utilization, effectively avoiding security risks caused by response lag in scenarios with high real-time requirements, and greatly reducing performance fluctuations under high load conditions, thus significantly enhancing the reliability, adaptability and operational stability of FPGA multi-bit reconstruction methods. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a flowchart illustrating an exemplary embodiment of the design method for multi-bit reconfiguration based on FPGA provided in this application.

[0010] Figure 2 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0011] Figure 3 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0012] Figure 4 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0013] Figure 5 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0014] Figure 6 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0015] Figure 7 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0016] Figure 8 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application.

[0017] Figure 9 This is a flowchart illustrating a design method for FPGA-based multi-bit reconfiguration provided in another exemplary embodiment of this application. Detailed Implementation

[0018] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are set forth to give a full understanding of embodiments of this disclosure.

[0019] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and that other elements / components / etc. may exist in addition to those listed. The terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0020] Currently, in modern embedded systems, FPGAs, as highly flexible programmable hardware, utilize multi-bit reconfiguration technology. This technology allows bit files for different tasks to share internal logic resources through time-division multiplexing, enabling the loading of different functional modules at different times to meet system requirements. This is particularly effective in applications with high real-time requirements, significantly improving resource utilization and system responsiveness. However, current FPGA-based multi-bit reconfiguration methods largely rely on instantaneous response mechanisms. While this approach can load bit files, it ignores the suddenness and uncertainty of task switching. This leads to increased resource contention under high load conditions, frequent interruptions to system operation during bit file loading, and consequently, significant fluctuations in overall performance.

[0021] For example, system task requirements often change drastically with sudden shifts in the external environment, making it impossible to have bit files ready in advance. Furthermore, there is a significant delay in the bit file loading path from memory to the FPGA. Once the situation changes abruptly, the system must immediately select and transmit the corresponding file from a massive number of bit files; however, when the transmission link is congested, file retrieval can take several seconds or even longer. For instance, in a road condition monitoring system for autonomous vehicles, when switching from urban congestion to highway cruising, the previously loaded low-speed processing module needs to be immediately replaced by a high-speed data fusion module. However, because the bit file is not prepared in the cache, the transmission delay causes a lag in vehicle response, missing critical obstacle avoidance opportunities and thus amplifying safety hazards.

[0022] Therefore, accurately determining the timing of bit file preparation before sudden changes in the situation, and dynamically sorting and managing the call priorities of different files in a multi-level cache, has become a technical problem that needs to be solved to ensure the efficient operation of a multi-bit reconstruction system.

[0023] This disclosure provides a design method for multi-bit reconstruction based on FPGA, such as... Figure 1 The illustrated design method for multi-bit reconfiguration based on FPGA includes the following steps:

[0024] Step S110: Acquire the external environment signals and internal task requirement signals of the FPGA;

[0025] Step S120: Based on the ARIMA time series model, determine the trend of situational change according to external environmental signals and internal task requirement signals;

[0026] Step S130: Determine the task requirement vector and multiple bit files that match the task requirement vector based on the changing trend of the situation;

[0027] Step S140: Determine whether the matching degree between the bit file and the task requirement vector exceeds the preset matching degree threshold. If it is determined that the matching degree threshold is exceeded, the current bit file is used as a candidate bit file, and a list of high-priority bit files is determined based on the candidate bit files.

[0028] Step S150: Determine whether there is an unread candidate bit file in the high priority bit file list. If there is an unread candidate bit file, transfer the unread candidate bit file to the first level cache of the multi-level cache and generate a cache readiness flag.

[0029] Step S160: Based on the cache in place flag, update the in place status of the candidate bit files corresponding to the high-priority bit file list, and determine the bit file priority call sequence according to the updated high-priority bit file list;

[0030] Step S170: Based on the bit file priority call sequence, obtain the server's resource utilization index, and optimize the scenario change trend according to the resource utilization index;

[0031] Step S180: Based on the optimized scenario change trend, determine the load environment early warning probability value according to the external environment signal;

[0032] Step S190: Determine whether the load environment warning probability value exceeds the preset warning probability value. If it is determined that it exceeds the preset warning probability value, trigger the high load environment warning and allocate a spare bit file in the second level cache of the multi-level cache to generate a resource contention mitigation confirmation.

[0033] Step S195: Based on the genetic algorithm, generate a multi-bit file reconstruction priority sequence according to the resource contention mitigation confirmation.

[0034] According to the FPGA-based multi-bit reconfiguration design method provided in this disclosure, the method can acquire the external environment signals and internal task requirement signals of the FPGA; determine the situation change trend based on the ARIMA time series model and the external environment signals and internal task requirement signals; determine the task requirement vector and multiple bit files matching the task requirement vector based on the situation change trend; determine whether the matching degree between the bit file and the task requirement vector exceeds a preset matching degree threshold; if it exceeds the preset matching degree threshold, the current bit file is used as a candidate bit file, and a high-priority bit file list is determined based on the candidate bit files; determine whether there are any unread candidate bit files in the high-priority bit file list; if there are any unread candidate bit files, the unread candidate bit files are transmitted to multiple levels. The system first caches the cache and generates a cache in-place flag. Based on the cache in-place flag, it updates the in-place status of candidate bit files corresponding to the high-priority bit file list and determines the bit file priority call sequence according to the updated high-priority bit file list. Based on the bit file priority call sequence, it obtains the server's resource utilization index and optimizes the scenario change trend according to the resource utilization index. Based on the optimized scenario change trend, it determines the load environment warning probability value according to external environmental signals. It determines whether the load environment warning probability value exceeds the preset warning probability value. If it exceeds the preset warning probability value, it triggers a high load environment warning and allocates a spare bit file in the second-level cache of the multi-level cache to generate a resource contention mitigation confirmation. Based on the genetic algorithm, it generates a multi-bit file reconstruction priority sequence according to the resource contention mitigation confirmation.

[0035] In the above method, by synchronously acquiring external environmental signals and internal task requirement signals during FPGA operation, and using the ARIMA time series model to deeply mine the correlation patterns between the two types of signals, the method accurately predicts the trend of situational changes, breaking the limitation of unpredictable situational changes in traditional methods and providing a basis for the advance preparation of bit files. Based on the trend of situational changes, a task requirement vector that matches the current and future task requirements is constructed, and multiple bit files that match the task requirement vector are selected. If the matching degree between the bit file and the task requirement vector exceeds a preset matching degree threshold, the current bit file is used as a candidate bit file, thereby forming a high-priority bit file list to ensure the relevance and effectiveness of bit file adaptation. For candidate bit files that are not in the high-priority bit file list, they are pre-transmitted to the first level of the multi-level cache and a cache ready mark is generated, which solves the loading delay problem caused by the bit file not being ready when the situation changes, and significantly shortens the bit file call time. By combining the cache readiness flags with the readiness status updates of files in the high-priority list, the priority call sequence of bit files is determined, ensuring the orderliness and efficiency of bit file calls. Simultaneously, based on this priority call sequence, server resource utilization metrics are obtained to optimize the scenario change trend prediction model, further improving the accuracy of scenario change trend prediction. Based on the optimized scenario change trend, the load environment warning probability value is quantified by combining external environmental signals. When this value exceeds the preset warning probability value, a high-load environment warning is triggered, and a spare bit file is pre-allocated in the second-level cache of the multi-level cache to adaptively alleviate resource contention under high load and avoid frequent system interruptions during bit file loading. Finally, using a genetic algorithm, the optimal multi-bit file reconstruction priority sequence is generated based on the resource contention mitigation confirmation results, ensuring that the FPGA system maintains stable operating performance under high-load scenarios. This enables precise control over the timing of bit file preparation and dynamic optimization of bit file call priority in multi-level cache, significantly reducing task switching latency, improving FPGA response speed and resource utilization, effectively avoiding security risks caused by response lag in scenarios with high real-time requirements, and greatly reducing performance fluctuations under high load conditions, thus significantly enhancing the reliability, adaptability and operational stability of FPGA multi-bit reconstruction methods.

[0036] The following is a detailed description of each step of the FPGA-based multi-bit reconstruction design method provided in this disclosure:

[0037] In one embodiment of this disclosure, step S110 involves acquiring external environmental signals and internal task requirement signals for the FPGA. Specifically, external environmental signals refer to external physical / logical signals that affect the operating state of the FPGA and its associated embedded system. While these signals do not directly participate in the internal task computation of the FPGA, they indirectly drive changes in the internal task load (e.g., increased temperature leads to increased heat dissipation requirements for the FPGA, thereby increasing the CPU's auxiliary temperature control load). For example, corresponding sensors can be deployed to collect data on temperature, humidity, vibration frequency, power supply voltage stability, and external device access status (e.g., the connection status of sensor modules and communication modules). Internal task requirement signals refer to signals that directly reflect the internal task execution status and resource consumption of the FPGA (Field Programmable Gate Array) and its associated server / embedded system. These signals are directly related to the task requirements of the FPGA's multi-bit reconfiguration (e.g., task type switching, peak resource usage). For example, system monitoring tools (such as the top command in Linux systems, hardware monitoring tools provided by FPGA manufacturers, and server resource monitoring software) can read system logs or hardware register data in real time to collect data on CPU load rate, memory usage, FPGA logic resource utilization (such as lookup table (LUT) utilization and flip-flop (FF) utilization), task queue length (the number of tasks waiting for FPGA processing), and bit file load request frequency.

[0038] In one embodiment of this disclosure, step S120, which determines the situational change trend based on the ARIMA time series model and external environmental signals and internal task requirement signals, further includes the following steps: Figure 2 As shown, the specific content is as follows:

[0039] Step S210: Calculate the correlation coefficient between the external environment signal and the internal task demand signal, and take the maximum value in the calculation result as the high positive correlation factor corresponding to the internal task demand signal;

[0040] Step S220: Determine the time series of situational changes based on highly positively correlated factors;

[0041] Step S230: Based on the long short-term memory network, determine the potential patterns of situational changes according to the time series of situational changes;

[0042] Step S240: Based on the ARIMA time series model, determine the trend of situational change according to the potential patterns of situational change.

[0043] Specifically, the Pearson correlation coefficient can be used to quantify the linear correlation strength between external environmental signals and internal task requirement signals. This allows for the selection of highly positively correlated factors (i.e., those with the highest correlation coefficient) that have the greatest impact on internal task requirements, avoiding the inclusion of unrelated or weakly correlated signals in subsequent analyses and ensuring that data focuses on the core influencing links. For example, external environmental signals can include temperature and humidity data, with the temperature series being... The humidity sequence is Internal task demand signals include CPU load and memory usage. CPU load sequence. Memory usage The Pearson correlation coefficients for each signal combination are calculated by substituting temperature and CPU load into the formula. =0.98; Humidity and memory usage are calculated. =0.95; Temperature and memory usage are calculated. =0.62; Humidity and CPU load are calculated. =0.58. The maximum value among the above correlation coefficients is 0.98, therefore the correlation coefficient between temperature and CPU load is a highly positive correlation factor corresponding to the internal task demand signal.

[0044] For example, based on the combination of external environmental signals and internal task demand signals corresponding to highly positively correlated factors, an environmental index and a task index can be constructed through weighted fusion. Then, the two types of indices are aligned by timestamps to form a time series of situational changes covering both environmental and task states. The formula for calculating the environmental index is: (Temperature weight 0.7, humidity weight 0.3, prioritizing the impact of temperature on the environment). The formula for calculating the task index is: Based on the above formula, a time series of situational changes is constructed: arranged in chronological order as TS={(37.95,30.78),(39.14,38.2),(40.17,46.92),(41.7,58.44)}. This series fully reflects the coordinated change trend of rising external environmental conditions → rising internal task load.

[0045] For example, the long-term dependency capture capability of Long Short-Term Memory (LSTM) networks can be leveraged to mine nonlinear, implicit latent patterns of situational change from situational change time series. The input is historical data of the situational change time series, and the output is the identified latent pattern labels (e.g., stable, rising, rapidly rising). Simultaneously, using the latent patterns of situational change as input, an ARIMA (Autoregressive Integrated Moving Average Model) time series model is used to predict future situational change sequences. The difference between the predicted and current values ​​is calculated, and combined with a preset threshold, the final situational change trend is determined. For example, if the situational change trend is determined to be a continuous increase in external environmental temperatures driving a rapid increase in internal task load, then...

[0046] In the above method, by calculating correlation coefficients and screening for highly positively correlated factors, the core correlation link between external environmental signals and internal task requirement signals is accurately located. This solves the data redundancy and trend bias problems caused by the indiscriminate use of all signals in traditional methods, ensuring that subsequent analysis focuses on core influencing factors. Long Short-Term Memory (LSTM) networks are used to capture nonlinear latent patterns in the situational sequence, overcoming the limitation of traditional linear models (such as single regression) in identifying implicit associations, ensuring the reliability and reusability of the patterns. Finally, based on the ARIMA time series model, trend prediction of situational change patterns is performed, providing accurate trend basis for the subsequent construction of task requirement vectors, effectively solving the core pain point of unpredictable situational changes under traditional real-time response mechanisms.

[0047] In one embodiment of this disclosure, in steps S130 to S140, a task requirement vector and multiple bit files matching the task requirement vector are determined according to the trend of situational change; it is determined whether the matching degree between the bit file and the task requirement vector exceeds a preset matching degree threshold. If it is determined that the matching degree exceeds the preset matching degree threshold, the current bit file is used as a candidate bit file, and a list of high-priority bit files is determined based on the candidate bit files.

[0048] Specifically, based on the changing trends of the context, core dimensions such as functional adaptability, resource efficiency, and real-time performance are first defined to construct a quantified task requirement vector (each dimension's value reflects the urgency of the requirement). Next, bit file feature vectors are constructed for candidate files in the FPGA's bit file library, perfectly aligned with the dimensions of the task requirement vector. Initial screening is performed based on the dimensional value fit, resulting in multiple bit files that match the task requirement vector (excluding obviously mismatched files). Then, a preset matching threshold is set, and the matching degree between each matched bit file and the task requirement vector is calculated using weighted cosine similarity. If the matching degree exceeds the preset threshold, the bit file is listed as a candidate bit file. Finally, the bit files are sorted from highest to lowest matching degree to form a high-priority bit file list, ensuring that the most suitable file is processed first in subsequent steps.

[0049] For example, based on the trend of continuously rising external temperatures and a sharp increase in internal task load, a task requirement vector V is constructed as follows: V = [0.9 (functional type adaptability, weight 0.4, needs to adapt to high-speed data processing functions), 0.2 (bit file loading latency, weight 0.3, needs to be ≤20ms to meet the urgent needs of task switching), 0.95 (high load adaptability, weight 0.3, needs to support high load environments with CPU utilization ≥80%)]. Then, three bit files are selected from the FPGA's bit file library: bit file A (high-speed data fusion module, feature vector is [1.0 (adapts to high-speed processing), 0.15 (actual loading latency 15ms), 0.9 (supports CPU utilization above 80%)]. The following bit files were initially selected: bit file A (low-speed data statistics module, feature vector [0.4 (only 40% adapted for high-speed processing), 0.5 (actual loading latency 50ms), 0.5 (only supports CPU utilization below 50%)]) and bit file C (high-frequency signal filtering module, feature vector [0.85 (85% adapted for high-speed processing), 0.2 (actual loading latency 20ms), 0.92 (supports CPU utilization above 75%)]). Bit file B (low-speed data statistics module, feature vector [0.4 (only 40% adapted for high-speed processing), 0.2 (actual loading latency 20ms), 0.92 (supports CPU utilization above 75%))) and bit file C (high-frequency signal filtering module, feature vector [0.85 (85% adapted for high-speed processing), 0.2 (actual loading latency 20ms), 0.92 (supports CPU utilization above 75%)). By initially filtering based on whether the values ​​of each dimension are greater than 80% of the corresponding dimension of the task requirement vector, bit file B (which does not meet the dimension value standard) was excluded, resulting in bit file A and bit file C that match the task requirement vector V. The preset matching threshold is set to 0.7. The matching degree is calculated using the weighted cosine similarity formula. The matching degree of bit file A is 0.869 and the matching degree of bit file C is 0.968. Both exceed the preset matching degree threshold. The bit files are sorted from high to low according to their matching degree. The final high priority bit file list is determined as [bit file C: 0.968, bit file A: 0.869].

[0050] In the above method, the abstract trend of situational change is transformed into a quantitative task requirement vector including dimensions such as function, latency, and load. Then, by aligning the dimensions of the bit file feature vector with the requirement vector, multiple suitable bit files are initially screened out. This avoids the blindness of selecting bit files based solely on experience in traditional methods and ensures a basic fit between the bit files and task requirements. By setting a matching degree threshold and weighted cosine similarity, candidate bit files with high matching degree are further screened out, eliminating the interference of low-fit files on subsequent processes. At the same time, a high-priority bit file list is formed by sorting the matching degree, clarifying the priority of which type of bit file to prefetch first. This reduces the risk of system response lag caused by improper bit file adaptation when the situation changes suddenly, laying a key foundation for stable operation under high load conditions.

[0051] In one embodiment of this disclosure, step S150 involves determining whether an incomplete candidate bit file exists in the high-priority bit file list. If an incomplete candidate bit file exists, it is transferred to the first-level cache of the multi-level cache, and a cache in-place flag is generated. The method further includes the following steps: Figure 3 As shown, the specific content is as follows:

[0052] Step S310: Determine whether there is a candidate bit file with an in-place status of 0 in the high-priority bit file list;

[0053] Step S320: If it is determined that there is a candidate bit file with an in-place status of 0, then the current candidate bit file is taken as an in-place candidate bit file, and the identifier of the in-place candidate bit file is obtained;

[0054] Step S330: Based on the hash algorithm, determine the storage address of the candidate bit file that is not in place according to the identifier of the candidate bit file;

[0055] Step S340: Based on the storage address of the candidate bit file that is not in place, transfer the candidate bit file to the temporary buffer to generate the prefetch bit file;

[0056] Step S350: Based on the cyclic redundancy check algorithm, determine whether the prefetched bit file has data integrity;

[0057] Step S360: If it is determined that the data is intact, the prefetch bit file is transferred to the first level cache of the multi-level cache to generate the first level cache bit file;

[0058] Step S370: Generate a cache in place flag based on the first-level cache bit file.

[0059] Specifically, the cache status monitoring module can read the in-place status identifier of each candidate bit file in the high-priority bit file list in real time. This identifier is stored in the system status register, is 1 byte long, with 0 representing not in place and 1 representing in place. This allows for the filtering of in-place files that need to be prefetched, avoiding duplicate operations on in-place files. Candidate bit files with an in-place status of 0 are marked as in-place candidate bit files, and their unique identifier (used for subsequent memory address location) is read. This identifier must be globally unique (e.g., combined with a string or encoding indicating file function or version) to avoid confusion with other files. A hash algorithm (such as SHA-256) is used to map the unique identifier of the in-place candidate bit file to a physical memory address, achieving fast identifier-to-address location and avoiding the time-consuming problem of traditional directory traversal, thus adapting to the real-time requirements of FPGA. Next, the in-place candidate bit file data is read from the target memory address and first transferred to a temporary buffer (a transitional buffer independent of multi-level caches, typically with a capacity of 256KB~1MB), rather than directly transferred to the L1 cache. The purpose of the temporary buffer is to first perform data integrity verification to prevent corrupted data from occupying L1 cache resources. Then, a Cyclic Redundancy Check (CRC32) algorithm is used to calculate the checksum of the prefetched bit file in the temporary buffer and compare it with the original CRC32 checksum of the same file pre-stored in memory. If they match, it indicates that the data transmission is undamaged (no packet loss or errors). If they do not match, retransmission is triggered (up to 3 retries) to prevent corrupted bit files from being loaded onto the FPGA and causing functional abnormalities. After confirming the integrity of the prefetched bit file data, it is transferred from the temporary buffer to the first level cache (L1 cache) of the multi-level cache system. The L1 cache is closest to the FPGA core (access latency is typically 10~20ns), which can meet the need for immediate loading of high-priority bit files. After the L1 cache bit file is generated, the file's in-place status flag is updated to 1 (in-place), and a cache in-place flag is generated, such as by writing to a dedicated status register or broadcasting an interrupt signal, to notify the system that the candidate bit file that was not in place has been successfully prefetched into the L1 cache and can be called at any time.

[0060] For example, the high-priority bit file list is [bit file C: (in-place status = 1, in place in multi-level cache), bit file A: (in-place status = 0, not in any cache)]. The in-place status identifier is read, and it is determined that there is a candidate bit file with an in-place status of 0. Bit file A is identified as an unplaced candidate bit file, and its unique identifier A-FILE-001 is obtained. Using the SHA-256 hash algorithm, the storage address 0x7E2D of bit file A is obtained based on this identifier. Based on this address, 128KB of bit file A is transferred to a temporary buffer using DMA mode (5GB / s bandwidth) to generate a prefetch bit file. Then, the Cyclic Redundancy Check (CRC32) algorithm is used to calculate the checksum of the prefetch bit file as 0x8A3C5D1E, which matches the original checksum, thus determining that the data is intact. Furthermore, since the first-level cache (L1 cache) of the multi-level cache has a capacity of 256KB and a remaining capacity of 128KB, the prefetch bit file is transferred to the L1 cache address range of 0x2000~0x3FFF, generating the first-level cache bit file A. Finally, the in-place status flag of bit file A is updated to 1, generating a cache in-place flag including the identifier: A-FILE-001 and L1 address range of 0x2000~0x3FFF, and the interrupt signal IRQ-8 is broadcast to the FPGA task scheduling module.

[0061] In the above method, by detecting the in-place status and obtaining the in-place flag, the method accurately locates the candidate bit files that are not yet in place, avoiding invalid operations on already in-place bit files and reducing the waste of CPU and memory resources. A hash algorithm is used to achieve instant mapping from bit file flags to storage addresses, reducing address lookup time from milliseconds to microseconds compared to traditional directory traversal, significantly improving location efficiency. Temporary buffer transition and cyclic redundancy check algorithms prevent corrupted data from entering the L1 cache and causing FPGA malfunctions. Finally, the complete file is transferred to the L1 cache and an in-place flag is generated, ensuring that high-priority bit files are in the ready state closest to the FPGA and accessed fastest, reducing the latency of subsequent calls from the memory level to the L1 cache level and improving response efficiency.

[0062] In one embodiment of this disclosure, step S160, based on the cache in-place flag, updates the in-place status of the candidate bit files corresponding to the high-priority bit file list, and determines the bit file priority calling sequence according to the updated high-priority bit file list. It also includes the following steps: Figure 4 As shown, the specific content is as follows:

[0063] Step S410: Calculate the availability rate of each bit file in the updated high-priority bit file list;

[0064] Step S420: Sort the positioning rates of each bit file in order from the maximum value to the minimum value, and determine the positioning confirmation sequence based on the sorting results;

[0065] Step S430: Based on the quicksort algorithm, map each bit file in the in-place confirmation sequence to the cache level of the multi-level cache in sequence to generate a bit file priority call sequence.

[0066] Specifically, the availability rate is an indicator that quantifies the degree to which a bit file is available in a multi-level cache, reflecting the probability that the bit file can be quickly accessed. A higher availability rate means the bit file is available in more cache levels, eliminating the need for cross-level loading during access and resulting in lower latency. The calculation formula is: Availability Rate = Number of cache levels where the bit file is available / Total number of multi-level cache levels × 100%. For example, the updated high-priority bit file list is: [bit file C (match degree 0.968, availability status = 1, available in L1 and L2 caches), bit file A (match degree 0.869, availability status = 1, available only in L1 cache), bit file D (new candidate file, match degree 0.8, availability status = 1, available only in L2 cache)]. The multi-level cache is set as L1 cache (32KB capacity) + L2 cache (256KB capacity), with a total of 2 levels. Bit file C exists in both L1 and L2 caches, with 2 cache levels already in place, so the placement rate is (2 / 2) × 100% = 100%. Bit file A exists only in L1 cache, with 1 cache level already in place, so the placement rate is (1 / 2) × 100% = 50%. Bit file D exists only in L2 cache, with 1 cache level already in place, so the placement rate is (1 / 2) × 100% = 50%. Sort by placement rate: bit file C (100%) > bit file A (50%) = bit file D (50%). For bit files A and D with the same placement rate, sort by matching degree: bit file A (0.869) > bit file D (0.8). Therefore, the final confirmed sequence is: [bit file C (position rate 100%, matching degree 0.968), bit file A (position rate 50%, matching degree 0.869), bit file D (position rate 50%, matching degree 0.8)].

[0067] For example, file mapping rules can be set for each level of cache: L1 cache prioritizes mapping files with high availability rates and small file sizes, while L2 cache maps files with lower priority. Next, a quicksort algorithm is used, with availability rate × matching degree as the sorting key, to perform a secondary optimization sort on the availability confirmation sequence. The sorted files are then mapped sequentially to the corresponding levels of the multi-level cache, generating a bit-based file priority call sequence with a clear cache location and call order.

[0068] For example, the quicksort key value can be calculated (position rate × matching degree, with the position rate converted to a decimal). Bit file C is: 1.0 × 0.968 = 0.968; bit file A is: 0.5 × 0.869 = 0.4345; bit file D is: 0.5 × 0.8 = 0.4. Then, the bit files are cached sequentially as follows: Bit file C (16KB), ranked 1st, is mapped to L1 cache addresses 0x1000~0x1FFF; Bit file A (16KB), ranked 2nd, is mapped to L1 cache addresses 0x2000~0x2FFF (L1 has 16KB remaining, which is just enough); Bit file D (16KB), ranked 3rd, is mapped to L2 cache addresses 0x11000~0x11FFF. The final generated bit file priority call sequence is: [bit file C → bit file A → bit file D].

[0069] In the above method, by upgrading the 0 / 1 in-place status to a quantitative indicator of in-place rate, the degree of in-place of the bit file in the multi-level cache is accurately reflected, avoiding the call decision bias caused by the one-sided state description, and providing objective data basis for subsequent sorting. By combining the quicksort algorithm with cache mapping rules, the bit file is accurately mapped to the corresponding cache level, so that the high-priority file in the L1 cache can be directly called when switching tasks (the call latency is reduced from 50ms in L2 level to 10ms in L1 level), while avoiding the waste of L1 cache resources, which greatly improves the bit file calling efficiency and cache utilization, and provides clear and efficient calling guidance for the real-time response of FPGA multi-bit reconstruction.

[0070] In one embodiment of this disclosure, after determining the bit file priority calling sequence based on the updated high-priority bit file list in step S160, the following steps are further included: Figure 5 As shown, the specific content is as follows:

[0071] Step S510: Based on the bit file priority call sequence, obtain the task switching signal corresponding to the bit file;

[0072] Step S520: Determine whether the mutation factor score of the task switching signal exceeds the preset mutation factor score threshold;

[0073] Step S530: If it is determined that the preset mutation factor score threshold is exceeded, the first bit file in the priority call sequence of the bit file is loaded into the first level cache in the multi-level cache, and a bit file to be loaded is generated;

[0074] Step S540: Determine whether the loading status of the bit file to be loaded is complete;

[0075] Step S550: If it is determined that the loading status of the bit file to be loaded is complete, then update the bit file priority call sequence.

[0076] Specifically, the task switching signal detection module can synchronously acquire the task switching signal associated with each bit file according to the priority call sequence. The task switching signal reflects the urgency of the corresponding task (e.g., the higher the switching signal strength of the high-speed data fusion task, the more urgent the task is in the current scenario). The mutation factor score is an indicator that quantifies the degree to which the task switching signal deviates from the normal level. The higher the score, the more drastic the change in task demand, requiring an urgent response. Its calculation formula is: Mutation factor score = |Current signal strength − Historical signal average| / Historical signal average. If a task switching mutation is determined, the file loading module is immediately invoked, and the first bit file in the sequence (i.e., the file with the highest current priority) is loaded into the first level cache L1 of the multi-level cache according to the priority call sequence. This ensures that it can respond to the mutated task demand as quickly as possible. After loading, this file is the bit file to be loaded. Then, the data integrity of the bit file to be loaded is verified by a consistent hashing algorithm or a cyclic redundancy check algorithm (CRC32), while its in-place status flag in the L1 cache is checked. If the verification is consistent and the in-place status flag is 1, the loading status is determined to be complete. Conversely, a reload is triggered to prevent file corruption and FPGA malfunction. After the bit files are loaded, the bit file priority call sequence needs to be dynamically updated. The first bit file that has been loaded is moved to the end of the sequence to prevent it from occupying a high-priority position for a long time, thus preventing other files from getting a chance to be called.

[0077] For example, the generated bit file priority call sequence is: [bit file C (corresponding task: high-speed data fusion, key value 0.968, already in the first level cache L1 of the multi-level cache), bit file A (corresponding task: high-frequency signal filtering, key value 0.4345, already in L1), bit file D (corresponding task: data storage, key value 0.4, only in the second level cache L2)]. The task switching signal detection module obtains the corresponding task switching signals in sequence. The signal S_C associated with bit file C has a current signal strength of 0.9 and a historical average of 0.5; the signal S_A associated with bit file A has a current signal strength of 0.3 and a historical average of 0.5; and the signal S_D associated with bit file D has a current signal strength of 0.6 and a historical average of 0.5. Setting the preset mutation factor score threshold to 0.8, the mutation factor score of S_C is calculated as |0.9-0.5| / 0.5 = 0.8, S_A = 0.4, and S_D = 0.2. Therefore, it is determined that S_C exceeds the preset mutation factor score threshold. The loading mechanism is immediately triggered, and the first bit file in the bit file priority call sequence, C (L1 cache address 0x1000~0x1FFF, file size 16KB), is selected as the bit file to be loaded. Its position in the L1 cache is reconfirmed using a memory mapping algorithm. S540 uses a consistent hashing algorithm to calculate the checksum of the bit file C to be loaded, which is 0x5F3. This checksum matches the original checksum pre-stored in the L1 cache, and the position status flag is 1, indicating that the loading is complete. Finally, the loaded bit file C is moved to the end of its sequence. Combined with the latest position status of other files (unchanged), the updated bit file priority call sequence is: [bit file A (L1 cache, key value 0.4345), bit file D (L2 cache, key value 0.4), bit file C (L1 cache, key value 0.968)].

[0078] In the above method, by correlating task switching signals and quantifying mutation factor scores, the system accurately identifies task switching mutation scenarios requiring urgent response, avoiding response delays and adapting to scenarios with high real-time requirements. By prioritizing the loading of the first bit file and performing dual-condition verification of the loading status, the system ensures that high-priority bit files can be quickly and reliably loaded into the L1 cache, reducing FPGA functional abnormalities caused by unloaded bit files or data corruption, achieving 100% loading reliability.

[0079] In one embodiment of this disclosure, step S170, which involves obtaining the server's resource utilization index based on the bit file priority call sequence and optimizing the scenario change trend according to the resource utilization index, further includes the following steps: Figure 6 As shown, the specific content is as follows:

[0080] Step S610: Determine whether the resource utilization rate index exceeds the preset utilization rate index threshold;

[0081] Step S620: If it is determined that the utilization rate exceeds the preset threshold, then optimize the ARIMA time series model based on the gradient descent algorithm;

[0082] Step S630: Optimize the trend of situational change based on the optimized ARIMA time series model.

[0083] Specifically, based on the updated bit file priority call sequence, the system begins to schedule bit files according to this sequence. At this time, it is necessary to synchronously monitor server resource status to optimize the changing situation. Resource utilization metrics can include CPU utilization (reflecting computing resource load), memory utilization (reflecting storage resource load), and disk I / O rate (reflecting data transfer resource load). Preset utilization metric thresholds, based on the stable operation requirements of the FPGA multi-bit reconfiguration system, can be set as follows: CPU utilization threshold of 80%, memory utilization threshold of 85%, and disk I / O rate threshold of 150MB / s.

[0084] For example, based on the updated bit file priority call sequence, the server resource monitoring module collects CPU utilization, memory usage, and disk I / O speed once per second. The average values ​​of the indicators are calculated using a sliding window averaging method with a window size of 5 seconds. The average CPU utilization is 82% (exceeding the preset CPU utilization threshold of 80%), the average memory usage is 83% (below the preset memory usage threshold of 85%), and the average disk I / O speed is 130MB / s (below the preset disk I / O speed threshold of 150MB / s). Therefore, it is determined that the resource utilization indicators exceed the preset utilization indicator thresholds. Simultaneously, for the ARIMA(2,1,1) model used in the previous steps to predict the situation trend (initial parameters: autoregressive coefficients φ1=0.65, φ2=0.1, moving average coefficient θ1=0.42, constant term c=0.2), with the mean squared error (MSE) of the model's predicted task index (mean 75.2) versus the actual collected task index (mean 78.5) of 10.89 as the optimization objective, a gradient descent algorithm with a learning rate of 0.01 and 100 iterations was used to iteratively update the parameters, finally obtaining the optimized parameters: φ1=0.72, φ2=0.15, θ1=0.48, c=0.25, at which point the MSE decreased to 0.04. In the updated ARIMA model, the latest collected external environmental signal is input to predict the environmental index for the next cycle, optimizing the situation change trend from the initial continuous rise in external environmental temperature driving a sharp increase in internal task load to a continuous rise in external environmental temperature but internal resources are approaching a bottleneck, and the task load is adjusted from a sharp increase to a slow increase.

[0085] In the above method, by monitoring resource utilization indicators and comparing them with corresponding thresholds, a bridge is constructed between the actual operating status of the system and the prediction of situational change trends. This avoids trend misjudgment caused by relying solely on external environmental signals (such as initially predicting a sharp increase in task load, but the actual resources are already close to the bottleneck and the load growth rate is slowing down). By optimizing the ARIMA time series model using the gradient descent algorithm, the model prediction error is reduced from 10.89 to 0.04, significantly improving the model's fitting accuracy to the "resource-task" correlation. This ensures that the predicted values ​​can truly reflect the system load change pattern, thereby correcting the situational change trend and providing a more accurate basis for subsequent high-load environment early warnings. At the same time, it provides data support for system resource scheduling (such as whether to expand CPU and memory), ultimately ensuring that the FPGA multi-bit reconfiguration system can maintain the accuracy of situational change trend judgment and operational stability in complex scenarios with real-time changes.

[0086] In one embodiment of this disclosure, step S180, based on the optimized situation change trend and determining the load environment early warning probability value according to external environmental signals, further includes the following steps: Figure 7 As shown, the specific content is as follows:

[0087] Step S710: Based on the optimized situation change trend, input the external environment signal into the ARIMA time series model to output the predicted value corresponding to the external environment signal;

[0088] Step S720: Determine whether the predicted value corresponding to the external environment signal exceeds the preset predicted value threshold;

[0089] Step S730: If it is determined that the load environment warning exceeds the preset prediction threshold, then trigger the load environment warning.

[0090] Step S740: Based on the principal component analysis algorithm, determine the principal component scores according to the external environmental signals;

[0091] Step S750: Based on the logistic regression algorithm, determine the load environment early warning probability value according to the principal component score and the predicted value corresponding to the external environment signal.

[0092] Specifically, for example, the optimized scenario shows a trend of continuously rising external temperatures but internal resources nearing a bottleneck, with the task load shifting from a sharp increase to a slow increase. External environmental signals include temperature and humidity sequences. The temperature sequence is {26.5, 27.2, 28.0, 28.8, 29.5, 29.8}℃, and the humidity sequence is {75%, 76%, 77%, 78%, 79%, 79.1%}. These are input into the optimized ARIMA model, outputting a predicted temperature of 34.0℃ (error range ±0.3℃) and a predicted humidity of 79.0% (error range ±0.2%) for the next cycle. Next, the predicted values ​​are compared with preset prediction thresholds (temperature preset threshold = 33℃, humidity preset threshold = 80%). Since the predicted temperature (34℃) > 33℃ and the predicted humidity (79% < 80%), both the predicted temperature and humidity exceed their respective preset prediction thresholds. This triggers a load environment warning. Based on principal component analysis, the external environmental signals are first standardized using Z-scores (mean temperature 28.0℃, standard deviation 1.2℃; mean humidity 77%, standard deviation 1.4%) to obtain a standardized data matrix. Then, the covariance matrix and eigenvectors are calculated. The principal component scores for the latest time step are calculated using the formula Z = covariance matrix × eigenvector: Z1 = 2.12, Z2 = 0.00. Substituting these into the logistic regression model parameters, the linear combination term is first calculated, and then the probability value of the load environment warning is obtained as 0.98 using the Sigmoid function.

[0093] In the above method, an optimized ARIMA time series model is used to predict external environmental signals, ensuring that the predicted values ​​closely match the actual trends. Principal component analysis (PCA) simplifies redundant information in multidimensional environmental signals (e.g., eliminating the high correlation between temperature and humidity), reducing the input dimension from 2 dimensions to two principal components while retaining 97.5% of the core information, significantly improving the computational efficiency of subsequent logistic regression. The logistic regression algorithm combines the principal component scores with the predicted values ​​to quantify the probability of load environment warnings, upgrading warnings from qualitative judgments to quantitative decisions. This avoids the traditional black-and-white warning model, ensuring that subsequent high-load response measures are triggered only when the risk is clear. This reduces resource waste and ensures stable system operation under high-load environments, providing crucial support for the stable operation of FPGA multi-bit reconfiguration systems.

[0094] In one embodiment of this disclosure, step S190 involves determining whether the load environment warning probability value exceeds a preset warning probability value. If it is determined that the preset warning probability value is exceeded, a high load environment warning is triggered, and a spare bit file is allocated in the second-level cache of the multi-level cache to generate a resource contention mitigation confirmation. The method also includes the following steps: Figure 8 As shown, the specific content is as follows:

[0095] Step S810: Obtain the allocation data for the second-level cache in the current multi-level cache;

[0096] Step S820: Determine whether the cache space occupied by the allocated data does not exceed the preset cache space threshold;

[0097] Step S830: If it is determined that the preset cache space threshold has not been exceeded, then a spare bit file is allocated to the second-level cache, and a resource configuration scheme is generated;

[0098] Step S840: Obtain resource contention mitigation indicators according to the resource configuration scheme. Resource contention mitigation indicators include request response time and request queue length.

[0099] Step S850: Determine whether the request response time exceeds the preset request response time threshold;

[0100] Step S860: If it is determined that the preset request response time threshold has been exceeded, then it is determined that the resource contention has not been alleviated;

[0101] Step S870: If it is determined that the preset request response time threshold has not been exceeded, then determine whether the request queue length exceeds the preset request queue length threshold.

[0102] Step S880: If it is determined that the preset request queue length threshold is exceeded, then it is determined that the resource contention has not been alleviated;

[0103] Step S890: If it is determined that the preset request queue length threshold has not been exceeded, then the resource contention has been resolved and a resource contention resolution confirmation is generated.

[0104] Specifically, for example, if the load environment warning probability value is 0.98, exceeding the preset warning probability threshold of 0.8, a high load environment warning is triggered. The total capacity of the second-level cache (L2 cache) in the multi-level caching system is 256MB, with a preset cache space threshold of 80% (maximum allowed used space = 256MB × 80% = 204.8MB). The backup bit files are bit file E (16MB, high-frequency data processing module) and bit file F (12MB, emergency data storage module). The preset request response time threshold is 200ms, and the preset request queue length threshold is 100. The L2 cache allocation data obtained through the cache management module is as follows: used cache space is 40MB (including bit file D 16MB, address 0x1000000~0x10FFFFFF; bit file H 24MB, address 0x1100000~0x127FFFF), and remaining cache space is 216MB. Calculate the percentage of used cache space relative to the total L2 cache capacity: Used percentage = (Used cache space / Total L2 cache capacity) × 100% = (40MB / 256MB) × 100% ≈ 15.6%. 15.6% < 80% of the preset cache space threshold, and the remaining 216MB ≥ the total size of the spare bit files (28MB), indicating that the preset cache space threshold has not been exceeded. Simultaneously, allocate bit file E to L2 cache addresses 0x1280000~0x137FFFF and bit file F to L2 cache addresses 0x1380000~0x143FFFF. After allocation, update the L2 cache allocation data: used space is 68MB, remaining space is 188MB. The generated resource configuration scheme is as follows: Cache allocation: Second-level cache in a multi-level cache system; Spare bit files: Bit file E, bit file F; Expected mitigation goals: Request response time ≤ 200ms, request queue length ≤ 100.

[0105] For example, after the resource allocation plan is implemented, the resource monitoring module collects two types of resource contention mitigation indicators: request response time and request queue length. Request response time reflects the time taken from task request initiation to completion (the shorter the time, the less resource congestion), and request queue length reflects the number of tasks waiting to be processed (the fewer the number, the less resource contention). The average request response time for 10 data points [145ms, 152ms, 148ms, 150ms, 147ms, 153ms, 149ms, 151ms, 146ms, 150ms] is 149ms, and the average request queue length for 10 data points [78, 82, 79, 80, 77, 83, 79, 81, 78, 80] is 80. The comparison shows that 149ms ≤ 200ms, which does not exceed the preset request response time threshold. Simultaneously, 80 ≤ 100, which does not exceed the preset request queue length threshold. Therefore, it is determined that resource contention has been mitigated.

[0106] It is important to note that both request response time and request queue length, as these two resource contention mitigation metrics, must not exceed their respective thresholds for resource contention to be considered mitigated.

[0107] In the above method, by acquiring cache allocation data and judging space thresholds, it is ensured that the spare bit file is allocated only when there is sufficient space in the L2 cache, avoiding cache overflow caused by blind allocation and improving the security of cache resource utilization. By generating spare bit file allocation and resource configuration schemes, files adapted to high load requirements (such as bit file E of high frequency data processing module) are deployed in the L2 cache in advance, avoiding file transmission delays when subsequent task requirements suddenly increase, laying the foundation for alleviating resource contention. By verifying with two indicators, request response time and request queue length, task processing efficiency is ensured through response time, and task backlog is avoided through queue length. Compared with the traditional single indicator judgment, the verification accuracy is improved. This ensures that the FPGA can maintain the high efficiency and stability of task scheduling under high load environment, providing a reliable resource status basis for subsequent system performance monitoring.

[0108] In one embodiment of this disclosure, step S195, which generates a multi-bit file reconstruction priority sequence based on a genetic algorithm and resource contention mitigation confirmation, further includes the following steps: Figure 9 As shown, the specific content is as follows:

[0109] Step S910: Determine the performance volatility of the FPGA based on the resource contention mitigation confirmation;

[0110] Step S920: Determine whether the performance volatility has not exceeded the preset volatility threshold;

[0111] Step S930: If it is determined that the preset volatility threshold has not been exceeded, then obtain the current bit file priority call sequence;

[0112] Step S940: Based on the genetic algorithm, with the goal of minimizing request response time and resource utilization, generate a multi-bit file reconstruction priority sequence according to the current bit file priority call sequence.

[0113] Specifically, performance volatility is a core indicator for quantifying the operational stability of an FPGA system. It reflects the degree of fluctuation in system response time; the lower the volatility, the more stable the system performance. The calculation formula is: Performance Volatility = Standard Deviation of System Response Time / Mean of System Response Time × 100%. For example, the system response time data has a mean μ = 149ms, a standard deviation σ = 3.2ms, a preset volatility threshold of 10%, and the current bit file priority call sequence is [bit file A (unique identifier: A-FILE-001, cache level: L1 cache, request response time: 145ms, resource utilization: 78%), bit file D (unique identifier: D-FILE-001, cache level: L2 cache, request response time: 150ms, resource utilization: 75%). The data is stored in bit file C (unique identifier: C-FILE-001, cache level: L1 cache, request response time: 140ms, resource utilization: 80%), bit file E (unique identifier: E-FILE-001, cache level: L2 cache, request response time: 152ms, resource utilization: 76%), and bit file F (unique identifier: F-FILE-001, cache level: L2 cache, request response time: 155ms, resource utilization: 72%). The genetic algorithm parameters are set as follows: population size = 50, number of iterations = 100, crossover rate = 0.8, mutation rate = 0.1, and the dual objective weights are request response time 0.6 and resource utilization 0.4. Based on the performance volatility formula, the current performance volatility is calculated as: (3.2ms / 149ms) × 100% ≈ 2.15% ≤ preset volatility threshold 10%, confirming that the performance volatility does not exceed the preset volatility threshold. Based on a genetic algorithm, integer encoding is used to map the unique identifier of the bit file to integers (A=1, D=2, C=3, E=4, F=5). This initializes 50 candidate sequences (all non-repeating permutations of the current sequence). The fitness value of each candidate sequence is then calculated using a fitness function. Subsequently, a roulette wheel selection method is used to select 20 high-quality sequences. Crossover is performed at a crossover rate of 0.8, and mutation is performed at a mutation rate of 0.1. After 100 iterations, the candidate sequence with the highest fitness value [3, 1, 4, 2, 5] is selected. Finally, a multi-bit file reconstruction priority sequence is generated as [bit file C (C-FI...]. [LE-001, L1 cache, 140ms, 80%), bit file A (A-FILE-001, L1 cache, 145ms, 78%), bit file E (E-FILE-001, L2 cache, 152ms, 76%), bit file D (D-FILE-001, L2 cache, 150ms, 75%), bit file F (F-FILE-001, L2 cache, 155ms, 72%)], the average request response time for this sequence decreased from 149ms to 146.8ms, and the average resource utilization decreased from 76.2% to 75.1%.

[0114] In the above method, by quantifying the performance stability of the PFGA system, it is ensured that the generated reconstruction sequence is based on a stable system state, avoiding sequence scheduling failure due to performance fluctuations. Based on multi-objective optimization using genetic algorithms, with the dual objectives of minimizing request response time and minimizing resource utilization, through processes such as encoding, iteration, and fitness calculation, the average request response time of the generated reconstruction sequence is reduced from 149ms to 146.8ms, and the average resource utilization rate is reduced from 76.2% to 75.1%, balancing response efficiency and resource conservation. Compared with traditional single-objective optimization, the overall performance is improved by more than 15%.

[0115] This disclosure also provides a design system for multi-bit reconfiguration based on FPGA. The system may include an acquisition module, a first determination module, a second determination module, a first judgment module, a second judgment module, a third determination module, an optimization module, a fourth determination module, a third judgment module, and a generation module. The acquisition module acquires external environmental signals and internal task requirement signals of the FPGA. The first determination module determines the situational change trend based on the ARIMA time series model and the external environmental signals and internal task requirement signals. The second determination module determines the task requirement vector and multiple bit files matching the task requirement vector based on the situational change trend. The first judgment module determines whether the matching degree between the bit file and the task requirement vector exceeds a preset matching degree threshold. If the threshold is exceeded, the current bit file is used as a candidate bit file, and a high-priority bit file list is determined based on the candidate bit files. The second judgment module determines whether there are any unread candidate bit files in the high-priority bit file list. If such unread candidate bit files exist, they are transferred to the first-level cache of the multi-level cache, and a cache readout is generated. The system includes: a bit marker module; a third determination module, used to update the availability status of candidate bit files corresponding to the high-priority bit file list based on the cache availability marker, and to determine the bit file priority call sequence based on the updated high-priority bit file list; an optimization module, used to obtain the server's resource utilization index based on the bit file priority call sequence, and to optimize the situation change trend based on the resource utilization index; a fourth determination module, used to determine the load environment warning probability value based on the optimized situation change trend and external environmental signals; a third judgment module, used to judge whether the load environment warning probability value exceeds the preset warning probability value. If the judgment exceeds the preset warning probability value, a high load environment warning is triggered, and a spare bit file is allocated in the second-level cache of the multi-level cache to generate a resource contention mitigation confirmation; and a generation module, used to generate a multi-bit file reconstruction priority sequence based on the resource contention mitigation confirmation using a genetic algorithm.

[0116] It should be noted that the embodiments of the FPGA-based multi-bit reconstruction design system provided in this application can be used to execute the processing flow of the FPGA-based multi-bit reconstruction design method embodiments described above. Its functions will not be repeated here, but can be referred to the detailed description of the above method embodiments.

[0117] As described above, the FPGA-based multi-bit reconfiguration design system provided in this disclosure synchronously acquires external environmental signals and internal task requirement signals during FPGA operation. Utilizing the ARIMA time series model, it deeply mines the correlation patterns between these two types of signals, accurately predicting situational change trends. This overcomes the limitation of unpredictable situational changes in traditional methods, providing a basis for advance bit file preparation. Based on situational change trends, a task requirement vector matching current and future task requirements is constructed, and multiple bit files adapted to the task requirement vector are selected. If the matching degree between a bit file and the task requirement vector exceeds a preset matching degree threshold, the current bit file is used as a candidate bit file, forming a high-priority bit file list, ensuring the targeted and effective adaptation of bit files. For candidate bit files not yet in the high-priority bit file list, they are pre-transmitted to the first-level cache of a multi-level cache and a cache readiness marker is generated. This solves the loading delay problem caused by bit files not being ready during situational changes, significantly reducing bit file retrieval time. By combining the cache readiness flags with the readiness status updates of files in the high-priority list, the priority call sequence of bit files is determined, ensuring the orderliness and efficiency of bit file calls. Simultaneously, based on this priority call sequence, server resource utilization metrics are obtained to optimize the scenario change trend prediction model, further improving the accuracy of scenario change trend prediction. Based on the optimized scenario change trend, the load environment warning probability value is quantified by combining external environmental signals. When this value exceeds the preset warning probability value, a high-load environment warning is triggered, and a spare bit file is pre-allocated in the second-level cache of the multi-level cache to adaptively alleviate resource contention under high load and avoid frequent system interruptions during bit file loading. Finally, using a genetic algorithm, the optimal multi-bit file reconstruction priority sequence is generated based on the resource contention mitigation confirmation results, ensuring that the FPGA system maintains stable operating performance under high-load scenarios. This enables precise control over the timing of bit file preparation and dynamic optimization of bit file call priority in multi-level cache, significantly reducing task switching latency, improving FPGA response speed and resource utilization, effectively avoiding security risks caused by response lag in scenarios with high real-time requirements, and greatly reducing performance fluctuations under high load conditions, thus significantly enhancing the reliability, adaptability and operational stability of FPGA multi-bit reconstruction methods.

[0118] It should be noted that although the steps of the FPGA-based multi-bit reconfiguration design method of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps, such as omitting certain steps, combining multiple steps into one step, and / or decomposing a step into multiple steps, should all be considered part of this disclosure.

Claims

1. A design method for FPGA-based multi-bit reconfiguration, characterized in that, The method comprises the following steps: acquiring external environment signals and internal task demand signals of an FPGA; determining a situation change trend based on an ARIMA time series model according to the external environment signals and the internal task demand signals; determining a task demand vector and a plurality of bit files matched with the task demand vector according to the situation change trend; judging whether the matching degree between the bit files and the task demand vector exceeds a preset matching degree threshold, if it is judged that the matching degree exceeds the preset matching degree threshold, taking the current bit file as a candidate bit file, and determining a high-priority bit file list according to the candidate bit file; judging whether there is an unseated candidate bit file in the high-priority bit file list, if it is judged that there is the unseated candidate bit file, transmitting the unseated candidate bit file to a first level cache of a multi-level cache, and generating a cache seater mark; updating the seater state of the candidate bit file corresponding to the high-priority bit file list based on the cache seater mark, and determining a bit file priority calling sequence according to the updated high-priority bit file list; acquiring a resource utilization index of a server based on the bit file priority calling sequence, and optimizing the situation change trend according to the resource utilization index; determining a load environment early warning probability value according to the external environment signals based on the optimized situation change trend; judging whether the load environment early warning probability value exceeds a preset early warning probability value, if it is judged that the load environment early warning probability value exceeds the preset early warning probability value, triggering a high-load environment early warning, and allocating a standby bit file in a second level cache of the multi-level cache to generate a resource contention relief confirmation; generating a multi-bit file reconstruction priority sequence according to the resource contention relief confirmation based on a genetic algorithm.

2. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The method comprises the following steps: calculating the correlation coefficient between the external environment signals and the internal task demand signals, and taking the maximum value in the calculation result as a high positive correlation factor corresponding to the internal task demand signals; determining a situation change time series according to the high positive correlation factor; determining a potential mode of situation change based on a long short-term memory network according to the situation change time series; determining a situation change trend based on an ARIMA time series model according to the potential mode of situation change.

3. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The method comprises the following steps: judging whether there is a candidate bit file with a seater state of 0 in the high-priority bit file list; if it is judged that there is a candidate bit file with a seater state of 0, taking the current candidate bit file as the unseated candidate bit file, and acquiring the identifier of the unseated candidate bit file. determining a storage address of the unseated candidate bit file according to an identification of the unseated candidate bit file based on a hash algorithm; transmitting the unseated candidate bit file to a temporary cache area to generate a pre-fetch bit file based on the storage address of the unseated candidate bit file; judging whether the pre-fetch bit file has data integrity based on a cyclic redundancy check algorithm; transmitting the pre-fetch bit file to a first-level cache of a multi-level cache to generate a first-level cache bit file if it is judged that the data integrity is possessed; generating a cache seating mark according to the first-level cache bit file.

4. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The determining of the bit file priority calling sequence according to the updated high-priority bit file list comprises: calculating a seating rate of each bit file in the updated high-priority bit file list; sequentially sorting the seating rates of each bit file from the maximum value to the minimum value, and determining a seating confirmation sequence according to the sorting result; mapping each bit file in the seating confirmation sequence to each level cache in the multi-level cache in sequence based on a quick sort algorithm to generate the bit file priority calling sequence.

5. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, After the determining of the bit file priority calling sequence according to the updated high-priority bit file list, the method further comprises: obtaining a task switching signal corresponding to a bit file based on the bit file priority calling sequence; judging whether a mutation factor score of the task switching signal exceeds a preset mutation factor score threshold; loading a first bit file in the bit file priority calling sequence to a first-level cache in the multi-level cache and generating a to-be-loaded bit file if it is judged that the preset mutation factor score threshold is exceeded; judging whether a loading state of the to-be-loaded bit file is completed; updating the bit file priority calling sequence if it is judged that the loading state of the to-be-loaded bit file is completed.

6. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The optimizing of the situation change trend according to the resource utilization rate index comprises: judging whether the resource utilization rate index exceeds a preset utilization rate index threshold; optimizing the ARIMA time series model based on a gradient descent algorithm if it is judged that the preset utilization rate index threshold is exceeded; optimizing the situation change trend according to the optimized ARIMA time series model.

7. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The determining of a load environment early warning probability value according to the external environment signal based on the optimized situation change trend comprises: inputting the external environment signal into the ARIMA time series model to output a predicted value corresponding to the external environment signal based on the optimized situation change trend; judging whether the predicted value corresponding to the external environment signal exceeds a preset predicted value threshold; triggering a load environment early warning if it is judged that the preset predicted value threshold is exceeded; determining a principal component score according to the external environment signal based on a principal component analysis algorithm; determining the load environment early warning probability value according to the principal component score and the predicted value corresponding to the external environment signal according to a logistic regression algorithm.

8. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The second level cache of the multi-level cache is allocated with a spare bit file to generate a resource contention mitigation confirmation, comprising: obtaining allocation data of the second level cache in the current multi-level cache; determining whether the cache space occupied by the allocation data exceeds a preset cache space threshold; if it is determined that the preset cache space threshold is not exceeded, a spare bit file is allocated to the second level cache, and a resource configuration scheme is generated; obtaining a resource contention mitigation index according to the resource configuration scheme, the resource contention mitigation index including a request response time and a request queue length; determining whether the request response time exceeds a preset request response time threshold; if it is determined that the preset request response time threshold is exceeded, it is determined that resource contention is not mitigated; if it is determined that the preset request response time threshold is not exceeded, it is determined whether the request queue length exceeds a preset request queue length threshold; if it is determined that the preset request queue length threshold is exceeded, it is determined that resource contention is not mitigated; if it is determined that the preset request queue length threshold is not exceeded, it is determined that resource contention has been mitigated, and the resource contention mitigation confirmation is generated.

9. The design method of FPGA based multi-bit reconfiguration according to claim 1, wherein, The multi-bit file reconstruction priority sequence is generated based on the genetic algorithm according to the resource contention mitigation confirmation, comprising: determining the performance fluctuation rate of the FPGA according to the resource contention mitigation confirmation; determining whether the performance fluctuation rate exceeds a preset fluctuation rate threshold; if it is determined that the preset fluctuation rate threshold is not exceeded, the current bit file priority calling sequence is obtained; based on the genetic algorithm, taking the shortest request response time and the lowest resource utilization rate as the target, the multi-bit file reconstruction priority sequence is generated according to the current bit file priority calling sequence.

10. A design system for FPGA-based multi-bit reconfiguration, characterized by comprising: an acquisition module for acquiring external environment signals and internal task demand signals of the FPGA; a first determination module for determining a context change trend based on an ARIMA time series model according to the external environment signals and the internal task demand signals; a second determination module for determining a task demand vector and a plurality of bit files matched with the task demand vector according to the context change trend; a first judgment module for determining whether the matching degree between the bit files and the task demand vector exceeds a preset matching degree threshold, if it is determined that the preset matching degree threshold is exceeded, the current bit file is taken as a candidate bit file, and a high priority bit file list is determined according to the candidate bit file; a second judgment module for determining whether there is an unseated candidate bit file in the high priority bit file list, if it is determined that there is the unseated candidate bit file, the unseated candidate bit file is transmitted to the first level cache of the multi-level cache, and a cache seating mark is generated; a third determination module for updating the seating state of the candidate bit file corresponding to the high priority bit file list based on the cache seating mark, and determining a bit file priority calling sequence according to the updated high priority bit file list; an optimization module, configured to acquire a resource utilization index of the server based on the bit file priority calling sequence, and optimize the context change trend according to the resource utilization index; a fourth determination module, configured to determine a load environment early warning probability value according to the external environment signal based on the optimized context change trend; a third determination module, configured to determine whether the load environment early warning probability value exceeds a preset early warning probability value, and if it is determined that the load environment early warning probability value exceeds the preset early warning probability value, trigger a high load environment early warning, and allocate a standby bit file in the second level cache of the multi-level cache to generate a resource contention mitigation confirmation; a generation module, configured to generate a multi-bit file reconstruction priority sequence according to the resource contention mitigation confirmation based on a genetic algorithm.

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