Silicon substrate interconnection yield prediction and optimization method
By establishing a yield prediction model at the wafer-level chip level, the yield prediction problem of complex interconnect structures is solved, enabling accurate prediction and optimization in the early stages of design, thereby improving design efficiency and production success rate.
Patent Information
- Application Number
- CN202511385026.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-01-16
AI Technical Summary
In wafer-level chip manufacturing, existing yield testing methods are not applicable to complex high-density interconnect structures, making it impossible to accurately predict interconnect yield before production, which affects production costs and performance.
By acquiring the location data and yield measurement data of multiple interconnect points to be measured on the target wafer-level substrate, a target yield prediction model is established. This model is then used to predict the yield of the interconnect points to be measured, and architecture adjustments and topology network optimizations are performed in the early stages of design.
It enables accurate prediction of interconnect yield before actual production, improves design efficiency, reduces production costs, and ensures the successful production and application of large-size interconnect substrates.
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Figure CN121350455A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wafer testing technology, and in particular to a method for predicting and optimizing the yield of silicon substrate interconnects. Background Technology
[0002] With the explosive growth in demand for artificial intelligence (AI) computing power, traditional graphics processing unit (GPU) clusters, which are connected by boards and cables and built into racks, face challenges such as high power consumption, limited bandwidth, and low space utilization when scaling up. To address these challenges, wafer-level chip technology has emerged. Wafer-level chips typically integrate multiple AI chips directly on the same large wafer, and use photolithographically etched metal interconnects to achieve direct interconnection between the chips. This approach can significantly improve bandwidth, computing power, and energy efficiency.
[0003] In wafer-level chip manufacturing, the wafer carrying interconnects is called a large-size substrate or silicon interposer. Compared to traditional chip interconnects, the interconnect lengths on the substrate in wafer-level chips far exceed 30mm, making the interconnect structure extremely complex and the wiring density extremely high. Therefore, controlling the yield of interconnects during wafer-level substrate manufacturing becomes particularly critical, directly affecting the cost and performance of the final product.
[0004] Therefore, before actual wafer-level chip production, there is an urgent need for a method that can accurately predict the interconnect yield of silicon substrates. Summary of the Invention
[0005] Therefore, it is necessary to provide a method for predicting and optimizing silicon substrate interconnect yield that can accurately predict substrate interconnect yield, in order to address the above-mentioned technical problems.
[0006] In a first aspect, this application provides a method for predicting the interconnect yield of silicon substrates. The method includes:
[0007] Acquire position data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate; the interconnect points to be measured are used to characterize the interconnect points on the interconnect lines of the target wafer-level substrate to be subjected to yield measurement;
[0008] Based on the location data of multiple interconnect points to be measured and the measured yield data, a target yield prediction model is determined; the target yield prediction model includes the mapping relationship between the location of interconnect points on the target wafer-level substrate and the yield.
[0009] Based on the target yield prediction model, the yield of the interconnect point to be predicted on the target wafer-level substrate is predicted, and the yield prediction result of the interconnect point to be predicted is obtained.
[0010] In one embodiment, determining the target yield prediction model based on the location data of the plurality of interconnect points to be measured and the yield measurement data includes:
[0011] Obtain the initial yield prediction model;
[0012] Using the initial yield prediction model and the location data of the interconnect point to be tested, the yield of the interconnect point to be tested is predicted to obtain the initial prediction result of the interconnect point to be tested;
[0013] Based on the initial prediction results of the interconnection points to be measured and the measured yield data, the parameters of the initial yield prediction model are optimized to determine the target yield prediction model.
[0014] In one embodiment, the step of optimizing the parameters of the initial yield prediction model based on the initial prediction result of the interconnection to be measured and the yield measurement data to determine the target yield prediction model includes:
[0015] Based on the initial prediction results of the interconnection points to be measured and the measured yield data, the parameters of the initial yield prediction model are optimized to obtain the intermediate yield prediction model.
[0016] Using the intermediate yield prediction model and the location data of the interconnect point to be tested, the yield of the interconnect point to be tested is predicted to obtain the intermediate prediction result of the interconnect point to be tested;
[0017] Using the intermediate yield prediction model and the location data of the interconnect point to be verified, the yield of the interconnect point to be verified is predicted to obtain the intermediate prediction result of the interconnect point to be verified; the interconnect point to be verified is an interconnect point on the interconnect line of the target wafer-level substrate that is different from the interconnect point to be measured.
[0018] If the intermediate prediction results of the interconnection point to be tested meet the first preset condition and the intermediate prediction results of the interconnection point to be verified meet the second preset condition, the intermediate yield prediction model is determined to be the target yield prediction model.
[0019] In one embodiment, the initial yield prediction model employs at least one of a Gaussian fitting model, a Fourier fitting model, and a Bayesian estimation model.
[0020] In one embodiment, acquiring the location data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate includes:
[0021] Identify multiple interconnect points to be measured in the target wafer-level substrate, and acquire the position data of the multiple interconnect points to be measured;
[0022] For each interconnection point to be tested, a DC test is performed on the interconnect line where the interconnection point is located to obtain the path impedance of the interconnect line where the interconnection point is located.
[0023] Based on the path impedance corresponding to the multiple interconnect points to be tested, the measured yield data of the multiple interconnect points to be tested are determined.
[0024] Secondly, this application also provides a method for optimizing a silicon substrate, the method comprising:
[0025] A wafer-level chip is provided; the wafer-level chip includes a wafer-level substrate;
[0026] The yield of target interconnect points on the wafer-level substrate is predicted using the silicon substrate interconnect yield prediction method provided in the first aspect of this application.
[0027] If the yield prediction result of the target interconnect does not meet the preset yield condition, the interconnect line where the target interconnect is located is adjusted, and / or the communication link in the wafer-level chip related to the target interconnect is adjusted.
[0028] Thirdly, this application also provides a silicon substrate interconnect yield prediction device. The device includes:
[0029] The acquisition module is used to acquire the position data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate; the interconnect points to be measured are used to characterize the interconnect points on the interconnect lines of the target wafer-level substrate that are to be subjected to yield measurement.
[0030] The determination module is used to determine a target yield prediction model based on the position data of multiple interconnect points to be measured and the yield measurement data; the target yield prediction model includes the mapping relationship between the position of interconnect points on the target wafer-level substrate and the yield;
[0031] The prediction module is used to predict the yield of the interconnect point to be predicted on the target wafer-level substrate based on the target yield prediction model, and obtain the yield prediction result of the interconnect point to be predicted.
[0032] Fourthly, this application also provides a silicon substrate optimization apparatus, the apparatus comprising:
[0033] A module is provided for providing a wafer-level chip; the wafer-level chip includes a wafer-level substrate;
[0034] The silicon substrate interconnect yield prediction device provided in the third aspect of this application is used to predict the yield of target interconnect points on the wafer-level substrate.
[0035] An optimization module is used to adjust the interconnect line where the target interconnect point is located, and / or adjust the communication link in the wafer-level chip related to the target interconnect point, when the yield prediction result of the target interconnect point does not meet the preset yield conditions.
[0036] Fifthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the silicon substrate interconnect yield prediction method provided in the first aspect of this application or the silicon substrate optimization method provided in the second aspect of this application.
[0037] Sixthly, this application also provides a computer-readable storage medium. This computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the silicon substrate interconnect yield prediction method provided in the first aspect of this application or the silicon substrate optimization method provided in the second aspect of this application.
[0038] In a seventh aspect, this application also provides a computer program product. This computer program product includes a computer program that, when executed by a processor, implements the silicon substrate interconnect yield prediction method provided in the first aspect of this application or the silicon substrate optimization method provided in the second aspect of this application.
[0039] The aforementioned silicon substrate interconnect yield prediction and optimization method acquires the position data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate. Based on the position data and yield measurement data of multiple interconnect points to be measured, a target yield prediction model is determined. The target yield prediction model includes the mapping relationship between the position and yield of interconnect points on the target wafer-level substrate. Based on the target yield prediction model, the yield of the interconnect points to be predicted on the target wafer-level substrate is predicted to obtain the yield prediction result of the interconnect points to be predicted. This application obtains discrete location data and yield measurement data of multiple test points on the interconnect lines of a wafer-level substrate. Based on this data, a target yield prediction model is determined. Then, this model is used to predict the yield of the interconnect points to be predicted on the target wafer-level substrate. Before expensive and time-consuming actual manufacturing, the yield prediction model obtained by combining the interconnect yield of the equipment production can be used to evaluate the yield feedback caused by the current structure. This allows for targeted and timely architectural adjustments, topology network optimization, and fault-tolerant design based on the yield feedback corresponding to the early stage of wafer-level chip design. Ultimately, this significantly improves design efficiency, reduces production costs, and improves actual performance, ensuring the successful production and application of large-size interconnect substrates. Attached Figure Description
[0040] Figure 1 This is a diagram illustrating the application environment of a silicon substrate interconnect yield prediction method in one embodiment.
[0041] Figure 2 This is a flowchart illustrating a silicon substrate interconnect yield prediction method in one embodiment;
[0042] Figure 3 This is a flowchart illustrating the process of determining a target yield prediction model in one embodiment;
[0043] Figure 4 This is a flowchart illustrating the process of determining the target yield prediction model in another embodiment;
[0044] Figure 5 This is a schematic diagram of a test point selection scheme for substrate yield measurement in one embodiment;
[0045] Figure 6 This is a flowchart illustrating the process of acquiring location data and measured yield data in one embodiment.
[0046] Figure 7 This is a flowchart illustrating a silicon substrate optimization method in one embodiment;
[0047] Figure 8 This is a schematic diagram of the interconnection point to be measured in one embodiment;
[0048] Figure 9 This is a schematic diagram of the continuous fitting yield function obtained after fitting discrete values of experimental test data to a Gaussian in one embodiment;
[0049] Figure 10 This is a schematic diagram illustrating the distribution of predicted yield with respect to wafer-level chip physical coordinates and the confidence level distribution in one embodiment.
[0050] Figure 11 This is a schematic diagram of the fitting results of the yield distribution at various points on the wafer in one embodiment;
[0051] Figure 12 This is a structural block diagram of a silicon substrate interconnect yield prediction device in one embodiment;
[0052] Figure 13 This is a structural block diagram of a silicon substrate optimization device in one embodiment;
[0053] Figure 14 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0055] Before describing the embodiments of this application, the relevant terms involved in this application will be explained.
[0056] Substrate (silicon interposer): The term "interposer" refers to a wafer that provides electrical interconnections for chips.
[0057] Vertical power supply unit: A PCB that performs voltage conversion from the bottom layer to the top layer, for example, 200V to 12V.
[0058] Transmission lines: also known as interconnects or interconnect wires, are generally made of copper wires and are on the micrometer scale.
[0059] Design iteration: The process of modifying interconnect parameters until signal integrity is satisfied.
[0060] Local interconnects: Several transmission lines that are close together, usually within a local area.
[0061] Computing resources: Server hardware resources used in the simulation.
[0062] Through-silicon via (TSV): A vertical conductive channel that runs through a silicon wafer to enable electrical connections between different layers.
[0063] Metal alignment: A critical process in semiconductor manufacturing used to ensure precise positional matching of metal structures between different layers.
[0064] Pre-bond stage: The process of making preliminary contact and fixing the surfaces of two wafers or chips to be bonded before formal bonding.
[0065] Coefficient of determination (R) 2 ): An index that measures the goodness of fit between model predictions and actual observations. The value ranges from 0 to 1. The closer the value is to 1, the better the model's prediction performance.
[0066] FIMV (Fill-in-the-Voltage Measurement): Used in chip testing, it is a current-driven voltage measurement method.
[0067] Confidence level: Used to describe the reliability of an estimation result.
[0068] The implementation environment of the solution provided in the embodiments of this application will be described below.
[0069] Current GPU clusters typically use a plug-and-play board connection and rack-mount setup. With the explosive growth in AI computing power demands, GPU clusters face three major challenges when scaling up: soaring power consumption, limited bandwidth, and low space resource utilization. In traditional technology, AI chips are first integrated onto their respective boards, which are then connected by cables. It is precisely these long-distance, large-size cables that severely limit the communication bandwidth between AI chips.
[0070] To address these pain points, wafer-level chip technology has emerged, which integrates multiple AI chips directly onto a single wafer. Interconnects between the chips are achieved through internally photolithographically etched metal interconnects, replacing the need for traditional cable connections on circuit boards. Practical experience has demonstrated that this integration method offers significant advantages in improving bandwidth and computing power while reducing power consumption, and it has broad application prospects.
[0071] In wafer-level chip manufacturing, multiple AI chips are directly interconnected on the same wafer using metal lines. The wafer carrying these interconnects can be referred to as a large-size substrate or a silicon interposer. This application primarily addresses the large-size substrate of this wafer-level chip, where the large-size substrate can be a passive substrate, meaning it contains only metal interconnects and no active devices.
[0072] Furthermore, in the unique structure of wafer-level chips, each AI chip has its own vertical power supply unit on the back side of the substrate. This means that the area occupied by the AI chip on a large substrate depends primarily on the area of the AI chip itself and the projected area of the power supply unit on the back side of the substrate. Due to process limitations, the area of the vertical power supply unit on the back side is generally much larger than the area of the AI chip itself. Therefore, the area occupied by the AI chip on the substrate may be up to twice the area of the AI chip itself, resulting in a large spacing between the AI chips. Due to the increased chip spacing, the interconnect length required to achieve interconnection between AI chips on the substrate is much longer than that of existing chip products (usually within 3 mm), typically exceeding 30 mm, forming unique long-distance interconnects.
[0073] Due to the high cost and long production cycle of wafer-level systems, traditional yield testing, which can only be performed after wafer fabrication is completed, is no longer sufficient. The complex interconnect structures and extremely high wiring density of wafer-level chips render existing yield testing solutions unsuitable for this specific scenario. Therefore, there is an urgent need for an end-to-end, full-process design methodology for predicting and providing feedback on wafer-level interconnect yield. This would allow for yield assessment in the early stages of upper-level architecture design, and enable adjustments to the design and the introduction of fault-tolerant mechanisms based on feedback results. This is crucial for guiding the production and deployment of large-size wafer-level substrates.
[0074] The silicon substrate interconnect yield prediction method and silicon substrate optimization method provided in the embodiments of this application can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or placed in the cloud or on other network servers. Terminal 102 or server 104 can test the yield of silicon substrate interconnects, directly using the test results to fit a predictive model for substrate interconnect yield. Based on the fitted yield prediction model, the yield at different interconnect coordinate points on the silicon substrate can be predicted, as well as the yield distribution at physical locations on the silicon substrate. This can guide the design and iteration of wafer-level chips. In the early stages of wafer-level system architecture design, feedback from the substrate interconnect yield of equipment production is used to adjust the wafer topology network design and design corresponding fault-tolerance mechanisms to achieve an end-to-end closed-loop design scheme.
[0075] The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, and smart in-vehicle systems. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted devices. The server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.
[0076] In one embodiment, such as Figure 2 As shown, a method for predicting the interconnect yield of silicon substrates is provided, which is then applied to... Figure 1 Taking the server in the example, the following steps are included:
[0077] Step 202: Obtain the location data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate.
[0078] Among them, the interconnect points to be measured are used to characterize the interconnect points on the interconnect lines of the target wafer-level substrate that are to be measured for yield. The interconnect points can refer to points on the interconnect lines.
[0079] In this embodiment, the interconnect point to be measured can be any point on the interconnect line of the target wafer-level substrate, which is used to characterize a specific physical location on the target wafer-level substrate. The location data of the interconnect point to be measured can include the coordinate data of the interconnect point to be measured on the target wafer-level substrate.
[0080] In this application embodiment, the measured yield data of the interconnect point to be measured can refer to the interconnect performance data of the interconnect point to be measured obtained through physical measurement. It can be used to characterize the probability that the point can work normally when it is part of an interconnect path. The measured yield data of this application embodiment can reflect the manufacturing quality or defect probability of the physical location of the point, providing basic data for subsequent yield prediction models, enabling them to reflect the quality differences at different locations on the wafer.
[0081] For example, the server can select several interconnect points to be tested from the interconnect lines of the target wafer-level substrate according to the circuit design structure of the target wafer-level substrate and using preset rules. The server can control the corresponding testing equipment to perform physical measurements on each selected interconnect point to determine its connectivity. This measurement process can generate a discrete dataset containing the physical location coordinates of all interconnect points to be tested and their corresponding yield measurement data.
[0082] Step 204: Based on the location data of multiple interconnect points to be measured and the measured yield data, determine the target yield prediction model.
[0083] The target yield prediction model includes the mapping relationship between the location of interconnect points on the target wafer-level substrate and the yield.
[0084] For example, the server can use a model fitting method to fit the discrete dataset, which includes location data and measured yield data, so that the generated prediction curve, plane or model fits all measured data points as accurately as possible. The successfully fitted model will transform the discrete measured yield data into a continuous yield prediction function. This model function can output the predicted yield value corresponding to a given interconnection point location.
[0085] Step 206: Based on the target yield prediction model, predict the yield of the interconnect points to be predicted on the target wafer-level substrate, and obtain the yield prediction results of the interconnect points to be predicted.
[0086] The interconnect points to be predicted can be interconnect points on the wafer-level substrate that have not yet undergone yield testing but require yield evaluation, or they can be interconnect points that have already undergone yield testing, in order to verify the accuracy of the yield prediction model. The yield prediction result can refer to the estimated value reflecting the interconnect performance of the interconnect points to be predicted, calculated by the yield prediction model.
[0087] For example, the server can receive different but clearly defined interconnect coordinates, input this location data into a defined target yield prediction model, and obtain the yield prediction results for the corresponding location data output by the target yield prediction model. Based on the yield prediction results, the server can make targeted changes to the wafer-level system architecture, simulating the topology network adjustment process involved in wafer-level chip design iterations.
[0088] In the aforementioned silicon substrate interconnect yield prediction method, the location data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate are obtained. Based on the location data and yield measurement data of multiple interconnect points to be measured, a target yield prediction model is determined. The target yield prediction model includes the mapping relationship between the location and yield of interconnect points on the target wafer-level substrate. Based on the target yield prediction model, the yield of the interconnect points to be predicted on the target wafer-level substrate is predicted to obtain the yield prediction result of the interconnect points to be predicted. This application embodiment acquires discrete location data and measured yield data of multiple test points on the interconnect lines of a wafer-level substrate. Based on this data, a target yield prediction model is determined. This model is then used to predict the yield of the interconnect points on the target wafer-level substrate. This allows for the evaluation of yield feedback from the current structure by combining the yield prediction model obtained from the interconnect yield of the equipment before expensive and time-consuming actual manufacturing. This enables targeted and timely adjustments to the architecture, optimization of the topology network, and fault-tolerant design based on the yield feedback corresponding to the early stage of wafer-level chip design. Ultimately, this significantly improves design efficiency, reduces production costs, and enhances actual performance, ensuring the successful production and application of large-size interconnect substrates.
[0089] In one exemplary embodiment, such as Figure 3 As shown, step 204 may include steps 302 to 306, wherein:
[0090] Step 302: Obtain the initial yield prediction model.
[0091] The initial yield prediction model can refer to a function or algorithm with a specific mathematical form that is pre-selected before data fitting and parameter optimization.
[0092] For example, the initial yield prediction model can be implemented using a numerical analysis model, which may include at least one of a Gaussian fitting model, a Fourier fitting model, and a Bayesian estimation model. The initial yield prediction model can also be implemented using a machine learning model, such as a support vector machine model or a neural network model.
[0093] Step 304: Using the initial yield prediction model and the location data of the interconnect points to be tested, the yield of the interconnect points to be tested is predicted to obtain the initial prediction results of the interconnect points to be tested.
[0094] The initial prediction result refers to the yield estimate calculated by the initial yield prediction model based on the location information of the interconnect points to be measured, before the model parameters have been calibrated and optimized with actual data.
[0095] For example, the server inputs the location data of the interconnect point to be measured on the target wafer-level chip obtained in step 202 into the initial yield prediction model, and obtains the initial prediction result of the interconnect point to be measured output by the initial yield prediction model.
[0096] Step 306: Based on the initial prediction results of the interconnect points to be measured and the measured yield data, optimize the parameters of the initial yield prediction model to determine the target yield prediction model.
[0097] Parameter optimization can refer to the process of iteratively adjusting the internal variables of the model, such as the coefficients, center points, and standard deviations of the function, in order to minimize the difference between the model's prediction results and the actual measured data.
[0098] For example, the server can compare the initial prediction result obtained in step 304 with the measured yield data obtained in step 202. For instance, it can calculate the error between the two sets of data, such as the mean squared error (MSE), and then use an optimization algorithm, such as gradient descent or least squares, to iteratively adjust the model parameters based on the error until the model's prediction result can accurately fit all measured data points. When the optimization reaches a preset accuracy requirement (e.g., the error approaches zero), the final parameter values will be determined, thereby generating a target yield prediction model that can be used to predict the yield of the entire wafer-level substrate.
[0099] In this embodiment, by optimizing the model parameters using the initial prediction results and measured yield data, the accuracy and reliability of the final prediction model can be ensured, enabling it to accurately map the yield distribution at any location on the wafer-level substrate, thereby providing a solid and reliable data foundation for subsequent design guidance.
[0100] In one exemplary embodiment, such as Figure 4 As shown, step 306 may include steps 402 to 408, wherein:
[0101] Step 402: Based on the initial prediction results of the interconnection points to be measured and the measured yield data, optimize the parameters of the initial yield prediction model to obtain the intermediate yield prediction model.
[0102] The intermediate yield prediction model refers to the yield prediction model obtained by fitting the location data and measured yield data of multiple interconnect points to be tested. This intermediate yield prediction model is a model that iteratively optimizes the parameters of the initial yield prediction model using multiple sets of initial prediction results and measured yield data of the interconnect points to be tested.
[0103] Step 404: Using the intermediate yield prediction model and the location data of the interconnection point to be tested, the yield of the interconnection point to be tested is predicted to obtain the intermediate prediction result of the interconnection point to be tested.
[0104] In this embodiment of the application, after obtaining the intermediate yield prediction model, the server can design a comparative experiment to verify whether the intermediate yield prediction model can accurately predict the interconnect yield based on the coordinates of random interconnects at the wafer level.
[0105] For example, the server can select the yield of the measured coordinates to test the intermediate yield prediction model. For the measured coordinates, the server can select the location data of the interconnection point to be measured and the measured yield data in step 202, input the location data of the interconnection point to be measured into the intermediate yield prediction model, obtain the intermediate prediction result of the interconnection point to be measured output by the intermediate yield prediction model, and determine that the intermediate yield prediction model can accurately predict the measured coordinates if the intermediate prediction result of the interconnection point to be measured meets the first preset condition.
[0106] The first preset condition may include the difference between the predicted yield represented by the intermediate prediction result of the interconnection point to be tested and the measured yield data of the interconnection point to be tested satisfying a difference condition, such as the R-value of the predicted yield and the measured yield. 2 The mean square error (MSE) is 1.000, and the mean square error (MSE) is 0.000.
[0107] Step 406: Using the intermediate yield prediction model and the location data of the interconnect to be verified, the yield of the interconnect to be verified is predicted to obtain the intermediate prediction result of the interconnect to be verified.
[0108] Among them, the interconnect points to be verified are the interconnect points on the interconnect lines of the target wafer-level substrate that are different from the interconnect points to be measured.
[0109] For example, the server can select yield values for unmeasured coordinates to test the intermediate yield prediction model. For unmeasured coordinates, the server can select random coordinates on the interconnect lines of the target wafer-level substrate as the location data of the interconnect point to be verified. The location data of the interconnect point to be verified is input into the intermediate yield prediction model, and the intermediate prediction result of the interconnect point to be verified is obtained from the intermediate yield prediction model. If the intermediate prediction result of the interconnect point to be verified meets the second preset condition, it is determined that the intermediate yield prediction model can accurately predict for random coordinates.
[0110] The second preset condition may include the predicted yield of the intermediate prediction results of the interconnect to be verified belonging to a preset interval, such as the predicted yield being within the interval [0, 1]. The second preset condition may also include the predicted yield of the intermediate prediction results conforming to the distribution trend of the measured yield data of the interconnect to be tested.
[0111] In one possible implementation, the server can determine the measured yield distribution based on the location data and measured yield data of multiple interconnect points to be tested, such as an actual distribution map (heat map or 3D curve). Then, based on the location data and predicted yield of the interconnect points to be verified, the server can determine the predicted yield distribution, such as a predicted distribution map. By comparing the difference between the actual distribution map and the predicted distribution map, such as the shape and trend, the server can determine whether the predicted yield represented by the intermediate prediction result conforms to the distribution trend of the measured yield data of the interconnect points to be tested.
[0112] Alternatively, the server can calculate the statistical similarity between the predicted yield distribution and the measured yield distribution. For example, a correlation coefficient can be used to measure the spatial correlation between the two sets of data, or a KS test can be used to determine whether the two sets of data come from the same distribution. If the calculated statistical indicators (such as a high correlation coefficient or passing the KS test) meet the preset criteria, it can be determined that the predicted yield conforms to the distribution trend of the measured yield.
[0113] Step 408: If the intermediate prediction results of the interconnection points to be measured meet the first preset condition and the intermediate prediction results of the interconnection points to be verified meet the second preset condition, the intermediate yield prediction model is determined as the target yield prediction model.
[0114] In this embodiment, by performing dual verification on the intermediate yield prediction model, and simultaneously verifying its fitting accuracy to measured data and its generalization ability to unmeasured data, it is possible to ensure that the determined target yield prediction model is highly accurate and reliable, providing trustworthy prediction results for subsequent design.
[0115] In practical applications, during step 202, the server can determine multiple interconnect points to be tested based on the wafer-level system architecture design and circuit structure to obtain representative yield information. For example, the server can select points on metal interconnect lines with high requirements for alignment and connectivity at the boundary of the photolithography window. The server can also select TSV (Through Silicon Via) points that are crucial for connectivity after subsequent thinning processes. TSV points can refer to the endpoints or connection locations of TSV vias on the substrate surface or internal interconnect layers.
[0116] Please refer to Figure 5 In one possible implementation, the server can uniformly select multiple test windows on a large-size wafer substrate. Utilizing reusable test windows, each window defines the coordinates of an interconnect point for testing, representing a representative location on the interconnect. By applying this test window in a step-by-step, repetitive manner across the entire wafer's interconnect network, the server can efficiently select a sufficient number and uniformly distributed number of interconnect points to be tested, thereby providing comprehensive raw data for subsequent yield prediction models.
[0117] In one embodiment, such as Figure 6 As shown, step 202 includes:
[0118] Step 602: Determine multiple interconnect points to be measured in the target wafer-level substrate and obtain the location data of multiple interconnect points to be measured.
[0119] Step 604: For each interconnection point to be tested, perform a DC test on the interconnect line where the interconnection point is located to obtain the path impedance of the interconnect line where the interconnection point is located.
[0120] For example, in the prebond stage, the server can select the two endpoints of the interconnect line containing each interconnect point to be tested. These two endpoints can refer to the two ends of a specific interconnect line segment containing the interconnect point to be tested. Based on the C4 bumps corresponding to the two endpoints of the interconnect line in the chip design, a set of C4 bumps is determined to detect the connectivity of the interconnect line containing the interconnect point to be tested. The server can control the test equipment to perform tests on the C4 bump side to obtain the impedance value of the interconnect line path.
[0121] Specifically, for the interconnect point m1_rd to be tested, the server can select the coordinates of two points on an interconnect line where m1_rd is located, such as point m1_rd (i.e., as the endpoint) and point m1_ru, determine the C4 bump corresponding to point m1_rd and the C4 bump corresponding to point m1_ru, and then perform a DC test on these two bumps to obtain the path impedance between points m1_rd and m1_ru, so as to detect the connectivity between points m1_rd and m1_ru.
[0122] Step 606: Based on the path impedance corresponding to multiple interconnect points to be tested, determine the measured yield data of multiple interconnect points to be tested.
[0123] Please continue to refer to this. Figure 5 When measuring the yield of actual wafer-level system substrate interconnects, the test objects can be TSVs and metal interconnects in the substrate. The test covers metal alignment and connectivity at the illumination window boundary, as well as the connectivity of TSVs after thinning. Figure 5 The test circuit connection structure shown in the diagram, during the prebond stage, uses a DC test method on the C4 bump side to test the connection between two points of the same color (two bumps are a group). The test indicators are voltage and current. Then, the resistance value of the corresponding path is calculated based on the voltage and current. The resistance value is used to reflect the connectivity of the path, that is, to reflect the yield of the wafer-level system substrate interconnection, and the data of the entire wafer is recorded.
[0124] In one possible implementation, the server compares the path impedance of the interconnect to be tested with a preset impedance threshold range for each interconnect point to be tested, and determines the measured yield data of the interconnect point based on the comparison result. For example, the difference between the path impedance and the preset impedance threshold range can be quantified to obtain a continuous yield value between 0 and 1. The yield data can be determined as 1 (representing 100% normal operation). If the difference between the measured impedance and the preset impedance threshold range is greater than the difference threshold, it indicates that there is an open circuit or high impedance defect in the path, and the yield data of that point can be determined as 0 (representing that it cannot work normally).
[0125] In another possible implementation, the yield data for a specific test point can be determined using an efficiency-first iterative testing approach. First, the testing equipment can select a path passing through the test point and measure its impedance. If the impedance of this path is within a predefined acceptable range, the test point is considered acceptable, requiring no further testing, and the measured yield data can be quantified based on the specific impedance value. If the impedance of the first path is exceptionally high and it is deemed unacceptable, this does not necessarily indicate a problem with the test point itself. Therefore, the testing equipment can continue searching for other alternative paths passing through the same test point and measuring them. This process continues until a acceptable path is found, or if a pre-set number of alternative paths have been tested without finding an acceptable one, then the final measured yield data for that point is determined. This ensures a more rigorous determination of unacceptable points while improving the testing efficiency for acceptable points.
[0126] In this embodiment, by reasonably selecting interconnection points and using physical testing and data processing methods to obtain yield data, a highly accurate and representative original dataset can be provided for the yield prediction model, thereby ensuring the reliability of the entire prediction method.
[0127] To obtain an end-to-end, wafer-level substrate interconnect yield measurement, prediction, and feedback full-process design method, realizing a complete process from yield testing to fitting an accurate yield prediction model and finally feeding back to the design, this application embodiment also provides a silicon substrate optimization method. This method provides a simple and effective interconnect yield testing scheme and an accurate mathematical fitting model to support the end-to-end full-process design method, realizing a closed-loop design for the entire process from wafer yield testing, model prediction to feedback design, and meeting the need to adjust the wafer topology network architecture and introduce corresponding fault tolerance mechanisms based on the substrate yield prediction results.
[0128] In one embodiment, such as Figure 7 As shown, a silicon substrate optimization method is provided, which includes steps 702 to 706, wherein:
[0129] Step 702: Provide a wafer-level chip, the wafer-level chip including a wafer-level substrate.
[0130] For example, the server acquires or receives wafer-level chip design data to be optimized, including the complete layout of the wafer-level substrate and interconnect network information.
[0131] Step 704: The yield of the target interconnect point on the wafer-level substrate is predicted using the silicon substrate interconnect yield prediction method provided in the first aspect of the embodiments of this application.
[0132] Step 706: If the yield prediction result of the target interconnect does not meet the preset yield conditions, adjust the interconnect line where the target interconnect is located, and / or adjust the communication link related to the target interconnect in the wafer-level chip.
[0133] The server can process interconnect points whose yield does not meet the preset standard based on the prediction results of step 704. For example, it can make physical adjustments to the interconnect line where the interconnect point is located (such as changing the routing or width), or reconfigure or adjust the communication links in the entire chip that depend on the interconnect point, such as introducing redundancy or backup paths, to improve the overall yield and reliability.
[0134] The server in this application embodiment can guide the design of wafer-level chips through a target yield prediction model. By selecting interconnect coordinate points, the yield prediction result is obtained based on the target yield prediction model and the coordinate position of the interconnect coordinate points. Based on the yield prediction result, the architecture and interconnect design in the wafer-level chip can be modified, and a fault tolerance mechanism is introduced to ensure that the wafer-level chip functions can be correctly implemented.
[0135] For example, redundant designs can be implemented in areas with low interconnect yield, such as introducing more interconnect lines. Alternatively, the communication strategy between AI chips in the wafer-level chip can be changed to allow the original data flow to bypass these areas with low interconnect yield as much as possible, thereby ensuring that the data can be transmitted correctly and promoting the production of large-size wafer-level chip substrates.
[0136] In this embodiment, the above-described silicon substrate optimization method enables the establishment of a closed-loop method for the entire process of yield measurement of wafer-level system substrates, fitting of measurement results to obtain a prediction model, and use of the prediction model to provide feedback guidance for specific wafer-level system architecture and fault-tolerant design.
[0137] The following section will further illustrate this application through an end-to-end process design.
[0138] In one embodiment, a silicon substrate optimization method is provided, the method comprising:
[0139] Step A: Obtain the location data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate.
[0140] For example, to detect the metal alignment and connectivity of the substrate at the photomask window boundary and the connectivity of the TSV after thinning, 330 groups of two bumps were tested on the C4 bump side of the prebond stage using a DC test method. Since the circuit under test is a passive device, the FIMV method can be used to apply a small current, measure the voltage, and calculate the corresponding resistance to obtain the connectivity between two coordinate points on the large-size substrate.
[0141] Please refer to Figure 8 An example is shown showing nine test points under a single photomask window, named m1_ld, m1_rd, m1_ru, m2_ld, m2_rd, m2_ru, m3_ld, m3_rd, and m3_ru. The position data of the nine test points are represented by their horizontal and vertical coordinates on the wafer-level substrate, as shown in Table 1. Data for the entire wafer is recorded, and some data is shown in Table 2. In Table 2, X represents the horizontal identifier of the test window, and Y represents the vertical identifier of the test window. The combination of X and Y uniquely identifies a specific test window. m1_ru_rd can represent the path impedance between points m1_ru and m1_rd. For example, the preset yield threshold range can be... The impedance of the connection is Within this range, the yield is considered acceptable; otherwise, a yield problem exists. For example, in the X-8, Y-1 test window, the path impedance between points m1_ru and m1_rd within this window is 20006.3. This is considered unqualified; under the test window of X-4 and Y-2, the path impedance between points m1_ru and m1_rd in this window is 136.008. If it is, it can be considered qualified.
[0142] Table 1
[0143]
[0144] Table 2
[0145]
[0146] Step B: Based on the location data of multiple interconnect points to be measured and the measured yield data, determine the intermediate yield prediction model.
[0147] For example, based on the discrete raw data obtained in step A, a prediction model can be generated using the model fitting method. This can generate 1 million grids. At the same time, the parameters are adjusted to optimize the fitting effect. The fitting results show that the two-dimensional Gaussian model can well meet the specific requirements of the prediction model.
[0148] The two-dimensional Gaussian distribution function can be expressed as: .
[0149] In the formula, The predicted amplitude of yield. and These are the horizontal and vertical coordinates of the wafer-level chip. and These are the standard deviations in the horizontal and vertical directions, respectively. This indicates the degree of baseline offset.
[0150] Please refer to Figure 9 , Figure 9 In the diagram (a), discrete points obtained from actual data characterize the interconnect yield at various points on the wafer, ranging from [0, 1]. Figure 9 In (b), the continuous grid distribution after Gaussian fitting is represented, which is the direct mapping relationship between fitting yield and topological position. The measured data shows that the yield is lower in the lower right region of the wafer.
[0151] Photolithography step-and-paste is a commonly used semiconductor manufacturing technique that transfers large-scale circuit patterns by repeatedly exposing a small photomask pattern step-by-step onto the entire large wafer. In this embodiment, when processing large wafers such as 12 inches, the photolithography equipment needs to operate within its maximum range of motion. As the mechanical platform moves towards the edge of the wafer, especially the farthest lower right region, the equipment approaches its mechanical limits. At this extreme position, the equipment's accuracy and stability decrease, leading to increased equipment errors in exposure and alignment. Simultaneously, each step of alignment and exposure during the step-and-paste process generates minute errors. These errors do not cancel each other out but accumulate gradually with each exposure step. Since the equipment typically starts from a fixed point (e.g., the upper left corner) and gradually moves towards the lower right, all accumulated errors are concentrated in the last few exposure areas, i.e., the lower right of the wafer, resulting in a significant decrease in interconnect quality in this area and consequently, extremely low yield.
[0152] Step C: Validate the intermediate yield prediction model. If the intermediate yield prediction model meets the conditions, determine it as the target yield prediction model.
[0153] For example, based on the fitted model obtained in step B, verify whether it can predict interconnect yield from the random interconnect coordinates of wafer-level chips. Design a comparative experiment to test the yield of the prediction model for both measured coordinates and random coordinates. For measured coordinates, compare the predicted yield with the measured yield. A mean squared error (MSE) of 0.000 is considered an accurate prediction. For random coordinates, a predicted yield within the range [0, 1] and conforming to the distribution trend of the measured yield is considered acceptable. The test results for random coordinates are shown in Table 3 below. By inputting ten randomly generated test point coordinates, the interconnect yield of that area can be predicted, and all results are within the acceptable range.
[0154] Table 3
[0155]
[0156] Step D: Based on the target yield prediction model, predict the yield of the interconnect points to be predicted on the target wafer-level substrate, and obtain the yield prediction results of the interconnect points to be predicted.
[0157] For example, after verification, based on the wafer-level chip architecture, interconnect coordinate points of different specifications and granularities are set. These could include coarse-grained photomask splicing window coordinate points, or even fine-grained topological coordinate information for multiple interconnect lines within a window. Figure 10 As shown, Figure 10 In the middle (a), the predicted yield can be represented as a function of the wafer-level chip physical coordinates. Figure 10 In the diagram (b), the confidence level distribution can be represented. The yield distribution prediction results for a specific wafer-level interconnect topology are given using a fitted model, such as... Figure 11 As shown.
[0158] Step E: If the yield prediction result of the target interconnect does not meet the preset yield conditions, adjust the interconnect line where the target interconnect is located, and / or adjust the communication link related to the target interconnect in the wafer-level chip.
[0159] For example, based on the wafer-level chip substrate yield prediction results obtained in step D, please continue to refer to... Figure 11 The green area indicates a good yield, while the red area indicates a poor yield. Based on this fitting prediction result, upper-level designers can easily modify the current wafer-level system architecture and identify where fault-tolerant mechanisms need to be introduced. Specifically, for areas with low interconnect yield, redundant design can be introduced by designing more interconnects to ensure the correctness of data transmission. Alternatively, the communication strategy between AI chips can be changed to minimize the flow of data in these areas with low interconnect yield, thus providing a reference for the design of wafer-level systems.
[0160] In this embodiment, traditional chip yield testing can only be determined after wafer production is completed. However, due to the high cost and long cycle of wafer-level systems, yield assessment needs to be performed in the early stages of architecture design. This allows upper-level designers to make architectural changes and fault-tolerant designs based on yield prediction results, optimizing the layout in advance. To address these pain points, this application proposes a complete process: from obtaining yield data through experimental testing based on actual interconnect structure design, to generating a prediction model based on the yield data, and finally, using the prediction model to evaluate the yield of the current wafer-level system architecture design to guide upper-level designers in making architectural modifications and fault-tolerant designs. This forms a closed-loop, efficient design optimization system, enabling wafer-level systems to achieve rapid design iteration and performance optimization in the early stages of architecture design using the methods described in the design process, ensuring the production and implementation of wafer-level large-size interconnect substrate designs.
[0161] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0162] Based on the same inventive concept, this application also provides a silicon substrate interconnect yield prediction device for implementing the silicon substrate interconnect yield prediction method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more silicon substrate interconnect yield prediction device embodiments provided below can be found in the limitations of the silicon substrate interconnect yield prediction method described above, and will not be repeated here.
[0163] In one embodiment, such as Figure 12 As shown, a silicon substrate interconnect yield prediction device 1200 is provided, including: an acquisition module 1202, a determination module 1204, and a prediction module 1206, wherein:
[0164] The acquisition module 1202 is used to acquire the position data and yield measurement data of multiple interconnect points to be measured in the target wafer-level substrate; the interconnect points to be measured are used to characterize the interconnect points on the interconnect lines of the target wafer-level substrate that are to be subjected to yield measurement.
[0165] The determination module 1204 is used to determine a target yield prediction model based on the position data of multiple interconnect points to be measured and the yield measurement data; the target yield prediction model includes the mapping relationship between the position of interconnect points on the target wafer-level substrate and the yield.
[0166] The prediction module 1206 is used to predict the yield of the interconnect point to be predicted on the target wafer-level substrate based on the target yield prediction model, and obtain the yield prediction result of the interconnect point to be predicted.
[0167] Based on the same inventive concept, this application also provides a silicon substrate optimization apparatus for implementing the silicon substrate optimization method described above. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations in one or more embodiments of the silicon substrate optimization apparatus provided below can be found in the limitations of the silicon substrate optimization method described above, and will not be repeated here.
[0168] In one embodiment, such as Figure 13 As shown, a silicon substrate optimization apparatus is provided, including: a providing module 1302, a silicon substrate interconnect yield prediction device 1200, and an optimization module 1304, wherein:
[0169] A module 1302 is provided for providing a wafer-level chip; the wafer-level chip includes a wafer-level substrate.
[0170] A silicon substrate interconnect yield prediction device 1200 is used to predict the yield of target interconnect points on the wafer-level substrate.
[0171] The optimization module 1304 is used to adjust the interconnect line where the target interconnect point is located, and / or adjust the communication link in the wafer-level chip related to the target interconnect point when the yield prediction result of the target interconnect point does not meet the preset yield conditions.
[0172] Each module in the aforementioned silicon substrate interconnect yield prediction device or silicon substrate optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.
[0173] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 14As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a silicon substrate interconnect yield prediction method or a silicon substrate optimization method.
[0174] Those skilled in the art will understand that Figure 14 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0175] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.
[0176] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.
[0177] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0178] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.
[0179] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0180] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0181] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A method for predicting yield of silicon substrate interconnects, comprising: The method comprises: obtaining position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield; determining a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between the positions of the interconnection points on the target wafer-level substrate and the yields; predicting the yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model to obtain a yield prediction result of the to-be-predicted interconnection point.
2. The method of claim 1, wherein, The method comprises: obtaining position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield; determining a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between the positions of the interconnection points on the target wafer-level substrate and the yields; predicting the yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model to obtain a yield prediction result of the to-be-predicted interconnection point.
3. The method of claim 2, wherein, The method comprises: obtaining position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield; determining a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between the positions of the interconnection points on the target wafer-level substrate and the yields; predicting the yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model to obtain a yield prediction result of the to-be-predicted interconnection point. The method comprises:
4. The method of claim 2, wherein, obtaining position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield; 5. The method according to any one of claims 1 to 4, characterized in that, determining a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between the positions of the interconnection points on the target wafer-level substrate and the yields; predicting the yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model to obtain a yield prediction result of the to-be-predicted interconnection point. The method comprises: obtaining position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield; 6. A method of optimizing a silicon substrate, comprising: determining a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between the positions of the interconnection points on the target wafer-level substrate and the yields; predicting the yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model to obtain a yield prediction result of the to-be-predicted interconnection point. The method comprises: obtaining position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield; determining a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between the positions of the interconnection points on the target wafer-level substrate and the yields; predicting the yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model to obtain a yield prediction result of the to-be-predicted interconnection point. The method comprises: providing a wafer-level chip; the wafer-level chip comprises a wafer-level substrate; The method as claimed in any one of claims 1 to 5 is used to predict the yield of a target interconnection point on the wafer-level substrate. In a case where the yield prediction result of the target interconnection point does not satisfy a preset yield condition, an interconnection line where the target interconnection point is located is adjusted, and / or a communication link related to the target interconnection point in the wafer-level chip is adjusted.
7. A silicon substrate interconnect yield prediction apparatus, comprising: The device comprises: An acquisition module is configured to acquire position data and yield measurement data of a plurality of to-be-measured interconnection points in a target wafer-level substrate; the to-be-measured interconnection points are used to represent interconnection points on an interconnection line of the target wafer-level substrate to be measured for yield. A determination module is configured to determine a target yield prediction model based on the position data and the yield measurement data of the plurality of to-be-measured interconnection points; the target yield prediction model comprises a mapping relationship between positions and yields of interconnection points on the target wafer-level substrate. A prediction module is configured to predict a yield of a to-be-predicted interconnection point on the target wafer-level substrate based on the target yield prediction model, to obtain a yield prediction result of the to-be-predicted interconnection point.
8. A silicon substrate optimization apparatus, characterized by, The device comprises: A providing module is configured to provide a wafer-level chip; the wafer-level chip comprises a wafer-level substrate. The silicon substrate interconnection yield prediction device as claimed in claim 7 is used to predict a yield of a target interconnection point on the wafer-level substrate. An optimization module is configured to, in a case where a yield prediction result of the target interconnection point does not satisfy a preset yield condition, adjust an interconnection line where the target interconnection point is located, and / or adjust a communication link related to the target interconnection point in the wafer-level chip. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor executes the computer program to implement the steps of the method of any one of claims 1 to 6.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.