Variable gain amplification unit and dual-mode variable gain amplifier

Abstract

The invention discloses a variable gain amplification unit and a dual-mode variable gain amplifier, and relates to the technical field of radio frequency integrated circuits. The variable gain amplifier aims to solve the problem that an existing variable gain amplifier cannot meet existing control requirements. According to the variable gain amplification unit and the dual-mode variable gain amplifier, the reconstruction of the gain change range can be realized by adjusting the bias voltage and the number of the cascaded VGA arrays, and different design requirements are met; in the VGA mode, the gain of the amplifier is controlled by the analog voltage and is continuously adjustable in the gain change range. In the PGA mode, the gain of the amplifier is controlled by a digital signal, and the linearity of gain change is extremely high. The circuit is built based on the VGA units with simple structures, and has the advantages of being easy to implement and low in power consumption.

Description

Technical Field

[0001] This application belongs to the field of radio frequency integrated circuit technology, and in particular relates to variable gain amplifiers. Background Technology

[0002] Signal strength can vary significantly due to uncertainties such as distance and obstruction. Therefore, signal receiver systems typically employ Automatic Gain Control (AGC) loops to adjust the signal amplitude within a certain range, ensuring the proper functioning of the A / D converter and reducing the bit error rate. The Variable Gain Amplifier (VGA) or Programmable Gain Amplifier (PGA), as the most crucial component of the AGC loop, requires extensive optimization design.

[0003] As an important module in receivers, VGA has been the subject of extensive research by numerous scholars. However, based on current technology, it generally suffers from the following problems:

[0004] 1. For VGAs with cascaded open-loop amplifiers, the gain is controlled by analog voltage, and its gain change is continuous. However, there is a conflict between the gain change range and linearity. A higher gain change range often means worse linearity. When there are too many cascaded amplifiers, it will also cause problems with area, power consumption and stability.

[0005] 2. For VGAs used in closed loops, the gain is controlled by digital signals. The relationship between the gain variation range and linearity is not significant. Using a closed-loop amplifier with feedback resistors can often achieve good linearity while ensuring the gain variation range. However, the gain variation of such VGAs is often not linear. The gain can only be adjusted to a certain preset value. Furthermore, such VGAs have a large number of feedback resistors and switches, and their area and power consumption are often higher than those of VGAs used in open loops.

[0006] 3. For some gain requirements that need both analog voltage control and digital signal control, it is difficult to find a suitable structure on the market to meet the requirements, or its area and power consumption are seriously excessive. Therefore, designing a low-power, small-area integrated dual-mode variable gain amplifier is an urgent problem to be solved. Summary of the Invention

[0007] This application aims to address the problem that existing variable gain amplifiers cannot meet current control requirements, and provides a distributed variable gain amplifier unit and a dual-mode variable gain amplifier.

[0008] The first aspect of this application provides a variable gain amplification unit, including: PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6, and NMOS transistor M7;

[0009] The gate of the PMOS transistor M1 is used as the bias voltage connection terminal, the source is used as the power supply connection terminal, and the drain is connected to the source of the PMOS transistor M2 and the source of the PMOS transistor M3, respectively.

[0010] The gate of PMOS transistor M2 and the gate of PMOS transistor M3 serve as the positive input terminal and the negative input terminal, respectively.

[0011] The drain of the PMOS transistor M2, the source of the PMOS transistor M4, and the gate and drain of the NMOS transistor M6 are connected and serve as the negative output terminal.

[0012] The drain of the PMOS transistor M3, the source of the PMOS transistor M5, and the gate and drain of the NMOS transistor M7 are connected and serve as the positive output terminal.

[0013] The gate and drain of PMOS transistor M4, the gate and drain of PMOS transistor M5, the source of NMOS transistor M6, and the source of NMOS transistor M7 together serve as ground terminals.

[0014] The body terminals of both NMOS transistor M6 and NMOS transistor M7 serve as control voltage connection terminals.

[0015] In one possible design, all MOSFETs operate in the saturation region.

[0016] In one possible design, the gain of the variable gain amplifier unit The expression is:

[0017] ,

[0018] in, , , These are the transconductances of PMOS transistors M3, M5, and M7, respectively; similarly, , , These are the transconductances of PMOS transistors M2, M4, and M6, respectively.

[0019] A second aspect of this application provides a dual-mode variable gain amplifier, comprising: a plurality of the aforementioned variable gain amplification units and a mode switching circuit;

[0020] Multiple variable gain amplifier units are cascaded to form multiple VGA arrays with different gains, and the multiple VGA arrays with different gains are connected to each other through switches.

[0021] The mode switching circuit is used to switch between digital control mode and analog control mode for the dual-mode variable gain amplifier.

[0022] In one possible design, the mode switching circuit includes an OR logic gate and a MOS switch;

[0023] The OR logic gate and the MOS switch are used to switch between digital control mode and analog control mode.

[0024] In one possible design, under digital control mode, when the digital signal controlling the nth VGA array is 0, the output signal of the (n-1)th VGA array skips the nth VGA array; when the digital signal controlling the nth VGA array is 1, the output signal of the (n-1)th VGA array is input to the nth VGA array.

[0025] In analog control mode, all VGA arrays are connected to the circuit, and the gain of the dual-mode variable gain amplifier is controlled by analog control voltage.

[0026] In one possible design, the multiple VGA arrays with different gains are VGA arrays with gains of 0dB, 1dB, 2dB, 4dB, 8dB, 16dB, 32dB, and 64dB, respectively.

[0027] The VGA arrays with gains of 0dB, 1dB, 2dB, and 4dB are all independent variable gain amplification units;

[0028] The 8dB gain VGA array is constructed by two cascaded 4dB gain VGA arrays.

[0029] The 16dB gain VGA array is constructed by two cascaded 8dB gain VGA arrays.

[0030] The 32dB gain VGA array is constructed by two cascaded 16dB gain VGA arrays.

[0031] The 64dB gain VGA array is constructed by two cascaded 32dB gain VGA arrays.

[0032] In one possible design, all switches between the remaining VGA arrays, except for the 0dB gain VGA array, are 4-input-4-output MOS switches.

[0033] In one possible design, the 4-input-4-output MOS switch selects the signal path according to the control signal.

[0034] In one possible design, the control signal is and The input signal of the MOS switch is and The output signal is and ,have:

[0035] , hour, , Turn off;

[0036] , hour, , Turn off;

[0037] , hour, , Turn off;

[0038] , hour, , Turn off.

[0039] The beneficial effects of this application are:

[0040] This application can reconstruct the gain variation range by adjusting the bias voltage and the number of cascaded VGA arrays to meet different design requirements.

[0041] This application can switch gain control modes: in VGA mode, the amplifier gain is controlled by analog voltage and is continuously adjustable within the gain variation range; in PGA mode, the amplifier gain is controlled by digital signal, and the linearity of gain variation is extremely high.

[0042] This application is based on a simple VGA unit and has the advantages of being easy to implement and having low power consumption. Attached Figure Description

[0043] Figure 1 The circuit diagram of the variable gain amplifier unit described in Specific Implementation Method 1 is shown below.

[0044] Figure 2 The circuit diagram of the dual-mode variable gain amplifier described in Specific Implementation Method 1 is shown below.

[0045] Figure 3The schematic diagram of the 4-input-4-output MOS switch circuit described in Specific Implementation Method 1 is shown below.

[0046] Figure 4 This is a schematic diagram of the simulation results for the PGA mode of a variable gain amplifier.

[0047] Figure 5 This is a schematic diagram of the simulation results for a variable gain amplifier in VGA mode. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0049] Specific implementation method one: Refer to Figure 1 This embodiment specifically describes the variable gain amplification unit, which includes:

[0050] The PMOS transistor M1 is used as the tail current transistor, the PMOS transistors M2 and M3 are used as differential input pairs, the PMOS transistors M4 and M5 are used as loads connected by diodes, and the NMOS transistors M6 and M7 are used as the tail current transistors.

[0051] The first PMOS transistor M1 is a tail current transistor. Its gate terminal is connected to the bias voltage (Vbias), its source terminal is connected to the power supply, and its drain terminal is connected to the source terminals of the second PMOS transistor M2 and the third PMOS transistor M3, respectively.

[0052] The second PMOS transistor M2 and the third PMOS transistor M3 are both input PMOS transistors, with their gate terminals connected to the positive input terminal (vin+) and the negative input terminal (vin-), respectively.

[0053] The fourth PMOS transistor M4, the fifth PMOS transistor M5, the first NMOS transistor M6, and the second NMOS transistor M7 are all load transistors, forming a load structure;

[0054] The body terminals of the first NMOS transistor (M6) and the second NMOS transistor (M7) are simultaneously connected to the control voltage (Vctrl);

[0055] The gate and drain terminals of the first NMOS transistor M6, the drain terminal of the second PMOS transistor M2, and the source terminal of the fourth PMOS transistor M4 are all connected to the negative output terminal Vout-.

[0056] The gate and drain terminals of the second NMOS transistor M7, the drain terminal of the third PMOS transistor M3, and the source terminal of the fifth PMOS transistor M5 are all connected to the positive output terminal Vout+.

[0057] The gate and drain terminals of the fourth PMOS transistor M4, the source terminal of the first NMOS transistor M6, the source terminal of the second NMOS transistor M7, and the gate and drain terminals of the fifth PMOS transistor M5 are all connected to the power supply ground.

[0058] All MOSFETs are operating in the saturation region.

[0059] The gain expression for the variable gain amplifier unit is:

[0060] (1),

[0061] In equation (1), , , These are the transconductances of PMOS transistors M3, M5, and M7, respectively; similarly, , , The transconductances of PMOS transistors M2, M4, and M6 are respectively; ( The expression is:

[0062] (2),

[0063] In equation (2), The mobility of holes in PMOS or electrons in NMOS is expressed in cm⁻¹. 2 / V·s; The gate oxide capacitance per unit area, expressed in F / cm². 2 ; The aspect ratio of the device; Let be the leakage current of the MOSFET, and its expression is:

[0064] (3),

[0065] In equation (3), This is the gate-source voltage difference of the MOSFET. The threshold voltage of the MOSFET is expressed as follows:

[0066] (4),

[0067] In equation (4), Zero bias voltage, For built-in potential, The attenuation coefficient is ( , , (These are all process-related parameters). This represents the voltage difference between the source and body terminals of the MOSFET.

[0068] When the control voltage increases, the body voltage of NMOS transistors M6 and M7 increases, causing their... The threshold voltage decreases as shown in formula (4). Furthermore, according to formula (3), the current flowing through NMOS transistors M6 and M7 increases. Since the current in the circuit has the relationship shown in formula (5):

[0069] (5),

[0070] Therefore, the current flowing through PMOS transistors M4 and M5 decreases, as shown in equation (5). , , , , , These represent the currents flowing through PMOS transistors M2, M3, M4, M5, M6, and M7, respectively.

[0071] According to formula (2), the transconductance of PMOS transistors M4 and M5 can be determined. and Reduce the transconductance of NMOS transistors M6 and M7 and As the voltage increases, the aspect ratio of PMOS transistors M4 and M5 is much larger than that of NMOS transistors M6 and M7. and The reduction is much greater than and The amount of increase, i.e. and Reduce, due to and The value of is constant, so according to formula (1), the gain of the circuit increases and vice versa.

[0072] Specific Implementation Method Two: Refer to Figure 2 This embodiment describes a distributed dual-mode variable gain amplifier, which includes multiple variable gain amplification units with a small gain variation range but high precision, as described in Specific Embodiment 1.

[0073] According to the gain requirements, variable gain amplifier units are cascaded to form multiple VGA arrays with different gains. The gain of the VGA unit is adjusted by setting different bias voltages internally. VGA arrays with different gain ranges are connected by MOS switches. Switching between digital signal and analog voltage gain control modes is realized by OR logic gates and MOS switches.

[0074] Reference Figure 2 As shown, a variable gain amplifier that generates a gain range of 0-128dB requires VGA arrays of 0dB, 1dB, 2dB, 4dB, 8dB, 16dB, 32dB, and 64dB. Among them, the 0dB, 1dB, 2dB, and 4dB arrays are implemented by a single VGA unit, the 8dB array is implemented by cascading two 4dB VGA units, the 16dB array is implemented by cascading two 8dB VGA units, and so on.

[0075] Adjacent VGA arrays are connected via 4-input - 4-output MOS switches, with each switch connected end-to-end, such as... Figure 3 As shown; the MOS switch responds to the control signal ( , The signal path is selected to enable or bypass the array. The switch output states are as follows when the control signals are presented in different combinations:

[0076] , When, output , Turn off;

[0077] , When, output , Turn off;

[0078] , When, output , Turn off;

[0079] , When, output , Turn off.

[0080] This embodiment also includes a mode switching circuit, which uses OR logic gates and MOS switches to switch between digital control mode (PGA mode) and analog control mode (VGA mode).

[0081] In PGA mode (module=0), the gain is controlled by a digital control signal (ctl<0:6>). The control voltage terminal of the VGA unit is connected to the built-in control voltage via a MOS switch. The amplifier gain is adjusted by changing the gain control signal ctl<0:6>. The decimal number corresponding to the binary number ctl<0:6> is the amplifier gain. Its specific working principle is as follows:

[0082] When the digital signal ctl controls the nth level VGA array <n>When ctl is 0, the output signal of the previous stage will skip the current stage array through a 4-input - 4-output switch, and this array will not affect the overall gain; when ctl... <n>When the value is 1, the output of the previous stage will be connected to the input of this stage array through a 4-input - 4-output switch. At this time, the overall gain of the circuit will increase the gain corresponding to this stage array.

[0083] For example, when the control signal ctl of the 16dB array <4> When =0, the output of the 8dB array will be output from L4+ and L4- to the next stage switch via switches, instead of being input to the 16dB array. This is equivalent to skipping the 16dB VGA array; when ctl <4> When x = 1, the output of the 8dB array will be input to the 16dB array through a switch, and the output of the 16dB array will be sent to the next stage switch. At this time, the 16dB array is cascaded between Vin and Vout, so the total gain is (x+16)dB.

[0084] In VGA mode (module=1), the control voltage terminal of the VGA unit is connected to the external control voltage through a MOS switch, and all digital control signals are set to high level (all digital control signals are 1), that is, all VGA arrays are connected to the circuit. At this time, the amplifier gain is controlled by the external analog control voltage (Vctrl).

[0085] Figure 4 The simulation results of the variable gain amplifier in PGA mode of this embodiment are shown. The results show that the gain of the amplifier can change from 0dB to 127dB in the process of ctl<0:6> changing from 0000000 to 1111111, and the error of each gain value compared with the standard value does not exceed ±0.05dB, which is suitable for situations that require precise gain setting.

[0086] Figure 5 The simulation results of the variable gain amplifier in VGA mode of this embodiment are shown. The results show that when the control voltage changes from 0 to 0.6V, the amplifier gain changes continuously from 0dB to 157dB. Compared with the PGA mode, the linearity is poor but the gain change range is wider, which is suitable for situations where the gain needs to be continuously changed.

[0087] While specific embodiments of this application have been described herein with reference to them, it should be understood that these embodiments are merely examples of the principles and applications of this application. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of this application as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.< / n> < / n>

Claims

1. A variable gain amplification unit, characterized by, Comprise: PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6 and NMOS transistor M7; The gate of the PMOS transistor M1 is connected as a bias voltage connection end, the source is connected as a power supply connection end, and the drain is connected to the source of the PMOS transistor M2 and the source of the PMOS transistor M3 respectively; The gate of the PMOS transistor M2 and the gate of the PMOS transistor M3 are connected as a positive input end and a negative input end respectively; The drain of the PMOS transistor M2, the source of the PMOS transistor M4, and the gate and drain of the NMOS transistor M6 are connected and connected as a negative output end; The drain of the PMOS transistor M3, the source of the PMOS transistor M5, and the gate and drain of the NMOS transistor M7 are connected and connected as a positive output end; The gate and drain of the PMOS transistor M4, the gate and drain of the PMOS transistor M5, the source of the NMOS transistor M6, and the source of the NMOS transistor M7 are collectively connected as a ground connection end; The body terminal of the NMOS transistor M6 and the body terminal of the NMOS transistor M7 are both connected as a control voltage connection end.

2. The variable gain amplification unit of claim 1, wherein, All MOS transistors work in the saturation region.

3. A variable gain amplification unit according to claim 1 or 2, characterised in that, The gain of the variable gain amplification unit The expression is: ， wherein, , , are the transconductances of PMOS transistor M3, PMOS transistor M5, NMOS transistor M7, respectively; and, , , are the transconductances of PMOS transistor M2, PMOS transistor M4, NMOS transistor M6, respectively.

4. A dual mode variable gain amplifier characterized by, Comprise: A plurality of variable gain amplification units and mode switching circuits according to claim 1; A plurality of variable gain amplification units are connected in cascade to form a plurality of VGA arrays with different gains, and the plurality of VGA arrays with different gains are connected through switches; The mode switching circuit is used for switching the dual-mode variable gain amplifier between a digital control mode and an analog control mode.

5. The dual-mode variable gain amplifier of claim 4, wherein, The mode switching circuit comprises an OR logic gate and a MOS switch; The OR logic gate and the MOS switch are used for switching between the digital control mode and the analog control mode.

6. The dual-mode variable gain amplifier according to claim 4, wherein In the digital control mode, when the digital signal controlling the nth VGA array is 0, the output signal of the (n-1)th VGA array skips the nth VGA array, and when the digital signal controlling the nth VGA array is 1, the output signal of the (n-1)th VGA array is input to the nth VGA array; In the analog control mode, all VGA arrays are connected to the circuit, and the gain of the dual-mode variable gain amplifier is controlled by an analog control voltage.

7. The dual-mode variable gain amplifier of claim 4, wherein, The plurality of VGA arrays with different gains are 0db, 1db, 2db, 4db, 8db, 16db, 32db, and 64db gain VGA arrays respectively; The 0db, 1db, 2db, and 4db gain VGA arrays are all independent variable gain amplification units; The 8db gain VGA array is composed of two cascaded 4db gain VGA arrays; The 16db gain VGA array is composed of two cascaded 8db gain VGA arrays; The 32db gain VGA array is composed of two cascaded 16db gain VGA arrays; The 64db gain VGA array is composed of two cascaded 32db gain VGA arrays.

8. The dual-mode variable gain amplifier of claim 7, wherein, The switches between all the VGA arrays except the 0 db gain VGA array are 4-input-4-output MOS switches.

9. The dual-mode variable gain amplifier of claim 8, wherein, The 4-input-4-output MOS switches select signal paths according to control signals.

10. The dual-mode variable gain amplifier of claim 9, wherein, The control signal is and The input signal of the MOS switch is and The output signal is and There are: , , , off , when, , off; , time, , off; , , , off.

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