Chip packaging method and packaging structure

Abstract

The embodiment of the invention provides a chip packaging method and a packaging structure, and the method comprises the steps: forming a bridge chip, and enabling an active surface of the bridge chip to be provided with a grindable chip bonding film; providing a carrier plate and forming a molding compound conductive column on the carrier plate; bonding and fixing the bridging chip on the carrier plate through the grindable chip bonding film; forming a first plastic packaging layer on the carrier plate, and grinding and thinning the first surface of the first plastic packaging layer to expose the plastic packaging material conductive columns and the non-active surfaces of the bridging chips; removing the carrier plate and grinding the grindable chip bonding film and the second surface of the first plastic packaging layer to expose the plastic packaging material conductive columns and the active surface of the bridging chip; respectively forming a first rewiring layer and a second rewiring layer which are electrically connected with the bridging chip and the plastic package material conductive columns on the second surface and the first surface of the first plastic package layer; and mounting and fixing the plurality of chips on the second rewiring layer, and forming a second plastic package layer wrapping the plurality of cores. According to the chip packaging method, the cost is saved, the yield is improved, and the reliability is improved.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging method and packaging structure. Background Technology

[0002] With the rise of AI technology, the demand for high-performance computing chips in data centers is growing rapidly. Compared to traditional consumer-grade chips, computing chips have a larger area, greater storage capacity, and higher requirements for interconnect speed. To achieve faster computing speeds, larger data storage capacity, and more functions, semiconductor chips are evolving towards higher integration levels. The higher the integration level of a semiconductor chip, the smaller its feature size. As chip manufacturing processes reach the 2nm limit, improving performance by shrinking wafer feature sizes would result in a significant cost increase. Against this backdrop, achieving performance improvements through advanced packaging and high-density interconnects has become the most cost-effective option.

[0003] COWOS-L advanced packaging technology was developed in this context. By embedding bridge chip stacking technology, it can achieve high-density interconnection between GPU / CPU and HBM. At the same time, it can achieve vertical interlayer interconnection by using technologies such as through-silicon vias, solving the power supply problem of HBM3, making the package more compact and the chip lead distance shorter, thereby greatly improving the frequency and power characteristics of the circuit.

[0004] The existing COWOS-L advanced packaging has the following problems: 1) Embedding bridge chips using thermocompression bonding requires expensive equipment investment, leading to increased costs. 2) Current processes require chemical mechanical polishing (CMP) to expose copper in TSVs, but CMP equipment is expensive to purchase and maintain, and process control is complex. 3) After exposing copper in ultra-high density TSVs, Cu ions may diffuse, causing leakage anomalies and affecting chip reliability. 4) During fabrication, controlling the amount of polishing material is difficult, easily leading to process deviations and yield losses. 5) Due to the small spacing between copper pads and copper bumps, the molding compound cannot fully fill the gaps during molding, creating voids and affecting packaging quality.

[0005] To address the aforementioned issues, it is necessary to propose a chip packaging method and structure that is rationally designed and effectively solves these problems. Summary of the Invention

[0006] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a chip packaging method and packaging structure.

[0007] One aspect of this disclosure provides a chip packaging method, the method comprising: A bridging chip is formed, wherein the active surface of the bridging chip is provided with a grindable chip adhesive film; A carrier plate is provided on which molding compound conductive pillars are formed; The bridging chip is bonded and fixed to the carrier board using the grindable chip adhesive film; A first molding layer is formed on the carrier substrate, and a first surface of the first molding layer is thinned to expose the molding material conductive pillars and the non-active surface of the bridging chip; Remove the carrier board and grind the second surface of the grindable chip adhesive film and the first molding layer to expose the conductive pillars of the molding compound and the active surface of the bridging chip; A first rewiring layer and a second rewiring layer are formed on the second surface and the first surface of the first molding layer, respectively, which are electrically connected to the bridging chip and the conductive pillars of the molding compound. Multiple chips are mounted and fixed on the second wiring layer, and a second molding layer is formed on the second wiring layer to encapsulate the multiple chips.

[0008] Optionally, the process of forming the bridge chip includes: A wafer is provided, the wafer being provided with through-silicon vias; A plurality of conductive bumps electrically connected to the through-silicon vias are formed on the first surface of the wafer; The second surface of the wafer is thinned by grinding to expose the through-silicon vias, and a protective layer is formed on the thinned second surface of the wafer, with the through-silicon vias exposed in the protective layer; An interconnect wiring layer electrically connected to the through-silicon via is formed on the protective layer; The grindable chip adhesive film is attached to the interconnect wiring layer; The wafer is diced to form multiple individual bridge chips.

[0009] Optionally, the thickness of the grindable chip adhesive film is 25 μm to 30 μm.

[0010] Optionally, the step of forming an interconnect wiring layer electrically connected to the through-silicon via on the protective layer includes: An interconnect dielectric layer is formed on the protective layer; The interconnect dielectric layer is graphically represented, and multiple openings are formed on the interconnect dielectric layer; An interconnecting metal layer is formed within the opening, wherein the thickness of the interconnecting metal layer is greater than the thickness of the conductive bump.

[0011] Optionally, thinning the first surface of the first molding layer to expose the conductive pillars of the molding compound and the non-active surface of the bridging chip includes: The first surface of the first molding layer is ground and thinned so that the exposed conductive pillars of the molding material are flush with the conductive bumps.

[0012] Optionally, grinding the second surface of the grindable chip adhesive film and the first molding layer to expose the conductive pillars of the molding compound and the active surface of the bridging chip includes: The grindable chip adhesive film is removed by grinding to expose the interconnect metal layer; Simultaneously, the second surface of the first molding layer is ground to expose the molding material conductive pillars; wherein the exposed molding material conductive pillars are flush with the interconnect metal layer.

[0013] Optionally, forming the molding compound conductive pillars on the carrier plate includes: A PI layer is pre-formed on the carrier plate; Multiple conductive pillars of the molding compound are formed on the PI layer using a dry film lamination process.

[0014] Optionally, the step of mounting and fixing multiple chips onto the second wiring layer includes: Multiple chips are flip-chip bonded to the second wiring layer for chip-to-wafer bonding. An underfill layer is formed between multiple chips and the second redistribution layer.

[0015] Optionally, after forming a second molding compound encapsulating the plurality of chips on the second redistribution layer, the method further includes: The side of the second molding layer opposite to the second redistribution layer is thinned by grinding to achieve the preset encapsulation thickness.

[0016] Another aspect of this disclosure provides a chip packaging structure, which is formed by packaging using the chip packaging method described above.

[0017] The chip packaging method and packaging structure disclosed herein include a millable chip adhesive film on the active surface of the bridging chip. This film is used to adhere and fix the bridging chip to the carrier board, replacing the traditional TCB process. Directly bonding the bridging chip simplifies the process, avoids expensive TCB equipment investment, and saves costs. The packaging process uses a grinding process instead of chemical mechanical polishing to expose copper, significantly reducing equipment costs and process complexity. A first and second wiring layers, electrically connected to the bridging chip and the molding compound conductive pillars, are formed on both sides of the first molding layer, achieving higher-density interconnection. This packaging method solves yield problems caused by insufficient grinding allowance and molding compound filling in traditional processes by precisely controlling the grinding amount and step sequence. By stacking and reassembling multiple chips to achieve interconnection, this packaging method can be widely applied in the field of high-computing-power chip technology, reducing costs and improving efficiency. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart of a chip packaging method according to one embodiment of the present disclosure; Figures 2 to 13 This is a schematic diagram of a chip packaging method according to another embodiment of the present disclosure. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] like Figure 1 As shown, one aspect of this disclosure provides a chip packaging method S100, which includes: S110. A bridging chip is formed, wherein the active surface of the bridging chip is provided with a grindable chip adhesive film.

[0021] Specifically, such as Figure 2 As shown, a wafer 110 is provided, wherein the wafer 110 is provided with a through silicon via 111.

[0022] like Figure 2 As shown, a plurality of conductive bumps 112 electrically connected to the through-silicon via 111 are formed on the first surface of the wafer 110. The conductive bumps 112 may be copper bumps.

[0023] like Figure 3As shown, multiple conductive bumps 112 on the first surface of wafer 110 are fixed to a temporary carrier 114 using temporary bonding adhesive 113. Then, the second surface of wafer 110 is ground and thinned to expose the through-silicon vias 111. A protective layer 115 is formed on the thinned second surface of wafer 110 using a CVD process, wherein the through-silicon vias 111 are exposed in the protective layer 115.

[0024] like Figure 4 As shown, an interconnect wiring layer of a predetermined thickness is formed on the protective layer 115, electrically connected to the through-silicon via 111. Specifically, an interconnect dielectric layer 116 is formed on the protective layer 115; the interconnect dielectric layer 116 is patterned using an exposure and development process, forming multiple openings on the interconnect dielectric layer 116; an interconnect metal layer 117 can be formed within the openings using an electroplating process, wherein the thickness of the interconnect metal layer 117 is greater than the thickness of the conductive bump 112. It should be noted that the number of interconnect dielectric layers 116 and interconnect metal layers 117 is not specifically limited and can be selected according to actual needs. The thickness of the formed interconnect wiring layer should be sufficiently thick to provide sufficient polishing allowance for subsequent polishing processes.

[0025] like Figure 5 As shown, the grindable chip adhesive film 120 is bonded onto the interconnect wiring layer. Specifically, in this embodiment, the thickness of the grindable chip adhesive film 120 is 25 μm to 30 μm to facilitate subsequent grinding.

[0026] Finally, the temporary carrier 114 is removed, and the interconnect wiring layer is fixed onto the dicing tape. The wafer 110 is then diced to form the structure shown below. Figure 5 The diagram shows multiple individual bridging chips A. In each bridging chip A, the surface with multiple conductive bumps 112 is its non-active surface, and the surface with the interconnect wiring layer is its active surface. In other words, the active surface of the bridging chip A is provided with a grindable chip adhesive film 120.

[0027] In this embodiment, during the formation of the bridging chip, a protective layer 115 is formed on the second surface of the thinned wafer 110, providing effective protection after the copper is exposed in the through-silicon vias (TSVs). This solves the leakage current abnormality that may be caused by Cu ion diffusion after the copper is exposed in the ultra-high density TSVs. An interconnect wiring layer of a preset thickness is formed on the protective layer 115, which is electrically connected to the TSVs 111. By setting an interconnect wiring layer with a preset thickness, the overall thickness of the bridging chip is increased, providing sufficient grinding amount for the subsequent grinding process and reducing the process problem of grinding amount margin control during the preparation process.

[0028] S120. Provide a carrier plate, on which molding compound conductive pillars are formed.

[0029] like Figure 6 As shown, a carrier plate 130 is provided, wherein the carrier plate 130 may be a glass carrier plate. A PI layer 140 is pre-formed on the carrier plate 130 by a coating process. Then, a plurality of molding compound conductive pillars 150 are formed on the PI layer 140 by a dry film lamination process. The molding compound conductive pillars 150 may be copper pillars.

[0030] S130. The bridging chip is attached and fixed to the carrier board using the grindable chip adhesive film.

[0031] like Figure 7 As shown, the bridging chip A is adhered and fixed to the carrier board 130 using a grindable chip adhesive film 120. Specifically, the grindable chip adhesive film 120 of the bridging chip A is adhered and fixed to the PI layer 140 on the carrier board 130. By providing the PI layer 140 on the carrier board 130, the bonding force between the bridging chip A and the carrier board 130 can be increased. In addition, by pre-forming the PI layer 140 on the carrier board 130, the leakage current abnormality that may be caused by Cu ion diffusion after copper exposure in ultra-high density TSVs can also be solved.

[0032] In this embodiment, the bridging chip is bonded to the carrier board using a grindable chip adhesive film, replacing the traditional TCB process. This directly bonds the bridging chip, simplifying the process, avoiding expensive TCB equipment investment, and saving costs.

[0033] S140. A first molding layer is formed on the carrier board, and the first surface of the first molding layer is ground and thinned to expose the conductive pillars of the molding compound and the non-active surface of the bridging chip.

[0034] like Figure 7 As shown, a first molding layer 160 is formed on the carrier board 130 using resin. The first molding layer 160 encapsulates the bridging chip A and the molding compound conductive pillar 150, thus protecting the bridging chip A and the molding compound conductive pillar 150.

[0035] like Figure 8 As shown, the first surface of the first molding compound 160 is thinned by grinding so that the exposed molding compound conductive pillars 150 are flush with the conductive bumps 112 of the bridging chip A, thereby facilitating wiring on the first surface of the thinned first molding compound 160 and improving the reliability of the chip packaging structure. S150. Remove the carrier board and grind the second surface of the grindable chip adhesive film and the first molding layer to expose the conductive pillars of the molding compound and the active surface of the bridging chip.

[0036] like Figure 9As shown, the carrier plate 130 is removed, and the thinned first molding layer 160 is fixed to the temporary carrier plate 114 with temporary bonding adhesive 113.

[0037] The polishable chip adhesive film 120 is removed by a polishing process to expose the interconnect metal layer. Specifically, the interconnect metal layer 117 of the active surface of the bridging chip A is exposed by the polishing process. The thickness of the interconnect metal layer 117 after polishing can be set according to the packaging requirements, and this embodiment does not impose a specific limitation.

[0038] Simultaneously, the second surface of the first molding compound 160 is ground to expose the molding compound conductive pillars 150; wherein, the exposed molding compound conductive pillars 150 are flush with the interconnect metal layer. That is, the exposed molding compound conductive pillars 150 on the second surface of the thinned first molding compound 160 are flush with the exposed interconnect metal layer 117, which facilitates subsequent wiring on the second surface of the first molding compound 160 and improves the reliability of the chip packaging structure.

[0039] S160. A first rewiring layer and a second rewiring layer are formed on the second surface and the first surface of the first molding compound, respectively, to be electrically connected to the bridging chip and the conductive pillars of the molding compound.

[0040] like Figure 10 As shown, a first rewiring layer 171 is formed on the second surface of the thinned first molding compound 160, which is electrically connected to the interconnect metal layer 117 of the bridging chip and the molding compound conductive pillars 150, respectively. The number of first rewiring layers 171 is not limited and can be 2P2M type, etc. After forming the first rewiring layer 171, a plurality of first solder balls 172 electrically connected to it are formed on the first rewiring layer 171. The signals of the bridging chip A are led out through the plurality of first solder balls 172.

[0041] like Figure 11 As shown, multiple first solder balls 172 are fixed to a temporary carrier board 114 using temporary bonding adhesive 113. A second rewiring layer 173 is formed on the first surface of the first molding compound 160, which is electrically connected to the conductive bumps 112 of the bridging chip A and the conductive pillars 150 of the molding compound. The number of second rewiring layers 173 is not limited and can be 3P3M type, etc. After forming the second rewiring layer 173, multiple second solder balls 174 electrically connected to it are formed on the second rewiring layer 173. The signals of the bridging chip A are led out through the multiple second solder balls 174.

[0042] In this embodiment, a first rewiring layer and a second rewiring layer are formed on both sides of the first molding layer, respectively, to electrically connect the bridging chip and the conductive pillars of the molding compound, thereby achieving higher density interconnection.

[0043] S170. A plurality of chips are mounted and fixed on the second wiring layer, and a second molding compound is formed on the second wiring layer to encapsulate the plurality of chips.

[0044] like Figure 12 As shown, multiple chips 180 are mounted and fixed to the second multiple wiring layer 173. These chips 180 can be of the same type or different types. In this embodiment, multiple HBM chips and SOC chips are flip-chip fixed to the second multiple wiring layer 173 for chip-to-wafer bonding. Underfill is applied between the multiple chips 180 and the second multiple wiring layer 173 to form an underfill layer 181. The underfill fills the fine gaps between the chips and the substrate, effectively solving the problem of incomplete underfill caused by excessively small bump spacing and improving packaging reliability.

[0045] like Figure 12 As shown, a second molding compound 190 is formed on the second redistribution layer 173 to encapsulate multiple chips 180, and the second molding compound 190 protects the multiple chips 180.

[0046] like Figure 13 As shown, the temporary carrier 114 is removed by laser debonding. According to the packaging requirements, the second molding layer 190 is ground and thinned to achieve the preset packaging thickness, thereby forming a chip packaging structure that meets the requirements.

[0047] The chip packaging method of this disclosure provides a bridging chip with a grindable chip adhesive film on its active surface. The bridging chip is adhered and fixed to the carrier board through the grindable chip adhesive film, replacing the traditional TCB process. Directly bonding the bridging chip simplifies the steps, avoids expensive TCB equipment investment, and saves costs. The packaging process uses a grinding process instead of chemical mechanical polishing to expose copper, which significantly reduces equipment costs and process complexity. A first wiring layer and a second wiring layer are formed on both sides of the first molding compound, respectively, to electrically connect the bridging chip and the conductive pillars of the molding compound, achieving higher density interconnection. This packaging method solves the yield problems caused by insufficient grinding allowance control and insufficient molding compound filling in traditional processes by precisely controlling the grinding amount and step sequence. This packaging method achieves top-to-bottom interconnection by stacking and reassembling multiple chips, and can be widely used in the field of high-computing-power chip technology, reducing costs and improving efficiency.

[0048] Another aspect of this disclosure provides a chip packaging structure, formed using the chip packaging method S100 described above. The specific packaging process of this chip packaging method S100 has been described in detail above and will not be repeated here.

[0049] The chip packaging structure of this disclosure saves costs, improves yield, and enhances reliability.

[0050] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip packaging method, characterized by, The method comprises: forming a bridge chip, wherein an active surface of the bridge chip is provided with a grindable die bonding film; providing a carrier plate, and forming a plastic encapsulating conductive pillar on the carrier plate; adhering and fixing the bridge chip to the carrier plate through the grindable die bonding film; forming a first plastic encapsulating layer on the carrier plate, and grinding and thinning a first surface of the first plastic encapsulating layer to expose the plastic encapsulating conductive pillar and a non-active surface of the bridge chip; removing the carrier plate, and grinding the grindable die bonding film and a second surface of the first plastic encapsulating layer to expose the plastic encapsulating conductive pillar and an active surface of the bridge chip; forming a first redistribution layer and a second redistribution layer on the second surface and the first surface of the first plastic encapsulating layer respectively, and electrically connecting the bridge chip and the plastic encapsulating conductive pillar respectively; adhering and fixing a plurality of chips to the second redistribution layer, and forming a second plastic encapsulating layer wrapping the plurality of chips on the second redistribution layer.

2. The method of claim 1, wherein, The forming of the bridge chip comprises: providing a wafer provided with a through silicon via; forming a plurality of conductive bumps electrically connected to the through silicon via on a first surface of the wafer; grinding and thinning a second surface of the wafer to expose the through silicon via, and forming a protection layer on the thinned second surface of the wafer, wherein the through silicon via is exposed to the protection layer; forming an interconnection wiring layer electrically connected to the through silicon via on the protection layer; adhering the grindable die bonding film to the interconnection wiring layer; cutting the wafer to form a plurality of separate bridge chips.

3. The method of claim 2, wherein, The thickness of the grindable die bonding film is 25 μm-30 μm.

4. The method of claim 2, wherein, The forming of the interconnection wiring layer electrically connected to the through silicon via on the protection layer comprises: forming an interconnection dielectric layer on the protection layer; patterning the interconnection dielectric layer to form a plurality of openings on the interconnection dielectric layer; forming an interconnection metal layer in the openings, wherein the thickness of the interconnection metal layer is greater than the thickness of the conductive bumps.

5. The method of claim 2, wherein, The grinding and thinning of the first surface of the first plastic encapsulating layer to expose the plastic encapsulating conductive pillar and the non-active surface of the bridge chip comprises: grinding and thinning the first surface of the first plastic encapsulating layer so that the exposed plastic encapsulating conductive pillar is flush with the conductive bumps.

6. The method of claim 4, wherein, The grinding of the grindable die bonding film and the second surface of the first plastic encapsulating layer to expose the plastic encapsulating conductive pillar and the active surface of the bridge chip comprises: grinding to remove the grindable die bonding film to expose the interconnection metal layer; grinding the second surface of the first plastic encapsulating layer to expose the plastic encapsulating conductive pillar at the same time, wherein the exposed plastic encapsulating conductive pillar is flush with the interconnection metal layer.

7. The method according to any one of claims 1 to 6, characterized in that, The forming of the plastic encapsulating conductive pillar on the carrier plate comprises: pre-forming a PI layer on the carrier plate; forming a plurality of the plastic encapsulating conductive pillars on the PI layer by using a dry film lamination process.

8. The method according to any one of claims 1 to 6, characterized in that, The adhering and fixing of the plurality of chips to the second redistribution layer comprises: adhering and fixing a plurality of chips to the second redistribution layer in a flip-chip form, and performing chip-to-wafer bonding; A bottom filling glue is filled between the plurality of chips and the second redistribution layer to form a bottom filling glue layer.

9. The method according to any one of claims 1 to 6, characterized in that, After forming the second plastic sealing layer wrapping the plurality of chips on the second redistribution layer, the method further comprises: Grinding and thinning the side of the second plastic sealing layer away from the second redistribution layer to a preset packaging thickness.

10. A chip package structure, comprising: The chip packaging method is adopted to form a package.

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