Binary linear code decoding method and device and storage medium
By receiving soft channel information for hard decision-making and reliability ranking, generating test error modes, and using logical weights and perturbation noise for decoding, the problem of high complexity in binary linear code decoding is solved, achieving flexible and efficient decoding and reducing latency.
Patent Information
- Application Number
- CN202410958623.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-17
- Publication Date
- 2026-01-20
AI Technical Summary
Existing general approximate ML decoding algorithms for binary linear codes are highly complex and unsuitable for hardware parallel implementation.
By receiving soft information from the channel, performing hard decision-making and reliability ranking, generating test error modes, and using logical weights and perturbation noise for decoding, the decoding complexity is reduced and the success rate is improved.
It reduces decoding complexity, enables flexible and efficient decoding, reduces latency, and improves decoding success rate.
Smart Images
Figure CN121367501A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductors, and particularly to a decoding method, device and storage medium of a binary linear code. BACKGROUND
[0002] Error correction code is an integral part of modern digital communication systems and storage system design. It adds redundant information to the information sequence to detect and correct errors in the transmission process, thereby improving the reliability of data transmission. For a given linear code, the maximum likelihood (ML) decoder has the optimal performance, but its complexity is usually high and not easy to implement. How to design a general decoding method for binary linear codes, i.e. a decoding method that does not depend on the encoding scheme of the linear code, to achieve or approach the performance of the ML decoding algorithm is a challenging problem.
[0003] At present, the common general approximate ML decoding algorithm for binary linear codes mainly includes the ordered statistic decoding (OSD) algorithm and its variants. However, the OSD algorithm depends on the reliability ordering of the received sequence, performs column permutation on the generator matrix of the code through reliability ordering, and then needs to perform Gaussian elimination to make the matrix into a systematic form. For a linear code with a code length of n, the complexity of Gaussian elimination is O(n 3 ), which is relatively high. In addition, the Gaussian elimination operation is not suitable for hardware parallel implementation.
[0004] Therefore, the current general approximate ML decoding algorithm for binary linear codes has the problem of high complexity. SUMMARY
[0005] Therefore, the present application provides a decoding method, device and storage medium for binary linear codes, which can reduce the decoding complexity of binary linear codes, is flexible and efficient, and reduces the decoding delay.
[0006] To achieve the above-mentioned purpose, the present application has the following technical solutions:
[0007] The present application provides a decoding method for binary linear codes, comprising:
[0008] receiving channel soft information and obtaining a check matrix, performing hard decision on the channel soft information to obtain a received sequence and a syndrome;
[0009] determining whether the value of the syndrome is a zero vector, and if the value of the syndrome is not a zero vector, it indicates that the received sequence has found an error;
[0010] Sort reliabilities of each received bit in the channel soft information to obtain a reliability sorting result, and reorder columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix;
[0011] Generate at least one test error pattern according to the logical weight, extract column elements of the reordered check matrix according to the test error pattern, and perform XOR operation on the extracted column elements of the reordered check matrix and the check subcode to obtain a test error pattern check subcode, wherein the logical weight is a sum of positions of non-zero elements in the test error vector;
[0012] Determine whether the value of the test error pattern check subcode is a zero vector, and if the value of the test error pattern check subcode is a zero vector, it indicates that decoding is successful, and decode the received sequence according to the test error vector to obtain a correct sequence;
[0013] If the value of the test error pattern check subcode is not a zero vector, perturb the channel soft information using perturbation noise, and repeatedly perform hard decision on the channel soft information to obtain a received sequence and a check subcode and subsequent steps.
[0014] Optionally, the generating at least one test error pattern according to the logical weight, extracting column elements of the reordered check matrix according to the test error pattern, and performing XOR operation on the extracted column elements of the reordered check matrix and the check subcode to obtain a test error pattern check subcode comprises:
[0015] Generate a plurality of test error patterns according to the logical weight, each test error pattern corresponding to a test error vector, and the test error pattern indicating positions of non-zero elements in the test error vector;
[0016] Determine column elements of the reordered check matrix corresponding to the non-zero elements of the test error vector according to the non-zero elements of the test error vector, and perform XOR operation on the column elements to obtain a first operation result;
[0017] Continue to perform XOR operation on the first operation result and the check subcode to obtain a test error pattern check subcode.
[0018] Optionally, the reordering columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix comprises:
[0019] Obtain a position change result of each received bit according to the reliability sorting result, and obtain a conversion vector according to the position change result;
[0020] Reorder columns of the check matrix according to the conversion vector to obtain a reordered check matrix.
[0021] Optionally, the decoding the received sequence according to the test error vector to obtain a correct sequence comprises:
[0022] performing inverse conversion on the test error vector according to the conversion vector to obtain an error estimation vector;
[0023] decoding the received sequence according to the error estimation vector to obtain a correct sequence.
[0024] Optionally, before the channel soft information is disturbed by the disturbance noise, the method further comprises:
[0025] if the value of the test error pattern syndrome is not a zero vector, determining whether the logic weight is greater than a weight threshold, and if the logic weight is less than or equal to the weight threshold, increasing the logic weight by a fixed step, and repeating the step of generating at least one test error vector according to the logic weight.
[0026] Optionally, the method further comprises:
[0027] if the logic weight is greater than the weight threshold, indicating decoding failure;
[0028] determining whether the number of times of re-decoding after decoding failure is greater than a maximum number of times of re-decoding, and if the number of times of re-decoding after decoding failure is less than or equal to the maximum number of times of re-decoding, disturbing the channel soft information by the disturbance noise, and repeating the steps of performing hard decision on the channel soft information to obtain a received sequence and a syndrome and the subsequent steps.
[0029] Optionally, the method further comprises:
[0030] determining whether the value of the syndrome is a zero vector, and if the value of the syndrome is a zero vector, indicating that no error is found in the received sequence, and exiting decoding.
[0031] Optionally, the check matrix is determined according to a corresponding relationship between a binary linear code and a check matrix, and the syndrome is calculated according to the received sequence and a transpose matrix of the check matrix.
[0032] The application provides a decoding device of a binary linear code, comprising:
[0033] a receiving unit configured to receive channel soft information and obtain a check matrix, perform hard decision on the channel soft information to obtain a received sequence and a syndrome;
[0034] a determining unit configured to determine whether the value of the syndrome is a zero vector, and if the value of the syndrome is not a zero vector, indicating that an error is found in the received sequence;
[0035] a sorting unit configured to sort the reliability of each received bit in the channel soft information to obtain a reliability sorting result, and reorder columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix;
[0036] an operation unit configured to generate at least one test error pattern according to a logical weight, extract column elements of the reordered check matrix according to the test error pattern, and perform an XOR operation on the extracted column elements of the reordered check matrix and the syndrome to obtain a test error pattern syndrome, wherein the logical weight is a sum of positions of non-zero elements in the test error vector;
[0037] a decoding unit configured to determine whether a value of the test error pattern syndrome is a zero vector, and if the value of the test error pattern syndrome is the zero vector, it indicates that decoding is successful, and decode the received sequence according to the test error vector to obtain a correct sequence;
[0038] a perturbation unit configured to, if the value of the test error pattern syndrome is not the zero vector, perturb the channel soft information with a perturbation noise, and repeatedly perform the subsequent steps of hard decision on the channel soft information to obtain a received sequence and a syndrome.
[0039] The application provides a computer readable storage medium, characterized by comprising instructions, when the instructions are executed on a computer, the computer executes the method according to any one of the preceding method.
[0040] The application provides a decoding method of a binary linear code, comprising the following steps: receiving channel soft information and obtaining a check matrix, performing hard decision on the channel soft information to obtain a received sequence and a syndrome, determining whether the value of the syndrome is a zero vector, if the value of the syndrome is not the zero vector, it is indicated that the received sequence has an error, sorting the reliability of each received bit in the channel soft information to obtain a reliability sorting result, and reordering the columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix. At least one test error pattern is generated according to a logical weight, column elements of the reordered check matrix are extracted according to the test error pattern, and the column elements of the reordered check matrix and the syndrome are subjected to an exclusive or operation to obtain a test error pattern syndrome, and the logical weight is the sum of the positions of non-zero elements in a test error vector. It is determined whether the value of the test error pattern syndrome is a zero vector, if the value of the test error pattern syndrome is a zero vector, it is indicated that the decoding is successful, and the received sequence is decoded according to the test error vector to obtain a correct sequence. If the value of the test error pattern syndrome is not a zero vector, the channel soft information is disturbed by using a disturbance noise, and the subsequent steps of performing hard decision on the channel soft information to obtain a received sequence and a syndrome are repeatedly performed. That is, the application generates a test error vector according to a logical weight, and decodes the binary linear code by using a plurality of test error vectors. Since the check matrix obtained according to the reliability sorting and the test error vector generated according to the logical weight are independent of the structure of the binary linear code, the decoding complexity is reduced, and after decoding failure, the channel soft information can be disturbed again by using a disturbance noise, so that multiple decoding is realized, and the decoding success is improved. The decoding method of the application can be applied to software and hardware, and flexible and efficient decoding can be realized, and finally the decoding delay is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0041] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.
[0042] Figure 1 A flowchart of a decoding method of a binary linear code provided by an embodiment of the application is shown;
[0043] Figure 2 A decoding process diagram of a binary linear code provided by an embodiment of the application is shown;
[0044] Figure 3 A decoding process diagram of a concatenated code provided by an embodiment of the application is shown;
[0045] Figure 4 A perturbation noise aided decoding diagram provided by an embodiment of the present application is shown;
[0046] Figure 5 A performance diagram of decoding using perturbation noise provided by an embodiment of the present application is shown;
[0047] Figure 6 A structure diagram of a decoding device of a binary linear code provided by an embodiment of the present application is shown. DETAILED DESCRIPTION
[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.
[0049] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.
[0050] At present, common general approximate ML decoding algorithms of binary linear codes mainly include ordered statistic decoding (OSD) algorithm and its variants, etc. However, OSD algorithm depends on the reliability ordering of the received sequence, performs column permutation on the generating matrix of the code through the reliability ordering, and also needs to perform Gaussian elimination after permutation to make the matrix into a systematic form. For a linear code with a code length of n, the complexity of Gaussian elimination is O(n 3 ), which is relatively high. In addition, the Gaussian elimination operation is not suitable for hardware parallel implementation.
[0051] Therefore, the current general approximate ML decoding algorithm of binary linear codes has the problem of high complexity.
[0052] Based on this, the application provides a decoding method of a binary linear code, comprising the following steps of: receiving channel soft information and obtaining a check matrix, performing hard decision on the channel soft information to obtain a received sequence and a syndrome, determining whether the value of the syndrome is a zero vector, if the value of the syndrome is not the zero vector, it is indicated that the received sequence has an error, sorting the reliability of each received bit in the channel soft information to obtain a reliability sorting result, and reordering the columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix. At least one test error pattern is generated according to a logical weight, column elements of the reordered check matrix are extracted according to the test error pattern, and the column elements of the reordered check matrix and the syndrome are subjected to an exclusive or operation to obtain a test error pattern syndrome, and the logical weight is the sum of the positions of non-zero elements in a test error vector. It is determined whether the value of the test error pattern syndrome is a zero vector, if the value of the test error pattern syndrome is a zero vector, it is indicated that the decoding is successful, and the received sequence is decoded according to the test error vector to obtain a correct sequence. If the value of each test error pattern syndrome is not a zero vector, the channel soft information is disturbed by using a disturbance noise, and the subsequent steps of performing hard decision on the channel soft information to obtain a received sequence and a syndrome are repeatedly executed. That is, the application generates a test error vector according to a logical weight, and decodes the binary linear code by using multiple test error vectors. Since the check matrix obtained according to the reliability sorting and the test error vector generated according to the logical weight are independent of the structure of the binary linear code, the decoding complexity is reduced, and after decoding failure, the channel soft information can be disturbed again by using a disturbance noise, thereby realizing multiple decoding and improving the decoding success rate. The decoding method of the application can be applied to software and hardware, and flexible and efficient decoding can be realized, and finally the decoding delay is reduced.
[0053] In order to better understand the technical solutions and technical effects of the application, specific embodiments will be described in detail below with reference to the drawings.
[0054] Reference Figure 1 As shown in the figure, a flowchart of a decoding method of a binary linear code provided by an embodiment of the application, the method comprises the following steps:
[0055] S101, receiving channel soft information and obtaining a check matrix, performing hard decision on the channel soft information to obtain a received sequence and a syndrome.
[0056] In the embodiments of the application, the check matrix of the binary linear code and the received channel soft information can be obtained, the channel soft information is subjected to hard decision to obtain a received sequence and a syndrome.
[0057] The channel soft information is the received signal value after demodulation at the receiving end, and the channel soft information can be subjected to hard decision to obtain the closest received sequence. The received sequence can be obtained by The channel soft information is represented by y.
[0058] The decoding process requires a parity check matrix, which can be represented by H. The parity check matrix H is known before decoding and stored in a register. Different binary linear codes correspond to different parity check matrices; that is, there is a correspondence between the parity check matrix and the binary linear code. Thus, the corresponding parity check matrix is determined based on the binary linear code. For an (n,k) linear block code C, where n represents the length of the encoded codeword and k represents the length of the information to be encoded, the parity check matrix H is an (nk)×n dimensional matrix, H=(s1,s2,…,s…). n ), where s i It is an (nk)×1 dimensional vector (1≤i≤n), and for any codeword c∈C, we have c·H T =0 (0 mentioned in the text refers to the zero vector).
[0059] Received sequence It is obtained by hard-decision processing of the channel soft information y. For Binary Phase Shift Keying (BPSK) modulation, the channel soft information y is a 1×n dimensional vector, and the received sequence... It is determined by making a decision after comparing the channel soft information y with a threshold.
[0060] As an example, y = (0.9, -0.07, -1.3, 0.5, 2.3), then after hard decision...
[0061] The checksum can be represented by S. After performing a hard decision on the channel soft information, a checksum can be obtained. The checksum can be used to determine whether errors are found in the received sequence obtained from the hard decision on the channel soft information, and whether decoding is required. Specifically, the checksum S can be derived from the received sequence... The transpose of the parity check matrix H T Calculated, i.e.
[0062] As an example, the channel soft information y is a 1×n dimensional vector, and the parity check S is a 1×(nk) dimensional vector, derived from the received sequence. The transpose of the parity check matrix H T Calculations show that
[0063] S102, determine whether the value of the checksum is a zero vector. If the value of the checksum is not a zero vector, it indicates that an error was found in the received sequence.
[0064] In the embodiments of the present application, whether the received sequence is a code word in the codebook can be determined according to the syndrome S. When the syndrome S≠0, that is, when the value of the syndrome is not a zero vector, the received sequence is not a code word in the codebook, which indicates that the received sequence has errors and needs to be decoded by error correction.
[0065] Correspondingly, when the syndrome S=0, that is, when the value of the syndrome is a zero vector, the received sequence is a code word in the codebook, which indicates that the received sequence has no errors and does not need to be decoded by error correction, and the decoding is directly exited.
[0066] S103, the reliability of each received bit in the channel soft information is sorted to obtain a reliability sorting result, and the columns of the check matrix are reordered according to the reliability sorting result to obtain a reordered check matrix.
[0067] In the embodiments of the present application, if the value of the syndrome is not a zero vector, the received sequence needs to be decoded by error correction. Considering that in BPSK modulation, the absolute value |y i of each channel soft information y i can be used to measure the hard decision reliability of the i th transmission bit. The larger |y i , the higher the reliability of the hard decision of the received bit , and the less likely it is that the received bit has errors. Therefore, the reliability of each received bit in the channel soft information can be sorted to obtain a reliability sorting result, and the columns of the check matrix are reordered according to the reliability sorting result to obtain a reordered check matrix, so as to participate in error correction coding subsequently by using the reordered check matrix.
[0068] As a possible implementation manner, after obtaining the reliability sorting result, the position change result of each received bit can be obtained according to the reliability sorting result, a conversion vector is obtained according to the position change result, and the columns of the check matrix are reordered according to the conversion vector to obtain a reordered check matrix. That is, the position change of each received bit is recorded in the conversion vector according to the reliability sorting result, so that the columns of the check matrix are sorted according to the conversion vector.
[0069] Specifically, the reliability of each received bit in the channel soft information can be sorted in ascending order, and the unreliable received bits are sorted in front and the reliable received bits are sorted in back to obtain a reliability sorting result. The reliability sorting result is recorded in a conversion vector, which can be represented by ind. The columns of the check matrix H are arranged according to the conversion vector ind to obtain a reordered check matrix, which can be represented by H_ind.
[0070] As an example, the channel soft information y=(0.9, -0.07, -1.3, 0.5, 2.3) is arranged in ascending order according to the reliabilities to obtain a reliability ordering result y_ind=(-0.07, 0.5, 0.9, -1.3, 2.3), a conversion vector ind=(2, 4, 1, 3, 5), and a sorted check matrix H_ind=(s2, s4, s1, s3, s5).
[0071] In S104, at least one test error pattern is generated according to the logistic weight, column elements of the sorted check matrix are extracted according to the test error pattern, and test error pattern syndrome is obtained by performing XOR operation on the extracted column elements of the sorted check matrix and the syndrome.
[0072] In the embodiments of the present application, the position of the receiving bit that may be wrong in the receiving sequence can be determined by using multiple test error patterns, and the test error pattern can be generated according to the logistic weight (LW). At least one test error pattern is generated according to the logistic weight, column elements of the sorted check matrix are extracted according to the test error pattern, and test error pattern syndrome is obtained by performing XOR operation on the extracted column elements of the sorted check matrix and the syndrome. Whether the decoding of the receiving sequence by using the test error vector can be successfully decoded can be determined according to the test error pattern syndrome.
[0073] At least one test error pattern is generated according to the logistic weight, wherein the logistic weight is the sum of the positions of the non-zero elements in the test error vector, that is, different test error vectors can be generated under the same logistic weight value, and the integer splitting algorithm can be used to generate multiple test error vectors under the same logistic weight.
[0074] As a possible implementation manner, multiple test error patterns can be first generated according to the logistic weight, and each test error pattern corresponds to a test error vector, wherein the test error pattern represents the position of the non-zero element in the test error vector, that is, different test error patterns can be generated under the same logistic weight value, and the integer splitting algorithm can be used to generate multiple test error patterns under the same logistic weight, and then the corresponding test error vector is obtained according to the test error pattern. The non-zero elements of the test error vector are used to determine the column elements of the sorted check matrix corresponding to the non-zero elements, and the column elements are subjected to XOR operation, that is, the column elements corresponding to the non-zero elements are subjected to XOR operation to obtain a first operation result, and the first operation result and the syndrome are subjected to XOR operation to obtain the test error pattern syndrome.
[0075] As an example, the test error patterns t p, the ascending order of the logical weight can be that the value of the logical weight increases from 1 by 1 each time, and each test error pattern t p corresponds to a test error vector e, and the position of all non-zero elements e i in the test error vector e corresponds to the column element s j in the sorted check matrix H_ind, which is subjected to an XOR operation, and then subjected to an XOR operation with the syndrome S, to obtain a test error pattern syndrome S.
[0076] In actual applications, the sorted check matrix obtained according to the ascending order of reliability and the test error pattern and the test error vector generated according to the ascending order of the logical weight are considered to enable error correction decoding to be performed on the most likely error bit or bits. For example, when LW = 1, the test error pattern is {(1)}; when LW = 2, the test error pattern is {(2)}; when LW = 3, the test error pattern is {(3), (1, 2)}; and when the value of LW is larger, LW = 12, the test error pattern includes {(12), (11, 1), (10, 2), (9, 3), (8, 4), (7, 5), (9, 2, 1), (8, 3, 1), (7, 4, 1), (6, 5, 1), (7, 3, 2), (6, 4, 2), (5, 4, 3), (6, 3, 2, 1), (5, 4, 2, 1)}. When n = 5 and LW = 7 at a certain moment, the test error pattern t p = (1, 2, 4), e = (1, 1, 0, 1, 0), H_ind = (s2, s4, s1, s3, s5), and then S = s2 + s4 + s3 + S.
[0077] To further reduce the decoding complexity, the length of the split can be limited when the integer is split, that is, test error patterns with a length exceeding the maximum Hamming weight P are deleted. For example, when LW = 28 and P = 6, the test error pattern {(1, 2, 3, 4, 5, 6, 7)} is deleted.
[0078] S105, determine whether the value of the test error pattern syndrome is a zero vector, and if the value of the test error pattern syndrome is a zero vector, it indicates that the decoding is successful, and the received sequence is decoded according to the test error vector to obtain a correct sequence.
[0079] In the embodiments of the present application, whether the decoding of the received sequence using the test error vector can be successfully decoded can be determined according to whether the value of the test error pattern syndrome is a zero vector. If the value of the test error pattern syndrome is a zero vector, it indicates that the decoding is successful, and the received sequence can be decoded according to the test error vector to obtain a correct sequence. That is, when the test error pattern syndrome S = 0, it indicates that the test error pattern t pIf the received sequence y$ can be corrected to a code word in the codebook, the decoding is considered correct.
[0080] Since the test error pattern is the error position of the received bits after reliability sorting, it can be converted to the correct position according to the reliability sorting result, and then the received sequence is corrected and decoded according to the correct position. Specifically, the test error vector can be inversely converted according to the conversion vector to obtain an error estimation vector, and the received sequence is decoded according to the error estimation vector to obtain a correct sequence, i.e., a decoded code word.
[0081] As an example, n = 5, when the test error pattern t p = (1, 2, 4), S = 0, ind = (2, 4, 1, 3, 5), the inversely converted test error pattern is t p = (2, 4, 3), the error estimation vector e = (0, 1, 1, 1, 0), and the decoded code word c = e + y is obtained.
[0082] S106, if the value of the test error pattern check sub is not a zero vector, the channel soft information is disturbed by the disturbance noise, and the subsequent steps of repeatedly performing hard decision on the channel soft information to obtain the received sequence and the check sub are executed.
[0083] In the embodiments of the present application, if the number of test error pattern check subs is multiple, and if the value of each test error pattern check sub is not a zero vector, it means that the test error vector under the current logic weight cannot be successfully corrected and decoded. After it is finally determined that decoding fails under each logic weight, the channel soft information can be disturbed by the disturbance noise, and the subsequent steps of repeatedly performing hard decision on the channel soft information to obtain the received sequence and the check sub are executed, i.e., the steps of S101-S106 are repeated.
[0084] By disturbing the channel soft information by the disturbance noise, the received sequence and the check sub obtained by performing hard decision on the disturbed channel soft information will also change accordingly, and the reliability sorting of the disturbed channel soft information will also change, thereby further improving the possibility of successful decoding.
[0085] In the embodiments of the present application, before the channel soft information is disturbed by the disturbance noise, it is considered that the greater the value of the logical weight is, the better the decoding performance is, but the decoding time and decoding complexity will also increase accordingly. Therefore, in order to reduce the decoding delay and decoding complexity, the weight threshold can be set, and when the logical weight is greater than the weight threshold, the decoding is exited. That is, under the current logical weight, if the value of the test error syndrome is not a zero vector, it means that the test error vector under the current logical weight cannot be successfully decoded by error correction, and it is determined whether the current logical weight is greater than the weight threshold. If the logical weight is less than or equal to the weight threshold, the logical weight is increased by a fixed step, for example, 1, and the step of generating at least one test error vector according to the logical weight is repeatedly executed, that is, a plurality of test error vectors are continuously generated according to the increased logical weight, and the process of continuously determining whether the plurality of test error vectors can be correctly decoded is continued. If the logical weight is greater than the weight threshold, it means that each test error vector generated by the logical weight less than or equal to the weight threshold cannot be correctly decoded by error correction, that is, the decoding fails, and the decoding can be directly exited to reduce the decoding delay.
[0086] As an example, reference is made to Figure 2 It is shown that the weight threshold can utilize the LW max It is shown that when the LW>LW max , the decoding is exited and the process returns to
[0087] In practical applications, in addition to determining whether the decoding fails by using the weight threshold of the logical weight, other conditions can also be used to determine whether the decoding fails. For example, for binary linear block codes, if the decoding fails and needs to be re-decoded, otherwise the decoding is successful and the decoding is exited. For concatenated codes, whether the outer code decoding fails can be used as a judgment condition. For example, for the concatenated code of the CRC code, the CRC check can be used as a condition for judging whether the decoding fails.
[0088] As an example, the present application takes the BCH concatenated CRC code as an example to explain the decoding process, the (127, 113) BCH code as the inner code and the (113, 101) CRC code as the outer code, reference is made to Figure 3As shown, after CRC encoding and BCH encoding on the information sequence of the binary linear code, the channel soft information is obtained by transmitting through the channel, and the channel soft information is decoded, that is, the inner code decoding process is performed, the inner code decoding process is the steps S101 to S105, whether the decoding fails is checked by CRC, if the decoding succeeds, the correct sequence is directly output, if the decoding fails, whether the number of re-decoding after the decoding fails is less than N is determined, if less, the disturbance noise is generated by using the noise generator, the channel soft information is disturbed by using the disturbance noise, and the inner code decoding process is re-performed, if greater, the decoding fails, and the decoding is exited.
[0089] In the embodiment of the present application, after confirming the decoding failure, re-decoding can also be performed until the decoding succeeds, but considering the decoding time problem, the maximum re-decoding number can be set, and after greater than the maximum re-decoding number, the decoding can be exited. That is, whether the number of re-decoding after the decoding fails is greater than the maximum re-decoding number can be determined, if the number of re-decoding after the decoding fails is less than or equal to the maximum re-decoding number, the channel soft information is disturbed by using the disturbance noise, and the steps of repeatedly performing the hard decision on the channel soft information, obtaining the received sequence and the syndrome and the subsequent steps are repeated.
[0090] Reference Figure 2 As shown, the number of re-decoding after the decoding fails can be represented by t, and the maximum re-decoding number can be represented by t max As shown, whether the number of re-decoding after the decoding fails t reaches the maximum re-decoding number t max , if t>t max , the decoding fails, and the decoding is exited, otherwise, after the channel soft information is disturbed by using the appropriate disturbance noise, the re-decoding process is performed by returning to step S101.
[0091] As an example, the disturbance noise can be formed by using the noise generator, and the disturbance noise can adopt the Gaussian noise or the noise obeying the uniform distribution on (-1, 1).
[0092] Reference Figure 4 As shown, the black solid dot represents the transmitted binary linear code, the cross sign represents the channel soft information, that is, the received signal, the black circle represents other code words in the codebook, and the area surrounded by the square dashed line is the error correction area of the decoding method. If the received sequence appears in the square area, the correct decoding can be performed. The two dashed circular areas and the long dashed circular area represent that after the information code word passes through the AWGN channel, the channel soft information randomly appears at any position in the circular area. The intermittent line circular area represents that after a certain degree of disturbance noise is independently applied to the channel soft information, the disturbed channel soft information can randomly appear at any position in the circular area. From Figure 4As can be seen, the channel soft information is disturbed and has a certain probability to appear in the square area, thereby being correctly decoded. It should be noted that the disturbance noise needs to be strong enough to disturb the ordering of the received bits of the channel soft information, that is, to disturb the ordering of the channel soft information, but cannot be too strong. If the disturbance noise is too strong, the initial channel soft information is submerged, and the decoding is meaningless.
[0093] As an example, Figure 5 For the LW max = 64, P = 6, t max = 100, the noise disturbance coefficient is 0.2, and the decoding performance of the uniform noise disturbance is compared with that without disturbance. It can be obviously observed that the decoding performance is greatly improved by adding the noise disturbance. Similarly, when the Gaussian noise is used as the disturbance, the appropriate disturbance strength also has the effect of improving the decoding performance.
[0094] As can be seen, the channel soft information is disturbed and has a certain probability to appear in the square area, thereby being correctly decoded. It should be noted that the disturbance noise needs to be strong enough to disturb the ordering of the received bits of the channel soft information, that is, to disturb the ordering of the channel soft information, but cannot be too strong. If the disturbance noise is too strong, the initial channel soft information is submerged, and the decoding is meaningless.
[0095] Based on the decoding method of the binary linear code provided in the above embodiments, an embodiment of the present application further provides a decoding device of a binary linear code. Referring to FIG. 2, Figure 6 FIG. 2 is a structural schematic diagram of a decoding device of a binary linear code provided in an embodiment of the present application. The decoding device 200 of the binary linear code provided in the embodiment of the present application comprises:
[0096] A receiving unit 210 is configured to receive channel soft information and obtain a check matrix, perform hard decision on the channel soft information, and obtain a received sequence and a syndrome;
[0097] A determining unit 220 is configured to determine whether the value of the syndrome is a zero vector. If the value of the syndrome is not a zero vector, it is indicated that the received sequence has found an error.
[0098] An ordering unit 230 is configured to order the reliability of each received bit in the channel soft information, obtain a reliability ordering result, reorder the columns of the check matrix according to the reliability ordering result, and obtain a reordered check matrix.
[0099] The operation unit 240 is configured to generate at least one test error pattern according to a logical weight, extract column elements of the sorted check matrix according to the test error pattern, and perform XOR operation on the extracted column elements of the sorted check matrix and the syndrome to obtain a test error pattern syndrome, wherein the logical weight is a sum of positions of non-zero elements in the test error vector;
[0100] The decoding unit 250 is configured to determine whether the value of the test error pattern syndrome is a zero vector, and if the value of the test error pattern syndrome is a zero vector, it indicates that decoding is successful, and decode the received sequence according to the test error vector to obtain a correct sequence.
[0101] The perturbation unit 260 is configured to, if the value of the test error pattern syndrome is not a zero vector, perturb the channel soft information by using a perturbation noise, and repeatedly perform hard decision on the channel soft information to obtain a received sequence and a syndrome and subsequent steps.
[0102] Optionally, the operation unit 240 is configured to:
[0103] generate a plurality of test error patterns according to a logical weight, wherein each test error pattern corresponds to a test error vector, and the test error pattern represents positions of non-zero elements in the test error vector;
[0104] determine column elements of the sorted check matrix corresponding to the non-zero elements of the test error vector according to the non-zero elements of the test error vector, and perform XOR operation on the column elements to obtain a first operation result;
[0105] continue to perform XOR operation on the first operation result and the syndrome to obtain a test error pattern syndrome.
[0106] Optionally, the sorting unit 230 is configured to:
[0107] obtain a position change result of each received bit according to the reliability sorting result, and obtain a conversion vector according to the position change result;
[0108] re-sort columns of the check matrix according to the conversion vector to obtain a sorted check matrix.
[0109] Optionally, the decoding unit 250 is configured to:
[0110] perform inverse conversion on the test error vector according to the conversion vector to obtain an error estimation vector;
[0111] decode the received sequence according to the error estimation vector to obtain a correct sequence.
[0112] Optionally, the apparatus further comprises an increasing unit configured to:
[0113] If the value of the test syndrome is not a zero vector, it is determined whether the logic weight is greater than a weight threshold, and if the logic weight is less than or equal to the weight threshold, the logic weight is increased by a fixed step, and the step of generating at least one test error vector according to the logic weight is repeatedly executed.
[0114] Optionally, the perturbation unit 260 is further configured to:
[0115] If the logic weight is greater than the weight threshold, it is indicated that decoding fails.
[0116] If the number of times of re-decoding after decoding fails is greater than a maximum number of times of re-decoding, the channel soft information is perturbed by the perturbation noise, and the steps of performing hard decision on the channel soft information, obtaining the received sequence and the syndrome, and the subsequent steps are repeatedly executed.
[0117] Optionally, the determining unit is further configured to:
[0118] It is determined whether the value of the syndrome is a zero vector, and if the value of the syndrome is a zero vector, it is indicated that no error is found in the received sequence, and the decoding is exited.
[0119] The embodiments of the present application further provide a computer readable storage medium for storing program codes, the program codes being used for executing any one of the methods in the foregoing embodiments.
[0120] In the context of the present application, the machine readable medium can be a tangible medium which can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine readable medium can be a machine readable signal medium or a machine readable storage medium. The machine readable medium can include, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. More specific examples of the machine readable storage medium can include one or more lines of electrical connections, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, compact disk read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the above.
[0121] It should be noted that the computer readable medium in the present application can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the present application, the computer readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer readable program code. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus. The program code contained in the computer readable medium can be transmitted by any suitable medium, including but not limited to a wire, a cable, a RF (radio frequency) or the like, or any suitable combination of the above.
[0122] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, they are described more simply, and the relevant parts can be referred to the part of the method embodiments.
[0123] The above is only the preferred embodiment of the present application. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application, by using the methods and technical contents disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical solution of the present application, all still belong to the scope of protection of the technical solution of the present application.
Claims
1. A decoding method of a binary linear code, characterized by, The method comprises the following steps: receiving channel soft information and obtaining a check matrix, performing hard decision on the channel soft information to obtain a received sequence and a syndrome; determining whether the value of the syndrome is a zero vector, and if the value of the syndrome is not a zero vector, it indicates that the received sequence has an error; sorting the reliability of each received bit in the channel soft information to obtain a reliability sorting result, and reordering the columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix; generating at least one test error pattern according to a logical weight, extracting column elements of the reordered check matrix according to the test error pattern, and performing XOR operation on the extracted column elements of the reordered check matrix and the syndrome to obtain a test error pattern syndrome, wherein the logical weight is the sum of the positions of non-zero elements in the test error vector; determining whether the value of the test error pattern syndrome is a zero vector, and if the value of the test error pattern syndrome is a zero vector, it indicates that the decoding is successful, and decoding the received sequence according to the test error pattern to obtain a correct sequence; if the value of the test error pattern syndrome is not a zero vector, perturbing the channel soft information using a perturbation noise, and repeatedly performing the hard decision on the channel soft information to obtain a received sequence and a syndrome and the subsequent steps.
2. The method of claim 1, wherein, The step of generating at least one test error pattern according to a logical weight, extracting column elements of the reordered check matrix according to the test error pattern, and performing XOR operation on the extracted column elements of the reordered check matrix and the syndrome to obtain a test error pattern syndrome comprises: generating multiple test error patterns according to a logical weight, each test error pattern corresponding to a test error vector, wherein the test error pattern represents the positions of non-zero elements in the test error vector; determining the column elements of the reordered check matrix corresponding to the non-zero elements of the test error vector according to the non-zero elements of the test error vector, and performing XOR operation on the column elements to obtain a first operation result; continuing to perform XOR operation on the first operation result and the syndrome to obtain a test error pattern syndrome.
3. The method of claim 1, wherein, The step of reordering the columns of the check matrix according to the reliability sorting result to obtain a reordered check matrix comprises: obtaining a position change result of each received bit according to the reliability sorting result, and obtaining a conversion vector according to the position change result; reordering the columns of the check matrix according to the conversion vector to obtain a reordered check matrix.
4. The method of claim 3, wherein, The step of decoding the received sequence according to the test error vector to obtain a correct sequence comprises: obtaining an error estimation vector by inversely converting the test error vector according to the conversion vector; decoding the received sequence according to the error estimation vector to obtain a correct sequence.
5. The method of claim 1, wherein, Before perturbing the channel soft information using a perturbation noise, the method further comprises: If the value of the test error pattern syndrome is not a zero vector, it is determined whether the logical weight is greater than a weight threshold, and if the logical weight is less than or equal to the weight threshold, the logical weight is increased by a fixed step, and the step of generating at least one test error pattern according to the logical weight is repeatedly performed.
6. The method of claim 5, wherein, The method further comprises: If the logical weight is greater than the weight threshold, a decoding failure is indicated; After determining the decoding failure, it is determined whether the number of re-decoding is greater than a maximum re-decoding number, and if the number of re-decoding is less than or equal to the maximum re-decoding number, the channel soft information is disturbed by a disturbance noise, and the subsequent steps of performing hard decision on the channel soft information to obtain a received sequence and a syndrome and performing the subsequent steps are repeatedly performed.
7. The method of claim 1, wherein, The method further comprises: If the value of the syndrome is a zero vector, it is indicated that no error is found in the received sequence, and the decoding is exited.
8. The method according to any one of claims 1 to 7, characterized in that, The check matrix is determined according to a binary linear code, and the syndrome is calculated according to the received sequence and a transpose matrix of the check matrix.
9. A decoding device of a binary linear code, characterized in that, Comprise: A receiving unit configured to receive channel soft information and obtain a check matrix, perform hard decision on the channel soft information to obtain a received sequence and a syndrome; A determining unit configured to determine whether the value of the syndrome is a zero vector, and if the value of the syndrome is not a zero vector, it is indicated that an error is found in the received sequence; An ordering unit configured to order the reliability of each received bit in the channel soft information to obtain a reliability ordering result, reorder columns of the check matrix according to the reliability ordering result to obtain a reordered check matrix; An operating unit configured to generate at least one test error pattern according to a logical weight, extract column elements of the reordered check matrix according to the test error pattern, and perform XOR operation on the extracted column elements of the reordered check matrix and the syndrome to obtain a test error pattern syndrome, wherein the logical weight is a sum of positions of non-zero elements in the test error vector; A decoding unit configured to determine whether the value of the test error pattern syndrome is a zero vector, and if the value of the test error pattern syndrome is a zero vector, it is indicated that the decoding is successful, and the received sequence is decoded according to the test error vector to obtain a correct sequence; A disturbing unit configured to, if the value of the test error pattern syndrome is not a zero vector, disturb the channel soft information by a disturbance noise, and repeatedly perform the subsequent steps of performing hard decision on the channel soft information to obtain a received sequence and a syndrome.
10. A computer-readable storage medium, characterized in that, The instructions, when executed on a computer, cause the computer to perform the method of any one of claims 1-8.