Encoding method, decoding method, communication node and storage medium

Abstract

Disclosed are an encoding method, a decoding method, a communication node and a storage medium. The encoding method comprises: determining a bit sequence to be encoded (110); determining a shortened sequence on the basis of the length of the bit sequence to be encoded and at least one of the following parameters: a lifting value and a code rate (120); and on the basis of a parity check matrix (PCM), the shortened sequence, a shortened systematic column size and the lifting value, encoding the bit sequence to be encoded, so as to obtain an encoded bit sequence (130).

Description

Encoding methods, decoding methods, communication nodes, and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411656435.1, filed with the Chinese Patent Office on November 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of wireless communication technology, such as an encoding method, a decoding method, a communication node, and a storage medium. Background Technology

[0003] With the rapid development of technologies such as big data, cloud computing, and latency-sensitive networks, the number of user devices in wireless communication networks is exploding. These networks will carry diverse applications and massive amounts of data, placing high demands on data transmission rates, throughput, reliability, and latency. Currently, with the development of virtual reality / augmented reality, intelligent transportation, intelligent industrial control, and intelligent logistics, the requirements for ultra-high data rates, ultra-low latency, and ultra-high reliability are becoming increasingly stringent. In future mobile communication air interface standard protocols, the peak rate requirement will increase by one or two orders of magnitude compared to existing 5G mobile communication systems. How to design encoding and decoding methods to improve data error correction performance, increase the robustness of data communication, and meet the requirements of higher peak rates has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides an encoding method, a decoding method, a communication node, and a storage medium.

[0005] This application provides an encoding method applied to a first communication node, including:

[0006] Determine the bit sequence to be encoded;

[0007] The shortened sequence is determined based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value, code rate;

[0008] The bit sequence to be encoded is encoded based on the parity check matrix (PCM), the shortened sequence, the shortened system column size (Kb), and the boost value to obtain the encoded bit sequence.

[0009] The shortened sequence includes a position index indicating the position where the Low Density Parity Check (LDPC) code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size of the PCM and greater than 0. The length of the bit sequence to be encoded and the boost value are both integers greater than 0. The code rate is a real number greater than 0 and less than 1. The number of rows and columns of the PCM are both integers greater than 0, and the number of columns is greater than the number of rows. The systematic column size of the PCM is the difference between the number of columns and the number of rows. The shortened systematic column size is an integer greater than 0 and not exceeding the systematic column size. The length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded.

[0010] This application also provides a decoding method applied to a second communication node, including:

[0011] Receive all or part of the data sequence to be decoded;

[0012] The shortening sequence is determined based on the length of the bit sequence to be encoded corresponding to the data sequence to be decoded and at least one of the following parameters: boost value, code rate;

[0013] Based on the parity check matrix PCM, the shortened sequence, the shortened system column size and the boost value, the data sequence to be decoded is subjected to LDPC decoding to obtain the decoded bit sequence, which is consistent with the bit sequence to be encoded.

[0014] The shortened sequence includes a position index indicating the position where the LDPC code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size of the PCM and greater than 0. The length of the decoded bit sequence and the boost value are both integers greater than 0. The code rate is a real number greater than 0 and less than 1. The number of rows and columns of the PCM are both integers greater than 0, and the number of columns is greater than the number of rows. The systematic column size of the PCM is the difference between the number of columns and the number of rows, and the shortened systematic column size is an integer greater than 0 and not exceeding the systematic column size.

[0015] This application also provides a communication node, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described encoding or decoding method.

[0016] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described encoding or decoding method. Attached Figure Description

[0017] Figure 1 is a schematic diagram of an application scenario of an encoding / decoding method provided in one embodiment;

[0018] Figure 2 is a flowchart of an encoding method provided in an embodiment;

[0019] Figure 3 is a flowchart of a decoding method provided in one embodiment;

[0020] Figure 4 is a schematic diagram of the performance curve of a shortened sequence provided in one embodiment;

[0021] Figure 5 is a schematic diagram of the performance curve of another shortened sequence provided in one embodiment;

[0022] Figure 6 is a schematic diagram of the performance curve of another shortened sequence provided in one embodiment;

[0023] Figure 7 is a schematic diagram of the performance curve of another shortened sequence provided in one embodiment;

[0024] Figure 8 is a schematic diagram of an encoding device provided in one embodiment;

[0025] Figure 9 is a schematic diagram of a decoding device provided in one embodiment;

[0026] Figure 10 is a schematic diagram of the hardware structure of a communication node according to an embodiment. Detailed Implementation

[0027] The present application will now be described in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. It should be noted that, unless otherwise specified, the embodiments and features described herein can be arbitrarily combined with each other. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0028] In wireless communication systems, the transmitting end performs channel coding on the data to be transmitted to obtain a coded bit subsequence, and then maps the coded bit subsequence into constellation modulation symbols before sending it to the receiving end. In the data transmission channel, errors can occur due to factors such as multipath propagation, noise, and interference. The transmitting end adds redundant information to the data to be transmitted through channel coding, allowing the receiving end to recover the original data from this redundancy, thus eliminating the distortion introduced during transmission. The receiving end needs to perform channel decoding on the received constellation modulation symbols to recover the transmitted data.

[0029] Commonly used channel coding methods include low-density parity-check coding, polar coding, turbo coding, and convolutional coding. Low-density parity-check coding is defined by a sparse (or low-density) parity-check matrix, and its decoding performance can be improved through iterative decoding, such as using belief-transfer decoding.

[0030] LDPC codes are a type of forward error correction coding. In the 5G New Radio (NR) standard, the physical layer uses LDPC codes as the primary coding scheme for the data channel. 5G LDPC codes employ a quasi-cyclic (QC) structure, which, in addition to maintaining excellent performance, allows for higher decoding parallelism. QC-LDPC codes have two base graphs (BGs). The LDPC code can be defined by the PCM and boost value of the BG. In this application, the PCM of the BG is collectively referred to as PCM, which is the unexpanded matrix in the QC-LDPC code. The expanded matrix is ​​called the extended PCM. In BG2, the size Kb of the system column is determined according to the input information bit length B, as shown in Table 1.

[0031] Table 1. Flowchart for determining the system column size based on the input information bit length.

[0032] The above determination process can be understood as follows: For BG2, Kb is determined based on the input information bit length B, thereby determining the amount of shortening. The shortening position starts from the last systematic column of BG. That is, within the range of the input information bit length corresponding to the same Kb value, regardless of the change in the magnitude of the boost value Z, there is only one shortening position sequence. For example, if the dimension of BG2 is 42*52 and the total number of systematic columns is the first 10 columns, when Kb=9, the 10th systematic column is shortened; when Kb=8, the 9th and 10th systematic columns are shortened; and when Kb=6, the 7th, 8th, 9th, and 10th systematic columns are shortened.

[0033] The shortening operation involves selecting certain positions within the codeword and deciding not to send information at these positions. Thus, the shortening positions are known at both the transmitting and receiving ends, and are typically set to null or 0 at these positions. For example, a PCM structure can be represented as follows: Among them, Hb s For the system column matrix, Hb pFor the check column matrix, the number of columns in the system column matrix is ​​kb, and the number of columns in the check column matrix is ​​mb. If the shortened position is the last L columns of the system column in the PCM, then the (kb-L)*Z+1 to kb*Z bits in the codeword are known at both the transmitting and receiving ends. It can be understood that the (kb-L)*Z+1 to kb*Z bits mentioned above are known at both the transmitting and receiving ends, such as being all equal to null or 0.

[0034] According to the 5G NR protocol, within the range of input information bit length corresponding to the same Kb value, multiple boost values ​​have the same shortening position sequence. However, the shortening position sequence may not be optimal for every boost value. In this embodiment, the shortening sequence is obtained based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value, code rate. This ensures higher reliability and higher data error correction performance under any selectable boost value or code rate, thereby increasing the robustness of data communication.

[0035] Figure 1 is a schematic diagram of an application scenario of an encoding / decoding method provided in an embodiment. As shown in Figure 1, the first communication node 100 can transmit the encoded bits to the second communication node 200, and the second communication node 200 can decode the received bits. In one example, the first communication node 100 and the second communication node 120 may include, but are not limited to, the following electronic devices: base station (BS), access point (AP), node B, g-node B (generalized node B, g node B), radio network controller (RNC), evolved node B (eNB), base station controller (BSC), base transceiver station (BTS), transceiver function (TF), radio router, radio transceiver, basic service set (BSS), extended service set (ESS), or radio base station (RBS). The first and second communication nodes can also be access terminals, user equipment (UE), user units, user stations, mobile stations, mobile stations, remote stations, remote terminals, mobile devices, user terminals, wireless communication equipment, user agents, or user devices. For example, the second communication node can be a cellular phone, cordless phone, Session Initiation Protocol (SIP) phone, Wireless Local Loop (WLL) station, Personal Digital Assistant (PDA), handheld device with wireless communication capabilities, computing device or other processing device connected to a wireless modem, in-vehicle device, wearable device, 5G network, or terminal device in future 5G or higher networks, etc., without specific limitations.

[0036] In light of the above application scenarios, the LDPC code encoding method in this embodiment is generally executed by an electronic device with a certain computing power. In some possible implementations, the LDPC encoding method can be implemented by the processor calling computer-readable instructions stored in the memory.

[0037] It is understood that the execution subject of the LDPC code encoding method provided in this embodiment may be, but is not limited to, the first communication node in the scenario diagram shown in Figure 1. Alternatively, those skilled in the art can choose to set the corresponding execution subject according to the actual application scenario, and this embodiment does not impose any restrictions. Here, in order to more conveniently describe the application scenario and principle of this application, the first communication node is often used as the execution subject of the LDPC code encoding method in the relevant parts of the following related embodiments, but this should not be construed as a limitation on the embodiments of this application.

[0038] Figure 2 is a flowchart of an encoding method provided in one embodiment. This method can be applied to a first communication node, which can be an encoding end. As shown in Figure 2, the method provided in this embodiment includes:

[0039] Step 110: Determine the bit sequence to be encoded.

[0040] Step 120: Determine the shortened sequence based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value, code rate.

[0041] Step 130: Encode the bit sequence to be encoded according to the parity check matrix PCM, the shortened sequence, the shortened system column size and the boost value to obtain the encoded bit sequence.

[0042] The shortened sequence includes a position index indicating the position where the LDPC code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size (kb) of the PCM and greater than 0. The length (B) of the bit sequence to be encoded and the boost value are both integers greater than 0. The code rate is a real number greater than 0 and less than 1. The number of rows (mb) and columns (nb) of the PCM are both integers greater than 0, and the number of columns (nb) is greater than the number of rows (mb). The systematic column size (kb) of the PCM is the difference between the number of columns (nb) and the number of rows (mb). The shortened systematic column size (Kb) is an integer greater than 0 and not exceeding the systematic column size (kb). The length (N) of the encoded bit sequence is an integer greater than the length (B) of the bit sequence to be encoded.

[0043] The encoding method of this embodiment obtains a shortened sequence based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value and code rate. It can obtain the optimal shortened sequence for different boost values ​​and different code rates. By shortening the LDPC code according to the optimal shortened sequence, it can ensure higher reliability under any selectable boost value, thereby improving the error correction performance of the data, increasing the robustness of data communication, and meeting the requirements of higher peak rates.

[0044] In one embodiment, determining a shortened sequence based on the length of the bit sequence to be encoded and a boost value includes: determining the size of the shortened system column based on the length of the bit sequence to be encoded; determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened system column; and determining a shortened sequence based on the boost value.

[0045] In one embodiment, among the M shortened sequences determined based on M different lifting values, at least two different shortened sequences exist; where M is an integer greater than 1; and the number of shortened sequences is a positive integer not exceeding M.

[0046] In one embodiment, determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened system column includes: determining the minimum value in the boost value set as the boost value; the values ​​in the boost value set satisfy that the product of the boost value and the size of the shortened system column is greater than or equal to the length of the bit sequence to be encoded.

[0047] In one embodiment, determining the shortening sequence based on the boost value includes: determining the shortening sequence according to a preset table or a preset procedure, wherein the preset table or the preset procedure is used to indicate the shortening sequence corresponding to each boost value interval.

[0048] In one embodiment, encoding the bit sequence to be encoded based on the PCM, the shortened sequence, the shortened hierarchical column size, and the boost value to obtain an encoded bit sequence includes: determining the zero-padded bit sequence to be encoded based on the shortened sequence, the PCM, the boost value, and the shortened hierarchical column size, wherein the length of the zero-padded bit sequence to be encoded is the product of the hierarchical column size and the boost value; and encoding the zero-padded bit sequence to be encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N.

[0049] In one embodiment, encoding the zero-padded bit sequence to be encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N includes: matrix expansion of the PCM based on the boost value Z to obtain an extended PCM corresponding to the zero-padded bit sequence to be encoded; and encoding the zero-padded bit sequence to be encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0050] In one embodiment, determining a shortened sequence based on the length and code rate of the bit sequence to be encoded includes: determining the size of the shortened system column based on the length of the bit sequence to be encoded; and obtaining the shortened sequence based on the size of the shortened system column and the code rate.

[0051] In one embodiment, obtaining a shortened sequence based on the shortened system column size and code rate includes: determining the shortened sequence according to a preset table or preset process, wherein the preset table or preset process is used to indicate the shortened sequence corresponding to the length range and code rate range of each bit sequence to be encoded.

[0052] In one embodiment, determining a shortened sequence based on the length of the bit sequence to be encoded, a boost value, and a code rate includes: determining the size of the shortened hierarchical column based on the length of the bit sequence to be encoded; determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened hierarchical column; and obtaining the shortened sequence based on the boost value and the code rate.

[0053] In one embodiment, determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened system column includes: determining the minimum value in the boost value set as the boost value; the values ​​in the boost value set satisfy: greater than or equal to a target value, wherein the target value is an integer not less than the ratio of the length of the bit sequence to be encoded to the size of the shortened system column.

[0054] In one embodiment, obtaining a shortened sequence based on the boost value and the bit rate includes one of the following: determining the shortened sequence according to a preset table or a preset procedure, wherein the preset table or the preset procedure is used to indicate the shortened sequence corresponding to each boost value interval and each bit rate interval.

[0055] In one embodiment, determining a shortened sequence based on the length and code rate of the bit sequence to be encoded includes: determining a first shortened sequence based on the code rate; determining a shortened system column size based on the length of the bit sequence to be encoded; and determining a shortened sequence based on the shortened system column size and the first shortened sequence.

[0056] In one embodiment, determining a first shortened sequence based on bitrate includes: determining a shortened sequence according to a preset table or a preset procedure, wherein the preset table or the preset procedure is used to indicate the first shortened sequence corresponding to each bitrate interval.

[0057] In one embodiment, determining a shortened sequence based on the shortened system column size and the first shortened sequence includes: determining the number of system columns to be shortened according to the system column size and the shortened system column size, and constructing a shortened sequence by taking the corresponding number of elements at preset positions in the first shortened sequence according to the number of system columns to be shortened.

[0058] In one embodiment, determining the shortened system column size based on the length of the bit sequence to be encoded includes: determining the shortened system column size according to a preset length range of the bit sequence to be encoded, where the length of the bit sequence to be encoded falls.

[0059] In one embodiment, the bit sequence to be encoded is encoded according to the PCM, the shortened sequence, the shortened systematic column size, and the boost value to obtain an encoded bit sequence, including:

[0060] The shortened PCM is determined based on the shortened sequence, PCM, and the shortened system column size.

[0061] Based on the shortened PCM and the boost value, the bit sequence to be encoded is encoded to obtain an encoded bit sequence of length N.

[0062] In one embodiment, encoding the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N includes: matrix expansion of the shortened PCM based on the boost value to obtain an extended PCM corresponding to the bit sequence to be encoded; and encoding the bit sequence to be encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0063] In one embodiment, the method further includes sending all or part of the bits of the encoded bit sequence to the second node.

[0064] Figure 3 is a flowchart of a decoding method provided in one embodiment. This method can be applied to a second communication node, which can be a decoding end. It should be noted that technical details not described in detail in this embodiment can be found in any of the above embodiments. As shown in Figure 3, the method provided in this embodiment includes:

[0065] Step 210: Receive all or part of the data in the data sequence to be decoded.

[0066] Step 220: Determine the shortening sequence based on the length of the bit sequence to be encoded corresponding to the data sequence to be decoded and at least one of the following parameters: boost value, code rate.

[0067] Step 230: Based on the parity check matrix PCM, the shortened sequence, the shortened system column size, and the boost value, perform LDPC decoding on the data sequence to be decoded to obtain the decoded bit sequence, which is consistent with the bit sequence to be encoded.

[0068] The shortened sequence includes a position index indicating the position where the LDPC code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size of the PCM and greater than 0. The length of the decoded bit sequence and the boost value are both integers greater than 0. The code rate is a real number greater than 0 and less than 1. The number of rows and columns of the PCM are both integers greater than 0, and the number of columns is greater than the number of rows. The systematic column size of the PCM is the difference between the number of columns and the number of rows, and the shortened systematic column size is an integer greater than 0 and not exceeding the systematic column size.

[0069] The encoding and decoding methods of this application are illustrated by way of some embodiments below.

[0070] Example 1

[0071] As shown in Figure 2, the encoding method involves encoding the bit sequence using a PCM, a shortening sequence, the shortened systematic column size, and a boost value. The shortening sequence is a list of position indices indicating the shortening positions of the systematic columns in the PCM according to the shortening positions. The number of elements in the shortening sequence is less than the systematic column size (kb) of the PCM and greater than 0. The PCM is a matrix of size mb*nb, where mb and nb are integers greater than 0, and nb is greater than mb. The boost value Z is an integer greater than 0. The shortened systematic column size Kb is an integer greater than 0 and less than or equal to kb, and kb is the difference between nb and mb. The length B of the bit sequence to be encoded is an integer greater than 0.

[0072] It is important to understand that in this application, kb refers to the number of systematic columns before shortening, and Kb refers to the number of systematic columns after shortening, where Kb is less than or equal to kb. This is because the shortening operation involves selecting certain positions in the codeword and deciding not to send information at these positions. The positions where the codeword is shortened are known at both the transmitting and receiving ends. The bits at the shortened positions in the codeword can be set to null or 0, so that null or 0 multiplied by the coding coefficient in the systematic column always equals 0. It can be understood that the systematic columns at the shortened positions do not participate in the actual coding process. Therefore, the systematic columns that actually participate in the coding process are called the systematic columns after shortening. In this application, the systematic columns before shortening are also simply referred to as systematic columns.

[0073] In one embodiment, a shortened sequence is obtained based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value and code rate. In this embodiment, obtaining a shortened sequence based on the length of the bit sequence to be encoded and the boost value includes: determining the shortened system column size Kb based on the length of the bit sequence to be encoded; determining the boost value based on the length of the bit sequence to be encoded and the shortened system column size Kb; and obtaining the shortened sequence based on the boost value.

[0074] In this embodiment, among the M shortened sequences determined based on M different lifting values, there are at least two different shortened sequences. That is, if there are M different lifting values, then among the M shortened sequences corresponding to the M lifting values, there are at least two different shortened sequences and at most M different shortened sequences.

[0075] It's understandable that there are two scenarios: one where M lift values ​​correspond to M distinct shortened sequences, and another where M lift values ​​correspond to fewer than M distinct shortened sequences, meaning there are at least two lift values ​​corresponding to one shortened sequence, where M is an integer greater than 1. In one example, there are at least two lift values ​​corresponding to two shortened sequences, where the two lift values ​​are not equal and satisfy the following conditions: the two shortened sequences have the same length, and the element values ​​in the two shortened sequences are different. In another example, the difference between the two lift values ​​is not less than a first threshold, where the first threshold is equal to 8, 12, 16, 20, 24, or 32. Based on this, the optimal shortened sequence for each lift value can be selected, improving the error correction performance of the data.

[0076] In one embodiment, determining the shortened system column size Kb based on the length B of the bit sequence to be encoded includes: obtaining the shortened system column size according to the preset length range of the bit sequence to be encoded, as shown in Table 1 in one example.

[0077] In one embodiment, determining the boost value based on the length B of the bit sequence to be encoded and the shortened system column size Kb includes: finding, from all possible boost values, a value such that Kb·Z c The minimum Z when ≥B holds true c The value is a definite promotion value. The preset set of optional promotion values ​​is a collection of all possible promotion values. In one example, the elements in the optional promotion value set can be represented as a*2. j Let 'a' belong to the set {2,3,5,7,9,11,13,15}, and 'j' belong to the set {0,1,2,3,4,5,6,7}. In one example, the optional promotion value sets are shown in Table 2. In one example, the index of the value 'a' is the index position of the values ​​in the set to which 'a' belongs, sorted from smallest to largest.

[0078] Table 2. Index of value 'a' and corresponding set of optional promotion values

[0079] In one embodiment, a shortened sequence is obtained based on the boost value. The shortened sequence can be obtained in the following ways, but is not limited to: a preset table or a preset process.

[0080] In this embodiment of the application, the representation of the shortened sequence can be at least one of the following:

[0081] Method 1: The shortened sequence is obtained from a preset table. The preset table indicates the shortened sequence corresponding to each boost value. The shortened sequence indicates the position where the system column of PCM is shortened. The preset table is shown in Table 3.

[0082] Table 3. Increase Value Range and Corresponding Shortening Sequence

[0083] In this embodiment, the boosting value range of the preset table can be more than just a range; it can also be an equality judgment. For example, the shortened sequence when Z = Z0 is S0 = [s 0,0 ,s 0,1 ,...,s 0,L-1 ].

[0084] In this embodiment, the number of elements in the shortened sequences corresponding to different lift value intervals in the aforementioned preset table can be equal or unequal. For example, in the example table 3 above, the number of elements in the shortened sequences corresponding to different lift value intervals is equal to L, where L is an integer greater than 0 and less than the system column size kb. The reason they can be unequal is that different lift value sizes may have different shortened system column sizes kb.

[0085] In another embodiment, the number L of elements in the shortened sequence corresponding to different lift value intervals in the aforementioned preset table can also be equal to 0. In one example, the number L of elements in the shortened sequence corresponding to different lift value intervals in the preset table is all equal to 0, indicating that no shortening is required under any lift value; in another example, the number L of elements in the shortened sequence corresponding to different lift value intervals in the preset table is different, and some of them are equal to 0, then no shortening is performed under the lift value interval corresponding to L=0.

[0086] In one example, the number of system columns (system column size) of the PCM of BG2 is kb = 10. When the length of the bit sequence to be encoded is B = 192, according to Table 1, Kb = 6 is obtained based on the length of the bit sequence to be encoded, and the boost value Z = 32 can be obtained based on B and Kb. At this time, the length of the shortened sequence L is equal to kb - Kb = 4. In another example, when the length of the bit sequence to be encoded is B = 512, according to Table 1, Kb = 8 is obtained based on the length of the bit sequence to be encoded, and the boost value Z = 64 can be obtained based on B and Kb. At this time, the length of the shortened sequence L is equal to kb - Kb = 2.

[0087] In this embodiment, the shortened sequence S0, S1, ..., S of the preset table is... M-1 There are at least two distinct shortened sequences, where the two shortened sequences are distinct in that an element in one shortened sequence does not belong to the other shortened sequence.

[0088] In this embodiment, the shortening sequence of the aforementioned preset table is used to indicate the position where the system column of the PCM is shortened. The column index value is used to indicate the position to be shortened, and the column index value is an integer greater than or equal to 0 and less than kb. In one example, as shown in Table 4, the dimension size of the PCM is 4*14, and the system column size before shortening is kb=10. If the shortening sequence corresponding to the boost value Z=64 is [8,9], then the bits in the codeword corresponding to the 9th column of the PCM [-1; 224; 240; 18] are known at both the transmitting and receiving ends, and the corresponding bit positions in the codeword are set to null or 0; and the bits in the codeword corresponding to the 10th column of the PCM [205; 252; -1; 128] are known at both the transmitting and receiving ends, and the corresponding bit positions in the codeword are set to null or 0.

[0089] Table 4 PCM

[0090] Understandably, the shortened sequence is used to indicate the position where the system column of the PCM is shortened. The size of the column index value is not limited to an integer greater than or equal to 0 and less than kb. For example, it can also be an integer greater than 0 and less than or equal to kb.

[0091] Based on an example of Method 1, the shortening sequence is obtained according to a preset table. The preset table is used to indicate the shortening sequence corresponding to each boost value. The shortening sequence is used to indicate the position where the system column of PCM is shortened. In this example, the shortening sequence when the boost value Z equals 8 is [5,6,8,9], and the shortening sequence when the boost value Z equals 16 is [6,7,8,9]. The preset table is shown in Table 5.

[0092] Table 5. Increase Value Range and Corresponding Shortening Sequence

[0093] In the above example, when Z equals 8 and PCM is as shown in Table 4, the shortened sequence [5,6,8,9] is selected. When the code rate is 5 / 6, the performance curve of the shortened sequence is shown as the solid line in Figure 4, and the dashed line is the performance curve of the shortened sequence [6,7,8,9]. It can be found that when the boost value Z equals 8, the shortened sequence [5,6,8,9] has better performance; where the vertical axis is the block error rate (BLER) and the horizontal axis is the signal-to-noise ratio.

[0094] In the above example, when Z equals 16 and PCM is as shown in Table 4, the shortened sequence [6,7,8,9] is selected. When the code rate is 5 / 6, the performance curve of the shortened sequence is shown by the dashed line in Figure 5, and the solid line is the performance curve of the shortened sequence [5,6,8,9]. It can be found that when the boost value Z equals 16, the shortened sequence [6,7,8,9] has better performance; where the vertical axis is the code block error rate and the horizontal axis is the signal-to-noise ratio.

[0095] Based on the above, choosing different shortening sequences for different boost values ​​can improve the error correction performance of the data.

[0096] Method 2: The shortening sequence is obtained according to a preset process. The preset process is used to indicate the shortening sequence corresponding to each boost value. The shortening sequence is used to indicate the position where the system column of PCM is shortened. In this method, the preset process is shown in Table 6.

[0097] Table 6 shows the preset procedure for obtaining the shortened sequence.

[0098] In this embodiment, the if condition in the above-mentioned preset process can be not only a range, but also an equality judgment. For example, the shortened sequence when Z == Z0 is S0 = [s 0,0 ,s 0,1 ,...,s 0,L-1 ].

[0099] In one example, the shortening sequence is obtained according to a preset procedure. The preset procedure indicates the shortening sequence corresponding to each boost value. The shortening sequence indicates the position where the PCM system column is shortened. In this example, the shortening sequence when the boost value Z equals 8 is [5,6,8,9], and the shortening sequence when the boost value Z equals 16 is [6,7,8,9]. The preset procedure can be expressed as follows:

[0100] Table 7 shows the preset process for obtaining the shortened sequence corresponding to the lift value.

[0101] In this embodiment, the number of elements in the shortened sequence corresponding to different boost value intervals in the above-mentioned preset process can be equal or unequal.

[0102] In this embodiment, the shortened sequence S0, S1, ..., S of the above-mentioned preset process is... M-1 There are at least two different shortened sequences, where the two shortened sequences are different in that an element in one shortened sequence does not belong to the other shortened sequence.

[0103] In this embodiment, the shortening sequence of the above-mentioned preset process is used to indicate the position where the system column of PCM is shortened. The column index value is used to indicate the position where it needs to be shortened, wherein the column index value is an integer greater than or equal to 0 and less than kb, or the column index value is an integer greater than 0 and less than or equal to kb.

[0104] In step 120, the element values ​​in the shortened sequence do not include the index values ​​corresponding to the system punctured columns. The system punctured column refers to the PCM system column corresponding to the bits in the encoded codeword that are not transmitted. At the receiving end, the probability that the codeword bits corresponding to the above system column are equal to 0 and 1 is equal. In one example, the PCM dimension is 4*14, the boost value Z = 256, and if there are two system punctured columns with column index 0 and column index 1, then the first 2*Z = 512 bits of the encoded codeword are not transmitted. At the receiving end, the probability that the first 512 bits of the codeword are equal to 0 and 1 is equal, and the shortened sequence in step 120 does not contain elements 0 and 1. Therefore, the range of elements in the shortened sequence is integers greater than 1 and less than 10.

[0105] In this embodiment, the encoded bit sequence is obtained based on at least the following parameters: shortened sequence, PCM, shortened systematic column size, boost value, and bit sequence to be encoded; wherein, the encoded bit sequence is obtained by encoding the PCM, shortened sequence, shortened systematic column size, and boost value into the bit sequence to be encoded; the shortened sequence is a list of position indices indicating that the LDPC code shortens the systematic column of the PCM according to the shortening position, and the number of elements in the shortened sequence is less than the systematic column size (kb) of the PCM and greater than 0; the PCM is a matrix of size mb*nb, the systematic column size kb is the difference between nb and mb, mb and nb are integers greater than 0, and nb is greater than mb; the boost value Z is an integer greater than 0; the shortened systematic column size Kb is an integer greater than 0 and less than or equal to kb; the length B of the bit sequence to be encoded is an integer greater than 0.

[0106] In one embodiment, the step of obtaining the encoded bit sequence based on at least the shortened sequence, PCM, shortened hierarchical column size, boost value, and parameters of the bit sequence to be encoded may include, but is not limited to: Step 1: Obtaining the zero-padded bit sequence to be encoded based on the determined shortened sequence, PCM, boost value, and shortened hierarchical column size; wherein the length of the zero-padded bit sequence to be encoded is kb*Z; Step 2: Encoding the zero-padded bit sequence to be encoded based on the PCM and boost value to obtain an encoded bit sequence of length N.

[0107] In step one, a zero-padded bit sequence to be encoded is obtained based on the determined shortened sequence, PCM, boost value, and shortened systematic column size. The zero-padded bit sequence to be encoded is a bit sequence of length B filled with zero bits to a length of kb*Z. In this embodiment, the positions for filling zero bits are the codeword bit positions corresponding to the shortened systematic columns in the shortened sequence and the additional padding positions. The number of zero-padded bits corresponding to L shortened systematic columns is L*Z, where L equals the difference between the size of the systematic column before shortening (kb) and the size of the systematic column after shortening (Kb). The additional zero-padded bits are kb*ZBL*Z zero bits filled at preset positions when kb*Z≥B+L*Z. In one example, the codeword positions with indices B+1 to Kb*Z are the additional padding positions.

[0108] In one example, the bit sequence to be encoded is represented as a = {a0, a1, ..., a...} B-1 The extra padding positions are at codeword positions from index B+1 to Kb*Z, at which point a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1}; Shorten the sequence so that the elements are the last L2 column of the system column, and you get a″={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 ,…,0 kb*Z-1 The positions of the padding zero bits are known at both the transmitting and receiving ends. The kb*ZB padding zero bits may be omitted when the first communication node sends encoded data to the second communication node.

[0109] In step two, the zero-padded bit sequence to be encoded is encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N. In one feasible approach, the encoded bit sequence b is obtained by encoding as follows: the PCM is matrix-extended based on the boost value Z to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded; the zero-padded bit sequence to be encoded is encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0110] In one embodiment, the length N of the encoded bit sequence includes zero-padded bits, and all or part of the remaining bit information is transmitted after excluding the zero-padded bits; in another embodiment, the length N of the encoded bit sequence does not include zero-padded bits, and all or part of the bit information of the encoded bit sequence without zero-padded bits is transmitted.

[0111] Here, the lift value Z serves as the dimension of the standard permutation matrix, enabling the expansion of the PCM. For example, elements indicating all-zero square matrices in the PCM can be replaced with Z*Z all-zero matrices. Similarly, elements indicating cyclic shifts of the identity matrix in the PCM can be replaced with cyclic shift matrices of the identity matrix. After these replacements, an extended PCM containing only 0s and 1s can be obtained. It should be understood that in this application, the PCM before the expansion of the BG is collectively referred to as PCM, and the PCM after the expansion of the BG is collectively referred to as extended PCM.

[0112] To facilitate understanding of the process of matrix expansion based on boosting values, we will first illustrate the specific representation of the parity matrix.

[0113] In one example, the extended PCM H of the LDPC code is an mb*Z row and nb*Z column matrix, composed of mb*nb submatrices, each of which is a different power of a Z*Z standard permutation matrix (corresponding to a cyclic shift matrix of the identity matrix) or a Z*Z all-zero square matrix. Matrix H has the following form:

[0114] if have That is, a Z*Z all-zero square matrix; if If the integer is greater than or equal to 0, the corresponding submatrix is ​​the standard permutation matrix P. The z×z standard permutation matrix P is shown below (the standard permutation matrix is ​​formed by cyclically shifting the identity matrix one bit to the right):

[0115] so, This allows each submatrix to be uniquely identified. If a submatrix is ​​a square matrix consisting entirely of zeros, the corresponding... Using -1 (or null values), if a submatrix is ​​obtained by cyclic shift 's' of the identity matrix, then... Equals s, therefore all This can form a PCM. Therefore, a PCM includes two types of elements: elements indicating an all-zero square matrix and elements indicating a cyclic shift of the identity matrix.

[0116] Z is the dimension of the standard permutation matrix (submatrix), and is called the lifting size. The base graph of the LDPC code is obtained by replacing the elements indicating cyclic shifts of the identity matrix in the PCM with "1" and replacing all elements indicating all-zero square matrices with "0". Therefore, the base graph of the LDPC code includes only two types of elements: "0" and "1", where "0" indicates an element at that index position that is an all-zero square matrix, and "1" indicates an element at that index position that is a cyclic shift of the identity matrix. For ease of description, only the elements indicating cyclic shifts of the identity matrix in the PCM and their row and column indices can be described, while the remaining row and column indices are assumed to indicate elements indicating all-zero square matrices. Alternatively, the elements indicating cyclic shifts of the identity matrix can be represented by their cyclic shift values, while the elements indicating all-zero square matrices can be described using -1, null values, or empty values.

[0117] In one example, a single LDPC code PCM (2 rows, 4 columns) is shown below, with a boost value of 4:

[0118] In this example, the extended PCM H is:

[0119] In this example, the corresponding base diagram is as follows:

[0120] Based on the specific representation of the parity check matrix, the following will explain the encoding process of the bit sequence to be encoded described in the embodiments of this application:

[0121] Step 1: Obtain the zero-padded bit sequence to be encoded based on the determined shortened sequence, PCM, boost value, and shortened system column size.

[0122] The length of the bit sequence to be encoded after zero padding is kb*Z, and the positions of the zero-padded bits are the codeword bit positions corresponding to the shortened system column in the shortened sequence and the additional padding positions.

[0123] In one example, the bit sequence to be encoded is represented as a = {a0, a1, ..., a...} B-1 The extra padding positions are at codeword positions from index B+1 to Kb*Z, at which point a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1}; Shorten the sequence so that the elements are the last L2 column of the system column, and you get a″={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 ,…,0 kb*Z-1}

[0124] Step 2: Encode the zero-padded bit sequence based on PCM and the boost value to obtain an encoded bit sequence of length N.

[0125] In this step, the zero-padded bit sequence to be encoded is described as a″={a0,a1,…,a…} B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 ,…,0 kb*Z-1 The output encoded bit sequences are b = {b0, b1, ..., b}. N-1 The length of the encoded bit sequence is N bits.

[0126] For the zero-padded bit sequence a″, the zero-padded bit sequence is encoded according to PCM and the boost value Z to obtain the encoded bit sequence b. The encoded bit sequence b is obtained by encoding according to the following process:

[0127] The PCM is matrix-extended based on the boost value Z to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded; the zero-padded bit sequence to be encoded is then encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0128] Among them, according to PCM H b And the boost value Z, determine the extended PCM as H, that is, H b Replace the elements of the zero-indexed square matrix with a Z*Z zero-indexed matrix, and then... b The elements of the identity matrix that are cyclically shifted are replaced with a Z*Z cyclic shift matrix of the identity matrix (the shift value is equal to the element value, and can be a rightward or leftward cyclic shift). Similarly, each extended PCM includes a system column matrix H. s And check column matrix H p That is, the extended PCM has the following structure:

[0129] Based on PCM H b The boost value Z is used to encode the bit sequence to obtain the encoded bit sequence. It can be understood that the encoded bit sequence can be calculated using the extended PCM H. v = H s ×a″,p=(H p ) -1 ×v

[0130] Therefore, the encoded bit sequence can be represented as The length of the encoded bit sequence is N.

[0131] In this embodiment, LDPC code shortening is an effective means of adjusting the code rate. It is achieved by selectively omitting some codeword positions while maintaining the excellent performance characteristics of the LDPC code as much as possible. Specifically, the shortening operation involves selecting certain positions in the codeword and deciding not to send information at these positions. In this way, the shortened positions are known at both the transmitting and receiving ends. Typically, the shortened positions are set to 0, without directly changing the size of the PCM. These shortened positions do not participate in the encoding process.

[0132] For the codeword bit position corresponding to the shortened systematic column in the shortened sequence, if the shortened position is the last L columns of the systematic column in the PCM, then the (kb-L)*Z+1 to kb*Z bits in the codeword are known at both the transmitting and receiving ends, for example, set to 0 at the position. Since one element in the shortened sequence refers to one column of the PCM, one element in the shortened sequence corresponds to a shortening of Z bits.

[0133] For additional padding positions, the size of the information bits to be encoded (the length of the bit sequence to be encoded) B may be less than the number of bits Kb*Z, therefore zero padding is required. The zero padding process described above can also be understood as a shortening operation. After padding, the bit sequence to be encoded becomes {a0, a1, ..., a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 The positions of the 0-filling bits are known at both the transmitting and receiving ends, and the first communication node can choose not to send these 0-filling bits.

[0134] Example 2

[0135] In this embodiment, based on the encoding method shown in Figure 2, the encoding method further includes: S140: sending all or part of the bits of the encoded bit sequence to the second communication node.

[0136] The length of the encoded bit sequence is N, and the number of encoded bits sent is E, where E is an integer less than or equal to N.

[0137] In one embodiment, a coded bit sequence of length E is obtained by bit selection of the coded bit sequence according to at least one of the following: punctured bit position, zero-padding shortened bit position, code rate, and length of the bit sequence to be encoded.

[0138] The length of the encoded bit sequence obtained above includes source information bits, zero-padding bits, and parity bits. The length of the encoded bit sequence may not meet the code rate requirements, so it is necessary to select a portion of the bits for transmission.

[0139] In this embodiment, the number of parity bits in the encoded bit sequence of length E is obtained according to at least the following method: (floor(B / R)-B+puncSysBit), and the number of parity bits punctured from the encoded bit sequence is obtained according to at least the following method: mb*Z-(floor(B / R)-B+puncSysBit). Where B is the length of the bit sequence to be encoded, puncSysBit is the number of system bit punctures, puncParBit is the number of parity bit punctures, R is the target bit rate, and floor() represents taking the largest integer less than or equal to the target value; besides floor(), ceil() or round() can also be used, representing taking the smallest integer greater than or equal to the target value and the integer with the smallest difference from the target value, respectively.

[0140] In the embodiments of this application, the punch bit positions are preset; in one example, the system bit punch positions are located at the first puncSysBit bits of the encoded bit sequence, and the parity bit punch positions are located at the last puncParBit bits of the encoded bit sequence.

[0141] In one example, an coded bit sequence of length E is a bit sequence obtained by deleting the first puncSysBit system punch bits, the kb*ZB zero-padding bits, and the last puncParBit check punch bits from an coded bit sequence of length N.

[0142] Example 3

[0143] In this embodiment, a shortened sequence is obtained based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value and code rate. Obtaining a shortened sequence based on the length of the bit sequence to be encoded and the code rate includes: determining the shortened systematic column size Kb based on the length of the bit sequence to be encoded; and obtaining the shortened sequence based on the shortened systematic column size Kb and the code rate.

[0144] In this embodiment, the beneficial effect of obtaining a shortened sequence based on the length of the bit sequence to be encoded and the code rate is that if a Kb value has only one shortened sequence at any code rate, then it is difficult for that shortened sequence to have good performance at any code rate. Therefore, the code rate is further refined, and a better shortened sequence is selected based on the code rate; while Kb is obtained based on the length of the bit sequence to be encoded, so a better shortened sequence can be obtained based on the length of the bit sequence to be encoded and the code rate.

[0145] In one embodiment, the above-mentioned determination of the shortened system column size Kb based on the length B of the bit sequence to be encoded can be achieved by obtaining the shortened system column size according to the preset length range of the bit sequence to be encoded, as shown in the logical expression in Table 1 in one example.

[0146] In this embodiment, obtaining a shortened sequence based on the length and code rate of the bit sequence to be encoded includes, but is not limited to, the following methods: preset table, preset process.

[0147] In this embodiment of the application, the representation of the obtained shortened sequence can be at least one of the following:

[0148] Method 1: The shortened sequence is obtained according to a preset table. The preset table indicates the shortened sequence corresponding to each bit sequence length range and bit rate range to be encoded. The shortened sequence indicates the position where the system column of PCM is shortened. In this method, the preset table can be represented as:

[0149] Table 8. Shortened sequences corresponding to the length and code rate ranges of the bit sequences to be encoded.

[0150] In this embodiment, the T shortened sequences in the j-th column of the preset table have the same number of elements, and shortened sequences in different columns may have the same number of elements. This is because although the length range of the bit sequence to be encoded is divided into multiple parts, these multiple bit length ranges may have the same shortened system column size Kb value. The shortened sequence in the preset table is represented as S. i,j i is an integer greater than or equal to 0 and less than T, j is an integer greater than or equal to 0 and less than M, T is the number of preset code rate ranges, M is the number of preset bit sequence length ranges to be encoded, and S i,j It can be represented as S i,j =[s i,j,0 ,s i,j,1 ,...,s i,j,L-1 ], where S i,j Each element indicates the position of the system column that needs to be shortened, and each element is an integer greater than or equal to 0 and less than kb.

[0151] In this embodiment, the length range of the bit sequence to be encoded in the preset table can be not only a range, but also an equality judgment, such as B == B1; the code rate range of the preset table can not only be a range, but also an equality judgment, such as R == R1.

[0152] In one embodiment, the T shortened sequences in the j-th column of the aforementioned preset table may contain the same shortened sequence, and at least two of the M shortened sequences in the i-th row of the aforementioned preset table may contain different shortened sequences. The two shortened sequences are different if an element in one shortened sequence does not belong to the other shortened sequence.

[0153] In one example based on this embodiment, the shortened sequence is obtained according to a preset table. The preset table is used to indicate the shortened sequence corresponding to each bit sequence length range and code rate range to be encoded. The shortened sequence is used to indicate the position where the system column of PCM is shortened. In this example, PCM is obtained according to BG2 of 5G NR. The dimension size of BG2 is 42*52 and the system column size is 10. The preset table in this example is shown in Table 9.

[0154] Table 9. Shortened sequences corresponding to the length and code rate ranges of the bit sequences to be encoded.

[0155] In the example above, when B equals 48 and the code rate R = 1 / 3, the shortened sequence [6,7,8,9] is selected. The performance curve of the shortened sequence at a code rate of 1 / 3 is shown by the dashed line in Figure 6, and the solid line is the performance curve of the shortened sequence [5,6,8,9]. It can be found that for B = 48, the shortened sequence [6,7,8,9] has better performance at a code rate R = 1 / 3. The vertical axis represents the code block error rate, and the horizontal axis represents the signal-to-noise ratio.

[0156] In the example above, when B = 96 and the code rate R = 1 / 3, the shortened sequence [2,7,8,9] is selected. The performance curve of the shortened sequence at a code rate of 1 / 3 is shown by the solid line in Figure 7, and the dashed line is the performance curve of the shortened sequence [6,7,8,9]. It can be found that for B = 96, the shortened sequence [2,7,8,9] has better performance at a code rate R = 1 / 3. The vertical axis represents the code block error rate, and the horizontal axis represents the signal-to-noise ratio.

[0157] In the example above, there is also a column in the preset table where the shortened sequence is the same at different bitrates. That is, when B equals 512, the shortened sequence is [8,9] when the bitrate is 5 / 6 and when the bitrate is 1 / 3.

[0158] Method 2: The shortened sequence is obtained according to a preset procedure. The preset procedure indicates the shortened sequence corresponding to each bit sequence length range and bit rate range to be encoded. The shortened sequence indicates the position where the system column of PCM is shortened. In this method, the preset procedure can be expressed as:

[0159] Table 10 Preset Procedure for Obtaining Shortened Sequences

[0160] In this method, the length range of the bit sequence to be encoded in the above-mentioned preset process can be not only a range, but also an equality judgment, such as B == B1; the bit rate range of the above-mentioned preset process can not only be a range, but also an equality judgment, such as R == R1.

[0161] Example 4

[0162] In this embodiment, a shortened sequence is obtained based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value and code rate. In this embodiment, obtaining a shortened sequence based on the length of the bit sequence to be encoded, the boost value, and the code rate includes: determining the shortened system column size Kb based on the length of the bit sequence to be encoded; determining the boost value based on the length of the bit sequence to be encoded and the shortened system column size Kb; and obtaining the shortened sequence based on the boost value and the code rate.

[0163] In this embodiment, the beneficial effect of obtaining a shortened sequence based on the length of the bit sequence to be encoded, the boost value, and the code rate is that if a boost value results in only one shortened sequence at any code rate, then it is difficult for that shortened sequence to achieve good performance at any code rate. Therefore, the code rate is further refined, and a better shortened sequence is selected based on the code rate; while the boost value is obtained based on the length of the bit sequence to be encoded and the shortened sequence, thereby obtaining a better shortened sequence based on the length of the bit sequence to be encoded, the boost value, and the code rate.

[0164] In this embodiment, the above-mentioned determination of the shortened system column size Kb based on the length B of the bit sequence to be encoded can be achieved by obtaining the shortened system column size according to the preset length range of the bit sequence to be encoded, as shown in the logical expression in Table 1 in one example.

[0165] In this embodiment, determining the boost value based on the length of the bit sequence to be encoded and the shortened system column size Kb includes: finding a boost value in the set of all possible boost values ​​that satisfies Kb·Z c The minimum Z when ≥B holds true c The value is a definite promotion value. The preset set of optional promotion values ​​is a collection of all possible promotion values; in one example, the elements in the optional promotion value set are represented as a*2. j , a equals the set {2,3,5,7,9,11,13,15}, j equals the set {0,1,2,3,4,5,6,7}.

[0166] In this embodiment, obtaining a shortened sequence based on the boost value and bit rate includes, but is not limited to, the following methods: preset table, preset process.

[0167] In this embodiment of the application, the representation of the obtained shortened sequence can be at least one of the following:

[0168] Method 1: The shortened sequence is obtained according to a preset table. The preset table is used to indicate the shortened sequence corresponding to each boost value interval and bit rate interval. The shortened sequence is used to indicate the position where the system column of PCM is shortened. In this method, the preset table is shown in Table 11.

[0169] Table 11 shows the shortened sequences corresponding to the boost value range and the bit rate range.

[0170] In this embodiment, the T shortened sequences in the j-th column of the preset table have the same number of elements, and shortened sequences in different columns may have the same number of elements. This is because although the boost value range is divided into multiple intervals, these multiple boost value ranges may have the same shortened system column size Kb value. For example, in BG2 of 5G NR, the shortened system column size is equal to 6 when Z=8 and Z=16. The shortened sequence in the preset table is represented as S. i,j i is an integer greater than or equal to 0 and less than T, j is an integer greater than or equal to 0 and less than M, T is the number of preset bitrate ranges, M is the number of preset boost value ranges, and S i,j It can be represented as S i,j =[s i,j,0 ,s i,j,1 ,...,s i,j,L-1 ], where S i,j Each element indicates the position of the system column that needs to be shortened, and each element is an integer greater than or equal to 0 and less than kb.

[0171] In this embodiment, the boost value range of the preset table can be more than just a range, or it can be an equality judgment, such as Z==Z1; the bit rate range of the preset table can be more than just a range, or it can be an equality judgment, such as R==R1.

[0172] In one embodiment, the T shortened sequences in the j-th column of the aforementioned preset table may contain the same shortened sequence, and at least two of the M shortened sequences in the i-th row of the aforementioned preset table may contain different shortened sequences. The two shortened sequences are different if an element in one shortened sequence does not belong to the other shortened sequence.

[0173] In one example based on this embodiment, the shortening sequence is obtained according to a preset table. The preset table indicates the shortening sequence corresponding to each boost value range and bit rate range. The shortening sequence indicates the position where the system column of PCM is shortened. In this example, PCM is obtained based on BG2 of 5G NR. The dimension of BG2 is 42*52, and the system column size is 10. The preset table in this example can be represented as follows:

[0174] Table 12 Shortening sequences corresponding to boost value range and bit rate range

[0175] In the example above, when Z equals 8 and the bitrate R = 1 / 3, the shortened sequence [6,7,8,9] is selected, and when the bitrate R equals 5 / 6, the shortened sequence [5,6,8,9] is selected. This is because when the bitrate is 1 / 3, the shortened sequence [6,7,8,9] has a lower data error rate than the shortened sequence [5,6,8,9].

[0176] Method 2: The shortened sequence is obtained according to a preset process. The preset process indicates the shortened sequence corresponding to each boost value range and bitrate range. The shortened sequence indicates the position where the PCM system column is shortened. In this method, the preset process can be expressed as:

[0177] Table 13 Preset Procedure for Obtaining Shortened Sequences

[0178] It is understood that the above examples are merely illustrative for better understanding of this embodiment. The shortened sequence can be other values, and the aforementioned boost value can be determined not only by whether it equals a preset value, but also by whether it falls within a preset interval. Similarly, the aforementioned bit rate can be determined not only by whether it equals a preset value, but also by whether it falls within a preset interval. For example, the length interval of the bit sequence to be encoded in the aforementioned preset process can not only be a range, but also an equality judgment, such as Z == Z1; the bit rate interval of the aforementioned preset process can not only be a range, but also an equality judgment, such as R == R1.

[0179] Example 5

[0180] In this embodiment, a shortened sequence is obtained based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value and code rate. In this embodiment, obtaining a target shortened sequence based on the length of the bit sequence to be encoded and the code rate includes: obtaining a first shortened sequence based on the code rate; determining the shortened hierarchical column size Kb based on the length of the bit sequence to be encoded; and determining the target shortened sequence based on the shortened hierarchical column size Kb and the first shortened sequence.

[0181] In this embodiment, the first shortened sequence is an ordered sequence. Two first shortened sequences are different if at least one element at the same position is different. This is because each code rate may correspond to the length of multiple bit sequences to be encoded, and also to multiple Kb values ​​and the number of system columns to be shortened. When the number of system columns to be shortened is less than the length of the first shortened sequence, one way to select the shortened sequence is to select the sequence consisting of the first few elements of the first shortened sequence as the shortened sequence for that Kb value.

[0182] In this embodiment, if there are M selectable bitrate values, then there are at least two distinct first shortening sequences and at most M distinct first shortening sequences. It can be understood that: one case is that M bitrate values ​​correspond to M distinct first shortening sequences; the second case is that M bitrate values ​​correspond to fewer than M distinct first shortening sequences, meaning there are at least two bitrate values ​​corresponding to one first shortening sequence, where M is an integer greater than 1. Beneficial effect: Selecting the optimal first shortening sequence for each bitrate value can improve the error correction performance of the data.

[0183] In one embodiment, a shortened sequence is obtained based on a bitrate value. The shortened sequence may be obtained according to, but is not limited to, a preset table or a preset process.

[0184] In this embodiment of the application, the representation of the obtained shortened sequence can be at least one of the following:

[0185] Method 1: The shortened sequence is obtained according to a preset table. The preset table is used to indicate the first shortened sequence corresponding to each bit rate value. The first shortened sequence is used to indicate the position where the system column of PCM is shortened. In this method, the preset table is shown in Table 14.

[0186] Table 14 shows the preset table for obtaining shortened sequences.

[0187] In this embodiment, the bitrate value range of the preset table can be more than just a range; it can also be an equality judgment. For example, the shortened sequence when R == R0 is S0 = [s 0,0 ,s 0,1 ,...,s 0,L-1 ].

[0188] Method 2: The shortened sequence is obtained according to a preset process. The preset process is used to indicate the first shortened sequence corresponding to each bit rate value. The first shortened sequence is used to indicate the position where the system column of PCM is shortened. In this method, the preset process is shown in Table 15.

[0189] Table 15 Preset Procedure for Obtaining Shortened Sequences

[0190] In this embodiment, the if condition in the above-mentioned preset process can be not only a range, but also an equality judgment. For example, the shortened sequence when R == R0 is S0 = [s 0,0 ,s 0,1 ,...,s 0,L-1 ].

[0191] In this embodiment, the number of elements in the shortened sequence corresponding to different boost value intervals in the preset table or preset process is equal to the preset maximum number of supported shortenings, where L is an integer greater than 0 and less than the system column size kb.

[0192] In this embodiment, the shortened system column size Kb is determined based on the length of the bit sequence to be encoded. This can be achieved by obtaining the shortened system column size according to a preset range of bit sequence lengths within which the length of the bit sequence to be encoded falls. In one example, the logical expression is shown in Table 1.

[0193] In this embodiment, after obtaining the shortened system column size Kb, the number of system columns that need to be shortened C can be obtained, where C = kb - Kb, and kb is the PCM system column size before shortening.

[0194] In this embodiment, determining the target shortened sequence based on the shortened system column size Kb and the first shortened sequence includes: if the code rate R is within the code rate interval R i ≤R <R i+1 For the first shortened sequence S i =[s i,0 ,s i,1 ,...,s i,L-1 The number of system columns to be shortened is C, and the target shortening sequence is a sequence consisting of C elements at preset positions in the first shortening sequence. In one example, the first C elements of the first shortening sequence are selected as the target shortening sequence; in another example, the last C elements of the first shortening sequence are selected as the target shortening sequence.

[0195] Example 6

[0196] In this embodiment, the step of obtaining the encoded bit sequence based on at least the shortened sequence, PCM, shortened systematic column size, boost value, and bit sequence to be encoded may include, but is not limited to:

[0197] Step 1: Obtain the shortened PCM based on the determined shortened sequence, PCM, and shortened systematic column size;

[0198] Step 2: Encode the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N;

[0199] The process of encoding the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N is as follows: obtain the boost value Z that matches the bit sequence to be encoded; perform matrix expansion on the shortened PCM based on the boost value Z to obtain the parity check matrix corresponding to the bit sequence to be encoded; and encode the bit sequence to be encoded based on the parity check matrix to obtain an encoded bit sequence of length N.

[0200] Step 1: Obtain the shortened PCM based on the determined shortened sequence, PCM, and shortened system column size.

[0201] The shortened PCM is a matrix formed by excluding the systematic columns indicated by the elements in the shortened sequence; in one example, the PCM is described as H b ,

[0202] The shortened sequence S can be described as S = [s0, s1, ..., s L-1 ], shortened PCM H bs It can be described as:

[0203] Where, [s0,s1,...,s L-1 Each element in the symbol is an integer greater than or equal to 0 and less than kb, and "\" represents the exclusion symbol.

[0204] Step 2: Encode the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N.

[0205] In this step, the input bit sequence to be encoded can be described as a = {a0, a1, ..., a...} B-1 Since B may be less than Kb*Z, a zero-padding shortening operation is required. When the padded bits are 0, we get a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 The output encoded bit sequence is b = {b0, b1, ..., b}. N-1 The length of the encoded bit sequence is N bits.

[0206] In this step, during the encoding process, when the product of the shortened PCM system column number Kb (shortened system column size Kb) and the boost value Z equals the length B of the bit sequence to be encoded, the corresponding information bits during encoding are a = {a0, a1, ..., a...} B-1 When the product of the shortened PCM system column number Kb and the boost value Z is greater than the length B of the bit sequence to be encoded, Kb*ZB zero bits are padded after the input bit sequence to be encoded to obtain a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 At this point, the corresponding information bits during encoding are a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1The Kb*ZB zero bits used for padding can be omitted when the first communication node sends encoded data to the second communication node.

[0207] For the bit sequence to be encoded, 'a' is encoded according to the shortened PCM and the boost value Z to obtain the encoded bit sequence 'b'. The encoded bit sequence 'b' is obtained by encoding according to the following process:

[0208] The shortened PCM is matrix-expanded based on the boost value Z to obtain the parity check matrix corresponding to the bit sequence to be encoded; the bit sequence to be encoded is then encoded based on the parity check matrix to obtain an encoded bit sequence of length N.

[0209] Among them, according to the shortened PCM H bs And the boost value Z, determine the extended PCM as H, that is, H bs Replace the elements of the zero-indexed square matrix with a Z*Z zero-indexed matrix, and then... bs The elements of the identity matrix that are cyclically shifted are replaced with a Z*Z cyclic shift matrix of the identity matrix (the shift value is equal to the element value, and can be a rightward or leftward cyclic shift). Similarly, each extended PCM includes a system column matrix H. s And check column matrix H p That is, the extended PCM has the following structure:

[0210] Based on shortened PCM H bs The boost value Z is used to encode the bit sequence to obtain the encoded bit sequence. It can be understood that the encoded bit sequence can be calculated using the extended PCM H. v = H s ×a′,p=(H p ) -1 ×v

[0211] Therefore, the encoded bit sequence can be represented as The length of the encoded bit sequence is N.

[0212] In this embodiment, LDPC code shortening is an effective means of adjusting the code rate. It is achieved by selectively omitting some codeword positions while maintaining the excellent performance characteristics of LDPC codes as much as possible. Specifically, the shortening operation involves selecting certain positions in the codeword and deciding not to send information at these positions. Thus, the shortened positions are known at both the transmitting and receiving ends. Typically, the shortened positions are set to 0, and these shortened positions do not participate in the encoding process. If the shortened position is the last L columns of the system column in the PCM, then the (kb-L)*Z+1 to kb*Z bits in the codeword are known at both the transmitting and receiving ends. Since one element in the shortened sequence refers to a column of the PCM, one element in the shortened sequence corresponds to a shortening of the boost value Z bits. In reality, the bit size B of the information to be encoded may be smaller than the total number of bits in the system column Kb*Z, therefore zero-padding is required. The zero-padding process of the bit sequence to be encoded described above can also be understood as a shortening operation. After padding, the bit sequence to be encoded becomes {a0, a1, ..., a...}. B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 The positions of the 0-filling bits are known at both the transmitting and receiving ends, and the first communication node can choose not to send these 0-filling bits.

[0213] Example 7

[0214] In this embodiment, upon receiving the data sequence to be decoded, the second communication node can perform data processing to obtain the original bit sequence to be encoded, as shown in Figure 3. The execution entity of this LDPC decoding method can be the aforementioned second communication node, or other electronic devices with certain computing capabilities. These electronic devices may include, for example, terminal devices, servers, or other processing devices. Terminal devices can be cellular phones, cordless phones, Session Initiation Protocol (SIP) phones, Wireless Local Loop (WLL) stations, Personal Digital Assistants (PDAs), handheld devices with wireless communication capabilities, computing devices, or other processing devices connected to a wireless modem, in-vehicle devices, wearable devices, 5G networks, or future 5G or higher networks. The decoding process of the second communication node can be as follows:

[0215] S210: Receive all or part of the data sequence to be decoded, corresponding to the encoded bit sequence;

[0216] S220: Obtain a shortened sequence based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value, code rate;

[0217] S230: Perform LDPC decoding on the data sequence to be decoded based on at least the following parameters to obtain the decoded bit sequence, which is consistent with the bit sequence to be encoded: shortened sequence, PCM, shortened system column size, boost value, and data sequence to be decoded.

[0218] The shortened sequence is identical to the data in the first processing node. It is a list of position indices indicating that the LDPC code shortens the systematic column of the PCM according to the shortening position. The number of elements in the shortened sequence is less than the systematic column size (kb) of the PCM and greater than 0. The PCM is a matrix of size mb*nb, where the systematic column size kb is the difference between nb and mb. Both mb and nb are integers greater than 0, and nb is greater than mb. The boost value Z is an integer greater than 0. The shortened systematic column size Kb is an integer greater than 0 and less than or equal to kb. The length B of the decoded bit sequence is an integer greater than 0. The code rate R is a real number greater than 0 and less than 1.

[0219] Here, for the received data sequence to be decoded, LDPC decoding can be performed on the data sequence to be decoded based on the shortened sequence, PCM, the size of the shortened systematic column, and the boost value to obtain the same decoded sequence as the bit sequence data to be encoded. The process of processing the encoded bit sequence is equivalent to the decoding process based on LDPC code, which corresponds to the encoding process, and will not be elaborated here.

[0220] This application also provides an encoding device. Figure 8 is a schematic diagram of an encoding device provided in one embodiment. As shown in Figure 8, the encoding device includes:

[0221] The first sequence determination module 310 is configured to determine the bit sequence to be encoded.

[0222] The second sequence determination module 320 is configured to determine a shortened sequence based on the length (B) of the bit sequence to be encoded and at least one of the following parameters: boost value, code rate;

[0223] The encoding module 330 is configured to encode the bit sequence to be encoded based on the parity check matrix PCM, the shortened sequence, the shortened system column size (Kb), and the boost value to obtain the encoded bit sequence.

[0224] The shortened sequence includes a position index indicating the position where the LDPC code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size (kb) of the PCM and greater than 0. The length (B) of the bit sequence to be encoded and the boost value are both integers greater than 0. The code rate is a real number greater than 0 and less than 1. The number of rows (mb) and columns (nb) of the PCM are both integers greater than 0, and the number of columns (nb) is greater than the number of rows (mb). The systematic column size (kb) of the PCM is the difference between the number of columns (nb) and the number of rows (mb). The shortened systematic column size (Kb) is an integer greater than 0 and not exceeding the systematic column size (kb). The length (N) of the encoded bit sequence is an integer greater than the length (B) of the bit sequence to be encoded.

[0225] In one embodiment, the apparatus further includes a transmitting module configured to transmit all or part of the bits of the encoded bit sequence to a second node.

[0226] In one embodiment, determining a shortened sequence based on the length of the bit sequence to be encoded and a boost value includes: determining the size of the shortened system column based on the length of the bit sequence to be encoded; determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened system column; and determining a shortened sequence based on the boost value.

[0227] In one embodiment, among the M shortened sequences determined based on M different lifting values, at least two different shortened sequences exist; where M is an integer greater than 1; and the number of shortened sequences is a positive integer not exceeding M.

[0228] In one embodiment, determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened system column includes: determining the minimum value in the boost value set as the boost value; the values ​​in the boost value set satisfy that the product of the boost value and the size of the shortened system column is greater than or equal to the length of the bit sequence to be encoded.

[0229] In one embodiment, determining the shortening sequence based on the boost value includes: determining the shortening sequence according to a preset table or a preset procedure, wherein the preset table or the preset procedure is used to indicate the shortening sequence corresponding to each boost value interval.

[0230] In one embodiment, encoding the bit sequence to be encoded based on the PCM, the shortened sequence, the shortened hierarchical column size, and the boost value to obtain an encoded bit sequence includes: determining the zero-padded bit sequence to be encoded based on the shortened sequence, the PCM, the boost value, and the shortened hierarchical column size, wherein the length of the zero-padded bit sequence to be encoded is the product of the hierarchical column size and the boost value; and encoding the zero-padded bit sequence to be encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N.

[0231] In one embodiment, encoding the zero-padded bit sequence to be encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N includes: matrix expansion of the PCM based on the boost value Z to obtain an extended PCM corresponding to the zero-padded bit sequence to be encoded; and encoding the zero-padded bit sequence to be encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0232] In one embodiment, determining a shortened sequence based on the length and code rate of the bit sequence to be encoded includes: determining the size of the shortened system column based on the length of the bit sequence to be encoded; and obtaining the shortened sequence based on the size of the shortened system column and the code rate.

[0233] In one embodiment, obtaining a shortened sequence based on the shortened system column size and code rate includes one of the following: determining the shortened sequence according to a preset table or preset process, wherein the preset table or preset process is used to indicate the shortened sequence corresponding to the length range and code rate range of each bit sequence to be encoded.

[0234] In one embodiment, determining a shortened sequence based on the length of the bit sequence to be encoded, a boost value, and a code rate includes: determining the size of the shortened hierarchical column based on the length of the bit sequence to be encoded; determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened hierarchical column; and obtaining the shortened sequence based on the boost value and the code rate.

[0235] In one embodiment, determining a boost value based on the length of the bit sequence to be encoded and the size of the shortened system column includes: determining the minimum value in the boost value set as the boost value; the values ​​in the boost value set satisfy: greater than or equal to a target value, wherein the target value is an integer not less than the ratio of the length of the bit sequence to be encoded to the size of the shortened system column.

[0236] In one embodiment, obtaining a shortened sequence based on the boost value and the bit rate includes one of the following: determining the shortened sequence according to a preset table or a preset procedure, wherein the preset table or the preset procedure is used to indicate the shortened sequence corresponding to each boost value interval and each bit rate interval.

[0237] In one embodiment, determining a shortened sequence based on the length and code rate of the bit sequence to be encoded includes: determining a first shortened sequence based on the code rate; determining a shortened system column size based on the length of the bit sequence to be encoded; and determining a shortened sequence based on the shortened system column size and the first shortened sequence.

[0238] In one embodiment, determining a first shortened sequence based on bitrate includes: determining a shortened sequence according to a preset table or a preset procedure, wherein the preset table or the preset procedure is used to indicate the first shortened sequence corresponding to each bitrate interval.

[0239] In one embodiment, determining a shortened sequence based on the shortened system column size and the first shortened sequence includes: determining the number of system columns to be shortened according to the system column size and the shortened system column size, and constructing a shortened sequence by taking the corresponding number of elements at preset positions in the first shortened sequence according to the number of system columns to be shortened.

[0240] In one embodiment, determining the shortened system column size based on the length of the bit sequence to be encoded includes: determining the shortened system column size according to a preset length range of the bit sequence to be encoded, where the length of the bit sequence to be encoded falls.

[0241] In one embodiment, encoding the bit sequence to be encoded based on the PCM, the shortened sequence, the shortened hierarchical column size, and the boost value to obtain an encoded bit sequence includes: determining the shortened PCM based on the shortened sequence, the PCM, and the shortened hierarchical column size; and encoding the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N.

[0242] In one embodiment, encoding the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N includes: matrix expansion of the shortened PCM based on the boost value to obtain an extended PCM corresponding to the bit sequence to be encoded; and encoding the bit sequence to be encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0243] The encoding device proposed in this embodiment belongs to the same concept as the encoding method proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the encoding method.

[0244] This application also provides a decoding device. Figure 9 is a schematic diagram of the structure of a decoding device provided in one embodiment. As shown in Figure 9, the decoding device includes:

[0245] The receiving module 410 is configured to receive all or part of the data in the data sequence to be decoded;

[0246] The sequence determination module 420 is configured to determine a shortened sequence based on the length of the bit sequence to be encoded corresponding to the data sequence to be decoded and at least one of the following parameters: boost value, code rate;

[0247] The decoding module 430 is configured to perform LDPC decoding on the data sequence to be decoded based on the parity check matrix PCM, the shortened sequence, the shortened system column size and the boost value, to obtain a decoded bit sequence, which is consistent with the bit sequence to be encoded.

[0248] The shortened sequence includes a position index indicating the position where the LDPC code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size of the PCM and greater than 0. The length of the decoded bit sequence and the boost value are both integers greater than 0. The code rate is a real number greater than 0 and less than 1. The number of rows and columns of the PCM are both integers greater than 0, and the number of columns is greater than the number of rows. The systematic column size of the PCM is the difference between the number of columns and the number of rows, and the shortened systematic column size is an integer greater than 0 and not exceeding the systematic column size.

[0249] The encoding device proposed in this embodiment and the decoding method proposed in the above embodiments belong to the same concept. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the decoding method.

[0250] This application also provides a communication node. Figure 10 is a schematic diagram of the hardware structure of a communication node provided in an embodiment. As shown in Figure 10, the communication node provided in this application includes a processor 510 and a memory 520. The processor 510 in the communication node can be one or more, and Figure 10 shows one processor 510 as an example. The memory 520 is configured to store one or more programs. The one or more programs are executed by the one or more processors 510, so that the one or more processors 510 implement the encoding method or decoding method as described in the embodiments of this application.

[0251] The communication node also includes: a communication device 530, an input device 540, and an output device 550.

[0252] The processor 510, memory 520, communication device 530, input device 540 and output device 550 in the communication node can be connected by a bus or other means. Figure 10 shows an example of connection by bus.

[0253] Input device 540 can be configured to receive input digital or character information, and generate key signal inputs related to user settings and function control of the communication node. Output device 550 may include display devices such as a display screen.

[0254] The communication device 530 may include a receiver and a transmitter. The communication device 530 is configured to perform information transmission and reception communication under the control of the processor 510.

[0255] The memory 520, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as program instructions / modules (e.g., modules in an encoding device) corresponding to the encoding and decoding methods described in the embodiments of this application. The memory 520 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required for at least one function; the data storage area may store data created based on the use of the communication node, etc. Furthermore, the memory 520 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 520 may further include memory remotely located relative to the processor 510, and these remote memories can be connected to the communication node via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0256] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements any of the encoding or decoding methods described in this application.

[0257] This application also provides a computer program storage product, including a computer program / instruction, which, when executed by a processor, implements any of the encoding or decoding methods described in this application.

[0258] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. The computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0259] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0260] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0261] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0262] This application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the encoding and decoding methods described in any of the above embodiments.

[0263] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0264] Those skilled in the art will understand that the term user terminal encompasses any suitable type of wireless user equipment, such as mobile phones, portable data processing portable web browsers, or vehicle-mounted mobile stations.

[0265] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0266] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0267] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on memory. Memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disk (CD), etc.). Computer-readable media may include non-transitory storage media. Data processors may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and processors based on multi-core processor architectures.

[0268] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. An encoding method applied to a first communication node, comprising: Determine the bit sequence to be encoded; The shortened sequence is determined based on the length of the bit sequence to be encoded and at least one of the following parameters: boost value, code rate; The bit sequence to be encoded is encoded based on the parity check matrix PCM, the shortened sequence, the shortened system column size, and the boost value to obtain the encoded bit sequence. The shortened sequence includes a position index, which indicates the position where the low-density parity-check (LDPC) code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size of the PCM and greater than 0. The length of the bit sequence to be encoded and the boost value are both integers greater than 0. The bit rate is a real number greater than 0 and less than 1; the number of rows and columns of the PCM are both integers greater than 0, and the number of columns is greater than the number of rows; the system column size of the PCM is the difference between the number of columns and the number of rows, and the shortened system column size is an integer greater than 0 and not exceeding the system column size; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded.

2. The method according to claim 1, wherein, Determining the shortened sequence based on the length and boost value of the bit sequence to be encoded includes: The shortened system column size is determined based on the length of the bit sequence to be encoded. The boost value is determined based on the length of the bit sequence to be encoded and the size of the shortened system column; The shortened sequence is determined based on the lift value.

3. The method according to claim 2, wherein, Among the M shortened sequences determined by M different lifting values, at least two are different shortened sequences; Where M is an integer greater than 1; the number of shortened sequences is a positive integer not exceeding M.

4. The method according to claim 2, wherein, Determining the boost value based on the length of the bit sequence to be encoded and the size of the shortened system column includes: The minimum value in the set of boost values ​​is determined as the boost value; The values ​​in the boost set satisfy the following condition: the product of the boost value and the shortened system column size is greater than or equal to the length of the bit sequence to be encoded.

5. The method according to claim 2, wherein, Determining the shortened sequence based on the lift value includes: The shortening sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the shortening sequence corresponding to each increase value interval.

6. The method according to claim 1, wherein, The bit sequence to be encoded is encoded according to the PCM, the shortened sequence, the shortened systematic column size, and the boost value to obtain the encoded bit sequence, including: Based on the shortened sequence, PCM, boost value, and shortened system column size, a zero-padded bit sequence to be encoded is determined, wherein the length of the zero-padded bit sequence to be encoded is the product of the system column size and the boost value; The zero-padded bit sequence to be encoded is encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N.

7. The method according to claim 6, wherein, The zero-padded bit sequence to be encoded is encoded based on the PCM and the boost value to obtain an encoded bit sequence of length N, including: Based on the boost value Z, the PCM is matrix-extended to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded. The zero-padded bit sequence to be encoded is encoded based on the extended PCM to obtain an encoded bit sequence of length N.

8. The method according to claim 1, wherein, Determining the shortened sequence based on the length and code rate of the bit sequence to be encoded includes: The shortened system column size is determined based on the length of the bit sequence to be encoded. The shortened sequence is obtained based on the shortened system column size and code rate.

9. The method according to claim 8, wherein, A shortened sequence is obtained based on the shortened system column size and code rate, including one of the following: The shortened sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the shortened sequence corresponding to each bit sequence length interval to be encoded and each code rate interval.

10. The method according to claim 1, wherein, Determining the shortened sequence based on the length, boost value, and code rate of the bit sequence to be encoded includes: The shortened system column size is determined based on the length of the bit sequence to be encoded. The boost value is determined based on the length of the bit sequence to be encoded and the size of the shortened system column; A shortened sequence is obtained based on the boost value and the bit rate.

11. The method according to claim 10, wherein, Determining the boost value based on the length of the bit sequence to be encoded and the size of the shortened system column includes: The minimum value in the set of boost values ​​is determined as the boost value; The values ​​in the boost value set satisfy the following condition: greater than or equal to the target value, where the target value is an integer not less than the ratio of the length of the bit sequence to be encoded to the size of the shortened system column.

12. The method according to claim 10, wherein, Based on the boost value and the bit rate, a shortened sequence is obtained, including one of the following: The shortened sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the shortened sequence corresponding to each boost value interval and each bit rate interval.

13. The method according to claim 1, wherein, Determining the shortened sequence based on the length and code rate of the bit sequence to be encoded includes: The first shortened sequence is determined based on the code rate; The shortened system column size is determined based on the length of the bit sequence to be encoded. The shortened sequence is determined based on the shortened system column size and the first shortened sequence.

14. The method according to claim 13, wherein, The first shortened sequence is determined based on the code rate, including: The shortened sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the first shortened sequence corresponding to each bit rate interval.

15. The method according to claim 13, wherein, Determining the shortened sequence based on the shortened system column size and the first shortened sequence includes: The number of system columns that need to be shortened is determined based on the system column size and the shortened system column size. Based on the number of system columns that need to be shortened, the corresponding number of elements at preset positions in the first shortening sequence are used to form a shortening sequence.

16. The method according to claim 1, wherein, The bit sequence to be encoded is encoded according to the PCM, the shortened sequence, the shortened systematic column size, and the boost value to obtain the encoded bit sequence, including: The shortened PCM is determined based on the shortened sequence, PCM, and the shortened system column size. Based on the shortened PCM and the boost value, the bit sequence to be encoded is encoded to obtain an encoded bit sequence of length N.

17. The method according to claim 16, wherein, Based on the shortened PCM and the boost value, the bit sequence to be encoded is encoded to obtain an encoded bit sequence of length N, including: Based on the boost value, the shortened PCM is matrix-expanded to obtain the extended PCM corresponding to the bit sequence to be encoded. The extended PCM is used to encode the bit sequence to be encoded, resulting in an encoded bit sequence of length N.

18. The method according to claim 1, further comprising: Send all or part of the encoded bit sequence to the second node.

19. A decoding method applied to a second communication node, comprising: Receive all or part of the data sequence to be decoded; The shortening sequence is determined based on the length of the bit sequence to be encoded corresponding to the data sequence to be decoded and at least one of the following parameters: boost value, code rate; Based on the parity check matrix PCM, the shortened sequence, the shortened system column size and the boost value, the data sequence to be decoded is subjected to low-density parity check (LDPC) decoding to obtain the decoded bit sequence, which is consistent with the bit sequence to be encoded. The shortened sequence includes a position index, which indicates the position where the LDPC code shortens the systematic column of the PCM. The number of elements in the shortened sequence is less than the systematic column size of the PCM and greater than 0. The length of the decoded bit sequence and the boost value are both integers greater than 0. The bitrate is a real number greater than 0 and less than 1; the number of rows and columns of the PCM are both integers greater than 0, and the number of columns is greater than the number of rows; the system column size of the PCM is the difference between the number of columns and the number of rows, and the shortened system column size is an integer greater than 0 and not exceeding the system column size.

20. A communication node, comprising: Memory, and at least one processor; The memory is configured to store at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the encoding method as described in any one of claims 1-18 or the decoding method as described in claims 1-19.

21. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the encoding method as described in any one of claims 1-18 or the decoding method as described in claims 1-19.

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